Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.603636 # Number of seconds simulated
4sim_ticks 2603636076000 # Number of ticks simulated
5final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.603635 # Number of seconds simulated
4sim_ticks 2603634694000 # Number of ticks simulated
5final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 264193 # Simulator instruction rate (inst/s)
8host_op_rate 336182 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 11426847777 # Simulator tick rate (ticks/s)
10host_mem_usage 395692 # Number of bytes of host memory used
11host_seconds 227.85 # Real time elapsed on the host
12sim_insts 60197128 # Number of instructions simulated
13sim_ops 76599899 # Number of ops (including micro ops) simulated

7host_inst_rate 156094 # Simulator instruction rate (inst/s)
8host_op_rate 198627 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6751306864 # Simulator tick rate (ticks/s)
10host_mem_usage 397752 # Number of bytes of host memory used
11host_seconds 385.65 # Real time elapsed on the host
12sim_insts 60197457 # Number of instructions simulated
13sim_ops 76600355 # Number of ops (including micro ops) simulated
14system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
15system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
16system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
17system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
18system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
19system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
20system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
21system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
22system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
23system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
24system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
25system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)

14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory

26system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
27system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
28system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory

17system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
19system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory

29system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
30system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
31system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
32system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
33system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
34system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory

23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory

35system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory

24system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory

36system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory

25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory

37system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory

28system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory

40system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory

32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory

44system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory

33system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s)

45system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
46system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s)

35system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)

47system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)

37system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s)

49system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s)

43system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s)

55system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s)

44system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s)

56system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s)
57system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s)

47system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)

59system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.readReqs 15494089 # Total number of read requests seen
53system.physmem.writeReqs 811479 # Total number of write requests seen
54system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
55system.physmem.bytesRead 991621696 # Total number of bytes read from memory
56system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
57system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
58system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()

61system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.readReqs 15494095 # Total number of read requests seen
65system.physmem.writeReqs 811481 # Total number of write requests seen
66system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
67system.physmem.bytesRead 991622080 # Total number of bytes read from memory
68system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
69system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
70system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()

59system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
60system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
61system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis

71system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
72system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
73system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis
75system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis
76system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis

65system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis

77system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis

66system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis
75system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis

78system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis
79system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis
80system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis
81system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis
82system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis
83system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis
84system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis
85system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis
86system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis
87system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis

76system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis

88system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis

77system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis

89system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis
91system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
92system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis

81system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis

93system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis

82system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis
91system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis

94system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis
95system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis
96system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis
97system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis
98system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis
99system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis
100system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis
101system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis
102system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis
103system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis

92system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis

104system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis

93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

105system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
106system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

95system.physmem.totGap 2603631716000 # Total gap between requests

107system.physmem.totGap 2603630334000 # Total gap between requests

96system.physmem.readPktSize::0 0 # Categorize read packet sizes
97system.physmem.readPktSize::1 0 # Categorize read packet sizes
98system.physmem.readPktSize::2 6652 # Categorize read packet sizes
99system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
100system.physmem.readPktSize::4 0 # Categorize read packet sizes
101system.physmem.readPktSize::5 0 # Categorize read packet sizes

108system.physmem.readPktSize::0 0 # Categorize read packet sizes
109system.physmem.readPktSize::1 0 # Categorize read packet sizes
110system.physmem.readPktSize::2 6652 # Categorize read packet sizes
111system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
112system.physmem.readPktSize::4 0 # Categorize read packet sizes
113system.physmem.readPktSize::5 0 # Categorize read packet sizes

102system.physmem.readPktSize::6 152013 # Categorize read packet sizes

114system.physmem.readPktSize::6 152019 # Categorize read packet sizes

103system.physmem.readPktSize::7 0 # Categorize read packet sizes
104system.physmem.readPktSize::8 0 # Categorize read packet sizes
105system.physmem.writePktSize::0 0 # categorize write packet sizes
106system.physmem.writePktSize::1 0 # categorize write packet sizes
107system.physmem.writePktSize::2 754018 # categorize write packet sizes
108system.physmem.writePktSize::3 0 # categorize write packet sizes
109system.physmem.writePktSize::4 0 # categorize write packet sizes
110system.physmem.writePktSize::5 0 # categorize write packet sizes

115system.physmem.readPktSize::7 0 # Categorize read packet sizes
116system.physmem.readPktSize::8 0 # Categorize read packet sizes
117system.physmem.writePktSize::0 0 # categorize write packet sizes
118system.physmem.writePktSize::1 0 # categorize write packet sizes
119system.physmem.writePktSize::2 754018 # categorize write packet sizes
120system.physmem.writePktSize::3 0 # categorize write packet sizes
121system.physmem.writePktSize::4 0 # categorize write packet sizes
122system.physmem.writePktSize::5 0 # categorize write packet sizes

111system.physmem.writePktSize::6 57461 # categorize write packet sizes

123system.physmem.writePktSize::6 57463 # categorize write packet sizes

112system.physmem.writePktSize::7 0 # categorize write packet sizes
113system.physmem.writePktSize::8 0 # categorize write packet sizes
114system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
115system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
116system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
117system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
118system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
119system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
120system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
121system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
122system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

124system.physmem.writePktSize::7 0 # categorize write packet sizes
125system.physmem.writePktSize::8 0 # categorize write packet sizes
126system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
127system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
128system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
129system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
130system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
131system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
132system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
133system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
134system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

123system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see

135system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see

140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see

152system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see

156system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see

168system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see

160system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see

172system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see

172system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see

184system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see

174system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see

186system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see

179system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see

191system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see

183system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

195system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

189system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays
190system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests
191system.physmem.totBusLat 61975012000 # Total cycles spent in databus access
192system.physmem.totBankLat 216185438000 # Total cycles spent in bank access
193system.physmem.avgQLat 242.04 # Average queueing delay per request
194system.physmem.avgBankLat 13953.07 # Average bank access latency per request

201system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays
202system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests
203system.physmem.totBusLat 61975036000 # Total cycles spent in databus access
204system.physmem.totBankLat 16863224000 # Total cycles spent in bank access
205system.physmem.avgQLat 18619.82 # Average queueing delay per request
206system.physmem.avgBankLat 1088.39 # Average bank access latency per request

195system.physmem.avgBusLat 4000.00 # Average bus latency per request

207system.physmem.avgBusLat 4000.00 # Average bus latency per request

196system.physmem.avgMemAccLat 18195.12 # Average memory access latency

208system.physmem.avgMemAccLat 23708.21 # Average memory access latency

197system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
198system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
199system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
200system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
201system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
202system.physmem.busUtil 2.51 # Data bus utilization in percentage

209system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
210system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
211system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
212system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
213system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
214system.physmem.busUtil 2.51 # Data bus utilization in percentage

203system.physmem.avgRdQLen 0.11 # Average read queue length over time
204system.physmem.avgWrQLen 12.38 # Average write queue length over time
205system.physmem.readRowHits 15449450 # Number of row buffer hits during reads
206system.physmem.writeRowHits 784611 # Number of row buffer hits during writes
207system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
208system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
209system.physmem.avgGap 159677.46 # Average gap between requests
210system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
211system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
212system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
213system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
214system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
215system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
216system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
217system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
218system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
219system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
220system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
221system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)

215system.physmem.avgRdQLen 0.14 # Average read queue length over time
216system.physmem.avgWrQLen 12.40 # Average write queue length over time
217system.physmem.readRowHits 15451886 # Number of row buffer hits during reads
218system.physmem.writeRowHits 785061 # Number of row buffer hits during writes
219system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
220system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes
221system.physmem.avgGap 159677.30 # Average gap between requests

222system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
223system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
224system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
225system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
226system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
227system.cf0.dma_write_txs 0 # Number of DMA write transactions.
228system.cpu.dtb.inst_hits 0 # ITB inst hits
229system.cpu.dtb.inst_misses 0 # ITB inst misses

230system.cpu.dtb.read_hits 14995523 # DTB read hits
231system.cpu.dtb.read_misses 7332 # DTB read misses
232system.cpu.dtb.write_hits 11230789 # DTB write hits

230system.cpu.dtb.read_hits 14995645 # DTB read hits
231system.cpu.dtb.read_misses 7331 # DTB read misses
232system.cpu.dtb.write_hits 11230857 # DTB write hits

233system.cpu.dtb.write_misses 2203 # DTB write misses
234system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
235system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
236system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
237system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
238system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB
239system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
240system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
241system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
242system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions

243system.cpu.dtb.read_accesses 15002855 # DTB read accesses
244system.cpu.dtb.write_accesses 11232992 # DTB write accesses

243system.cpu.dtb.read_accesses 15002976 # DTB read accesses
244system.cpu.dtb.write_accesses 11233060 # DTB write accesses

245system.cpu.dtb.inst_accesses 0 # ITB inst accesses

246system.cpu.dtb.hits 26226312 # DTB hits
247system.cpu.dtb.misses 9535 # DTB misses
248system.cpu.dtb.accesses 26235847 # DTB accesses
249system.cpu.itb.inst_hits 61491068 # ITB inst hits

246system.cpu.dtb.hits 26226502 # DTB hits
247system.cpu.dtb.misses 9534 # DTB misses
248system.cpu.dtb.accesses 26236036 # DTB accesses
249system.cpu.itb.inst_hits 61491397 # ITB inst hits

250system.cpu.itb.inst_misses 4471 # ITB inst misses
251system.cpu.itb.read_hits 0 # DTB read hits
252system.cpu.itb.read_misses 0 # DTB read misses
253system.cpu.itb.write_hits 0 # DTB write hits
254system.cpu.itb.write_misses 0 # DTB write misses
255system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
256system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
257system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
258system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
259system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
260system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
261system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
262system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
263system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
264system.cpu.itb.read_accesses 0 # DTB read accesses
265system.cpu.itb.write_accesses 0 # DTB write accesses

266system.cpu.itb.inst_accesses 61495539 # ITB inst accesses
267system.cpu.itb.hits 61491068 # DTB hits

266system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
267system.cpu.itb.hits 61491397 # DTB hits

268system.cpu.itb.misses 4471 # DTB misses

269system.cpu.itb.accesses 61495539 # DTB accesses
270system.cpu.numCycles 5207272152 # number of cpu cycles simulated

269system.cpu.itb.accesses 61495868 # DTB accesses
270system.cpu.numCycles 5207269388 # number of cpu cycles simulated

271system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
272system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

273system.cpu.committedInsts 60197128 # Number of instructions committed
274system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed
275system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses

273system.cpu.committedInsts 60197457 # Number of instructions committed
274system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
275system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses

276system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses

277system.cpu.num_func_calls 2139710 # number of times a function call or return occured
278system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls
279system.cpu.num_int_insts 68867725 # number of integer instructions

277system.cpu.num_func_calls 2139722 # number of times a function call or return occured
278system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls
279system.cpu.num_int_insts 68868122 # number of integer instructions

280system.cpu.num_fp_insts 10269 # number of float instructions

281system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read
282system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written

281system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
282system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written

283system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
284system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written

285system.cpu.num_mem_refs 27393681 # number of memory refs
286system.cpu.num_load_insts 15659530 # Number of load instructions
287system.cpu.num_store_insts 11734151 # Number of store instructions
288system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles
289system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles
290system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles
291system.cpu.idle_fraction 0.879363 # Percentage of idle cycles

285system.cpu.num_mem_refs 27393871 # number of memory refs
286system.cpu.num_load_insts 15659652 # Number of load instructions
287system.cpu.num_store_insts 11734219 # Number of store instructions
288system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles
289system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles
290system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles
291system.cpu.idle_fraction 0.879373 # Percentage of idle cycles

292system.cpu.kern.inst.arm 0 # number of arm instructions executed
293system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed

294system.cpu.icache.replacements 855500 # number of replacements
295system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use
296system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks.
297system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks.
298system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks.

294system.cpu.icache.replacements 855485 # number of replacements
295system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use
296system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks.
297system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks.
298system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks.

299system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit.

300system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor

300system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor

301system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy
302system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy

303system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits
304system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits
305system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits
306system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits
307system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits
308system.cpu.icache.overall_hits::total 60635056 # number of overall hits
309system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses
310system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses
311system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses
312system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses
313system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses
314system.cpu.icache.overall_misses::total 856012 # number of overall misses
315system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles
316system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles
317system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles
318system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles
319system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles
320system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles
321system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses)
322system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses)
323system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses
324system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses
325system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses
326system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses

303system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits
304system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits
305system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits
306system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits
307system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits
308system.cpu.icache.overall_hits::total 60635400 # number of overall hits
309system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses
310system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses
311system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses
312system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses
313system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses
314system.cpu.icache.overall_misses::total 855997 # number of overall misses
315system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles
316system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles
317system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles
318system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles
319system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles
320system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles
321system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses)
322system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses)
323system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses
324system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses
325system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses
326system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses

327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses
328system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses
329system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses
330system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses
331system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses
332system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses

333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency
334system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency
335system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
336system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency
337system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
338system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency

333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency
334system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency
335system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
336system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency
337system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
338system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency

339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
345system.cpu.icache.fast_writes 0 # number of fast writes performed
346system.cpu.icache.cache_copies 0 # number of cache copies performed

347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses
348system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses
349system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses
350system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses
351system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses
352system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses
353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles
354system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles
355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles
356system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles
357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles
358system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles

347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses
348system.cpu.icache.ReadReq_mshr_misses::total 855997 # number of ReadReq MSHR misses
349system.cpu.icache.demand_mshr_misses::cpu.inst 855997 # number of demand (read+write) MSHR misses
350system.cpu.icache.demand_mshr_misses::total 855997 # number of demand (read+write) MSHR misses
351system.cpu.icache.overall_mshr_misses::cpu.inst 855997 # number of overall MSHR misses
352system.cpu.icache.overall_mshr_misses::total 855997 # number of overall MSHR misses
353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles
354system.cpu.icache.ReadReq_mshr_miss_latency::total 9827690000 # number of ReadReq MSHR miss cycles
355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9827690000 # number of demand (read+write) MSHR miss cycles
356system.cpu.icache.demand_mshr_miss_latency::total 9827690000 # number of demand (read+write) MSHR miss cycles
357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9827690000 # number of overall MSHR miss cycles
358system.cpu.icache.overall_mshr_miss_latency::total 9827690000 # number of overall MSHR miss cycles

359system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles
360system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles
361system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles
362system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles
363system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses
364system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses
365system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses
366system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses
367system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses
368system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses

369system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency
370system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency
371system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
372system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
373system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
374system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency

369system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11480.986499 # average ReadReq mshr miss latency
370system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11480.986499 # average ReadReq mshr miss latency
371system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
372system.cpu.icache.demand_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency
373system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
374system.cpu.icache.overall_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency

375system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
376system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
377system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
378system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

380system.cpu.dcache.replacements 627255 # number of replacements
381system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use
382system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks.
383system.cpu.dcache.sampled_refs 627767 # Sample count of references to valid blocks.
384system.cpu.dcache.avg_refs 37.680956 # Average number of references to valid blocks.
385system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
386system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor
387system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy
388system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
389system.cpu.dcache.ReadReq_hits::cpu.data 13195024 # number of ReadReq hits
390system.cpu.dcache.ReadReq_hits::total 13195024 # number of ReadReq hits
391system.cpu.dcache.WriteReq_hits::cpu.data 9972994 # number of WriteReq hits
392system.cpu.dcache.WriteReq_hits::total 9972994 # number of WriteReq hits
393system.cpu.dcache.LoadLockedReq_hits::cpu.data 236273 # number of LoadLockedReq hits
394system.cpu.dcache.LoadLockedReq_hits::total 236273 # number of LoadLockedReq hits
395system.cpu.dcache.StoreCondReq_hits::cpu.data 247672 # number of StoreCondReq hits
396system.cpu.dcache.StoreCondReq_hits::total 247672 # number of StoreCondReq hits
397system.cpu.dcache.demand_hits::cpu.data 23168018 # number of demand (read+write) hits
398system.cpu.dcache.demand_hits::total 23168018 # number of demand (read+write) hits
399system.cpu.dcache.overall_hits::cpu.data 23168018 # number of overall hits
400system.cpu.dcache.overall_hits::total 23168018 # number of overall hits
401system.cpu.dcache.ReadReq_misses::cpu.data 368763 # number of ReadReq misses
402system.cpu.dcache.ReadReq_misses::total 368763 # number of ReadReq misses
403system.cpu.dcache.WriteReq_misses::cpu.data 250502 # number of WriteReq misses
404system.cpu.dcache.WriteReq_misses::total 250502 # number of WriteReq misses
405system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses
406system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses
407system.cpu.dcache.demand_misses::cpu.data 619265 # number of demand (read+write) misses
408system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses
409system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses
410system.cpu.dcache.overall_misses::total 619265 # number of overall misses
411system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205933000 # number of ReadReq miss cycles
412system.cpu.dcache.ReadReq_miss_latency::total 5205933000 # number of ReadReq miss cycles
413system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061519000 # number of WriteReq miss cycles
414system.cpu.dcache.WriteReq_miss_latency::total 8061519000 # number of WriteReq miss cycles
415system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154593000 # number of LoadLockedReq miss cycles
416system.cpu.dcache.LoadLockedReq_miss_latency::total 154593000 # number of LoadLockedReq miss cycles
417system.cpu.dcache.demand_miss_latency::cpu.data 13267452000 # number of demand (read+write) miss cycles
418system.cpu.dcache.demand_miss_latency::total 13267452000 # number of demand (read+write) miss cycles
419system.cpu.dcache.overall_miss_latency::cpu.data 13267452000 # number of overall miss cycles
420system.cpu.dcache.overall_miss_latency::total 13267452000 # number of overall miss cycles
421system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses)
422system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses)
423system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses)
424system.cpu.dcache.WriteReq_accesses::total 10223496 # number of WriteReq accesses(hits+misses)
425system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247673 # number of LoadLockedReq accesses(hits+misses)
426system.cpu.dcache.LoadLockedReq_accesses::total 247673 # number of LoadLockedReq accesses(hits+misses)
427system.cpu.dcache.StoreCondReq_accesses::cpu.data 247672 # number of StoreCondReq accesses(hits+misses)
428system.cpu.dcache.StoreCondReq_accesses::total 247672 # number of StoreCondReq accesses(hits+misses)
429system.cpu.dcache.demand_accesses::cpu.data 23787283 # number of demand (read+write) accesses
430system.cpu.dcache.demand_accesses::total 23787283 # number of demand (read+write) accesses
431system.cpu.dcache.overall_accesses::cpu.data 23787283 # number of overall (read+write) accesses
432system.cpu.dcache.overall_accesses::total 23787283 # number of overall (read+write) accesses
433system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027187 # miss rate for ReadReq accesses
434system.cpu.dcache.ReadReq_miss_rate::total 0.027187 # miss rate for ReadReq accesses
435system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
436system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
437system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046028 # miss rate for LoadLockedReq accesses
438system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046028 # miss rate for LoadLockedReq accesses
439system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses
440system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses
441system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses
442system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses
443system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14117.286713 # average ReadReq miss latency
444system.cpu.dcache.ReadReq_avg_miss_latency::total 14117.286713 # average ReadReq miss latency
445system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.455637 # average WriteReq miss latency
446system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.455637 # average WriteReq miss latency
447system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.789474 # average LoadLockedReq miss latency
448system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.789474 # average LoadLockedReq miss latency
449system.cpu.dcache.demand_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
450system.cpu.dcache.demand_avg_miss_latency::total 21424.514545 # average overall miss latency
451system.cpu.dcache.overall_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
452system.cpu.dcache.overall_avg_miss_latency::total 21424.514545 # average overall miss latency
453system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
454system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
455system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
456system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
457system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
458system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
459system.cpu.dcache.fast_writes 0 # number of fast writes performed
460system.cpu.dcache.cache_copies 0 # number of cache copies performed
461system.cpu.dcache.writebacks::writebacks 596013 # number of writebacks
462system.cpu.dcache.writebacks::total 596013 # number of writebacks
463system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368763 # number of ReadReq MSHR misses
464system.cpu.dcache.ReadReq_mshr_misses::total 368763 # number of ReadReq MSHR misses
465system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250502 # number of WriteReq MSHR misses
466system.cpu.dcache.WriteReq_mshr_misses::total 250502 # number of WriteReq MSHR misses
467system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses
468system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses
469system.cpu.dcache.demand_mshr_misses::cpu.data 619265 # number of demand (read+write) MSHR misses
470system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses
471system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses
472system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses
473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468407000 # number of ReadReq MSHR miss cycles
474system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468407000 # number of ReadReq MSHR miss cycles
475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560515000 # number of WriteReq MSHR miss cycles
476system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560515000 # number of WriteReq MSHR miss cycles
477system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131793000 # number of LoadLockedReq MSHR miss cycles
478system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131793000 # number of LoadLockedReq MSHR miss cycles
479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028922000 # number of demand (read+write) MSHR miss cycles
480system.cpu.dcache.demand_mshr_miss_latency::total 12028922000 # number of demand (read+write) MSHR miss cycles
481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028922000 # number of overall MSHR miss cycles
482system.cpu.dcache.overall_mshr_miss_latency::total 12028922000 # number of overall MSHR miss cycles
483system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182088074500 # number of ReadReq MSHR uncacheable cycles
484system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182088074500 # number of ReadReq MSHR uncacheable cycles
485system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708050000 # number of WriteReq MSHR uncacheable cycles
486system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708050000 # number of WriteReq MSHR uncacheable cycles
487system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200796124500 # number of overall MSHR uncacheable cycles
488system.cpu.dcache.overall_mshr_uncacheable_latency::total 200796124500 # number of overall MSHR uncacheable cycles
489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses
490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses
491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
493system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses
494system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # mshr miss rate for LoadLockedReq accesses
495system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses
496system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses
497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses
498system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses
499system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12117.286713 # average ReadReq mshr miss latency
500system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12117.286713 # average ReadReq mshr miss latency
501system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.455637 # average WriteReq mshr miss latency
502system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.455637 # average WriteReq mshr miss latency
503system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11560.789474 # average LoadLockedReq mshr miss latency
504system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11560.789474 # average LoadLockedReq mshr miss latency
505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
506system.cpu.dcache.demand_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
508system.cpu.dcache.overall_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
509system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
510system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
511system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
512system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
513system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
514system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
516system.cpu.l2cache.replacements 61906 # number of replacements
517system.cpu.l2cache.tagsinuse 50893.840705 # Cycle average of tags in use
518system.cpu.l2cache.total_refs 1682733 # Total number of references to valid blocks.
519system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks.
520system.cpu.l2cache.avg_refs 13.219887 # Average number of references to valid blocks.
521system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit.
522system.cpu.l2cache.occ_blocks::writebacks 37868.665520 # Average occupied blocks per requestor

380system.cpu.l2cache.replacements 61912 # number of replacements
381system.cpu.l2cache.tagsinuse 50893.937876 # Cycle average of tags in use
382system.cpu.l2cache.total_refs 1682687 # Total number of references to valid blocks.
383system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks.
384system.cpu.l2cache.avg_refs 13.219007 # Average number of references to valid blocks.
385system.cpu.l2cache.warmup_cycle 2553095791000 # Cycle when the warmup percentage was hit.
386system.cpu.l2cache.occ_blocks::writebacks 37868.725267 # Average occupied blocks per requestor

523system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor
524system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor

387system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor
388system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor

525system.cpu.l2cache.occ_blocks::cpu.inst 6995.476581 # Average occupied blocks per requestor
526system.cpu.l2cache.occ_blocks::cpu.data 6025.811619 # Average occupied blocks per requestor
527system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy

389system.cpu.l2cache.occ_blocks::cpu.inst 6995.530011 # Average occupied blocks per requestor
390system.cpu.l2cache.occ_blocks::cpu.data 6025.795614 # Average occupied blocks per requestor
391system.cpu.l2cache.occ_percent::writebacks 0.577831 # Average percentage of cache occupancy

528system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
529system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
530system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy

392system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
393system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
394system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy

531system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Average percentage of cache occupancy
532system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy
533system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits

395system.cpu.l2cache.occ_percent::cpu.data 0.091946 # Average percentage of cache occupancy
396system.cpu.l2cache.occ_percent::total 0.776580 # Average percentage of cache occupancy
397system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8699 # number of ReadReq hits

534system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits

398system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits

535system.cpu.l2cache.ReadReq_hits::cpu.inst 843788 # number of ReadReq hits
536system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits
537system.cpu.l2cache.ReadReq_hits::total 1226343 # number of ReadReq hits
538system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits
539system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits

399system.cpu.l2cache.ReadReq_hits::cpu.inst 843755 # number of ReadReq hits
400system.cpu.l2cache.ReadReq_hits::cpu.data 370324 # number of ReadReq hits
401system.cpu.l2cache.ReadReq_hits::total 1226326 # number of ReadReq hits
402system.cpu.l2cache.Writeback_hits::writebacks 596029 # number of Writeback hits
403system.cpu.l2cache.Writeback_hits::total 596029 # number of Writeback hits

540system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
541system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits

404system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
405system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits

542system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # number of ReadExReq hits
543system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits
544system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits

406system.cpu.l2cache.ReadExReq_hits::cpu.data 114426 # number of ReadExReq hits
407system.cpu.l2cache.ReadExReq_hits::total 114426 # number of ReadExReq hits
408system.cpu.l2cache.demand_hits::cpu.dtb.walker 8699 # number of demand (read+write) hits

545system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits

409system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits

546system.cpu.l2cache.demand_hits::cpu.inst 843788 # number of demand (read+write) hits
547system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits
548system.cpu.l2cache.demand_hits::total 1340761 # number of demand (read+write) hits
549system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits

410system.cpu.l2cache.demand_hits::cpu.inst 843755 # number of demand (read+write) hits
411system.cpu.l2cache.demand_hits::cpu.data 484750 # number of demand (read+write) hits
412system.cpu.l2cache.demand_hits::total 1340752 # number of demand (read+write) hits
413system.cpu.l2cache.overall_hits::cpu.dtb.walker 8699 # number of overall hits

550system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits

414system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits

551system.cpu.l2cache.overall_hits::cpu.inst 843788 # number of overall hits
552system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits
553system.cpu.l2cache.overall_hits::total 1340761 # number of overall hits

415system.cpu.l2cache.overall_hits::cpu.inst 843755 # number of overall hits
416system.cpu.l2cache.overall_hits::cpu.data 484750 # number of overall hits
417system.cpu.l2cache.overall_hits::total 1340752 # number of overall hits

554system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
555system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses

418system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
419system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses

556system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses
557system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses
558system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses
559system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses
560system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses
561system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
562system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses

420system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
421system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses
422system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses
423system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses
424system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
425system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses
426system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses

563system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
564system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses

427system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
428system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses

565system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses
566system.cpu.l2cache.demand_misses::cpu.data 143044 # number of demand (read+write) misses
567system.cpu.l2cache.demand_misses::total 153651 # number of demand (read+write) misses

429system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
430system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses
431system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses

568system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
569system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses

432system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
433system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses

570system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses
571system.cpu.l2cache.overall_misses::cpu.data 143044 # number of overall misses
572system.cpu.l2cache.overall_misses::total 153651 # number of overall misses

434system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
435system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses
436system.cpu.l2cache.overall_misses::total 153654 # number of overall misses

573system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles
574system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles

437system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles
438system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles

575system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 536335000 # number of ReadReq miss cycles
576system.cpu.l2cache.ReadReq_miss_latency::cpu.data 516987000 # number of ReadReq miss cycles
577system.cpu.l2cache.ReadReq_miss_latency::total 1053746500 # number of ReadReq miss cycles
578system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles
579system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles
580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102367500 # number of ReadExReq miss cycles
581system.cpu.l2cache.ReadExReq_miss_latency::total 6102367500 # number of ReadExReq miss cycles

439system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 532505000 # number of ReadReq miss cycles
440system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512702000 # number of ReadReq miss cycles
441system.cpu.l2cache.ReadReq_miss_latency::total 1045631500 # number of ReadReq miss cycles
442system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 461000 # number of UpgradeReq miss cycles
443system.cpu.l2cache.UpgradeReq_miss_latency::total 461000 # number of UpgradeReq miss cycles
444system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6086440000 # number of ReadExReq miss cycles
445system.cpu.l2cache.ReadExReq_miss_latency::total 6086440000 # number of ReadExReq miss cycles

582system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles
583system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles

446system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles
447system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles

584system.cpu.l2cache.demand_miss_latency::cpu.inst 536335000 # number of demand (read+write) miss cycles
585system.cpu.l2cache.demand_miss_latency::cpu.data 6619354500 # number of demand (read+write) miss cycles
586system.cpu.l2cache.demand_miss_latency::total 7156114000 # number of demand (read+write) miss cycles

448system.cpu.l2cache.demand_miss_latency::cpu.inst 532505000 # number of demand (read+write) miss cycles
449system.cpu.l2cache.demand_miss_latency::cpu.data 6599142000 # number of demand (read+write) miss cycles
450system.cpu.l2cache.demand_miss_latency::total 7132071500 # number of demand (read+write) miss cycles

587system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles
588system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles

451system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles
452system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles

589system.cpu.l2cache.overall_miss_latency::cpu.inst 536335000 # number of overall miss cycles
590system.cpu.l2cache.overall_miss_latency::cpu.data 6619354500 # number of overall miss cycles
591system.cpu.l2cache.overall_miss_latency::total 7156114000 # number of overall miss cycles
592system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses)

453system.cpu.l2cache.overall_miss_latency::cpu.inst 532505000 # number of overall miss cycles
454system.cpu.l2cache.overall_miss_latency::cpu.data 6599142000 # number of overall miss cycles
455system.cpu.l2cache.overall_miss_latency::total 7132071500 # number of overall miss cycles
456system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8704 # number of ReadReq accesses(hits+misses)

593system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)

457system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)

594system.cpu.l2cache.ReadReq_accesses::cpu.inst 854387 # number of ReadReq accesses(hits+misses)
595system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses)
596system.cpu.l2cache.ReadReq_accesses::total 1246808 # number of ReadReq accesses(hits+misses)
597system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses)
598system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses)
599system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses)
600system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses)
601system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604 # number of ReadExReq accesses(hits+misses)
602system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses)
603system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses

458system.cpu.l2cache.ReadReq_accesses::cpu.inst 854359 # number of ReadReq accesses(hits+misses)
459system.cpu.l2cache.ReadReq_accesses::cpu.data 380183 # number of ReadReq accesses(hits+misses)
460system.cpu.l2cache.ReadReq_accesses::total 1246797 # number of ReadReq accesses(hits+misses)
461system.cpu.l2cache.Writeback_accesses::writebacks 596029 # number of Writeback accesses(hits+misses)
462system.cpu.l2cache.Writeback_accesses::total 596029 # number of Writeback accesses(hits+misses)
463system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses)
464system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
465system.cpu.l2cache.ReadExReq_accesses::cpu.data 247609 # number of ReadExReq accesses(hits+misses)
466system.cpu.l2cache.ReadExReq_accesses::total 247609 # number of ReadExReq accesses(hits+misses)
467system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8704 # number of demand (read+write) accesses

604system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses

468system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses

605system.cpu.l2cache.demand_accesses::cpu.inst 854387 # number of demand (read+write) accesses
606system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses
607system.cpu.l2cache.demand_accesses::total 1494412 # number of demand (read+write) accesses
608system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses

469system.cpu.l2cache.demand_accesses::cpu.inst 854359 # number of demand (read+write) accesses
470system.cpu.l2cache.demand_accesses::cpu.data 627792 # number of demand (read+write) accesses
471system.cpu.l2cache.demand_accesses::total 1494406 # number of demand (read+write) accesses
472system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8704 # number of overall (read+write) accesses

609system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses

473system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses

610system.cpu.l2cache.overall_accesses::cpu.inst 854387 # number of overall (read+write) accesses
611system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses
612system.cpu.l2cache.overall_accesses::total 1494412 # number of overall (read+write) accesses

474system.cpu.l2cache.overall_accesses::cpu.inst 854359 # number of overall (read+write) accesses
475system.cpu.l2cache.overall_accesses::cpu.data 627792 # number of overall (read+write) accesses
476system.cpu.l2cache.overall_accesses::total 1494406 # number of overall (read+write) accesses

613system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
614system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses

477system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
478system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses

615system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses
616system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025931 # miss rate for ReadReq accesses
617system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
618system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses
619system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses
620system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537899 # miss rate for ReadExReq accesses
621system.cpu.l2cache.ReadExReq_miss_rate::total 0.537899 # miss rate for ReadExReq accesses

479system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses
480system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses
481system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses
482system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses
483system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses
484system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537876 # miss rate for ReadExReq accesses
485system.cpu.l2cache.ReadExReq_miss_rate::total 0.537876 # miss rate for ReadExReq accesses

622system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
623system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses

486system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
487system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses

624system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012405 # miss rate for demand accesses
625system.cpu.l2cache.demand_miss_rate::cpu.data 0.227862 # miss rate for demand accesses
626system.cpu.l2cache.demand_miss_rate::total 0.102817 # miss rate for demand accesses

488system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses
489system.cpu.l2cache.demand_miss_rate::cpu.data 0.227849 # miss rate for demand accesses
490system.cpu.l2cache.demand_miss_rate::total 0.102819 # miss rate for demand accesses

627system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
628system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses

491system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
492system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses

629system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012405 # miss rate for overall accesses
630system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862 # miss rate for overall accesses
631system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses

493system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses
494system.cpu.l2cache.overall_miss_rate::cpu.data 0.227849 # miss rate for overall accesses
495system.cpu.l2cache.overall_miss_rate::total 0.102819 # miss rate for overall accesses

632system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency
633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency

496system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency
497system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency

634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50602.415322 # average ReadReq miss latency
635system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52443.396226 # average ReadReq miss latency
636system.cpu.l2cache.ReadReq_avg_miss_latency::total 51490.178353 # average ReadReq miss latency
637system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency
638system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency
639system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45818.385566 # average ReadExReq miss latency
640system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45818.385566 # average ReadExReq miss latency

498system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50217.370803 # average ReadReq miss latency
499system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52003.448626 # average ReadReq miss latency
500system.cpu.l2cache.ReadReq_avg_miss_latency::total 51078.672268 # average ReadReq miss latency
501system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.347826 # average UpgradeReq miss latency
502system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.347826 # average UpgradeReq miss latency
503system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45699.826554 # average ReadExReq miss latency
504system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45699.826554 # average ReadExReq miss latency

641system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
642system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency

505system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
506system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency

643system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
644system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
645system.cpu.l2cache.demand_avg_miss_latency::total 46573.819891 # average overall miss latency

507system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency
508system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency
509system.cpu.l2cache.demand_avg_miss_latency::total 46416.438882 # average overall miss latency

646system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
647system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency

510system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
511system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency

648system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
649system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
650system.cpu.l2cache.overall_avg_miss_latency::total 46573.819891 # average overall miss latency

512system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency
513system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency
514system.cpu.l2cache.overall_avg_miss_latency::total 46416.438882 # average overall miss latency

651system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
652system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
653system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
654system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
655system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
656system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
657system.cpu.l2cache.fast_writes 0 # number of fast writes performed
658system.cpu.l2cache.cache_copies 0 # number of cache copies performed

515system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
516system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
517system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
518system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
519system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
520system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
521system.cpu.l2cache.fast_writes 0 # number of fast writes performed
522system.cpu.l2cache.cache_copies 0 # number of cache copies performed

659system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks
660system.cpu.l2cache.writebacks::total 57461 # number of writebacks

523system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks
524system.cpu.l2cache.writebacks::total 57463 # number of writebacks

661system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
662system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses

525system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
526system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses

663system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses
664system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses
665system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses
666system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses
667system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses
668system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
669system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses

527system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses
528system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses
529system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses
530system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses
531system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses
532system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses
533system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses

670system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
671system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses

534system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
535system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses

672system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses
673system.cpu.l2cache.demand_mshr_misses::cpu.data 143044 # number of demand (read+write) MSHR misses
674system.cpu.l2cache.demand_mshr_misses::total 153651 # number of demand (read+write) MSHR misses

536system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses
537system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses
538system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses

675system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
676system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses

539system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
540system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses

677system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses
678system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 # number of overall MSHR misses
679system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses

541system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses
542system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses
543system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses

680system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles
681system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles

544system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles
545system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles

682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398671075 # number of ReadReq MSHR miss cycles
683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 388940100 # number of ReadReq MSHR miss cycles
684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 787933191 # number of ReadReq MSHR miss cycles
685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28807316 # number of UpgradeReq MSHR miss cycles
686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28807316 # number of UpgradeReq MSHR miss cycles
687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371975723 # number of ReadExReq MSHR miss cycles
688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371975723 # number of ReadExReq MSHR miss cycles

546system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 394778574 # number of ReadReq MSHR miss cycles
547system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 384642089 # number of ReadReq MSHR miss cycles
548system.cpu.l2cache.ReadReq_mshr_miss_latency::total 779742679 # number of ReadReq MSHR miss cycles
549system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28851319 # number of UpgradeReq MSHR miss cycles
550system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28851319 # number of UpgradeReq MSHR miss cycles
551system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4356126157 # number of ReadExReq MSHR miss cycles
552system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4356126157 # number of ReadExReq MSHR miss cycles

689system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles
690system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles

553system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles
554system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles

691system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398671075 # number of demand (read+write) MSHR miss cycles
692system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4760915823 # number of demand (read+write) MSHR miss cycles
693system.cpu.l2cache.demand_mshr_miss_latency::total 5159908914 # number of demand (read+write) MSHR miss cycles

555system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 394778574 # number of demand (read+write) MSHR miss cycles
556system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4740768246 # number of demand (read+write) MSHR miss cycles
557system.cpu.l2cache.demand_mshr_miss_latency::total 5135868836 # number of demand (read+write) MSHR miss cycles

694system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles
695system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles

558system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles
559system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles

696system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398671075 # number of overall MSHR miss cycles
697system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4760915823 # number of overall MSHR miss cycles
698system.cpu.l2cache.overall_mshr_miss_latency::total 5159908914 # number of overall MSHR miss cycles

560system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 394778574 # number of overall MSHR miss cycles
561system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4740768246 # number of overall MSHR miss cycles
562system.cpu.l2cache.overall_mshr_miss_latency::total 5135868836 # number of overall MSHR miss cycles

699system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles

563system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles

700system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166694484565 # number of ReadReq MSHR uncacheable cycles
701system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166891951116 # number of ReadReq MSHR uncacheable cycles
702system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175103106 # number of WriteReq MSHR uncacheable cycles
703system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175103106 # number of WriteReq MSHR uncacheable cycles

564system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166684815565 # number of ReadReq MSHR uncacheable cycles
565system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166882282116 # number of ReadReq MSHR uncacheable cycles
566system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9180297506 # number of WriteReq MSHR uncacheable cycles
567system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9180297506 # number of WriteReq MSHR uncacheable cycles

704system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles

568system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles

705system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles
706system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles

569system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175865113071 # number of overall MSHR uncacheable cycles
570system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176062579622 # number of overall MSHR uncacheable cycles

707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
708system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses

571system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
572system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses

709system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses
710system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses
711system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses
712system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses
713system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses
714system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses
715system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses

573system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses
574system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses
575system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses
576system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses
577system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses
578system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537876 # mshr miss rate for ReadExReq accesses
579system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537876 # mshr miss rate for ReadExReq accesses

716system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
717system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses

580system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
581system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses

718system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses
719system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses
720system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses

582system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::total 0.102819 # mshr miss rate for demand accesses

721system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
722system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses

585system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses

723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses
724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses
725system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses

587system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses
588system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for overall accesses
589system.cpu.l2cache.overall_mshr_miss_rate::total 0.102819 # mshr miss rate for overall accesses

726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency
727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency

590system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency
591system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency

728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37614.027267 # average ReadReq mshr miss latency
729system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39454.260499 # average ReadReq mshr miss latency
730system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38501.499682 # average ReadReq mshr miss latency
731system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.402507 # average UpgradeReq mshr miss latency
732system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.402507 # average UpgradeReq mshr miss latency
733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32826.090753 # average ReadExReq mshr miss latency
734system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32826.090753 # average ReadExReq mshr miss latency

592system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37229.212939 # average ReadReq mshr miss latency
593system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39014.310681 # average ReadReq mshr miss latency
594system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38090.111817 # average ReadReq mshr miss latency
595system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10035.241391 # average UpgradeReq mshr miss latency
596system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10035.241391 # average UpgradeReq mshr miss latency
597system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32707.824249 # average ReadExReq mshr miss latency
598system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32707.824249 # average ReadExReq mshr miss latency

735system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
736system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency

599system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
600system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency

737system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
739system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency

601system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency
602system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency
603system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency

740system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency

604system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
605system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency

742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency

606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency
607system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency
608system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency

745system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
746system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
747system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
748system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
749system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
750system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
751system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
752system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
753system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

609system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
610system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
611system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
612system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
613system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
614system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
615system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
616system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
617system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

618system.cpu.dcache.replacements 627280 # number of replacements
619system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use
620system.cpu.dcache.total_refs 23655026 # Total number of references to valid blocks.
621system.cpu.dcache.sampled_refs 627792 # Sample count of references to valid blocks.
622system.cpu.dcache.avg_refs 37.679719 # Average number of references to valid blocks.
623system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
624system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor
625system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy
626system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
627system.cpu.dcache.ReadReq_hits::cpu.data 13195122 # number of ReadReq hits
628system.cpu.dcache.ReadReq_hits::total 13195122 # number of ReadReq hits
629system.cpu.dcache.WriteReq_hits::cpu.data 9973048 # number of WriteReq hits
630system.cpu.dcache.WriteReq_hits::total 9973048 # number of WriteReq hits
631system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits
632system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits
633system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits
634system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits
635system.cpu.dcache.demand_hits::cpu.data 23168170 # number of demand (read+write) hits
636system.cpu.dcache.demand_hits::total 23168170 # number of demand (read+write) hits
637system.cpu.dcache.overall_hits::cpu.data 23168170 # number of overall hits
638system.cpu.dcache.overall_hits::total 23168170 # number of overall hits
639system.cpu.dcache.ReadReq_misses::cpu.data 368781 # number of ReadReq misses
640system.cpu.dcache.ReadReq_misses::total 368781 # number of ReadReq misses
641system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses
642system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses
643system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses
644system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses
645system.cpu.dcache.demand_misses::cpu.data 619291 # number of demand (read+write) misses
646system.cpu.dcache.demand_misses::total 619291 # number of demand (read+write) misses
647system.cpu.dcache.overall_misses::cpu.data 619291 # number of overall misses
648system.cpu.dcache.overall_misses::total 619291 # number of overall misses
649system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201704000 # number of ReadReq miss cycles
650system.cpu.dcache.ReadReq_miss_latency::total 5201704000 # number of ReadReq miss cycles
651system.cpu.dcache.WriteReq_miss_latency::cpu.data 8045775500 # number of WriteReq miss cycles
652system.cpu.dcache.WriteReq_miss_latency::total 8045775500 # number of WriteReq miss cycles
653system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154787000 # number of LoadLockedReq miss cycles
654system.cpu.dcache.LoadLockedReq_miss_latency::total 154787000 # number of LoadLockedReq miss cycles
655system.cpu.dcache.demand_miss_latency::cpu.data 13247479500 # number of demand (read+write) miss cycles
656system.cpu.dcache.demand_miss_latency::total 13247479500 # number of demand (read+write) miss cycles
657system.cpu.dcache.overall_miss_latency::cpu.data 13247479500 # number of overall miss cycles
658system.cpu.dcache.overall_miss_latency::total 13247479500 # number of overall miss cycles
659system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses)
660system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses)
661system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses)
662system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses)
663system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses)
664system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses)
665system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses)
666system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses)
667system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses
668system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses
669system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses
670system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses
671system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses
672system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses
673system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
674system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
675system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses
676system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses
677system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses
678system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses
679system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses
680system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses
681system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency
682system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency
683system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency
684system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency
685system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency
686system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency
687system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
688system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency
689system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
690system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency
691system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697system.cpu.dcache.fast_writes 0 # number of fast writes performed
698system.cpu.dcache.cache_copies 0 # number of cache copies performed
699system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks
700system.cpu.dcache.writebacks::total 596029 # number of writebacks
701system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses
702system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses
703system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses
704system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
705system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses
706system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses
707system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses
708system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses
709system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses
710system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses
711system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles
712system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles
713system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles
714system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles
715system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles
716system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles
717system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # number of demand (read+write) MSHR miss cycles
718system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles
719system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles
720system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles
721system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles
722system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles
723system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles
724system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles
725system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles
726system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles
727system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses
728system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses
729system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
730system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
731system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses
732system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses
733system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses
734system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses
735system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses
736system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses
737system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency
738system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency
739system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency
740system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency
741system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency
742system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency
743system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
744system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
745system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
746system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
747system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
748system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
749system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
750system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
751system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
752system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
753system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

754system.iocache.replacements 0 # number of replacements
755system.iocache.tagsinuse 0 # Cycle average of tags in use
756system.iocache.total_refs 0 # Total number of references to valid blocks.
757system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
758system.iocache.avg_refs nan # Average number of references to valid blocks.
759system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
760system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
761system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
762system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
763system.iocache.blocked::no_targets 0 # number of cycles access was blocked
764system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
765system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
766system.iocache.fast_writes 0 # number of fast writes performed
767system.iocache.cache_copies 0 # number of cache copies performed

768system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles
769system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles
770system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles
771system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles

768system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles
769system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles
770system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles
771system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles