stats.txt (9312:e05e1b69ebf2) | stats.txt (9314:63e7cfff4188) |
---|---|
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.603636 # Number of seconds simulated 4sim_ticks 2603636076000 # Number of ticks simulated 5final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.603636 # Number of seconds simulated 4sim_ticks 2603636076000 # Number of ticks simulated 5final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 485506 # Simulator instruction rate (inst/s) 8host_op_rate 617798 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20998999798 # Simulator tick rate (ticks/s) | 7host_inst_rate 264193 # Simulator instruction rate (inst/s) 8host_op_rate 336182 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11426847777 # Simulator tick rate (ticks/s) |
10host_mem_usage 395692 # Number of bytes of host memory used | 10host_mem_usage 395692 # Number of bytes of host memory used |
11host_seconds 123.99 # Real time elapsed on the host | 11host_seconds 227.85 # Real time elapsed on the host |
12sim_insts 60197128 # Number of instructions simulated 13sim_ops 76599899 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory --- 95 unchanged lines hidden (view full) --- 115system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 120system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes 121system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 122system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 12sim_insts 60197128 # Number of instructions simulated 13sim_ops 76599899 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory --- 95 unchanged lines hidden (view full) --- 115system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 120system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes 121system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 122system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
123system.physmem.rdQLenPdf::0 15419651 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 56393 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 11796 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 2238 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 1067 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 810 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 393 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 217 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 134 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see | 123system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see |
134system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see | 134system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see |
135system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 74 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 49 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see | 135system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see |
140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 33 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 33 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
189system.physmem.totQLat 3755940486 # Total cycles spent in queuing delays 190system.physmem.totMemAccLat 281915228486 # Sum of mem lat for all requests | 189system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays 190system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests |
191system.physmem.totBusLat 61975012000 # Total cycles spent in databus access | 191system.physmem.totBusLat 61975012000 # Total cycles spent in databus access |
192system.physmem.totBankLat 216184276000 # Total cycles spent in bank access 193system.physmem.avgQLat 242.42 # Average queueing delay per request 194system.physmem.avgBankLat 13953.00 # Average bank access latency per request | 192system.physmem.totBankLat 216185438000 # Total cycles spent in bank access 193system.physmem.avgQLat 242.04 # Average queueing delay per request 194system.physmem.avgBankLat 13953.07 # Average bank access latency per request |
195system.physmem.avgBusLat 4000.00 # Average bus latency per request | 195system.physmem.avgBusLat 4000.00 # Average bus latency per request |
196system.physmem.avgMemAccLat 18195.41 # Average memory access latency | 196system.physmem.avgMemAccLat 18195.12 # Average memory access latency |
197system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s 198system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s 199system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s 200system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 201system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 202system.physmem.busUtil 2.51 # Data bus utilization in percentage 203system.physmem.avgRdQLen 0.11 # Average read queue length over time 204system.physmem.avgWrQLen 12.38 # Average write queue length over time | 197system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s 198system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s 199system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s 200system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 201system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 202system.physmem.busUtil 2.51 # Data bus utilization in percentage 203system.physmem.avgRdQLen 0.11 # Average read queue length over time 204system.physmem.avgWrQLen 12.38 # Average write queue length over time |
205system.physmem.readRowHits 15449465 # Number of row buffer hits during reads | 205system.physmem.readRowHits 15449450 # Number of row buffer hits during reads |
206system.physmem.writeRowHits 784611 # Number of row buffer hits during writes 207system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads 208system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes 209system.physmem.avgGap 159677.46 # Average gap between requests 210system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 211system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 212system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 213system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory --- 66 unchanged lines hidden (view full) --- 280system.cpu.num_fp_insts 10269 # number of float instructions 281system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read 282system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written 283system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 284system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 285system.cpu.num_mem_refs 27393681 # number of memory refs 286system.cpu.num_load_insts 15659530 # Number of load instructions 287system.cpu.num_store_insts 11734151 # Number of store instructions | 206system.physmem.writeRowHits 784611 # Number of row buffer hits during writes 207system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads 208system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes 209system.physmem.avgGap 159677.46 # Average gap between requests 210system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 211system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 212system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 213system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory --- 66 unchanged lines hidden (view full) --- 280system.cpu.num_fp_insts 10269 # number of float instructions 281system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read 282system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written 283system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 284system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 285system.cpu.num_mem_refs 27393681 # number of memory refs 286system.cpu.num_load_insts 15659530 # Number of load instructions 287system.cpu.num_store_insts 11734151 # Number of store instructions |
288system.cpu.num_idle_cycles 4579082960.576241 # Number of idle cycles 289system.cpu.num_busy_cycles 628189191.423759 # Number of busy cycles | 288system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles 289system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles |
290system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles 291system.cpu.idle_fraction 0.879363 # Percentage of idle cycles 292system.cpu.kern.inst.arm 0 # number of arm instructions executed 293system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed | 290system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles 291system.cpu.idle_fraction 0.879363 # Percentage of idle cycles 292system.cpu.kern.inst.arm 0 # number of arm instructions executed 293system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed |
294system.cpu.icache.replacements 855498 # number of replacements | 294system.cpu.icache.replacements 855500 # number of replacements |
295system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use | 295system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use |
296system.cpu.icache.total_refs 60635058 # Total number of references to valid blocks. 297system.cpu.icache.sampled_refs 856010 # Sample count of references to valid blocks. 298system.cpu.icache.avg_refs 70.834521 # Average number of references to valid blocks. | 296system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks. 297system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks. 298system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks. |
299system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. 300system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor 301system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy 302system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy | 299system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. 300system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor 301system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy 302system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy |
303system.cpu.icache.ReadReq_hits::cpu.inst 60635058 # number of ReadReq hits 304system.cpu.icache.ReadReq_hits::total 60635058 # number of ReadReq hits 305system.cpu.icache.demand_hits::cpu.inst 60635058 # number of demand (read+write) hits 306system.cpu.icache.demand_hits::total 60635058 # number of demand (read+write) hits 307system.cpu.icache.overall_hits::cpu.inst 60635058 # number of overall hits 308system.cpu.icache.overall_hits::total 60635058 # number of overall hits 309system.cpu.icache.ReadReq_misses::cpu.inst 856010 # number of ReadReq misses 310system.cpu.icache.ReadReq_misses::total 856010 # number of ReadReq misses 311system.cpu.icache.demand_misses::cpu.inst 856010 # number of demand (read+write) misses 312system.cpu.icache.demand_misses::total 856010 # number of demand (read+write) misses 313system.cpu.icache.overall_misses::cpu.inst 856010 # number of overall misses 314system.cpu.icache.overall_misses::total 856010 # number of overall misses 315system.cpu.icache.ReadReq_miss_latency::cpu.inst 11542526000 # number of ReadReq miss cycles 316system.cpu.icache.ReadReq_miss_latency::total 11542526000 # number of ReadReq miss cycles 317system.cpu.icache.demand_miss_latency::cpu.inst 11542526000 # number of demand (read+write) miss cycles 318system.cpu.icache.demand_miss_latency::total 11542526000 # number of demand (read+write) miss cycles 319system.cpu.icache.overall_miss_latency::cpu.inst 11542526000 # number of overall miss cycles 320system.cpu.icache.overall_miss_latency::total 11542526000 # number of overall miss cycles | 303system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits 304system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits 305system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits 306system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits 307system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits 308system.cpu.icache.overall_hits::total 60635056 # number of overall hits 309system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses 310system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses 311system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses 312system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses 313system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses 314system.cpu.icache.overall_misses::total 856012 # number of overall misses 315system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles 316system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles 317system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles 318system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles 319system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles 320system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles |
321system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) 322system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) 323system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses 324system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses 325system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses 326system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses 327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses 328system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses 329system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses 330system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses 331system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses 332system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses | 321system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) 322system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) 323system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses 324system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses 325system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses 326system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses 327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses 328system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses 329system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses 330system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses 331system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses 332system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses |
333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13484.101821 # average ReadReq miss latency 334system.cpu.icache.ReadReq_avg_miss_latency::total 13484.101821 # average ReadReq miss latency 335system.cpu.icache.demand_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency 336system.cpu.icache.demand_avg_miss_latency::total 13484.101821 # average overall miss latency 337system.cpu.icache.overall_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency 338system.cpu.icache.overall_avg_miss_latency::total 13484.101821 # average overall miss latency | 333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency 334system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency 335system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency 336system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency 337system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency 338system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency |
339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 345system.cpu.icache.fast_writes 0 # number of fast writes performed 346system.cpu.icache.cache_copies 0 # number of cache copies performed | 339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 345system.cpu.icache.fast_writes 0 # number of fast writes performed 346system.cpu.icache.cache_copies 0 # number of cache copies performed |
347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856010 # number of ReadReq MSHR misses 348system.cpu.icache.ReadReq_mshr_misses::total 856010 # number of ReadReq MSHR misses 349system.cpu.icache.demand_mshr_misses::cpu.inst 856010 # number of demand (read+write) MSHR misses 350system.cpu.icache.demand_mshr_misses::total 856010 # number of demand (read+write) MSHR misses 351system.cpu.icache.overall_mshr_misses::cpu.inst 856010 # number of overall MSHR misses 352system.cpu.icache.overall_mshr_misses::total 856010 # number of overall MSHR misses 353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9830506000 # number of ReadReq MSHR miss cycles 354system.cpu.icache.ReadReq_mshr_miss_latency::total 9830506000 # number of ReadReq MSHR miss cycles 355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9830506000 # number of demand (read+write) MSHR miss cycles 356system.cpu.icache.demand_mshr_miss_latency::total 9830506000 # number of demand (read+write) MSHR miss cycles 357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9830506000 # number of overall MSHR miss cycles 358system.cpu.icache.overall_mshr_miss_latency::total 9830506000 # number of overall MSHR miss cycles | 347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses 348system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses 349system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses 350system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses 351system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses 352system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses 353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles 354system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles 355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles 356system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles 357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles 358system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles |
359system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles 360system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles 361system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles 362system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles 363system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses 364system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses 365system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses 366system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses 367system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses 368system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses | 359system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles 360system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles 361system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles 362system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles 363system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses 364system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses 365system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses 366system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses 367system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses 368system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses |
369system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11484.101821 # average ReadReq mshr miss latency 370system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11484.101821 # average ReadReq mshr miss latency 371system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency 372system.cpu.icache.demand_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency 373system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency 374system.cpu.icache.overall_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency | 369system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency 370system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency 371system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency 372system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency 373system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency 374system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency |
375system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 376system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 377system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 378system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 380system.cpu.dcache.replacements 627255 # number of replacements 381system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use 382system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks. --- 20 unchanged lines hidden (view full) --- 403system.cpu.dcache.WriteReq_misses::cpu.data 250502 # number of WriteReq misses 404system.cpu.dcache.WriteReq_misses::total 250502 # number of WriteReq misses 405system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses 406system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses 407system.cpu.dcache.demand_misses::cpu.data 619265 # number of demand (read+write) misses 408system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses 409system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses 410system.cpu.dcache.overall_misses::total 619265 # number of overall misses | 375system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 376system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 377system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 378system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 380system.cpu.dcache.replacements 627255 # number of replacements 381system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use 382system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks. --- 20 unchanged lines hidden (view full) --- 403system.cpu.dcache.WriteReq_misses::cpu.data 250502 # number of WriteReq misses 404system.cpu.dcache.WriteReq_misses::total 250502 # number of WriteReq misses 405system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses 406system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses 407system.cpu.dcache.demand_misses::cpu.data 619265 # number of demand (read+write) misses 408system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses 409system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses 410system.cpu.dcache.overall_misses::total 619265 # number of overall misses |
411system.cpu.dcache.ReadReq_miss_latency::cpu.data 5206335000 # number of ReadReq miss cycles 412system.cpu.dcache.ReadReq_miss_latency::total 5206335000 # number of ReadReq miss cycles 413system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061427000 # number of WriteReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::total 8061427000 # number of WriteReq miss cycles 415system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154571000 # number of LoadLockedReq miss cycles 416system.cpu.dcache.LoadLockedReq_miss_latency::total 154571000 # number of LoadLockedReq miss cycles 417system.cpu.dcache.demand_miss_latency::cpu.data 13267762000 # number of demand (read+write) miss cycles 418system.cpu.dcache.demand_miss_latency::total 13267762000 # number of demand (read+write) miss cycles 419system.cpu.dcache.overall_miss_latency::cpu.data 13267762000 # number of overall miss cycles 420system.cpu.dcache.overall_miss_latency::total 13267762000 # number of overall miss cycles | 411system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205933000 # number of ReadReq miss cycles 412system.cpu.dcache.ReadReq_miss_latency::total 5205933000 # number of ReadReq miss cycles 413system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061519000 # number of WriteReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::total 8061519000 # number of WriteReq miss cycles 415system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154593000 # number of LoadLockedReq miss cycles 416system.cpu.dcache.LoadLockedReq_miss_latency::total 154593000 # number of LoadLockedReq miss cycles 417system.cpu.dcache.demand_miss_latency::cpu.data 13267452000 # number of demand (read+write) miss cycles 418system.cpu.dcache.demand_miss_latency::total 13267452000 # number of demand (read+write) miss cycles 419system.cpu.dcache.overall_miss_latency::cpu.data 13267452000 # number of overall miss cycles 420system.cpu.dcache.overall_miss_latency::total 13267452000 # number of overall miss cycles |
421system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.WriteReq_accesses::total 10223496 # number of WriteReq accesses(hits+misses) 425system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247673 # number of LoadLockedReq accesses(hits+misses) 426system.cpu.dcache.LoadLockedReq_accesses::total 247673 # number of LoadLockedReq accesses(hits+misses) 427system.cpu.dcache.StoreCondReq_accesses::cpu.data 247672 # number of StoreCondReq accesses(hits+misses) 428system.cpu.dcache.StoreCondReq_accesses::total 247672 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 435system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses 436system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses 437system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046028 # miss rate for LoadLockedReq accesses 438system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046028 # miss rate for LoadLockedReq accesses 439system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses 440system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses 441system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses 442system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses | 421system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.WriteReq_accesses::total 10223496 # number of WriteReq accesses(hits+misses) 425system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247673 # number of LoadLockedReq accesses(hits+misses) 426system.cpu.dcache.LoadLockedReq_accesses::total 247673 # number of LoadLockedReq accesses(hits+misses) 427system.cpu.dcache.StoreCondReq_accesses::cpu.data 247672 # number of StoreCondReq accesses(hits+misses) 428system.cpu.dcache.StoreCondReq_accesses::total 247672 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 435system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses 436system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses 437system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046028 # miss rate for LoadLockedReq accesses 438system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046028 # miss rate for LoadLockedReq accesses 439system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses 440system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses 441system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses 442system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses |
443system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14118.376844 # average ReadReq miss latency 444system.cpu.dcache.ReadReq_avg_miss_latency::total 14118.376844 # average ReadReq miss latency 445system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.088375 # average WriteReq miss latency 446system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.088375 # average WriteReq miss latency 447system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13558.859649 # average LoadLockedReq miss latency 448system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13558.859649 # average LoadLockedReq miss latency 449system.cpu.dcache.demand_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency 450system.cpu.dcache.demand_avg_miss_latency::total 21425.015139 # average overall miss latency 451system.cpu.dcache.overall_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency 452system.cpu.dcache.overall_avg_miss_latency::total 21425.015139 # average overall miss latency | 443system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14117.286713 # average ReadReq miss latency 444system.cpu.dcache.ReadReq_avg_miss_latency::total 14117.286713 # average ReadReq miss latency 445system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.455637 # average WriteReq miss latency 446system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.455637 # average WriteReq miss latency 447system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.789474 # average LoadLockedReq miss latency 448system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.789474 # average LoadLockedReq miss latency 449system.cpu.dcache.demand_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency 450system.cpu.dcache.demand_avg_miss_latency::total 21424.514545 # average overall miss latency 451system.cpu.dcache.overall_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency 452system.cpu.dcache.overall_avg_miss_latency::total 21424.514545 # average overall miss latency |
453system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 454system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 455system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 456system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 457system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 458system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 459system.cpu.dcache.fast_writes 0 # number of fast writes performed 460system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 465system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250502 # number of WriteReq MSHR misses 466system.cpu.dcache.WriteReq_mshr_misses::total 250502 # number of WriteReq MSHR misses 467system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses 468system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses 469system.cpu.dcache.demand_mshr_misses::cpu.data 619265 # number of demand (read+write) MSHR misses 470system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses 471system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses 472system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses | 453system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 454system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 455system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 456system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 457system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 458system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 459system.cpu.dcache.fast_writes 0 # number of fast writes performed 460system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 465system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250502 # number of WriteReq MSHR misses 466system.cpu.dcache.WriteReq_mshr_misses::total 250502 # number of WriteReq MSHR misses 467system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses 468system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses 469system.cpu.dcache.demand_mshr_misses::cpu.data 619265 # number of demand (read+write) MSHR misses 470system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses 471system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses 472system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses |
473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468809000 # number of ReadReq MSHR miss cycles 474system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468809000 # number of ReadReq MSHR miss cycles 475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560423000 # number of WriteReq MSHR miss cycles 476system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560423000 # number of WriteReq MSHR miss cycles 477system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131771000 # number of LoadLockedReq MSHR miss cycles 478system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131771000 # number of LoadLockedReq MSHR miss cycles 479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12029232000 # number of demand (read+write) MSHR miss cycles 480system.cpu.dcache.demand_mshr_miss_latency::total 12029232000 # number of demand (read+write) MSHR miss cycles 481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12029232000 # number of overall MSHR miss cycles 482system.cpu.dcache.overall_mshr_miss_latency::total 12029232000 # number of overall MSHR miss cycles 483system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182087740500 # number of ReadReq MSHR uncacheable cycles 484system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182087740500 # number of ReadReq MSHR uncacheable cycles 485system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708092000 # number of WriteReq MSHR uncacheable cycles 486system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708092000 # number of WriteReq MSHR uncacheable cycles 487system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200795832500 # number of overall MSHR uncacheable cycles 488system.cpu.dcache.overall_mshr_uncacheable_latency::total 200795832500 # number of overall MSHR uncacheable cycles | 473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468407000 # number of ReadReq MSHR miss cycles 474system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468407000 # number of ReadReq MSHR miss cycles 475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560515000 # number of WriteReq MSHR miss cycles 476system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560515000 # number of WriteReq MSHR miss cycles 477system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131793000 # number of LoadLockedReq MSHR miss cycles 478system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131793000 # number of LoadLockedReq MSHR miss cycles 479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028922000 # number of demand (read+write) MSHR miss cycles 480system.cpu.dcache.demand_mshr_miss_latency::total 12028922000 # number of demand (read+write) MSHR miss cycles 481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028922000 # number of overall MSHR miss cycles 482system.cpu.dcache.overall_mshr_miss_latency::total 12028922000 # number of overall MSHR miss cycles 483system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182088074500 # number of ReadReq MSHR uncacheable cycles 484system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182088074500 # number of ReadReq MSHR uncacheable cycles 485system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708050000 # number of WriteReq MSHR uncacheable cycles 486system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708050000 # number of WriteReq MSHR uncacheable cycles 487system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200796124500 # number of overall MSHR uncacheable cycles 488system.cpu.dcache.overall_mshr_uncacheable_latency::total 200796124500 # number of overall MSHR uncacheable cycles |
489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses 493system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses 494system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # mshr miss rate for LoadLockedReq accesses 495system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses 496system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses 497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses 498system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses | 489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses 493system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses 494system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # mshr miss rate for LoadLockedReq accesses 495system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses 496system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses 497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses 498system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses |
499system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12118.376844 # average ReadReq mshr miss latency 500system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12118.376844 # average ReadReq mshr miss latency 501system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.088375 # average WriteReq mshr miss latency 502system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.088375 # average WriteReq mshr miss latency 503system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11558.859649 # average LoadLockedReq mshr miss latency 504system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11558.859649 # average LoadLockedReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency | 499system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12117.286713 # average ReadReq mshr miss latency 500system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12117.286713 # average ReadReq mshr miss latency 501system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.455637 # average WriteReq mshr miss latency 502system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.455637 # average WriteReq mshr miss latency 503system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11560.789474 # average LoadLockedReq mshr miss latency 504system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11560.789474 # average LoadLockedReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency |
509system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 510system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 511system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 512system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 513system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 514system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 516system.cpu.l2cache.replacements 61906 # number of replacements | 509system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 510system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 511system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 512system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 513system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 514system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 516system.cpu.l2cache.replacements 61906 # number of replacements |
517system.cpu.l2cache.tagsinuse 50893.840844 # Cycle average of tags in use 518system.cpu.l2cache.total_refs 1682731 # Total number of references to valid blocks. | 517system.cpu.l2cache.tagsinuse 50893.840705 # Cycle average of tags in use 518system.cpu.l2cache.total_refs 1682733 # Total number of references to valid blocks. |
519system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks. | 519system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks. |
520system.cpu.l2cache.avg_refs 13.219871 # Average number of references to valid blocks. | 520system.cpu.l2cache.avg_refs 13.219887 # Average number of references to valid blocks. |
521system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit. | 521system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit. |
522system.cpu.l2cache.occ_blocks::writebacks 37868.665500 # Average occupied blocks per requestor | 522system.cpu.l2cache.occ_blocks::writebacks 37868.665520 # Average occupied blocks per requestor |
523system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor 524system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor | 523system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor 524system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor |
525system.cpu.l2cache.occ_blocks::cpu.inst 6995.476724 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_blocks::cpu.data 6025.811636 # Average occupied blocks per requestor | 525system.cpu.l2cache.occ_blocks::cpu.inst 6995.476581 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_blocks::cpu.data 6025.811619 # Average occupied blocks per requestor |
527system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy 528system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 530system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy 531system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Average percentage of cache occupancy 532system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy 533system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits 534system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits | 527system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy 528system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 530system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy 531system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Average percentage of cache occupancy 532system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy 533system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits 534system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits |
535system.cpu.l2cache.ReadReq_hits::cpu.inst 843786 # number of ReadReq hits | 535system.cpu.l2cache.ReadReq_hits::cpu.inst 843788 # number of ReadReq hits |
536system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits | 536system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits |
537system.cpu.l2cache.ReadReq_hits::total 1226341 # number of ReadReq hits | 537system.cpu.l2cache.ReadReq_hits::total 1226343 # number of ReadReq hits |
538system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits 539system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits 540system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 541system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 542system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # number of ReadExReq hits 543system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits 544system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits 545system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits | 538system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits 539system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits 540system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 541system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 542system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # number of ReadExReq hits 543system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits 544system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits 545system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits |
546system.cpu.l2cache.demand_hits::cpu.inst 843786 # number of demand (read+write) hits | 546system.cpu.l2cache.demand_hits::cpu.inst 843788 # number of demand (read+write) hits |
547system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits | 547system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits |
548system.cpu.l2cache.demand_hits::total 1340759 # number of demand (read+write) hits | 548system.cpu.l2cache.demand_hits::total 1340761 # number of demand (read+write) hits |
549system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits 550system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits | 549system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits 550system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits |
551system.cpu.l2cache.overall_hits::cpu.inst 843786 # number of overall hits | 551system.cpu.l2cache.overall_hits::cpu.inst 843788 # number of overall hits |
552system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits | 552system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits |
553system.cpu.l2cache.overall_hits::total 1340759 # number of overall hits | 553system.cpu.l2cache.overall_hits::total 1340761 # number of overall hits |
554system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 555system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 556system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses 557system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses 558system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses 559system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses 560system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses 561system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses --- 5 unchanged lines hidden (view full) --- 567system.cpu.l2cache.demand_misses::total 153651 # number of demand (read+write) misses 568system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 569system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 570system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses 571system.cpu.l2cache.overall_misses::cpu.data 143044 # number of overall misses 572system.cpu.l2cache.overall_misses::total 153651 # number of overall misses 573system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles | 554system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 555system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 556system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses 557system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses 558system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses 559system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses 560system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses 561system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses --- 5 unchanged lines hidden (view full) --- 567system.cpu.l2cache.demand_misses::total 153651 # number of demand (read+write) misses 568system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 569system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 570system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses 571system.cpu.l2cache.overall_misses::cpu.data 143044 # number of overall misses 572system.cpu.l2cache.overall_misses::total 153651 # number of overall misses 573system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles |
575system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 535011000 # number of ReadReq miss cycles 576system.cpu.l2cache.ReadReq_miss_latency::cpu.data 517367000 # number of ReadReq miss cycles 577system.cpu.l2cache.ReadReq_miss_latency::total 1052802500 # number of ReadReq miss cycles | 575system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 536335000 # number of ReadReq miss cycles 576system.cpu.l2cache.ReadReq_miss_latency::cpu.data 516987000 # number of ReadReq miss cycles 577system.cpu.l2cache.ReadReq_miss_latency::total 1053746500 # number of ReadReq miss cycles |
578system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles 579system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles | 578system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles 579system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles |
580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102272500 # number of ReadExReq miss cycles 581system.cpu.l2cache.ReadExReq_miss_latency::total 6102272500 # number of ReadExReq miss cycles | 580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102367500 # number of ReadExReq miss cycles 581system.cpu.l2cache.ReadExReq_miss_latency::total 6102367500 # number of ReadExReq miss cycles |
582system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles 583system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles | 582system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles 583system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles |
584system.cpu.l2cache.demand_miss_latency::cpu.inst 535011000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 6619639500 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 7155075000 # number of demand (read+write) miss cycles | 584system.cpu.l2cache.demand_miss_latency::cpu.inst 536335000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 6619354500 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 7156114000 # number of demand (read+write) miss cycles |
587system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles | 587system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles |
589system.cpu.l2cache.overall_miss_latency::cpu.inst 535011000 # number of overall miss cycles 590system.cpu.l2cache.overall_miss_latency::cpu.data 6619639500 # number of overall miss cycles 591system.cpu.l2cache.overall_miss_latency::total 7155075000 # number of overall miss cycles | 589system.cpu.l2cache.overall_miss_latency::cpu.inst 536335000 # number of overall miss cycles 590system.cpu.l2cache.overall_miss_latency::cpu.data 6619354500 # number of overall miss cycles 591system.cpu.l2cache.overall_miss_latency::total 7156114000 # number of overall miss cycles |
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704system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles | 704system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles |
705system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175863203171 # number of overall MSHR uncacheable cycles 706system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176060669722 # number of overall MSHR uncacheable cycles | 705system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles 706system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles |
707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 708system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses 709system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses 710system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses 711system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses 712system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses 713system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses 714system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses --- 5 unchanged lines hidden (view full) --- 720system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses 721system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 722system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses 723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses 724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses 725system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency | 707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 708system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses 709system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses 710system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses 711system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses 712system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses 713system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses 714system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses --- 5 unchanged lines hidden (view full) --- 720system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses 721system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 722system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses 723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses 724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses 725system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency |
728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37489.063025 # average ReadReq mshr miss latency 729system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39492.807466 # average ReadReq mshr miss latency 730system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38455.347716 # average ReadReq mshr miss latency 731system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.142758 # average UpgradeReq mshr miss latency 732system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.142758 # average UpgradeReq mshr miss latency 733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32825.399929 # average ReadExReq mshr miss latency 734system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32825.399929 # average ReadExReq mshr miss latency | 728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37614.027267 # average ReadReq mshr miss latency 729system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39454.260499 # average ReadReq mshr miss latency 730system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38501.499682 # average ReadReq mshr miss latency 731system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.402507 # average UpgradeReq mshr miss latency 732system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.402507 # average UpgradeReq mshr miss latency 733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32826.090753 # average ReadExReq mshr miss latency 734system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32826.090753 # average ReadExReq mshr miss latency |
735system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency 736system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency | 735system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency 736system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency |
737system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency | 737system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency |
740system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency | 740system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency |
742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency 744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency | 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency 744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency |
745system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 746system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 747system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 748system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 749system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 750system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 751system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 752system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 7 unchanged lines hidden (view full) --- 760system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.iocache.blocked::no_targets 0 # number of cycles access was blocked 764system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.iocache.fast_writes 0 # number of fast writes performed 767system.iocache.cache_copies 0 # number of cache copies performed | 745system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 746system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 747system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 748system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 749system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 750system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 751system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 752system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 7 unchanged lines hidden (view full) --- 760system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.iocache.blocked::no_targets 0 # number of cycles access was blocked 764system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.iocache.fast_writes 0 # number of fast writes performed 767system.iocache.cache_copies 0 # number of cache copies performed |
768system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of ReadReq MSHR uncacheable cycles 769system.iocache.ReadReq_mshr_uncacheable_latency::total 1052670853165 # number of ReadReq MSHR uncacheable cycles 770system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of overall MSHR uncacheable cycles 771system.iocache.overall_mshr_uncacheable_latency::total 1052670853165 # number of overall MSHR uncacheable cycles | 768system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles 769system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles 770system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles 771system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles |
772system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 773system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 774system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 775system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 776system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 777 778---------- End Simulation Statistics ---------- | 772system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 773system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 774system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 775system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 776system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 777 778---------- End Simulation Statistics ---------- |