| stats.txt (9308:f634a34f2f0b) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.624627 # Number of seconds simulated 4sim_ticks 2624627401000 # Number of ticks simulated 5final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.603636 # Number of seconds simulated 4sim_ticks 2603636076000 # Number of ticks simulated 5final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 463403 # Simulator instruction rate (inst/s) 8host_op_rate 589674 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20203281292 # Simulator tick rate (ticks/s) 10host_mem_usage 381220 # Number of bytes of host memory used 11host_seconds 129.91 # Real time elapsed on the host 12sim_insts 60201162 # Number of instructions simulated 13sim_ops 76605148 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory | 7host_inst_rate 485506 # Simulator instruction rate (inst/s) 8host_op_rate 617798 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20998999798 # Simulator tick rate (ticks/s) 10host_mem_usage 395692 # Number of bytes of host memory used 11host_seconds 123.99 # Real time elapsed on the host 12sim_insts 60197128 # Number of instructions simulated 13sim_ops 76599899 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory 19system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory | 17system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory |
| 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory | 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory |
| 24system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory | 24system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory |
| 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory | 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory |
| 33system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s) | 33system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15494089 # Total number of read requests seen 53system.physmem.writeReqs 811479 # Total number of write requests seen 54system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 991621696 # Total number of bytes read from memory 56system.physmem.bytesWritten 51934656 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2603631716000 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 6652 # Categorize read packet sizes 99system.physmem.readPktSize::3 15335424 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 152013 # Categorize read packet sizes 103system.physmem.readPktSize::7 0 # Categorize read packet sizes 104system.physmem.readPktSize::8 0 # Categorize read packet sizes 105system.physmem.writePktSize::0 0 # categorize write packet sizes 106system.physmem.writePktSize::1 0 # categorize write packet sizes 107system.physmem.writePktSize::2 754018 # categorize write packet sizes 108system.physmem.writePktSize::3 0 # categorize write packet sizes 109system.physmem.writePktSize::4 0 # categorize write packet sizes 110system.physmem.writePktSize::5 0 # categorize write packet sizes 111system.physmem.writePktSize::6 57461 # categorize write packet sizes 112system.physmem.writePktSize::7 0 # categorize write packet sizes 113system.physmem.writePktSize::8 0 # categorize write packet sizes 114system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 120system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes 121system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 122system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 123system.physmem.rdQLenPdf::0 15419651 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 56393 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 11796 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 2238 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 1067 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 810 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 393 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 217 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 134 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 74 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 49 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 156system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 189system.physmem.totQLat 3755940486 # Total cycles spent in queuing delays 190system.physmem.totMemAccLat 281915228486 # Sum of mem lat for all requests 191system.physmem.totBusLat 61975012000 # Total cycles spent in databus access 192system.physmem.totBankLat 216184276000 # Total cycles spent in bank access 193system.physmem.avgQLat 242.42 # Average queueing delay per request 194system.physmem.avgBankLat 13953.00 # Average bank access latency per request 195system.physmem.avgBusLat 4000.00 # Average bus latency per request 196system.physmem.avgMemAccLat 18195.41 # Average memory access latency 197system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s 198system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s 199system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s 200system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 201system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 202system.physmem.busUtil 2.51 # Data bus utilization in percentage 203system.physmem.avgRdQLen 0.11 # Average read queue length over time 204system.physmem.avgWrQLen 12.38 # Average write queue length over time 205system.physmem.readRowHits 15449465 # Number of row buffer hits during reads 206system.physmem.writeRowHits 784611 # Number of row buffer hits during writes 207system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads 208system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes 209system.physmem.avgGap 159677.46 # Average gap between requests |
| 52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 64system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 65system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 66system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 67system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 68system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 69system.cf0.dma_write_txs 0 # Number of DMA write transactions. 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses | 210system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 211system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 212system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 213system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 214system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 215system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 216system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 217system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 222system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 223system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 224system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 225system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 226system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 227system.cf0.dma_write_txs 0 # Number of DMA write transactions. 228system.cpu.dtb.inst_hits 0 # ITB inst hits 229system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 72system.cpu.dtb.read_hits 14996727 # DTB read hits 73system.cpu.dtb.read_misses 7361 # DTB read misses 74system.cpu.dtb.write_hits 11231610 # DTB write hits 75system.cpu.dtb.write_misses 2211 # DTB write misses | 230system.cpu.dtb.read_hits 14995523 # DTB read hits 231system.cpu.dtb.read_misses 7332 # DTB read misses 232system.cpu.dtb.write_hits 11230789 # DTB write hits 233system.cpu.dtb.write_misses 2203 # DTB write misses |
| 76system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 234system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 235system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 236system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 237system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 238system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB 239system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 82system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch | 240system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch |
| 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 241system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 242system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 85system.cpu.dtb.read_accesses 15004088 # DTB read accesses 86system.cpu.dtb.write_accesses 11233821 # DTB write accesses | 243system.cpu.dtb.read_accesses 15002855 # DTB read accesses 244system.cpu.dtb.write_accesses 11232992 # DTB write accesses |
| 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 245system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 88system.cpu.dtb.hits 26228337 # DTB hits 89system.cpu.dtb.misses 9572 # DTB misses 90system.cpu.dtb.accesses 26237909 # DTB accesses 91system.cpu.itb.inst_hits 61495131 # ITB inst hits | 246system.cpu.dtb.hits 26226312 # DTB hits 247system.cpu.dtb.misses 9535 # DTB misses 248system.cpu.dtb.accesses 26235847 # DTB accesses 249system.cpu.itb.inst_hits 61491068 # ITB inst hits |
| 92system.cpu.itb.inst_misses 4471 # ITB inst misses 93system.cpu.itb.read_hits 0 # DTB read hits 94system.cpu.itb.read_misses 0 # DTB read misses 95system.cpu.itb.write_hits 0 # DTB write hits 96system.cpu.itb.write_misses 0 # DTB write misses 97system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 98system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 99system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 100system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 101system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 102system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 103system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 104system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.itb.read_accesses 0 # DTB read accesses 107system.cpu.itb.write_accesses 0 # DTB write accesses | 250system.cpu.itb.inst_misses 4471 # ITB inst misses 251system.cpu.itb.read_hits 0 # DTB read hits 252system.cpu.itb.read_misses 0 # DTB read misses 253system.cpu.itb.write_hits 0 # DTB write hits 254system.cpu.itb.write_misses 0 # DTB write misses 255system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 256system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 257system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 258system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 259system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 260system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 261system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 262system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 263system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 264system.cpu.itb.read_accesses 0 # DTB read accesses 265system.cpu.itb.write_accesses 0 # DTB write accesses |
| 108system.cpu.itb.inst_accesses 61499602 # ITB inst accesses 109system.cpu.itb.hits 61495131 # DTB hits | 266system.cpu.itb.inst_accesses 61495539 # ITB inst accesses 267system.cpu.itb.hits 61491068 # DTB hits |
| 110system.cpu.itb.misses 4471 # DTB misses | 268system.cpu.itb.misses 4471 # DTB misses |
| 111system.cpu.itb.accesses 61499602 # DTB accesses 112system.cpu.numCycles 5249254802 # number of cpu cycles simulated | 269system.cpu.itb.accesses 61495539 # DTB accesses 270system.cpu.numCycles 5207272152 # number of cpu cycles simulated |
| 113system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 114system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 271system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 115system.cpu.committedInsts 60201162 # Number of instructions committed 116system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed 117system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses | 273system.cpu.committedInsts 60197128 # Number of instructions committed 274system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed 275system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses |
| 118system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses | 276system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses |
| 119system.cpu.num_func_calls 2139915 # number of times a function call or return occured 120system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls 121system.cpu.num_int_insts 68872531 # number of integer instructions | 277system.cpu.num_func_calls 2139710 # number of times a function call or return occured 278system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls 279system.cpu.num_int_insts 68867725 # number of integer instructions |
| 122system.cpu.num_fp_insts 10269 # number of float instructions | 280system.cpu.num_fp_insts 10269 # number of float instructions |
| 123system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read 124system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written | 281system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read 282system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written |
| 125system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 126system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 283system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 284system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 127system.cpu.num_mem_refs 27395680 # number of memory refs 128system.cpu.num_load_insts 15660706 # Number of load instructions 129system.cpu.num_store_insts 11734974 # Number of store instructions 130system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles 131system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles 132system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles 133system.cpu.idle_fraction 0.871333 # Percentage of idle cycles | 285system.cpu.num_mem_refs 27393681 # number of memory refs 286system.cpu.num_load_insts 15659530 # Number of load instructions 287system.cpu.num_store_insts 11734151 # Number of store instructions 288system.cpu.num_idle_cycles 4579082960.576241 # Number of idle cycles 289system.cpu.num_busy_cycles 628189191.423759 # Number of busy cycles 290system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles 291system.cpu.idle_fraction 0.879363 # Percentage of idle cycles |
| 134system.cpu.kern.inst.arm 0 # number of arm instructions executed | 292system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 135system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed 136system.cpu.icache.replacements 855895 # number of replacements 137system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use 138system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks. 139system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks. 140system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks. 141system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. 142system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor 143system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy 144system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy 145system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits 146system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits 147system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits 148system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits 149system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits 150system.cpu.icache.overall_hits::total 60638724 # number of overall hits 151system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses 152system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses 153system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses 154system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses 155system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses 156system.cpu.icache.overall_misses::total 856407 # number of overall misses 157system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles 158system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles 159system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles 160system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles 161system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles 162system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles 163system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses) 164system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses) 165system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses 166system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses 167system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses 168system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses 169system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses 170system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses 171system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses 172system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses 173system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses 174system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses 175system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency 176system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency 177system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency 178system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency 179system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency 180system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency | 293system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed 294system.cpu.icache.replacements 855498 # number of replacements 295system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use 296system.cpu.icache.total_refs 60635058 # Total number of references to valid blocks. 297system.cpu.icache.sampled_refs 856010 # Sample count of references to valid blocks. 298system.cpu.icache.avg_refs 70.834521 # Average number of references to valid blocks. 299system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. 300system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor 301system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy 302system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy 303system.cpu.icache.ReadReq_hits::cpu.inst 60635058 # number of ReadReq hits 304system.cpu.icache.ReadReq_hits::total 60635058 # number of ReadReq hits 305system.cpu.icache.demand_hits::cpu.inst 60635058 # number of demand (read+write) hits 306system.cpu.icache.demand_hits::total 60635058 # number of demand (read+write) hits 307system.cpu.icache.overall_hits::cpu.inst 60635058 # number of overall hits 308system.cpu.icache.overall_hits::total 60635058 # number of overall hits 309system.cpu.icache.ReadReq_misses::cpu.inst 856010 # number of ReadReq misses 310system.cpu.icache.ReadReq_misses::total 856010 # number of ReadReq misses 311system.cpu.icache.demand_misses::cpu.inst 856010 # number of demand (read+write) misses 312system.cpu.icache.demand_misses::total 856010 # number of demand (read+write) misses 313system.cpu.icache.overall_misses::cpu.inst 856010 # number of overall misses 314system.cpu.icache.overall_misses::total 856010 # number of overall misses 315system.cpu.icache.ReadReq_miss_latency::cpu.inst 11542526000 # number of ReadReq miss cycles 316system.cpu.icache.ReadReq_miss_latency::total 11542526000 # number of ReadReq miss cycles 317system.cpu.icache.demand_miss_latency::cpu.inst 11542526000 # number of demand (read+write) miss cycles 318system.cpu.icache.demand_miss_latency::total 11542526000 # number of demand (read+write) miss cycles 319system.cpu.icache.overall_miss_latency::cpu.inst 11542526000 # number of overall miss cycles 320system.cpu.icache.overall_miss_latency::total 11542526000 # number of overall miss cycles 321system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) 322system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) 323system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses 324system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses 325system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses 326system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses 327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses 328system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses 329system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses 330system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses 331system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses 332system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses 333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13484.101821 # average ReadReq miss latency 334system.cpu.icache.ReadReq_avg_miss_latency::total 13484.101821 # average ReadReq miss latency 335system.cpu.icache.demand_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency 336system.cpu.icache.demand_avg_miss_latency::total 13484.101821 # average overall miss latency 337system.cpu.icache.overall_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency 338system.cpu.icache.overall_avg_miss_latency::total 13484.101821 # average overall miss latency |
| 181system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 182system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 183system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 184system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 185system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 186system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 187system.cpu.icache.fast_writes 0 # number of fast writes performed 188system.cpu.icache.cache_copies 0 # number of cache copies performed | 339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 345system.cpu.icache.fast_writes 0 # number of fast writes performed 346system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 189system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses 190system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses 191system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses 192system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses 193system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses 194system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses 195system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles 196system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles 197system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles 198system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles 199system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles 200system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles 201system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles 202system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles 203system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles 204system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles 205system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 207system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses 208system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 209system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses 210system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses 211system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency 212system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency 213system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency 214system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency 215system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency 216system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency | 347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856010 # number of ReadReq MSHR misses 348system.cpu.icache.ReadReq_mshr_misses::total 856010 # number of ReadReq MSHR misses 349system.cpu.icache.demand_mshr_misses::cpu.inst 856010 # number of demand (read+write) MSHR misses 350system.cpu.icache.demand_mshr_misses::total 856010 # number of demand (read+write) MSHR misses 351system.cpu.icache.overall_mshr_misses::cpu.inst 856010 # number of overall MSHR misses 352system.cpu.icache.overall_mshr_misses::total 856010 # number of overall MSHR misses 353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9830506000 # number of ReadReq MSHR miss cycles 354system.cpu.icache.ReadReq_mshr_miss_latency::total 9830506000 # number of ReadReq MSHR miss cycles 355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9830506000 # number of demand (read+write) MSHR miss cycles 356system.cpu.icache.demand_mshr_miss_latency::total 9830506000 # number of demand (read+write) MSHR miss cycles 357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9830506000 # number of overall MSHR miss cycles 358system.cpu.icache.overall_mshr_miss_latency::total 9830506000 # number of overall MSHR miss cycles 359system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles 360system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles 361system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles 362system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles 363system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses 364system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses 365system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses 366system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses 367system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses 368system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses 369system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11484.101821 # average ReadReq mshr miss latency 370system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11484.101821 # average ReadReq mshr miss latency 371system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency 372system.cpu.icache.demand_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency 373system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency 374system.cpu.icache.overall_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency |
| 217system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 218system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 219system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 220system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 221system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 375system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 376system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 377system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 378system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 222system.cpu.dcache.replacements 627232 # number of replacements 223system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use 224system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks. 225system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks. 226system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks. 227system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. 228system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor 229system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy 230system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy 231system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits 232system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits 233system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits 234system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits 235system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits 236system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits 237system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits 238system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits 239system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits 240system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits 241system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits 242system.cpu.dcache.overall_hits::total 23170010 # number of overall hits 243system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses 244system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses 245system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses 246system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses 247system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses 248system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses 249system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses 250system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses 251system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses 252system.cpu.dcache.overall_misses::total 619246 # number of overall misses 253system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles 254system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles 256system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles 257system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles 258system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles 259system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # number of demand (read+write) miss cycles 260system.cpu.dcache.demand_miss_latency::total 14169509500 # number of demand (read+write) miss cycles 261system.cpu.dcache.overall_miss_latency::cpu.data 14169509500 # number of overall miss cycles 262system.cpu.dcache.overall_miss_latency::total 14169509500 # number of overall miss cycles 263system.cpu.dcache.ReadReq_accesses::cpu.data 13564965 # number of ReadReq accesses(hits+misses) 264system.cpu.dcache.ReadReq_accesses::total 13564965 # number of ReadReq accesses(hits+misses) 265system.cpu.dcache.WriteReq_accesses::cpu.data 10224291 # number of WriteReq accesses(hits+misses) 266system.cpu.dcache.WriteReq_accesses::total 10224291 # number of WriteReq accesses(hits+misses) 267system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) 268system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) 269system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) 270system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) 271system.cpu.dcache.demand_accesses::cpu.data 23789256 # number of demand (read+write) accesses 272system.cpu.dcache.demand_accesses::total 23789256 # number of demand (read+write) accesses 273system.cpu.dcache.overall_accesses::cpu.data 23789256 # number of overall (read+write) accesses 274system.cpu.dcache.overall_accesses::total 23789256 # number of overall (read+write) accesses 275system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027180 # miss rate for ReadReq accesses 276system.cpu.dcache.ReadReq_miss_rate::total 0.027180 # miss rate for ReadReq accesses 277system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024505 # miss rate for WriteReq accesses 278system.cpu.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses 279system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046013 # miss rate for LoadLockedReq accesses 280system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046013 # miss rate for LoadLockedReq accesses 281system.cpu.dcache.demand_miss_rate::cpu.data 0.026030 # miss rate for demand accesses 282system.cpu.dcache.demand_miss_rate::total 0.026030 # miss rate for demand accesses 283system.cpu.dcache.overall_miss_rate::cpu.data 0.026030 # miss rate for overall accesses 284system.cpu.dcache.overall_miss_rate::total 0.026030 # miss rate for overall accesses 285system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.455941 # average ReadReq miss latency 286system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.455941 # average ReadReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35797.044068 # average WriteReq miss latency 288system.cpu.dcache.WriteReq_avg_miss_latency::total 35797.044068 # average WriteReq miss latency 289system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.573309 # average LoadLockedReq miss latency 290system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.573309 # average LoadLockedReq miss latency 291system.cpu.dcache.demand_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency 292system.cpu.dcache.demand_avg_miss_latency::total 22881.874893 # average overall miss latency 293system.cpu.dcache.overall_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency 294system.cpu.dcache.overall_avg_miss_latency::total 22881.874893 # average overall miss latency | 380system.cpu.dcache.replacements 627255 # number of replacements 381system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use 382system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks. 383system.cpu.dcache.sampled_refs 627767 # Sample count of references to valid blocks. 384system.cpu.dcache.avg_refs 37.680956 # Average number of references to valid blocks. 385system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit. 386system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor 387system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy 388system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy 389system.cpu.dcache.ReadReq_hits::cpu.data 13195024 # number of ReadReq hits 390system.cpu.dcache.ReadReq_hits::total 13195024 # number of ReadReq hits 391system.cpu.dcache.WriteReq_hits::cpu.data 9972994 # number of WriteReq hits 392system.cpu.dcache.WriteReq_hits::total 9972994 # number of WriteReq hits 393system.cpu.dcache.LoadLockedReq_hits::cpu.data 236273 # number of LoadLockedReq hits 394system.cpu.dcache.LoadLockedReq_hits::total 236273 # number of LoadLockedReq hits 395system.cpu.dcache.StoreCondReq_hits::cpu.data 247672 # number of StoreCondReq hits 396system.cpu.dcache.StoreCondReq_hits::total 247672 # number of StoreCondReq hits 397system.cpu.dcache.demand_hits::cpu.data 23168018 # number of demand (read+write) hits 398system.cpu.dcache.demand_hits::total 23168018 # number of demand (read+write) hits 399system.cpu.dcache.overall_hits::cpu.data 23168018 # number of overall hits 400system.cpu.dcache.overall_hits::total 23168018 # number of overall hits 401system.cpu.dcache.ReadReq_misses::cpu.data 368763 # number of ReadReq misses 402system.cpu.dcache.ReadReq_misses::total 368763 # number of ReadReq misses 403system.cpu.dcache.WriteReq_misses::cpu.data 250502 # number of WriteReq misses 404system.cpu.dcache.WriteReq_misses::total 250502 # number of WriteReq misses 405system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses 406system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses 407system.cpu.dcache.demand_misses::cpu.data 619265 # number of demand (read+write) misses 408system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses 409system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses 410system.cpu.dcache.overall_misses::total 619265 # number of overall misses 411system.cpu.dcache.ReadReq_miss_latency::cpu.data 5206335000 # number of ReadReq miss cycles 412system.cpu.dcache.ReadReq_miss_latency::total 5206335000 # number of ReadReq miss cycles 413system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061427000 # number of WriteReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::total 8061427000 # number of WriteReq miss cycles 415system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154571000 # number of LoadLockedReq miss cycles 416system.cpu.dcache.LoadLockedReq_miss_latency::total 154571000 # number of LoadLockedReq miss cycles 417system.cpu.dcache.demand_miss_latency::cpu.data 13267762000 # number of demand (read+write) miss cycles 418system.cpu.dcache.demand_miss_latency::total 13267762000 # number of demand (read+write) miss cycles 419system.cpu.dcache.overall_miss_latency::cpu.data 13267762000 # number of overall miss cycles 420system.cpu.dcache.overall_miss_latency::total 13267762000 # number of overall miss cycles 421system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.WriteReq_accesses::total 10223496 # number of WriteReq accesses(hits+misses) 425system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247673 # number of LoadLockedReq accesses(hits+misses) 426system.cpu.dcache.LoadLockedReq_accesses::total 247673 # number of LoadLockedReq accesses(hits+misses) 427system.cpu.dcache.StoreCondReq_accesses::cpu.data 247672 # number of StoreCondReq accesses(hits+misses) 428system.cpu.dcache.StoreCondReq_accesses::total 247672 # number of StoreCondReq accesses(hits+misses) 429system.cpu.dcache.demand_accesses::cpu.data 23787283 # number of demand (read+write) accesses 430system.cpu.dcache.demand_accesses::total 23787283 # number of demand (read+write) accesses 431system.cpu.dcache.overall_accesses::cpu.data 23787283 # number of overall (read+write) accesses 432system.cpu.dcache.overall_accesses::total 23787283 # number of overall (read+write) accesses 433system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027187 # miss rate for ReadReq accesses 434system.cpu.dcache.ReadReq_miss_rate::total 0.027187 # miss rate for ReadReq accesses 435system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses 436system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses 437system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046028 # miss rate for LoadLockedReq accesses 438system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046028 # miss rate for LoadLockedReq accesses 439system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses 440system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses 441system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses 442system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses 443system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14118.376844 # average ReadReq miss latency 444system.cpu.dcache.ReadReq_avg_miss_latency::total 14118.376844 # average ReadReq miss latency 445system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.088375 # average WriteReq miss latency 446system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.088375 # average WriteReq miss latency 447system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13558.859649 # average LoadLockedReq miss latency 448system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13558.859649 # average LoadLockedReq miss latency 449system.cpu.dcache.demand_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency 450system.cpu.dcache.demand_avg_miss_latency::total 21425.015139 # average overall miss latency 451system.cpu.dcache.overall_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency 452system.cpu.dcache.overall_avg_miss_latency::total 21425.015139 # average overall miss latency |
| 295system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 296system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 297system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 300system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 301system.cpu.dcache.fast_writes 0 # number of fast writes performed 302system.cpu.dcache.cache_copies 0 # number of cache copies performed | 453system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 454system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 455system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 456system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 457system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 458system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 459system.cpu.dcache.fast_writes 0 # number of fast writes performed 460system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 303system.cpu.dcache.writebacks::writebacks 595999 # number of writebacks 304system.cpu.dcache.writebacks::total 595999 # number of writebacks 305system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368699 # number of ReadReq MSHR misses 306system.cpu.dcache.ReadReq_mshr_misses::total 368699 # number of ReadReq MSHR misses 307system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250547 # number of WriteReq MSHR misses 308system.cpu.dcache.WriteReq_mshr_misses::total 250547 # number of WriteReq MSHR misses 309system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11397 # number of LoadLockedReq MSHR misses 310system.cpu.dcache.LoadLockedReq_mshr_misses::total 11397 # number of LoadLockedReq MSHR misses 311system.cpu.dcache.demand_mshr_misses::cpu.data 619246 # number of demand (read+write) MSHR misses 312system.cpu.dcache.demand_mshr_misses::total 619246 # number of demand (read+write) MSHR misses 313system.cpu.dcache.overall_mshr_misses::cpu.data 619246 # number of overall MSHR misses 314system.cpu.dcache.overall_mshr_misses::total 619246 # number of overall MSHR misses 315system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463269500 # number of ReadReq MSHR miss cycles 316system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463269500 # number of ReadReq MSHR miss cycles 317system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8467748000 # number of WriteReq MSHR miss cycles 318system.cpu.dcache.WriteReq_mshr_miss_latency::total 8467748000 # number of WriteReq MSHR miss cycles 319system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131961000 # number of LoadLockedReq MSHR miss cycles 320system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131961000 # number of LoadLockedReq MSHR miss cycles 321system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931017500 # number of demand (read+write) MSHR miss cycles 322system.cpu.dcache.demand_mshr_miss_latency::total 12931017500 # number of demand (read+write) MSHR miss cycles 323system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931017500 # number of overall MSHR miss cycles 324system.cpu.dcache.overall_mshr_miss_latency::total 12931017500 # number of overall MSHR miss cycles 325system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182084322500 # number of ReadReq MSHR uncacheable cycles 326system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182084322500 # number of ReadReq MSHR uncacheable cycles 327system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41323476000 # number of WriteReq MSHR uncacheable cycles 328system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41323476000 # number of WriteReq MSHR uncacheable cycles 329system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223407798500 # number of overall MSHR uncacheable cycles 330system.cpu.dcache.overall_mshr_uncacheable_latency::total 223407798500 # number of overall MSHR uncacheable cycles 331system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027180 # mshr miss rate for ReadReq accesses 332system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027180 # mshr miss rate for ReadReq accesses 333system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses 334system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses 335system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046013 # mshr miss rate for LoadLockedReq accesses 336system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046013 # mshr miss rate for LoadLockedReq accesses 337system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for demand accesses 338system.cpu.dcache.demand_mshr_miss_rate::total 0.026030 # mshr miss rate for demand accesses 339system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for overall accesses 340system.cpu.dcache.overall_mshr_miss_rate::total 0.026030 # mshr miss rate for overall accesses 341system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.455941 # average ReadReq mshr miss latency 342system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.455941 # average ReadReq mshr miss latency 343system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33797.044068 # average WriteReq mshr miss latency 344system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33797.044068 # average WriteReq mshr miss latency 345system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.573309 # average LoadLockedReq mshr miss latency 346system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.573309 # average LoadLockedReq mshr miss latency 347system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency 348system.cpu.dcache.demand_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency 349system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency 350system.cpu.dcache.overall_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency | 461system.cpu.dcache.writebacks::writebacks 596013 # number of writebacks 462system.cpu.dcache.writebacks::total 596013 # number of writebacks 463system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368763 # number of ReadReq MSHR misses 464system.cpu.dcache.ReadReq_mshr_misses::total 368763 # number of ReadReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250502 # number of WriteReq MSHR misses 466system.cpu.dcache.WriteReq_mshr_misses::total 250502 # number of WriteReq MSHR misses 467system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses 468system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses 469system.cpu.dcache.demand_mshr_misses::cpu.data 619265 # number of demand (read+write) MSHR misses 470system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses 471system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses 472system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses 473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468809000 # number of ReadReq MSHR miss cycles 474system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468809000 # number of ReadReq MSHR miss cycles 475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560423000 # number of WriteReq MSHR miss cycles 476system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560423000 # number of WriteReq MSHR miss cycles 477system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131771000 # number of LoadLockedReq MSHR miss cycles 478system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131771000 # number of LoadLockedReq MSHR miss cycles 479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12029232000 # number of demand (read+write) MSHR miss cycles 480system.cpu.dcache.demand_mshr_miss_latency::total 12029232000 # number of demand (read+write) MSHR miss cycles 481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12029232000 # number of overall MSHR miss cycles 482system.cpu.dcache.overall_mshr_miss_latency::total 12029232000 # number of overall MSHR miss cycles 483system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182087740500 # number of ReadReq MSHR uncacheable cycles 484system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182087740500 # number of ReadReq MSHR uncacheable cycles 485system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708092000 # number of WriteReq MSHR uncacheable cycles 486system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708092000 # number of WriteReq MSHR uncacheable cycles 487system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200795832500 # number of overall MSHR uncacheable cycles 488system.cpu.dcache.overall_mshr_uncacheable_latency::total 200795832500 # number of overall MSHR uncacheable cycles 489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses 493system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses 494system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # mshr miss rate for LoadLockedReq accesses 495system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses 496system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses 497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses 498system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses 499system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12118.376844 # average ReadReq mshr miss latency 500system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12118.376844 # average ReadReq mshr miss latency 501system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.088375 # average WriteReq mshr miss latency 502system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.088375 # average WriteReq mshr miss latency 503system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11558.859649 # average LoadLockedReq mshr miss latency 504system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11558.859649 # average LoadLockedReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency |
| 351system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 352system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 353system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 354system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 355system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 356system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 357system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 509system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 510system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 511system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 512system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 513system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 514system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 358system.cpu.l2cache.replacements 61916 # number of replacements 359system.cpu.l2cache.tagsinuse 50867.720143 # Cycle average of tags in use 360system.cpu.l2cache.total_refs 1683066 # Total number of references to valid blocks. 361system.cpu.l2cache.sampled_refs 127296 # Sample count of references to valid blocks. 362system.cpu.l2cache.avg_refs 13.221672 # Average number of references to valid blocks. 363system.cpu.l2cache.warmup_cycle 2574019400000 # Cycle when the warmup percentage was hit. 364system.cpu.l2cache.occ_blocks::writebacks 37864.952088 # Average occupied blocks per requestor 365system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885583 # Average occupied blocks per requestor 366system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor 367system.cpu.l2cache.occ_blocks::cpu.inst 6985.681192 # Average occupied blocks per requestor 368system.cpu.l2cache.occ_blocks::cpu.data 6013.199864 # Average occupied blocks per requestor 369system.cpu.l2cache.occ_percent::writebacks 0.577773 # Average percentage of cache occupancy | 516system.cpu.l2cache.replacements 61906 # number of replacements 517system.cpu.l2cache.tagsinuse 50893.840844 # Cycle average of tags in use 518system.cpu.l2cache.total_refs 1682731 # Total number of references to valid blocks. 519system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks. 520system.cpu.l2cache.avg_refs 13.219871 # Average number of references to valid blocks. 521system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit. 522system.cpu.l2cache.occ_blocks::writebacks 37868.665500 # Average occupied blocks per requestor 523system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor 524system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor 525system.cpu.l2cache.occ_blocks::cpu.inst 6995.476724 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_blocks::cpu.data 6025.811636 # Average occupied blocks per requestor 527system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy |
| 370system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 371system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 528system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 372system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy 373system.cpu.l2cache.occ_percent::cpu.data 0.091754 # Average percentage of cache occupancy 374system.cpu.l2cache.occ_percent::total 0.776180 # Average percentage of cache occupancy 375system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8772 # number of ReadReq hits 376system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits 377system.cpu.l2cache.ReadReq_hits::cpu.inst 844153 # number of ReadReq hits 378system.cpu.l2cache.ReadReq_hits::cpu.data 370237 # number of ReadReq hits 379system.cpu.l2cache.ReadReq_hits::total 1226711 # number of ReadReq hits 380system.cpu.l2cache.Writeback_hits::writebacks 595999 # number of Writeback hits 381system.cpu.l2cache.Writeback_hits::total 595999 # number of Writeback hits | 530system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy 531system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Average percentage of cache occupancy 532system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy 533system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits 534system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits 535system.cpu.l2cache.ReadReq_hits::cpu.inst 843786 # number of ReadReq hits 536system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits 537system.cpu.l2cache.ReadReq_hits::total 1226341 # number of ReadReq hits 538system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits 539system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits |
| 382system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 383system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits | 540system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 541system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits |
| 384system.cpu.l2cache.ReadExReq_hits::cpu.data 114469 # number of ReadExReq hits 385system.cpu.l2cache.ReadExReq_hits::total 114469 # number of ReadExReq hits 386system.cpu.l2cache.demand_hits::cpu.dtb.walker 8772 # number of demand (read+write) hits 387system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits 388system.cpu.l2cache.demand_hits::cpu.inst 844153 # number of demand (read+write) hits 389system.cpu.l2cache.demand_hits::cpu.data 484706 # number of demand (read+write) hits 390system.cpu.l2cache.demand_hits::total 1341180 # number of demand (read+write) hits 391system.cpu.l2cache.overall_hits::cpu.dtb.walker 8772 # number of overall hits 392system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits 393system.cpu.l2cache.overall_hits::cpu.inst 844153 # number of overall hits 394system.cpu.l2cache.overall_hits::cpu.data 484706 # number of overall hits 395system.cpu.l2cache.overall_hits::total 1341180 # number of overall hits | 542system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # number of ReadExReq hits 543system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits 544system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits 545system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits 546system.cpu.l2cache.demand_hits::cpu.inst 843786 # number of demand (read+write) hits 547system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits 548system.cpu.l2cache.demand_hits::total 1340759 # number of demand (read+write) hits 549system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits 550system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits 551system.cpu.l2cache.overall_hits::cpu.inst 843786 # number of overall hits 552system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits 553system.cpu.l2cache.overall_hits::total 1340759 # number of overall hits |
| 396system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 397system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses | 554system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 555system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses |
| 398system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses 399system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses 400system.cpu.l2cache.ReadReq_misses::total 20482 # number of ReadReq misses 401system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses 402system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses 403system.cpu.l2cache.ReadExReq_misses::cpu.data 133179 # number of ReadExReq misses 404system.cpu.l2cache.ReadExReq_misses::total 133179 # number of ReadExReq misses | 556system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses 557system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses 558system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses 559system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses 560system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses 561system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses 562system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses |
| 405system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 406system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses | 563system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 564system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses |
| 407system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses 408system.cpu.l2cache.demand_misses::cpu.data 143038 # number of demand (read+write) misses 409system.cpu.l2cache.demand_misses::total 153661 # number of demand (read+write) misses | 565system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::cpu.data 143044 # number of demand (read+write) misses 567system.cpu.l2cache.demand_misses::total 153651 # number of demand (read+write) misses |
| 410system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 411system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses | 568system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 569system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses |
| 412system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses 413system.cpu.l2cache.overall_misses::cpu.data 143038 # number of overall misses 414system.cpu.l2cache.overall_misses::total 153661 # number of overall misses 415system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles 416system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles 417system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 552086500 # number of ReadReq miss cycles 418system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512764500 # number of ReadReq miss cycles 419system.cpu.l2cache.ReadReq_miss_latency::total 1065268500 # number of ReadReq miss cycles 420system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1041000 # number of UpgradeReq miss cycles 421system.cpu.l2cache.UpgradeReq_miss_latency::total 1041000 # number of UpgradeReq miss cycles 422system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6925666500 # number of ReadExReq miss cycles 423system.cpu.l2cache.ReadExReq_miss_latency::total 6925666500 # number of ReadExReq miss cycles 424system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles 425system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles 426system.cpu.l2cache.demand_miss_latency::cpu.inst 552086500 # number of demand (read+write) miss cycles 427system.cpu.l2cache.demand_miss_latency::cpu.data 7438431000 # number of demand (read+write) miss cycles 428system.cpu.l2cache.demand_miss_latency::total 7990935000 # number of demand (read+write) miss cycles 429system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles 430system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles 431system.cpu.l2cache.overall_miss_latency::cpu.inst 552086500 # number of overall miss cycles 432system.cpu.l2cache.overall_miss_latency::cpu.data 7438431000 # number of overall miss cycles 433system.cpu.l2cache.overall_miss_latency::total 7990935000 # number of overall miss cycles 434system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8777 # number of ReadReq accesses(hits+misses) 435system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3552 # number of ReadReq accesses(hits+misses) 436system.cpu.l2cache.ReadReq_accesses::cpu.inst 854768 # number of ReadReq accesses(hits+misses) 437system.cpu.l2cache.ReadReq_accesses::cpu.data 380096 # number of ReadReq accesses(hits+misses) 438system.cpu.l2cache.ReadReq_accesses::total 1247193 # number of ReadReq accesses(hits+misses) 439system.cpu.l2cache.Writeback_accesses::writebacks 595999 # number of Writeback accesses(hits+misses) 440system.cpu.l2cache.Writeback_accesses::total 595999 # number of Writeback accesses(hits+misses) 441system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) 442system.cpu.l2cache.UpgradeReq_accesses::total 2899 # number of UpgradeReq accesses(hits+misses) 443system.cpu.l2cache.ReadExReq_accesses::cpu.data 247648 # number of ReadExReq accesses(hits+misses) 444system.cpu.l2cache.ReadExReq_accesses::total 247648 # number of ReadExReq accesses(hits+misses) 445system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8777 # number of demand (read+write) accesses 446system.cpu.l2cache.demand_accesses::cpu.itb.walker 3552 # number of demand (read+write) accesses 447system.cpu.l2cache.demand_accesses::cpu.inst 854768 # number of demand (read+write) accesses 448system.cpu.l2cache.demand_accesses::cpu.data 627744 # number of demand (read+write) accesses 449system.cpu.l2cache.demand_accesses::total 1494841 # number of demand (read+write) accesses 450system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8777 # number of overall (read+write) accesses 451system.cpu.l2cache.overall_accesses::cpu.itb.walker 3552 # number of overall (read+write) accesses 452system.cpu.l2cache.overall_accesses::cpu.inst 854768 # number of overall (read+write) accesses 453system.cpu.l2cache.overall_accesses::cpu.data 627744 # number of overall (read+write) accesses 454system.cpu.l2cache.overall_accesses::total 1494841 # number of overall (read+write) accesses 455system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses | 570system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses 571system.cpu.l2cache.overall_misses::cpu.data 143044 # number of overall misses 572system.cpu.l2cache.overall_misses::total 153651 # number of overall misses 573system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles 575system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 535011000 # number of ReadReq miss cycles 576system.cpu.l2cache.ReadReq_miss_latency::cpu.data 517367000 # number of ReadReq miss cycles 577system.cpu.l2cache.ReadReq_miss_latency::total 1052802500 # number of ReadReq miss cycles 578system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles 579system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles 580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102272500 # number of ReadExReq miss cycles 581system.cpu.l2cache.ReadExReq_miss_latency::total 6102272500 # number of ReadExReq miss cycles 582system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles 583system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles 584system.cpu.l2cache.demand_miss_latency::cpu.inst 535011000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 6619639500 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 7155075000 # number of demand (read+write) miss cycles 587system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles 589system.cpu.l2cache.overall_miss_latency::cpu.inst 535011000 # number of overall miss cycles 590system.cpu.l2cache.overall_miss_latency::cpu.data 6619639500 # number of overall miss cycles 591system.cpu.l2cache.overall_miss_latency::total 7155075000 # number of overall miss cycles 592system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses) 593system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) 594system.cpu.l2cache.ReadReq_accesses::cpu.inst 854385 # number of ReadReq accesses(hits+misses) 595system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses) 596system.cpu.l2cache.ReadReq_accesses::total 1246806 # number of ReadReq accesses(hits+misses) 597system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses) 598system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses) 599system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) 600system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) 601system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604 # number of ReadExReq accesses(hits+misses) 602system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses) 603system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses 604system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses 605system.cpu.l2cache.demand_accesses::cpu.inst 854385 # number of demand (read+write) accesses 606system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses 607system.cpu.l2cache.demand_accesses::total 1494410 # number of demand (read+write) accesses 608system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses 609system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses 610system.cpu.l2cache.overall_accesses::cpu.inst 854385 # number of overall (read+write) accesses 611system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses 612system.cpu.l2cache.overall_accesses::total 1494410 # number of overall (read+write) accesses 613system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses |
| 456system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses | 614system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses |
| 457system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses 458system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025938 # miss rate for ReadReq accesses 459system.cpu.l2cache.ReadReq_miss_rate::total 0.016422 # miss rate for ReadReq accesses 460system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991031 # miss rate for UpgradeReq accesses 461system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991031 # miss rate for UpgradeReq accesses 462system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537775 # miss rate for ReadExReq accesses 463system.cpu.l2cache.ReadExReq_miss_rate::total 0.537775 # miss rate for ReadExReq accesses 464system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000570 # miss rate for demand accesses | 615system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025931 # miss rate for ReadReq accesses 617system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses 618system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses 619system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses 620system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537899 # miss rate for ReadExReq accesses 621system.cpu.l2cache.ReadExReq_miss_rate::total 0.537899 # miss rate for ReadExReq accesses 622system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses |
| 465system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses | 623system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses |
| 466system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012419 # miss rate for demand accesses 467system.cpu.l2cache.demand_miss_rate::cpu.data 0.227860 # miss rate for demand accesses 468system.cpu.l2cache.demand_miss_rate::total 0.102794 # miss rate for demand accesses 469system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000570 # miss rate for overall accesses | 624system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012405 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::cpu.data 0.227862 # miss rate for demand accesses 626system.cpu.l2cache.demand_miss_rate::total 0.102817 # miss rate for demand accesses 627system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses |
| 470system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses | 628system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses |
| 471system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012419 # miss rate for overall accesses 472system.cpu.l2cache.overall_miss_rate::cpu.data 0.227860 # miss rate for overall accesses 473system.cpu.l2cache.overall_miss_rate::total 0.102794 # miss rate for overall accesses 474system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency 475system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 476system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52010.032972 # average ReadReq miss latency 477system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.788011 # average ReadReq miss latency 478system.cpu.l2cache.ReadReq_avg_miss_latency::total 52009.984377 # average ReadReq miss latency 479system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 362.339018 # average UpgradeReq miss latency 480system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 362.339018 # average UpgradeReq miss latency 481system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52002.691866 # average ReadExReq miss latency 482system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52002.691866 # average ReadExReq miss latency 483system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency 484system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 485system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency 486system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency 487system.cpu.l2cache.demand_avg_miss_latency::total 52003.663910 # average overall miss latency 488system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency 489system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 490system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency 491system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency 492system.cpu.l2cache.overall_avg_miss_latency::total 52003.663910 # average overall miss latency | 629system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012405 # miss rate for overall accesses 630system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862 # miss rate for overall accesses 631system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses 632system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency 633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency 634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50477.497877 # average ReadReq miss latency 635system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52481.943599 # average ReadReq miss latency 636system.cpu.l2cache.ReadReq_avg_miss_latency::total 51444.050818 # average ReadReq miss latency 637system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency 638system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency 639system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45817.672278 # average ReadExReq miss latency 640system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45817.672278 # average ReadExReq miss latency 641system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency 642system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency 643system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::total 46567.057813 # average overall miss latency 646system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency 650system.cpu.l2cache.overall_avg_miss_latency::total 46567.057813 # average overall miss latency |
| 493system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 494system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 495system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 496system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 497system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 498system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 499system.cpu.l2cache.fast_writes 0 # number of fast writes performed 500system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 651system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 654system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 656system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 657system.cpu.l2cache.fast_writes 0 # number of fast writes performed 658system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 501system.cpu.l2cache.writebacks::writebacks 57455 # number of writebacks 502system.cpu.l2cache.writebacks::total 57455 # number of writebacks | 659system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks 660system.cpu.l2cache.writebacks::total 57461 # number of writebacks |
| 503system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 504system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses | 661system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 662system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses |
| 505system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses 506system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses 507system.cpu.l2cache.ReadReq_mshr_misses::total 20482 # number of ReadReq MSHR misses 508system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses 509system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses 510system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133179 # number of ReadExReq MSHR misses 511system.cpu.l2cache.ReadExReq_mshr_misses::total 133179 # number of ReadExReq MSHR misses | 663system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses 664system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses 665system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses 666system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses 667system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses 668system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses 669system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses |
| 512system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 513system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses | 670system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 671system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses |
| 514system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses 515system.cpu.l2cache.demand_mshr_misses::cpu.data 143038 # number of demand (read+write) MSHR misses 516system.cpu.l2cache.demand_mshr_misses::total 153661 # number of demand (read+write) MSHR misses | 672system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses 673system.cpu.l2cache.demand_mshr_misses::cpu.data 143044 # number of demand (read+write) MSHR misses 674system.cpu.l2cache.demand_mshr_misses::total 153651 # number of demand (read+write) MSHR misses |
| 517system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 518system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses | 675system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 676system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses |
| 519system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses 520system.cpu.l2cache.overall_mshr_misses::cpu.data 143038 # number of overall MSHR misses 521system.cpu.l2cache.overall_mshr_misses::total 153661 # number of overall MSHR misses 522system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles 523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles 524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 424634000 # number of ReadReq MSHR miss cycles 525system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394375000 # number of ReadReq MSHR miss cycles 526system.cpu.l2cache.ReadReq_mshr_miss_latency::total 819329000 # number of ReadReq MSHR miss cycles 527system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114934000 # number of UpgradeReq MSHR miss cycles 528system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114934000 # number of UpgradeReq MSHR miss cycles 529system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5327448000 # number of ReadExReq MSHR miss cycles 530system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5327448000 # number of ReadExReq MSHR miss cycles 531system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles 532system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles 533system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 424634000 # number of demand (read+write) MSHR miss cycles 534system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5721823000 # number of demand (read+write) MSHR miss cycles 535system.cpu.l2cache.demand_mshr_miss_latency::total 6146777000 # number of demand (read+write) MSHR miss cycles 536system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles 537system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles 538system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 424634000 # number of overall MSHR miss cycles 539system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5721823000 # number of overall MSHR miss cycles 540system.cpu.l2cache.overall_mshr_miss_latency::total 6146777000 # number of overall MSHR miss cycles 541system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles 542system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166685236000 # number of ReadReq MSHR uncacheable cycles 543system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166950076000 # number of ReadReq MSHR uncacheable cycles 544system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31792706500 # number of WriteReq MSHR uncacheable cycles 545system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31792706500 # number of WriteReq MSHR uncacheable cycles 546system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles 547system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198477942500 # number of overall MSHR uncacheable cycles 548system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198742782500 # number of overall MSHR uncacheable cycles 549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses | 677system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses 678system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 # number of overall MSHR misses 679system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses 680system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles 681system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 397346579 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389320096 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 786988691 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28812314 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28812314 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371883715 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371883715 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 397346579 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4761203811 # number of demand (read+write) MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::total 5158872406 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles 695system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 397346579 # number of overall MSHR miss cycles 697system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4761203811 # number of overall MSHR miss cycles 698system.cpu.l2cache.overall_mshr_miss_latency::total 5158872406 # number of overall MSHR miss cycles 699system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles 700system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688827565 # number of ReadReq MSHR uncacheable cycles 701system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166886294116 # number of ReadReq MSHR uncacheable cycles 702system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9174375606 # number of WriteReq MSHR uncacheable cycles 703system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9174375606 # number of WriteReq MSHR uncacheable cycles 704system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles 705system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175863203171 # number of overall MSHR uncacheable cycles 706system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176060669722 # number of overall MSHR uncacheable cycles 707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses |
| 550system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses | 708system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses |
| 551system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses 552system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025938 # mshr miss rate for ReadReq accesses 553system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses 554system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses 555system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses 556system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537775 # mshr miss rate for ReadExReq accesses 557system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537775 # mshr miss rate for ReadExReq accesses 558system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses | 709system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses 710system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses 711system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses 712system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses 713system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses 714system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses 715system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses 716system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses |
| 559system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses | 717system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses |
| 560system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses 561system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses 562system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses 563system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses | 718system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses 719system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses 720system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses 721system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses |
| 564system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses | 722system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses |
| 565system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses 566system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses 567system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses 568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency 573system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency 574system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency 575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency 576system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency 577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 578system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 579system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency 580system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency 582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency | 723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses 724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses 725system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency 728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37489.063025 # average ReadReq mshr miss latency 729system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39492.807466 # average ReadReq mshr miss latency 730system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38455.347716 # average ReadReq mshr miss latency 731system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.142758 # average UpgradeReq mshr miss latency 732system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.142758 # average UpgradeReq mshr miss latency 733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32825.399929 # average ReadExReq mshr miss latency 734system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32825.399929 # average ReadExReq mshr miss latency 735system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency 736system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency 737system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency 740system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency 744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency |
| 587system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 588system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 589system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 590system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 591system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 592system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 593system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 594system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 7 unchanged lines hidden (view full) --- 602system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 603system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 604system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 605system.iocache.blocked::no_targets 0 # number of cycles access was blocked 606system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 607system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 608system.iocache.fast_writes 0 # number of fast writes performed 609system.iocache.cache_copies 0 # number of cache copies performed | 745system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 746system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 747system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 748system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 749system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 750system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 751system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 752system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 7 unchanged lines hidden (view full) --- 760system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.iocache.blocked::no_targets 0 # number of cycles access was blocked 764system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.iocache.fast_writes 0 # number of fast writes performed 767system.iocache.cache_copies 0 # number of cache copies performed |
| 610system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles 611system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles 612system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles 613system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles | 768system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of ReadReq MSHR uncacheable cycles 769system.iocache.ReadReq_mshr_uncacheable_latency::total 1052670853165 # number of ReadReq MSHR uncacheable cycles 770system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of overall MSHR uncacheable cycles 771system.iocache.overall_mshr_uncacheable_latency::total 1052670853165 # number of overall MSHR uncacheable cycles |
| 614system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 615system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 616system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 617system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 618system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 619 620---------- End Simulation Statistics ---------- | 772system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 773system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 774system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 775system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 776system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 777 778---------- End Simulation Statistics ---------- |