| stats.txt (9289:a31a1243a3ed) | stats.txt (9308:f634a34f2f0b) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.624688 # Number of seconds simulated 4sim_ticks 2624688000000 # Number of ticks simulated 5final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.624627 # Number of seconds simulated 4sim_ticks 2624627401000 # Number of ticks simulated 5final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 509092 # Simulator instruction rate (inst/s) 8host_op_rate 647812 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22195691402 # Simulator tick rate (ticks/s) 10host_mem_usage 379628 # Number of bytes of host memory used 11host_seconds 118.25 # Real time elapsed on the host 12sim_insts 60201138 # Number of instructions simulated 13sim_ops 76605123 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory | 7host_inst_rate 463403 # Simulator instruction rate (inst/s) 8host_op_rate 589674 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20203281292 # Simulator tick rate (ticks/s) 10host_mem_usage 381220 # Number of bytes of host memory used 11host_seconds 129.91 # Real time elapsed on the host 12sim_insts 60201162 # Number of instructions simulated 13sim_ops 76605148 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory 19system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory 19system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory |
| 20system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory | 20system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory |
| 22system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory | 22system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory |
| 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory | 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory |
| 24system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory | 24system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory | 29system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory |
| 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory | 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory |
| 33system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s) |
| 52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 64system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 65system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 66system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 67system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 68system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 69system.cf0.dma_write_txs 0 # Number of DMA write transactions. 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses | 52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 64system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 65system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 66system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 67system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 68system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 69system.cf0.dma_write_txs 0 # Number of DMA write transactions. 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 72system.cpu.dtb.read_hits 14996726 # DTB read hits 73system.cpu.dtb.read_misses 7357 # DTB read misses 74system.cpu.dtb.write_hits 11231612 # DTB write hits | 72system.cpu.dtb.read_hits 14996727 # DTB read hits 73system.cpu.dtb.read_misses 7361 # DTB read misses 74system.cpu.dtb.write_hits 11231610 # DTB write hits |
| 75system.cpu.dtb.write_misses 2211 # DTB write misses 76system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 75system.cpu.dtb.write_misses 2211 # DTB write misses 76system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 80system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB | 80system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB |
| 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 85system.cpu.dtb.read_accesses 15004083 # DTB read accesses 86system.cpu.dtb.write_accesses 11233823 # DTB write accesses | 85system.cpu.dtb.read_accesses 15004088 # DTB read accesses 86system.cpu.dtb.write_accesses 11233821 # DTB write accesses |
| 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 88system.cpu.dtb.hits 26228338 # DTB hits 89system.cpu.dtb.misses 9568 # DTB misses 90system.cpu.dtb.accesses 26237906 # DTB accesses 91system.cpu.itb.inst_hits 61495107 # ITB inst hits | 88system.cpu.dtb.hits 26228337 # DTB hits 89system.cpu.dtb.misses 9572 # DTB misses 90system.cpu.dtb.accesses 26237909 # DTB accesses 91system.cpu.itb.inst_hits 61495131 # ITB inst hits |
| 92system.cpu.itb.inst_misses 4471 # ITB inst misses 93system.cpu.itb.read_hits 0 # DTB read hits 94system.cpu.itb.read_misses 0 # DTB read misses 95system.cpu.itb.write_hits 0 # DTB write hits 96system.cpu.itb.write_misses 0 # DTB write misses 97system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 98system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 99system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 100system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 101system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 102system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 103system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 104system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.itb.read_accesses 0 # DTB read accesses 107system.cpu.itb.write_accesses 0 # DTB write accesses | 92system.cpu.itb.inst_misses 4471 # ITB inst misses 93system.cpu.itb.read_hits 0 # DTB read hits 94system.cpu.itb.read_misses 0 # DTB read misses 95system.cpu.itb.write_hits 0 # DTB write hits 96system.cpu.itb.write_misses 0 # DTB write misses 97system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 98system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 99system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 100system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 101system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 102system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 103system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 104system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.itb.read_accesses 0 # DTB read accesses 107system.cpu.itb.write_accesses 0 # DTB write accesses |
| 108system.cpu.itb.inst_accesses 61499578 # ITB inst accesses 109system.cpu.itb.hits 61495107 # DTB hits | 108system.cpu.itb.inst_accesses 61499602 # ITB inst accesses 109system.cpu.itb.hits 61495131 # DTB hits |
| 110system.cpu.itb.misses 4471 # DTB misses | 110system.cpu.itb.misses 4471 # DTB misses |
| 111system.cpu.itb.accesses 61499578 # DTB accesses 112system.cpu.numCycles 5249376000 # number of cpu cycles simulated | 111system.cpu.itb.accesses 61499602 # DTB accesses 112system.cpu.numCycles 5249254802 # number of cpu cycles simulated |
| 113system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 114system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 113system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 114system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 115system.cpu.committedInsts 60201138 # Number of instructions committed 116system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed 117system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses | 115system.cpu.committedInsts 60201162 # Number of instructions committed 116system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed 117system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses |
| 118system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses | 118system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses |
| 119system.cpu.num_func_calls 2139913 # number of times a function call or return occured 120system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls 121system.cpu.num_int_insts 68872510 # number of integer instructions | 119system.cpu.num_func_calls 2139915 # number of times a function call or return occured 120system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls 121system.cpu.num_int_insts 68872531 # number of integer instructions |
| 122system.cpu.num_fp_insts 10269 # number of float instructions | 122system.cpu.num_fp_insts 10269 # number of float instructions |
| 123system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read 124system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written | 123system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read 124system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written |
| 125system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 126system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 125system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 126system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 127system.cpu.num_mem_refs 27395681 # number of memory refs 128system.cpu.num_load_insts 15660705 # Number of load instructions 129system.cpu.num_store_insts 11734976 # Number of store instructions 130system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles 131system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles 132system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles 133system.cpu.idle_fraction 0.871278 # Percentage of idle cycles | 127system.cpu.num_mem_refs 27395680 # number of memory refs 128system.cpu.num_load_insts 15660706 # Number of load instructions 129system.cpu.num_store_insts 11734974 # Number of store instructions 130system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles 131system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles 132system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles 133system.cpu.idle_fraction 0.871333 # Percentage of idle cycles |
| 134system.cpu.kern.inst.arm 0 # number of arm instructions executed 135system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed | 134system.cpu.kern.inst.arm 0 # number of arm instructions executed 135system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed |
| 136system.cpu.icache.replacements 855878 # number of replacements 137system.cpu.icache.tagsinuse 510.920723 # Cycle average of tags in use 138system.cpu.icache.total_refs 60638717 # Total number of references to valid blocks. 139system.cpu.icache.sampled_refs 856390 # Sample count of references to valid blocks. 140system.cpu.icache.avg_refs 70.807362 # Average number of references to valid blocks. | 136system.cpu.icache.replacements 855895 # number of replacements 137system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use 138system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks. 139system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks. 140system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks. |
| 141system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. | 141system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. |
| 142system.cpu.icache.occ_blocks::cpu.inst 510.920723 # Average occupied blocks per requestor | 142system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor |
| 143system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy 144system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy | 143system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy 144system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy |
| 145system.cpu.icache.ReadReq_hits::cpu.inst 60638717 # number of ReadReq hits 146system.cpu.icache.ReadReq_hits::total 60638717 # number of ReadReq hits 147system.cpu.icache.demand_hits::cpu.inst 60638717 # number of demand (read+write) hits 148system.cpu.icache.demand_hits::total 60638717 # number of demand (read+write) hits 149system.cpu.icache.overall_hits::cpu.inst 60638717 # number of overall hits 150system.cpu.icache.overall_hits::total 60638717 # number of overall hits 151system.cpu.icache.ReadReq_misses::cpu.inst 856390 # number of ReadReq misses 152system.cpu.icache.ReadReq_misses::total 856390 # number of ReadReq misses 153system.cpu.icache.demand_misses::cpu.inst 856390 # number of demand (read+write) misses 154system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses 155system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses 156system.cpu.icache.overall_misses::total 856390 # number of overall misses 157system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles 158system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles 159system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles 160system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles 161system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles 162system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles 163system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) 164system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) 165system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses 166system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses 167system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses 168system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses | 145system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits 146system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits 147system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits 148system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits 149system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits 150system.cpu.icache.overall_hits::total 60638724 # number of overall hits 151system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses 152system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses 153system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses 154system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses 155system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses 156system.cpu.icache.overall_misses::total 856407 # number of overall misses 157system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles 158system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles 159system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles 160system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles 161system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles 162system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles 163system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses) 164system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses) 165system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses 166system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses 167system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses 168system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses |
| 169system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses 170system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses 171system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses 172system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses 173system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses 174system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses | 169system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses 170system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses 171system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses 172system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses 173system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses 174system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses |
| 175system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency 176system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency 177system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency 178system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency 179system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency 180system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency | 175system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency 176system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency 177system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency 178system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency 179system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency 180system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency |
| 181system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 182system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 183system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 184system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 185system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 186system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 187system.cpu.icache.fast_writes 0 # number of fast writes performed 188system.cpu.icache.cache_copies 0 # number of cache copies performed | 181system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 182system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 183system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 184system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 185system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 186system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 187system.cpu.icache.fast_writes 0 # number of fast writes performed 188system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 189system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856390 # number of ReadReq MSHR misses 190system.cpu.icache.ReadReq_mshr_misses::total 856390 # number of ReadReq MSHR misses 191system.cpu.icache.demand_mshr_misses::cpu.inst 856390 # number of demand (read+write) MSHR misses 192system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses 193system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses 194system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses 195system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles 196system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles 197system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles 198system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles 199system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles 200system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles | 189system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses 190system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses 191system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses 192system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses 193system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses 194system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses 195system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles 196system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles 197system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles 198system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles 199system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles 200system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles |
| 201system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles 202system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles 203system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles 204system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles 205system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 207system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses 208system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 209system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses 210system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses | 201system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles 202system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles 203system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles 204system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles 205system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 207system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses 208system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 209system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses 210system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses |
| 211system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency 212system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency 213system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency 214system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency 215system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency 216system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency | 211system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency 212system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency 213system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency 214system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency 215system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency 216system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency |
| 217system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 218system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 219system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 220system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 221system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 217system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 218system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 219system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 220system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 221system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 222system.cpu.dcache.replacements 627203 # number of replacements 223system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use 224system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks. 225system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks. 226system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks. | 222system.cpu.dcache.replacements 627232 # number of replacements 223system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use 224system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks. 225system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks. 226system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks. |
| 227system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. | 227system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. |
| 228system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor | 228system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor |
| 229system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy 230system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy | 229system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy 230system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy |
| 231system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits 232system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits 233system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits 234system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits 235system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits 236system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits | 231system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits 232system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits 233system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits 234system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits 235system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits 236system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits |
| 237system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits 238system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits | 237system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits 238system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits |
| 239system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits 240system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits 241system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits 242system.cpu.dcache.overall_hits::total 23170043 # number of overall hits 243system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses 244system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses 245system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses 246system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses 247system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses 248system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses 249system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses 250system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses 251system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses 252system.cpu.dcache.overall_misses::total 619214 # number of overall misses 253system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles 254system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles 256system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles 257system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles 258system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles 259system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles 260system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles 261system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles 262system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles 263system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) 264system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) 265system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) 266system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses) | 239system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits 240system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits 241system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits 242system.cpu.dcache.overall_hits::total 23170010 # number of overall hits 243system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses 244system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses 245system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses 246system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses 247system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses 248system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses 249system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses 250system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses 251system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses 252system.cpu.dcache.overall_misses::total 619246 # number of overall misses 253system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles 254system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles 255system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles 256system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles 257system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles 258system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles 259system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # number of demand (read+write) miss cycles 260system.cpu.dcache.demand_miss_latency::total 14169509500 # number of demand (read+write) miss cycles 261system.cpu.dcache.overall_miss_latency::cpu.data 14169509500 # number of overall miss cycles 262system.cpu.dcache.overall_miss_latency::total 14169509500 # number of overall miss cycles 263system.cpu.dcache.ReadReq_accesses::cpu.data 13564965 # number of ReadReq accesses(hits+misses) 264system.cpu.dcache.ReadReq_accesses::total 13564965 # number of ReadReq accesses(hits+misses) 265system.cpu.dcache.WriteReq_accesses::cpu.data 10224291 # number of WriteReq accesses(hits+misses) 266system.cpu.dcache.WriteReq_accesses::total 10224291 # number of WriteReq accesses(hits+misses) |
| 267system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) 268system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) 269system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) 270system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) | 267system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) 268system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) 269system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) 270system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) |
| 271system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses 272system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses 273system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses 274system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses 275system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses 276system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses 277system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses 278system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses 279system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses 280system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses 281system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses 282system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses 283system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses 284system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses 285system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency 286system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency 288system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency 289system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency 290system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency 291system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency 292system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency 293system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency 294system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency | 271system.cpu.dcache.demand_accesses::cpu.data 23789256 # number of demand (read+write) accesses 272system.cpu.dcache.demand_accesses::total 23789256 # number of demand (read+write) accesses 273system.cpu.dcache.overall_accesses::cpu.data 23789256 # number of overall (read+write) accesses 274system.cpu.dcache.overall_accesses::total 23789256 # number of overall (read+write) accesses 275system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027180 # miss rate for ReadReq accesses 276system.cpu.dcache.ReadReq_miss_rate::total 0.027180 # miss rate for ReadReq accesses 277system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024505 # miss rate for WriteReq accesses 278system.cpu.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses 279system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046013 # miss rate for LoadLockedReq accesses 280system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046013 # miss rate for LoadLockedReq accesses 281system.cpu.dcache.demand_miss_rate::cpu.data 0.026030 # miss rate for demand accesses 282system.cpu.dcache.demand_miss_rate::total 0.026030 # miss rate for demand accesses 283system.cpu.dcache.overall_miss_rate::cpu.data 0.026030 # miss rate for overall accesses 284system.cpu.dcache.overall_miss_rate::total 0.026030 # miss rate for overall accesses 285system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.455941 # average ReadReq miss latency 286system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.455941 # average ReadReq miss latency 287system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35797.044068 # average WriteReq miss latency 288system.cpu.dcache.WriteReq_avg_miss_latency::total 35797.044068 # average WriteReq miss latency 289system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.573309 # average LoadLockedReq miss latency 290system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.573309 # average LoadLockedReq miss latency 291system.cpu.dcache.demand_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency 292system.cpu.dcache.demand_avg_miss_latency::total 22881.874893 # average overall miss latency 293system.cpu.dcache.overall_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency 294system.cpu.dcache.overall_avg_miss_latency::total 22881.874893 # average overall miss latency |
| 295system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 296system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 297system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 300system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 301system.cpu.dcache.fast_writes 0 # number of fast writes performed 302system.cpu.dcache.cache_copies 0 # number of cache copies performed | 295system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 296system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 297system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 300system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 301system.cpu.dcache.fast_writes 0 # number of fast writes performed 302system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 303system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks 304system.cpu.dcache.writebacks::total 595968 # number of writebacks 305system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses 306system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses 307system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses 308system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses 309system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses 310system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses 311system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses 312system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses 313system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses 314system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses 315system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles 316system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles 317system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles 318system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles 319system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles 320system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles 321system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles 322system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles 323system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles 324system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles 325system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles 326system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles 327system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles 328system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles 329system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles 330system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles 331system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses 332system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses 333system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses 334system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024501 # mshr miss rate for WriteReq accesses 335system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046025 # mshr miss rate for LoadLockedReq accesses 336system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046025 # mshr miss rate for LoadLockedReq accesses 337system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for demand accesses 338system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses 339system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses 340system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses 341system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency 342system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency 343system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency 344system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency 345system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency 346system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency 347system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency 348system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency 349system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency 350system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency | 303system.cpu.dcache.writebacks::writebacks 595999 # number of writebacks 304system.cpu.dcache.writebacks::total 595999 # number of writebacks 305system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368699 # number of ReadReq MSHR misses 306system.cpu.dcache.ReadReq_mshr_misses::total 368699 # number of ReadReq MSHR misses 307system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250547 # number of WriteReq MSHR misses 308system.cpu.dcache.WriteReq_mshr_misses::total 250547 # number of WriteReq MSHR misses 309system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11397 # number of LoadLockedReq MSHR misses 310system.cpu.dcache.LoadLockedReq_mshr_misses::total 11397 # number of LoadLockedReq MSHR misses 311system.cpu.dcache.demand_mshr_misses::cpu.data 619246 # number of demand (read+write) MSHR misses 312system.cpu.dcache.demand_mshr_misses::total 619246 # number of demand (read+write) MSHR misses 313system.cpu.dcache.overall_mshr_misses::cpu.data 619246 # number of overall MSHR misses 314system.cpu.dcache.overall_mshr_misses::total 619246 # number of overall MSHR misses 315system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463269500 # number of ReadReq MSHR miss cycles 316system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463269500 # number of ReadReq MSHR miss cycles 317system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8467748000 # number of WriteReq MSHR miss cycles 318system.cpu.dcache.WriteReq_mshr_miss_latency::total 8467748000 # number of WriteReq MSHR miss cycles 319system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131961000 # number of LoadLockedReq MSHR miss cycles 320system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131961000 # number of LoadLockedReq MSHR miss cycles 321system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931017500 # number of demand (read+write) MSHR miss cycles 322system.cpu.dcache.demand_mshr_miss_latency::total 12931017500 # number of demand (read+write) MSHR miss cycles 323system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931017500 # number of overall MSHR miss cycles 324system.cpu.dcache.overall_mshr_miss_latency::total 12931017500 # number of overall MSHR miss cycles 325system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182084322500 # number of ReadReq MSHR uncacheable cycles 326system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182084322500 # number of ReadReq MSHR uncacheable cycles 327system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41323476000 # number of WriteReq MSHR uncacheable cycles 328system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41323476000 # number of WriteReq MSHR uncacheable cycles 329system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223407798500 # number of overall MSHR uncacheable cycles 330system.cpu.dcache.overall_mshr_uncacheable_latency::total 223407798500 # number of overall MSHR uncacheable cycles 331system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027180 # mshr miss rate for ReadReq accesses 332system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027180 # mshr miss rate for ReadReq accesses 333system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses 334system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses 335system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046013 # mshr miss rate for LoadLockedReq accesses 336system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046013 # mshr miss rate for LoadLockedReq accesses 337system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for demand accesses 338system.cpu.dcache.demand_mshr_miss_rate::total 0.026030 # mshr miss rate for demand accesses 339system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for overall accesses 340system.cpu.dcache.overall_mshr_miss_rate::total 0.026030 # mshr miss rate for overall accesses 341system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.455941 # average ReadReq mshr miss latency 342system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.455941 # average ReadReq mshr miss latency 343system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33797.044068 # average WriteReq mshr miss latency 344system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33797.044068 # average WriteReq mshr miss latency 345system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.573309 # average LoadLockedReq mshr miss latency 346system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.573309 # average LoadLockedReq mshr miss latency 347system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency 348system.cpu.dcache.demand_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency 349system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency 350system.cpu.dcache.overall_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency |
| 351system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 352system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 353system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 354system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 355system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 356system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 357system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 351system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 352system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 353system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 354system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 355system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 356system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 357system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 358system.cpu.l2cache.replacements 61913 # number of replacements 359system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use 360system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks. 361system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. 362system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks. 363system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit. 364system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor 365system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor | 358system.cpu.l2cache.replacements 61916 # number of replacements 359system.cpu.l2cache.tagsinuse 50867.720143 # Cycle average of tags in use 360system.cpu.l2cache.total_refs 1683066 # Total number of references to valid blocks. 361system.cpu.l2cache.sampled_refs 127296 # Sample count of references to valid blocks. 362system.cpu.l2cache.avg_refs 13.221672 # Average number of references to valid blocks. 363system.cpu.l2cache.warmup_cycle 2574019400000 # Cycle when the warmup percentage was hit. 364system.cpu.l2cache.occ_blocks::writebacks 37864.952088 # Average occupied blocks per requestor 365system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885583 # Average occupied blocks per requestor |
| 366system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor | 366system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor |
| 367system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor 368system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor 369system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy | 367system.cpu.l2cache.occ_blocks::cpu.inst 6985.681192 # Average occupied blocks per requestor 368system.cpu.l2cache.occ_blocks::cpu.data 6013.199864 # Average occupied blocks per requestor 369system.cpu.l2cache.occ_percent::writebacks 0.577773 # Average percentage of cache occupancy |
| 370system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 371system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 372system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy | 370system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 371system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 372system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy |
| 373system.cpu.l2cache.occ_percent::cpu.data 0.091768 # Average percentage of cache occupancy 374system.cpu.l2cache.occ_percent::total 0.776184 # Average percentage of cache occupancy 375system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits 376system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits 377system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits 378system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits 379system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits 380system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits 381system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits | 373system.cpu.l2cache.occ_percent::cpu.data 0.091754 # Average percentage of cache occupancy 374system.cpu.l2cache.occ_percent::total 0.776180 # Average percentage of cache occupancy 375system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8772 # number of ReadReq hits 376system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits 377system.cpu.l2cache.ReadReq_hits::cpu.inst 844153 # number of ReadReq hits 378system.cpu.l2cache.ReadReq_hits::cpu.data 370237 # number of ReadReq hits 379system.cpu.l2cache.ReadReq_hits::total 1226711 # number of ReadReq hits 380system.cpu.l2cache.Writeback_hits::writebacks 595999 # number of Writeback hits 381system.cpu.l2cache.Writeback_hits::total 595999 # number of Writeback hits |
| 382system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 383system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits | 382system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 383system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits |
| 384system.cpu.l2cache.ReadExReq_hits::cpu.data 114435 # number of ReadExReq hits 385system.cpu.l2cache.ReadExReq_hits::total 114435 # number of ReadExReq hits 386system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits 387system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits 388system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits 389system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits 390system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits 391system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits 392system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits 393system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits 394system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits 395system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits | 384system.cpu.l2cache.ReadExReq_hits::cpu.data 114469 # number of ReadExReq hits 385system.cpu.l2cache.ReadExReq_hits::total 114469 # number of ReadExReq hits 386system.cpu.l2cache.demand_hits::cpu.dtb.walker 8772 # number of demand (read+write) hits 387system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits 388system.cpu.l2cache.demand_hits::cpu.inst 844153 # number of demand (read+write) hits 389system.cpu.l2cache.demand_hits::cpu.data 484706 # number of demand (read+write) hits 390system.cpu.l2cache.demand_hits::total 1341180 # number of demand (read+write) hits 391system.cpu.l2cache.overall_hits::cpu.dtb.walker 8772 # number of overall hits 392system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits 393system.cpu.l2cache.overall_hits::cpu.inst 844153 # number of overall hits 394system.cpu.l2cache.overall_hits::cpu.data 484706 # number of overall hits 395system.cpu.l2cache.overall_hits::total 1341180 # number of overall hits |
| 396system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 397system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 398system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses | 396system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 397system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 398system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses |
| 399system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses 400system.cpu.l2cache.ReadReq_misses::total 20481 # number of ReadReq misses | 399system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses 400system.cpu.l2cache.ReadReq_misses::total 20482 # number of ReadReq misses |
| 401system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses 402system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses | 401system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses 402system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses |
| 403system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses 404system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses | 403system.cpu.l2cache.ReadExReq_misses::cpu.data 133179 # number of ReadExReq misses 404system.cpu.l2cache.ReadExReq_misses::total 133179 # number of ReadExReq misses |
| 405system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 406system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 407system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses | 405system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 406system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 407system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses |
| 408system.cpu.l2cache.demand_misses::cpu.data 143034 # number of demand (read+write) misses 409system.cpu.l2cache.demand_misses::total 153657 # number of demand (read+write) misses | 408system.cpu.l2cache.demand_misses::cpu.data 143038 # number of demand (read+write) misses 409system.cpu.l2cache.demand_misses::total 153661 # number of demand (read+write) misses |
| 410system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 411system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 412system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses | 410system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 411system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 412system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses |
| 413system.cpu.l2cache.overall_misses::cpu.data 143034 # number of overall misses 414system.cpu.l2cache.overall_misses::total 153657 # number of overall misses | 413system.cpu.l2cache.overall_misses::cpu.data 143038 # number of overall misses 414system.cpu.l2cache.overall_misses::total 153661 # number of overall misses |
| 415system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles 416system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles | 415system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles 416system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles |
| 417system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles 418system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles 419system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles 420system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles 421system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles 422system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles 423system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles | 417system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 552086500 # number of ReadReq miss cycles 418system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512764500 # number of ReadReq miss cycles 419system.cpu.l2cache.ReadReq_miss_latency::total 1065268500 # number of ReadReq miss cycles 420system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1041000 # number of UpgradeReq miss cycles 421system.cpu.l2cache.UpgradeReq_miss_latency::total 1041000 # number of UpgradeReq miss cycles 422system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6925666500 # number of ReadExReq miss cycles 423system.cpu.l2cache.ReadExReq_miss_latency::total 6925666500 # number of ReadExReq miss cycles |
| 424system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles 425system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles | 424system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles 425system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles |
| 426system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles 427system.cpu.l2cache.demand_miss_latency::cpu.data 7447598500 # number of demand (read+write) miss cycles 428system.cpu.l2cache.demand_miss_latency::total 8001378500 # number of demand (read+write) miss cycles | 426system.cpu.l2cache.demand_miss_latency::cpu.inst 552086500 # number of demand (read+write) miss cycles 427system.cpu.l2cache.demand_miss_latency::cpu.data 7438431000 # number of demand (read+write) miss cycles 428system.cpu.l2cache.demand_miss_latency::total 7990935000 # number of demand (read+write) miss cycles |
| 429system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles 430system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles | 429system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles 430system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles |
| 431system.cpu.l2cache.overall_miss_latency::cpu.inst 553362500 # number of overall miss cycles 432system.cpu.l2cache.overall_miss_latency::cpu.data 7447598500 # number of overall miss cycles 433system.cpu.l2cache.overall_miss_latency::total 8001378500 # number of overall miss cycles 434system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses) 435system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses) 436system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses) 437system.cpu.l2cache.ReadReq_accesses::cpu.data 380104 # number of ReadReq accesses(hits+misses) 438system.cpu.l2cache.ReadReq_accesses::total 1247179 # number of ReadReq accesses(hits+misses) 439system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses) 440system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses) | 431system.cpu.l2cache.overall_miss_latency::cpu.inst 552086500 # number of overall miss cycles 432system.cpu.l2cache.overall_miss_latency::cpu.data 7438431000 # number of overall miss cycles 433system.cpu.l2cache.overall_miss_latency::total 7990935000 # number of overall miss cycles 434system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8777 # number of ReadReq accesses(hits+misses) 435system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3552 # number of ReadReq accesses(hits+misses) 436system.cpu.l2cache.ReadReq_accesses::cpu.inst 854768 # number of ReadReq accesses(hits+misses) 437system.cpu.l2cache.ReadReq_accesses::cpu.data 380096 # number of ReadReq accesses(hits+misses) 438system.cpu.l2cache.ReadReq_accesses::total 1247193 # number of ReadReq accesses(hits+misses) 439system.cpu.l2cache.Writeback_accesses::writebacks 595999 # number of Writeback accesses(hits+misses) 440system.cpu.l2cache.Writeback_accesses::total 595999 # number of Writeback accesses(hits+misses) |
| 441system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) 442system.cpu.l2cache.UpgradeReq_accesses::total 2899 # number of UpgradeReq accesses(hits+misses) | 441system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) 442system.cpu.l2cache.UpgradeReq_accesses::total 2899 # number of UpgradeReq accesses(hits+misses) |
| 443system.cpu.l2cache.ReadExReq_accesses::cpu.data 247611 # number of ReadExReq accesses(hits+misses) 444system.cpu.l2cache.ReadExReq_accesses::total 247611 # number of ReadExReq accesses(hits+misses) 445system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses 446system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses 447system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses 448system.cpu.l2cache.demand_accesses::cpu.data 627715 # number of demand (read+write) accesses 449system.cpu.l2cache.demand_accesses::total 1494790 # number of demand (read+write) accesses 450system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses 451system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses 452system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses 453system.cpu.l2cache.overall_accesses::cpu.data 627715 # number of overall (read+write) accesses 454system.cpu.l2cache.overall_accesses::total 1494790 # number of overall (read+write) accesses | 443system.cpu.l2cache.ReadExReq_accesses::cpu.data 247648 # number of ReadExReq accesses(hits+misses) 444system.cpu.l2cache.ReadExReq_accesses::total 247648 # number of ReadExReq accesses(hits+misses) 445system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8777 # number of demand (read+write) accesses 446system.cpu.l2cache.demand_accesses::cpu.itb.walker 3552 # number of demand (read+write) accesses 447system.cpu.l2cache.demand_accesses::cpu.inst 854768 # number of demand (read+write) accesses 448system.cpu.l2cache.demand_accesses::cpu.data 627744 # number of demand (read+write) accesses 449system.cpu.l2cache.demand_accesses::total 1494841 # number of demand (read+write) accesses 450system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8777 # number of overall (read+write) accesses 451system.cpu.l2cache.overall_accesses::cpu.itb.walker 3552 # number of overall (read+write) accesses 452system.cpu.l2cache.overall_accesses::cpu.inst 854768 # number of overall (read+write) accesses 453system.cpu.l2cache.overall_accesses::cpu.data 627744 # number of overall (read+write) accesses 454system.cpu.l2cache.overall_accesses::total 1494841 # number of overall (read+write) accesses |
| 455system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses | 455system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses |
| 456system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses | 456system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses |
| 457system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses | 457system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses |
| 458system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025935 # miss rate for ReadReq accesses | 458system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025938 # miss rate for ReadReq accesses |
| 459system.cpu.l2cache.ReadReq_miss_rate::total 0.016422 # miss rate for ReadReq accesses 460system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991031 # miss rate for UpgradeReq accesses 461system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991031 # miss rate for UpgradeReq accesses | 459system.cpu.l2cache.ReadReq_miss_rate::total 0.016422 # miss rate for ReadReq accesses 460system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991031 # miss rate for UpgradeReq accesses 461system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991031 # miss rate for UpgradeReq accesses |
| 462system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537844 # miss rate for ReadExReq accesses 463system.cpu.l2cache.ReadExReq_miss_rate::total 0.537844 # miss rate for ReadExReq accesses | 462system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537775 # miss rate for ReadExReq accesses 463system.cpu.l2cache.ReadExReq_miss_rate::total 0.537775 # miss rate for ReadExReq accesses |
| 464system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000570 # miss rate for demand accesses | 464system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000570 # miss rate for demand accesses |
| 465system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000844 # miss rate for demand accesses | 465system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses |
| 466system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012419 # miss rate for demand accesses | 466system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012419 # miss rate for demand accesses |
| 467system.cpu.l2cache.demand_miss_rate::cpu.data 0.227865 # miss rate for demand accesses 468system.cpu.l2cache.demand_miss_rate::total 0.102795 # miss rate for demand accesses | 467system.cpu.l2cache.demand_miss_rate::cpu.data 0.227860 # miss rate for demand accesses 468system.cpu.l2cache.demand_miss_rate::total 0.102794 # miss rate for demand accesses |
| 469system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000570 # miss rate for overall accesses | 469system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000570 # miss rate for overall accesses |
| 470system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000844 # miss rate for overall accesses | 470system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses |
| 471system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012419 # miss rate for overall accesses | 471system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012419 # miss rate for overall accesses |
| 472system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865 # miss rate for overall accesses 473system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses | 472system.cpu.l2cache.overall_miss_rate::cpu.data 0.227860 # miss rate for overall accesses 473system.cpu.l2cache.overall_miss_rate::total 0.102794 # miss rate for overall accesses |
| 474system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency 475system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency | 474system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency 475system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency |
| 476system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52130.240226 # average ReadReq miss latency 477system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52051.886792 # average ReadReq miss latency 478system.cpu.l2cache.ReadReq_avg_miss_latency::total 52092.549192 # average ReadReq miss latency 479system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency 480system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency 481system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52069.975071 # average ReadExReq miss latency 482system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52069.975071 # average ReadExReq miss latency | 476system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52010.032972 # average ReadReq miss latency 477system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.788011 # average ReadReq miss latency 478system.cpu.l2cache.ReadReq_avg_miss_latency::total 52009.984377 # average ReadReq miss latency 479system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 362.339018 # average UpgradeReq miss latency 480system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 362.339018 # average UpgradeReq miss latency 481system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52002.691866 # average ReadExReq miss latency 482system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52002.691866 # average ReadExReq miss latency |
| 483system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency 484system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency | 483system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency 484system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency |
| 485system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency 486system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency 487system.cpu.l2cache.demand_avg_miss_latency::total 52072.983984 # average overall miss latency | 485system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency 486system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency 487system.cpu.l2cache.demand_avg_miss_latency::total 52003.663910 # average overall miss latency |
| 488system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency 489system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency | 488system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency 489system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency |
| 490system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency 491system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency 492system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency | 490system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency 491system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency 492system.cpu.l2cache.overall_avg_miss_latency::total 52003.663910 # average overall miss latency |
| 493system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 494system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 495system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 496system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 497system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 498system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 499system.cpu.l2cache.fast_writes 0 # number of fast writes performed 500system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 493system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 494system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 495system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 496system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 497system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 498system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 499system.cpu.l2cache.fast_writes 0 # number of fast writes performed 500system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 501system.cpu.l2cache.writebacks::writebacks 57452 # number of writebacks 502system.cpu.l2cache.writebacks::total 57452 # number of writebacks | 501system.cpu.l2cache.writebacks::writebacks 57455 # number of writebacks 502system.cpu.l2cache.writebacks::total 57455 # number of writebacks |
| 503system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 504system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses 505system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses | 503system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 504system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses 505system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses |
| 506system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses 507system.cpu.l2cache.ReadReq_mshr_misses::total 20481 # number of ReadReq MSHR misses | 506system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses 507system.cpu.l2cache.ReadReq_mshr_misses::total 20482 # number of ReadReq MSHR misses |
| 508system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses 509system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses | 508system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses 509system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses |
| 510system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses 511system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses | 510system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133179 # number of ReadExReq MSHR misses 511system.cpu.l2cache.ReadExReq_mshr_misses::total 133179 # number of ReadExReq MSHR misses |
| 512system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 513system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses 514system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses | 512system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 513system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses 514system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses |
| 515system.cpu.l2cache.demand_mshr_misses::cpu.data 143034 # number of demand (read+write) MSHR misses 516system.cpu.l2cache.demand_mshr_misses::total 153657 # number of demand (read+write) MSHR misses | 515system.cpu.l2cache.demand_mshr_misses::cpu.data 143038 # number of demand (read+write) MSHR misses 516system.cpu.l2cache.demand_mshr_misses::total 153661 # number of demand (read+write) MSHR misses |
| 517system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 518system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses 519system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses | 517system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 518system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses 519system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses |
| 520system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 # number of overall MSHR misses 521system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses | 520system.cpu.l2cache.overall_mshr_misses::cpu.data 143038 # number of overall MSHR misses 521system.cpu.l2cache.overall_mshr_misses::total 153661 # number of overall MSHR misses |
| 522system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles 523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles | 522system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles 523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles |
| 524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425912000 # number of ReadReq MSHR miss cycles 525system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394750500 # number of ReadReq MSHR miss cycles 526system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820982500 # number of ReadReq MSHR miss cycles 527system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115023000 # number of UpgradeReq MSHR miss cycles 528system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115023000 # number of UpgradeReq MSHR miss cycles 529system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5336288000 # number of ReadExReq MSHR miss cycles 530system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5336288000 # number of ReadExReq MSHR miss cycles | 524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 424634000 # number of ReadReq MSHR miss cycles 525system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394375000 # number of ReadReq MSHR miss cycles 526system.cpu.l2cache.ReadReq_mshr_miss_latency::total 819329000 # number of ReadReq MSHR miss cycles 527system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114934000 # number of UpgradeReq MSHR miss cycles 528system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114934000 # number of UpgradeReq MSHR miss cycles 529system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5327448000 # number of ReadExReq MSHR miss cycles 530system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5327448000 # number of ReadExReq MSHR miss cycles |
| 531system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles 532system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles | 531system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles 532system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles |
| 533system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425912000 # number of demand (read+write) MSHR miss cycles 534system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5731038500 # number of demand (read+write) MSHR miss cycles 535system.cpu.l2cache.demand_mshr_miss_latency::total 6157270500 # number of demand (read+write) MSHR miss cycles | 533system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 424634000 # number of demand (read+write) MSHR miss cycles 534system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5721823000 # number of demand (read+write) MSHR miss cycles 535system.cpu.l2cache.demand_mshr_miss_latency::total 6146777000 # number of demand (read+write) MSHR miss cycles |
| 536system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles 537system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles | 536system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles 537system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles |
| 538system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425912000 # number of overall MSHR miss cycles 539system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5731038500 # number of overall MSHR miss cycles 540system.cpu.l2cache.overall_mshr_miss_latency::total 6157270500 # number of overall MSHR miss cycles | 538system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 424634000 # number of overall MSHR miss cycles 539system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5721823000 # number of overall MSHR miss cycles 540system.cpu.l2cache.overall_mshr_miss_latency::total 6146777000 # number of overall MSHR miss cycles |
| 541system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles | 541system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles |
| 542system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763232500 # number of ReadReq MSHR uncacheable cycles 543system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028072500 # number of ReadReq MSHR uncacheable cycles 544system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856015000 # number of WriteReq MSHR uncacheable cycles 545system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856015000 # number of WriteReq MSHR uncacheable cycles | 542system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166685236000 # number of ReadReq MSHR uncacheable cycles 543system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166950076000 # number of ReadReq MSHR uncacheable cycles 544system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31792706500 # number of WriteReq MSHR uncacheable cycles 545system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31792706500 # number of WriteReq MSHR uncacheable cycles |
| 546system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles | 546system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles |
| 547system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198619247500 # number of overall MSHR uncacheable cycles 548system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198884087500 # number of overall MSHR uncacheable cycles | 547system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198477942500 # number of overall MSHR uncacheable cycles 548system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198742782500 # number of overall MSHR uncacheable cycles |
| 549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses | 549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses |
| 550system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses | 550system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses |
| 551system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses | 551system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses |
| 552system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses | 552system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025938 # mshr miss rate for ReadReq accesses |
| 553system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses 554system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses 555system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses | 553system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses 554system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses 555system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses |
| 556system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses 557system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses | 556system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537775 # mshr miss rate for ReadExReq accesses 557system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537775 # mshr miss rate for ReadExReq accesses |
| 558system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses | 558system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses |
| 559system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses | 559system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses |
| 560system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses | 560system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses |
| 561system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses 562system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses | 561system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses 562system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses |
| 563system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses | 563system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses |
| 564system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses | 564system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses |
| 565system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses | 565system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses |
| 566system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses 567system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses | 566system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses 567system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses |
| 568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency | 568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency |
| 570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency 573system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency 574system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency 575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency 576system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency | 570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency 571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency 572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency 573system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency 574system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency 575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency 576system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency |
| 577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 578system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency | 577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 578system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency |
| 579system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency 580system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency | 579system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency 580system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency 581system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency |
| 582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency | 582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency |
| 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency | 584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency 585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency 586system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency |
| 587system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 588system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 589system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 590system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 591system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 592system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 593system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 594system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 7 unchanged lines hidden (view full) --- 602system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 603system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 604system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 605system.iocache.blocked::no_targets 0 # number of cycles access was blocked 606system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 607system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 608system.iocache.fast_writes 0 # number of fast writes performed 609system.iocache.cache_copies 0 # number of cache copies performed | 587system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 588system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 589system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 590system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 591system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 592system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 593system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 594system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 7 unchanged lines hidden (view full) --- 602system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 603system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 604system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 605system.iocache.blocked::no_targets 0 # number of cycles access was blocked 606system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 607system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 608system.iocache.fast_writes 0 # number of fast writes performed 609system.iocache.cache_copies 0 # number of cache copies performed |
| 610system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles 611system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles 612system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles 613system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles | 610system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles 611system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles 612system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles 613system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles |
| 614system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 615system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 616system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 617system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 618system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 619 620---------- End Simulation Statistics ---------- | 614system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 615system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 616system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 617system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 618system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 619 620---------- End Simulation Statistics ---------- |