1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 2.629150 # Number of seconds simulated
4sim_ticks 2629149747000 # Number of ticks simulated
5final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 2.624688 # Number of seconds simulated
4sim_ticks 2624688029000 # Number of ticks simulated
5final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 556259 # Simulator instruction rate (inst/s)
8host_op_rate 707830 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 24290841486 # Simulator tick rate (ticks/s)
10host_mem_usage 380276 # Number of bytes of host memory used
11host_seconds 108.24 # Real time elapsed on the host
12sim_insts 60207390 # Number of instructions simulated
13sim_ops 76612873 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory
19system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory
23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory
25system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory
32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s)
| 7host_inst_rate 388710 # Simulator instruction rate (inst/s)
8host_op_rate 494628 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 16947208284 # Simulator tick rate (ticks/s)
10host_mem_usage 385844 # Number of bytes of host memory used
11host_seconds 154.87 # Real time elapsed on the host
12sim_insts 60201138 # Number of instructions simulated
13sim_ops 76605123 # Number of ops (including micro ops) simulated
|
52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
60system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
63system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
| 14system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
15system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
16system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
17system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
18system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
19system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
20system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
21system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
22system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
23system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
24system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
25system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
64system.cpu.l2cache.replacements 62933 # number of replacements
65system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use
66system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks.
67system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks.
68system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks.
69system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit.
70system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor
71system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor
72system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor
73system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor
74system.cpu.l2cache.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor
75system.cpu.l2cache.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy
76system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy
77system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
78system.cpu.l2cache.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy
79system.cpu.l2cache.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy
80system.cpu.l2cache.occ_percent::total 0.791359 # Average percentage of cache occupancy
81system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits
82system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits
83system.cpu.l2cache.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits
84system.cpu.l2cache.ReadReq_hits::cpu.data 370308 # number of ReadReq hits
85system.cpu.l2cache.ReadReq_hits::total 1226888 # number of ReadReq hits
86system.cpu.l2cache.Writeback_hits::writebacks 596416 # number of Writeback hits
87system.cpu.l2cache.Writeback_hits::total 596416 # number of Writeback hits
88system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
89system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
90system.cpu.l2cache.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits
91system.cpu.l2cache.ReadExReq_hits::total 113846 # number of ReadExReq hits
92system.cpu.l2cache.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits
93system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits
94system.cpu.l2cache.demand_hits::cpu.inst 844195 # number of demand (read+write) hits
95system.cpu.l2cache.demand_hits::cpu.data 484154 # number of demand (read+write) hits
96system.cpu.l2cache.demand_hits::total 1340734 # number of demand (read+write) hits
97system.cpu.l2cache.overall_hits::cpu.dtb.walker 8836 # number of overall hits
98system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits
99system.cpu.l2cache.overall_hits::cpu.inst 844195 # number of overall hits
100system.cpu.l2cache.overall_hits::cpu.data 484154 # number of overall hits
101system.cpu.l2cache.overall_hits::total 1340734 # number of overall hits
102system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses
103system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
104system.cpu.l2cache.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses
105system.cpu.l2cache.ReadReq_misses::cpu.data 10261 # number of ReadReq misses
106system.cpu.l2cache.ReadReq_misses::total 20880 # number of ReadReq misses
107system.cpu.l2cache.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses
108system.cpu.l2cache.UpgradeReq_misses::total 2845 # number of UpgradeReq misses
109system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses
110system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses
111system.cpu.l2cache.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses
112system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
113system.cpu.l2cache.demand_misses::cpu.inst 10613 # number of demand (read+write) misses
114system.cpu.l2cache.demand_misses::cpu.data 144085 # number of demand (read+write) misses
115system.cpu.l2cache.demand_misses::total 154704 # number of demand (read+write) misses
116system.cpu.l2cache.overall_misses::cpu.dtb.walker 4 # number of overall misses
117system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
118system.cpu.l2cache.overall_misses::cpu.inst 10613 # number of overall misses
119system.cpu.l2cache.overall_misses::cpu.data 144085 # number of overall misses
120system.cpu.l2cache.overall_misses::total 154704 # number of overall misses
121system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles
122system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles
123system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles
124system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles
125system.cpu.l2cache.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles
126system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
127system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
128system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles
129system.cpu.l2cache.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles
130system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles
131system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles
132system.cpu.l2cache.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles
133system.cpu.l2cache.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles
134system.cpu.l2cache.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles
135system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles
136system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles
137system.cpu.l2cache.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles
138system.cpu.l2cache.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles
139system.cpu.l2cache.overall_miss_latency::total 8049111500 # number of overall miss cycles
140system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses)
141system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
142system.cpu.l2cache.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses)
143system.cpu.l2cache.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses)
144system.cpu.l2cache.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses)
145system.cpu.l2cache.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses)
146system.cpu.l2cache.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses)
147system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses)
148system.cpu.l2cache.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses)
149system.cpu.l2cache.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses)
150system.cpu.l2cache.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses)
151system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses
152system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
153system.cpu.l2cache.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses
154system.cpu.l2cache.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses
155system.cpu.l2cache.demand_accesses::total 1495438 # number of demand (read+write) accesses
156system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses
157system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
158system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses
159system.cpu.l2cache.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses
160system.cpu.l2cache.overall_accesses::total 1495438 # number of overall (read+write) accesses
161system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses
162system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses
163system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses
164system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses
165system.cpu.l2cache.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses
166system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses
167system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses
168system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses
169system.cpu.l2cache.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses
170system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses
171system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses
172system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses
173system.cpu.l2cache.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses
174system.cpu.l2cache.demand_miss_rate::total 0.103451 # miss rate for demand accesses
175system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses
176system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses
177system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses
178system.cpu.l2cache.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses
179system.cpu.l2cache.overall_miss_rate::total 0.103451 # miss rate for overall accesses
180system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
181system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
182system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency
183system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency
184system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency
185system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency
186system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency
187system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency
188system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency
189system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
190system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
191system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
192system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
193system.cpu.l2cache.demand_avg_miss_latency::total 52029.110430 # average overall miss latency
194system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
195system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
196system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
197system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
198system.cpu.l2cache.overall_avg_miss_latency::total 52029.110430 # average overall miss latency
199system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
200system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
201system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
202system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
203system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
204system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
205system.cpu.l2cache.fast_writes 0 # number of fast writes performed
206system.cpu.l2cache.cache_copies 0 # number of cache copies performed
207system.cpu.l2cache.writebacks::writebacks 58379 # number of writebacks
208system.cpu.l2cache.writebacks::total 58379 # number of writebacks
209system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses
210system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
211system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses
212system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses
213system.cpu.l2cache.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses
214system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses
215system.cpu.l2cache.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses
216system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses
217system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses
218system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses
219system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
220system.cpu.l2cache.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses
221system.cpu.l2cache.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses
222system.cpu.l2cache.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses
223system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses
224system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
225system.cpu.l2cache.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses
226system.cpu.l2cache.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses
227system.cpu.l2cache.overall_mshr_misses::total 154704 # number of overall MSHR misses
228system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles
229system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles
230system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles
231system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles
232system.cpu.l2cache.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles
233system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles
234system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles
235system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles
236system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles
237system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles
238system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
239system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles
240system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles
241system.cpu.l2cache.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles
242system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles
243system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles
244system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles
245system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles
246system.cpu.l2cache.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles
247system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
248system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles
249system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles
250system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles
251system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles
252system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
253system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles
254system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles
255system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses
256system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses
257system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses
258system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses
259system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses
260system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses
261system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses
262system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses
263system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses
264system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses
265system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses
266system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses
267system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses
268system.cpu.l2cache.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses
269system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses
270system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses
271system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses
272system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses
273system.cpu.l2cache.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses
274system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
275system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
276system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency
277system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency
278system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency
279system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency
280system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency
281system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency
282system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency
283system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
284system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
285system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
286system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
287system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
288system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
289system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
290system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
291system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
292system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
293system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
294system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
295system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
296system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
297system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
298system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
299system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
300system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
301system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 26system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
27system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
28system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
29system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory
30system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory
31system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory
32system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory
33system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory
34system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory
35system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
36system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory
37system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
45system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory
46system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s)
55system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s)
56system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s)
57system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s)
|
302system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
303system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
304system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
305system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
306system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
307system.cf0.dma_write_txs 0 # Number of DMA write transactions.
308system.cpu.dtb.inst_hits 0 # ITB inst hits
309system.cpu.dtb.inst_misses 0 # ITB inst misses
| 64system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
65system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
66system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
67system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
68system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
69system.cf0.dma_write_txs 0 # Number of DMA write transactions.
70system.cpu.dtb.inst_hits 0 # ITB inst hits
71system.cpu.dtb.inst_misses 0 # ITB inst misses
|
310system.cpu.dtb.read_hits 14998169 # DTB read hits
311system.cpu.dtb.read_misses 7372 # DTB read misses
312system.cpu.dtb.write_hits 11231565 # DTB write hits
313system.cpu.dtb.write_misses 2270 # DTB write misses
| 72system.cpu.dtb.read_hits 14996726 # DTB read hits
73system.cpu.dtb.read_misses 7357 # DTB read misses
74system.cpu.dtb.write_hits 11231612 # DTB write hits
75system.cpu.dtb.write_misses 2211 # DTB write misses
|
314system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
316system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
317system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
| 76system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
78system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
79system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
318system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
| 80system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB
|
319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
| 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
320system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch
| 82system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch
|
321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
322system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
| 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
323system.cpu.dtb.read_accesses 15005541 # DTB read accesses
324system.cpu.dtb.write_accesses 11233835 # DTB write accesses
| 85system.cpu.dtb.read_accesses 15004083 # DTB read accesses
86system.cpu.dtb.write_accesses 11233823 # DTB write accesses
|
325system.cpu.dtb.inst_accesses 0 # ITB inst accesses
| 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
326system.cpu.dtb.hits 26229734 # DTB hits
327system.cpu.dtb.misses 9642 # DTB misses
328system.cpu.dtb.accesses 26239376 # DTB accesses
329system.cpu.itb.inst_hits 61501359 # ITB inst hits
| 88system.cpu.dtb.hits 26228338 # DTB hits
89system.cpu.dtb.misses 9568 # DTB misses
90system.cpu.dtb.accesses 26237906 # DTB accesses
91system.cpu.itb.inst_hits 61495107 # ITB inst hits
|
330system.cpu.itb.inst_misses 4471 # ITB inst misses
331system.cpu.itb.read_hits 0 # DTB read hits
332system.cpu.itb.read_misses 0 # DTB read misses
333system.cpu.itb.write_hits 0 # DTB write hits
334system.cpu.itb.write_misses 0 # DTB write misses
335system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
336system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
337system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
338system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
339system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
340system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
341system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
342system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
343system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
344system.cpu.itb.read_accesses 0 # DTB read accesses
345system.cpu.itb.write_accesses 0 # DTB write accesses
| 92system.cpu.itb.inst_misses 4471 # ITB inst misses
93system.cpu.itb.read_hits 0 # DTB read hits
94system.cpu.itb.read_misses 0 # DTB read misses
95system.cpu.itb.write_hits 0 # DTB write hits
96system.cpu.itb.write_misses 0 # DTB write misses
97system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
98system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
99system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
100system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
101system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
102system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
103system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
104system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
105system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
106system.cpu.itb.read_accesses 0 # DTB read accesses
107system.cpu.itb.write_accesses 0 # DTB write accesses
|
346system.cpu.itb.inst_accesses 61505830 # ITB inst accesses
347system.cpu.itb.hits 61501359 # DTB hits
| 108system.cpu.itb.inst_accesses 61499578 # ITB inst accesses
109system.cpu.itb.hits 61495107 # DTB hits
|
348system.cpu.itb.misses 4471 # DTB misses
| 110system.cpu.itb.misses 4471 # DTB misses
|
349system.cpu.itb.accesses 61505830 # DTB accesses
350system.cpu.numCycles 5258299494 # number of cpu cycles simulated
| 111system.cpu.itb.accesses 61499578 # DTB accesses
112system.cpu.numCycles 5249376058 # number of cpu cycles simulated
|
351system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
352system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 113system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
114system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
353system.cpu.committedInsts 60207390 # Number of instructions committed
354system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed
355system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses
| 115system.cpu.committedInsts 60201138 # Number of instructions committed
116system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed
117system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses
|
356system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
| 118system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
357system.cpu.num_func_calls 2140176 # number of times a function call or return occured
358system.cpu.num_conditional_control_insts 7948958 # number of instructions that are conditional controls
359system.cpu.num_int_insts 68878830 # number of integer instructions
| 119system.cpu.num_func_calls 2139913 # number of times a function call or return occured
120system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls
121system.cpu.num_int_insts 68872510 # number of integer instructions
|
360system.cpu.num_fp_insts 10269 # number of float instructions
| 122system.cpu.num_fp_insts 10269 # number of float instructions
|
361system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read
362system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written
| 123system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read
124system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written
|
363system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
364system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
| 125system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
126system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
365system.cpu.num_mem_refs 27397151 # number of memory refs
366system.cpu.num_load_insts 15662227 # Number of load instructions
367system.cpu.num_store_insts 11734924 # Number of store instructions
368system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles
369system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles
370system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles
371system.cpu.idle_fraction 0.868680 # Percentage of idle cycles
| 127system.cpu.num_mem_refs 27395681 # number of memory refs
128system.cpu.num_load_insts 15660705 # Number of load instructions
129system.cpu.num_store_insts 11734976 # Number of store instructions
130system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles
131system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles
132system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles
133system.cpu.idle_fraction 0.871278 # Percentage of idle cycles
|
372system.cpu.kern.inst.arm 0 # number of arm instructions executed
| 134system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
373system.cpu.kern.inst.quiesce 83013 # number of quiesce instructions executed
374system.cpu.icache.replacements 855930 # number of replacements
375system.cpu.icache.tagsinuse 510.898307 # Cycle average of tags in use
376system.cpu.icache.total_refs 60644917 # Total number of references to valid blocks.
377system.cpu.icache.sampled_refs 856442 # Sample count of references to valid blocks.
378system.cpu.icache.avg_refs 70.810302 # Average number of references to valid blocks.
379system.cpu.icache.warmup_cycle 19819985000 # Cycle when the warmup percentage was hit.
380system.cpu.icache.occ_blocks::cpu.inst 510.898307 # Average occupied blocks per requestor
381system.cpu.icache.occ_percent::cpu.inst 0.997848 # Average percentage of cache occupancy
382system.cpu.icache.occ_percent::total 0.997848 # Average percentage of cache occupancy
383system.cpu.icache.ReadReq_hits::cpu.inst 60644917 # number of ReadReq hits
384system.cpu.icache.ReadReq_hits::total 60644917 # number of ReadReq hits
385system.cpu.icache.demand_hits::cpu.inst 60644917 # number of demand (read+write) hits
386system.cpu.icache.demand_hits::total 60644917 # number of demand (read+write) hits
387system.cpu.icache.overall_hits::cpu.inst 60644917 # number of overall hits
388system.cpu.icache.overall_hits::total 60644917 # number of overall hits
389system.cpu.icache.ReadReq_misses::cpu.inst 856442 # number of ReadReq misses
390system.cpu.icache.ReadReq_misses::total 856442 # number of ReadReq misses
391system.cpu.icache.demand_misses::cpu.inst 856442 # number of demand (read+write) misses
392system.cpu.icache.demand_misses::total 856442 # number of demand (read+write) misses
393system.cpu.icache.overall_misses::cpu.inst 856442 # number of overall misses
394system.cpu.icache.overall_misses::total 856442 # number of overall misses
395system.cpu.icache.ReadReq_miss_latency::cpu.inst 12566277500 # number of ReadReq miss cycles
396system.cpu.icache.ReadReq_miss_latency::total 12566277500 # number of ReadReq miss cycles
397system.cpu.icache.demand_miss_latency::cpu.inst 12566277500 # number of demand (read+write) miss cycles
398system.cpu.icache.demand_miss_latency::total 12566277500 # number of demand (read+write) miss cycles
399system.cpu.icache.overall_miss_latency::cpu.inst 12566277500 # number of overall miss cycles
400system.cpu.icache.overall_miss_latency::total 12566277500 # number of overall miss cycles
401system.cpu.icache.ReadReq_accesses::cpu.inst 61501359 # number of ReadReq accesses(hits+misses)
402system.cpu.icache.ReadReq_accesses::total 61501359 # number of ReadReq accesses(hits+misses)
403system.cpu.icache.demand_accesses::cpu.inst 61501359 # number of demand (read+write) accesses
404system.cpu.icache.demand_accesses::total 61501359 # number of demand (read+write) accesses
405system.cpu.icache.overall_accesses::cpu.inst 61501359 # number of overall (read+write) accesses
406system.cpu.icache.overall_accesses::total 61501359 # number of overall (read+write) accesses
| 135system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
136system.cpu.icache.replacements 855878 # number of replacements
137system.cpu.icache.tagsinuse 510.920723 # Cycle average of tags in use
138system.cpu.icache.total_refs 60638717 # Total number of references to valid blocks.
139system.cpu.icache.sampled_refs 856390 # Sample count of references to valid blocks.
140system.cpu.icache.avg_refs 70.807362 # Average number of references to valid blocks.
141system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit.
142system.cpu.icache.occ_blocks::cpu.inst 510.920723 # Average occupied blocks per requestor
143system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy
144system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy
145system.cpu.icache.ReadReq_hits::cpu.inst 60638717 # number of ReadReq hits
146system.cpu.icache.ReadReq_hits::total 60638717 # number of ReadReq hits
147system.cpu.icache.demand_hits::cpu.inst 60638717 # number of demand (read+write) hits
148system.cpu.icache.demand_hits::total 60638717 # number of demand (read+write) hits
149system.cpu.icache.overall_hits::cpu.inst 60638717 # number of overall hits
150system.cpu.icache.overall_hits::total 60638717 # number of overall hits
151system.cpu.icache.ReadReq_misses::cpu.inst 856390 # number of ReadReq misses
152system.cpu.icache.ReadReq_misses::total 856390 # number of ReadReq misses
153system.cpu.icache.demand_misses::cpu.inst 856390 # number of demand (read+write) misses
154system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses
155system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses
156system.cpu.icache.overall_misses::total 856390 # number of overall misses
157system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles
158system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles
159system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles
160system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles
161system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles
162system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles
163system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses)
164system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses)
165system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses
166system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses
167system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses
168system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses
|
407system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
408system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
409system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
410system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
411system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
412system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
| 169system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
170system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
171system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
172system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
173system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
174system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
|
413system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14672.654424 # average ReadReq miss latency
414system.cpu.icache.ReadReq_avg_miss_latency::total 14672.654424 # average ReadReq miss latency
415system.cpu.icache.demand_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency
416system.cpu.icache.demand_avg_miss_latency::total 14672.654424 # average overall miss latency
417system.cpu.icache.overall_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency
418system.cpu.icache.overall_avg_miss_latency::total 14672.654424 # average overall miss latency
| 175system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency
176system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency
177system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency
178system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency
179system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency
180system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency
|
419system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
420system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
421system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
422system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
423system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
424system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
425system.cpu.icache.fast_writes 0 # number of fast writes performed
426system.cpu.icache.cache_copies 0 # number of cache copies performed
| 181system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
182system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
183system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
184system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
185system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
186system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
187system.cpu.icache.fast_writes 0 # number of fast writes performed
188system.cpu.icache.cache_copies 0 # number of cache copies performed
|
427system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856442 # number of ReadReq MSHR misses
428system.cpu.icache.ReadReq_mshr_misses::total 856442 # number of ReadReq MSHR misses
429system.cpu.icache.demand_mshr_misses::cpu.inst 856442 # number of demand (read+write) MSHR misses
430system.cpu.icache.demand_mshr_misses::total 856442 # number of demand (read+write) MSHR misses
431system.cpu.icache.overall_mshr_misses::cpu.inst 856442 # number of overall MSHR misses
432system.cpu.icache.overall_mshr_misses::total 856442 # number of overall MSHR misses
433system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9995044500 # number of ReadReq MSHR miss cycles
434system.cpu.icache.ReadReq_mshr_miss_latency::total 9995044500 # number of ReadReq MSHR miss cycles
435system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9995044500 # number of demand (read+write) MSHR miss cycles
436system.cpu.icache.demand_mshr_miss_latency::total 9995044500 # number of demand (read+write) MSHR miss cycles
437system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9995044500 # number of overall MSHR miss cycles
438system.cpu.icache.overall_mshr_miss_latency::total 9995044500 # number of overall MSHR miss cycles
439system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
440system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
441system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
442system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
| 189system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856390 # number of ReadReq MSHR misses
190system.cpu.icache.ReadReq_mshr_misses::total 856390 # number of ReadReq MSHR misses
191system.cpu.icache.demand_mshr_misses::cpu.inst 856390 # number of demand (read+write) MSHR misses
192system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses
193system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses
194system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses
195system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852692500 # number of ReadReq MSHR miss cycles
196system.cpu.icache.ReadReq_mshr_miss_latency::total 9852692500 # number of ReadReq MSHR miss cycles
197system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852692500 # number of demand (read+write) MSHR miss cycles
198system.cpu.icache.demand_mshr_miss_latency::total 9852692500 # number of demand (read+write) MSHR miss cycles
199system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852692500 # number of overall MSHR miss cycles
200system.cpu.icache.overall_mshr_miss_latency::total 9852692500 # number of overall MSHR miss cycles
201system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles
202system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles
203system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles
204system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles
|
443system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses
444system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses
446system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
447system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
448system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
| 205system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses
206system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
207system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses
208system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
209system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
210system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
|
449system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.427770 # average ReadReq mshr miss latency
450system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.427770 # average ReadReq mshr miss latency
451system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency
452system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency
453system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency
454system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency
| 211system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.913065 # average ReadReq mshr miss latency
212system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.913065 # average ReadReq mshr miss latency
213system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency
214system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency
215system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency
216system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency
|
455system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
456system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
457system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
458system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
459system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 217system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
218system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
219system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
220system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
221system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
460system.cpu.dcache.replacements 627727 # number of replacements
461system.cpu.dcache.tagsinuse 511.877273 # Cycle average of tags in use
462system.cpu.dcache.total_refs 23657788 # Total number of references to valid blocks.
463system.cpu.dcache.sampled_refs 628239 # Sample count of references to valid blocks.
464system.cpu.dcache.avg_refs 37.657306 # Average number of references to valid blocks.
465system.cpu.dcache.warmup_cycle 661351000 # Cycle when the warmup percentage was hit.
466system.cpu.dcache.occ_blocks::cpu.data 511.877273 # Average occupied blocks per requestor
467system.cpu.dcache.occ_percent::cpu.data 0.999760 # Average percentage of cache occupancy
468system.cpu.dcache.occ_percent::total 0.999760 # Average percentage of cache occupancy
469system.cpu.dcache.ReadReq_hits::cpu.data 13196825 # number of ReadReq hits
470system.cpu.dcache.ReadReq_hits::total 13196825 # number of ReadReq hits
471system.cpu.dcache.WriteReq_hits::cpu.data 9973191 # number of WriteReq hits
472system.cpu.dcache.WriteReq_hits::total 9973191 # number of WriteReq hits
473system.cpu.dcache.LoadLockedReq_hits::cpu.data 236701 # number of LoadLockedReq hits
474system.cpu.dcache.LoadLockedReq_hits::total 236701 # number of LoadLockedReq hits
475system.cpu.dcache.StoreCondReq_hits::cpu.data 248200 # number of StoreCondReq hits
476system.cpu.dcache.StoreCondReq_hits::total 248200 # number of StoreCondReq hits
477system.cpu.dcache.demand_hits::cpu.data 23170016 # number of demand (read+write) hits
478system.cpu.dcache.demand_hits::total 23170016 # number of demand (read+write) hits
479system.cpu.dcache.overall_hits::cpu.data 23170016 # number of overall hits
480system.cpu.dcache.overall_hits::total 23170016 # number of overall hits
481system.cpu.dcache.ReadReq_misses::cpu.data 369069 # number of ReadReq misses
482system.cpu.dcache.ReadReq_misses::total 369069 # number of ReadReq misses
483system.cpu.dcache.WriteReq_misses::cpu.data 250541 # number of WriteReq misses
484system.cpu.dcache.WriteReq_misses::total 250541 # number of WriteReq misses
485system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses
486system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses
487system.cpu.dcache.demand_misses::cpu.data 619610 # number of demand (read+write) misses
488system.cpu.dcache.demand_misses::total 619610 # number of demand (read+write) misses
489system.cpu.dcache.overall_misses::cpu.data 619610 # number of overall misses
490system.cpu.dcache.overall_misses::total 619610 # number of overall misses
491system.cpu.dcache.ReadReq_miss_latency::cpu.data 5742174000 # number of ReadReq miss cycles
492system.cpu.dcache.ReadReq_miss_latency::total 5742174000 # number of ReadReq miss cycles
493system.cpu.dcache.WriteReq_miss_latency::cpu.data 9260838000 # number of WriteReq miss cycles
494system.cpu.dcache.WriteReq_miss_latency::total 9260838000 # number of WriteReq miss cycles
495system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170995500 # number of LoadLockedReq miss cycles
496system.cpu.dcache.LoadLockedReq_miss_latency::total 170995500 # number of LoadLockedReq miss cycles
497system.cpu.dcache.demand_miss_latency::cpu.data 15003012000 # number of demand (read+write) miss cycles
498system.cpu.dcache.demand_miss_latency::total 15003012000 # number of demand (read+write) miss cycles
499system.cpu.dcache.overall_miss_latency::cpu.data 15003012000 # number of overall miss cycles
500system.cpu.dcache.overall_miss_latency::total 15003012000 # number of overall miss cycles
501system.cpu.dcache.ReadReq_accesses::cpu.data 13565894 # number of ReadReq accesses(hits+misses)
502system.cpu.dcache.ReadReq_accesses::total 13565894 # number of ReadReq accesses(hits+misses)
503system.cpu.dcache.WriteReq_accesses::cpu.data 10223732 # number of WriteReq accesses(hits+misses)
504system.cpu.dcache.WriteReq_accesses::total 10223732 # number of WriteReq accesses(hits+misses)
505system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248201 # number of LoadLockedReq accesses(hits+misses)
506system.cpu.dcache.LoadLockedReq_accesses::total 248201 # number of LoadLockedReq accesses(hits+misses)
507system.cpu.dcache.StoreCondReq_accesses::cpu.data 248200 # number of StoreCondReq accesses(hits+misses)
508system.cpu.dcache.StoreCondReq_accesses::total 248200 # number of StoreCondReq accesses(hits+misses)
509system.cpu.dcache.demand_accesses::cpu.data 23789626 # number of demand (read+write) accesses
510system.cpu.dcache.demand_accesses::total 23789626 # number of demand (read+write) accesses
511system.cpu.dcache.overall_accesses::cpu.data 23789626 # number of overall (read+write) accesses
512system.cpu.dcache.overall_accesses::total 23789626 # number of overall (read+write) accesses
513system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027206 # miss rate for ReadReq accesses
514system.cpu.dcache.ReadReq_miss_rate::total 0.027206 # miss rate for ReadReq accesses
515system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024506 # miss rate for WriteReq accesses
516system.cpu.dcache.WriteReq_miss_rate::total 0.024506 # miss rate for WriteReq accesses
517system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046333 # miss rate for LoadLockedReq accesses
518system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046333 # miss rate for LoadLockedReq accesses
519system.cpu.dcache.demand_miss_rate::cpu.data 0.026045 # miss rate for demand accesses
520system.cpu.dcache.demand_miss_rate::total 0.026045 # miss rate for demand accesses
521system.cpu.dcache.overall_miss_rate::cpu.data 0.026045 # miss rate for overall accesses
522system.cpu.dcache.overall_miss_rate::total 0.026045 # miss rate for overall accesses
523system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15558.537834 # average ReadReq miss latency
524system.cpu.dcache.ReadReq_avg_miss_latency::total 15558.537834 # average ReadReq miss latency
525system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36963.363282 # average WriteReq miss latency
526system.cpu.dcache.WriteReq_avg_miss_latency::total 36963.363282 # average WriteReq miss latency
527system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14869.173913 # average LoadLockedReq miss latency
528system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14869.173913 # average LoadLockedReq miss latency
529system.cpu.dcache.demand_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency
530system.cpu.dcache.demand_avg_miss_latency::total 24213.637611 # average overall miss latency
531system.cpu.dcache.overall_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency
532system.cpu.dcache.overall_avg_miss_latency::total 24213.637611 # average overall miss latency
| 222system.cpu.dcache.replacements 627202 # number of replacements
223system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use
224system.cpu.dcache.total_refs 23656924 # Total number of references to valid blocks.
225system.cpu.dcache.sampled_refs 627714 # Sample count of references to valid blocks.
226system.cpu.dcache.avg_refs 37.687425 # Average number of references to valid blocks.
227system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit.
228system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor
229system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy
230system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy
231system.cpu.dcache.ReadReq_hits::cpu.data 13196261 # number of ReadReq hits
232system.cpu.dcache.ReadReq_hits::total 13196261 # number of ReadReq hits
233system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits
234system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits
235system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits
236system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits
237system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits
238system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits
239system.cpu.dcache.demand_hits::cpu.data 23170044 # number of demand (read+write) hits
240system.cpu.dcache.demand_hits::total 23170044 # number of demand (read+write) hits
241system.cpu.dcache.overall_hits::cpu.data 23170044 # number of overall hits
242system.cpu.dcache.overall_hits::total 23170044 # number of overall hits
243system.cpu.dcache.ReadReq_misses::cpu.data 368703 # number of ReadReq misses
244system.cpu.dcache.ReadReq_misses::total 368703 # number of ReadReq misses
245system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses
246system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses
247system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses
248system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses
249system.cpu.dcache.demand_misses::cpu.data 619213 # number of demand (read+write) misses
250system.cpu.dcache.demand_misses::total 619213 # number of demand (read+write) misses
251system.cpu.dcache.overall_misses::cpu.data 619213 # number of overall misses
252system.cpu.dcache.overall_misses::total 619213 # number of overall misses
253system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201080500 # number of ReadReq miss cycles
254system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles
255system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles
256system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles
257system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles
258system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles
259system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles
260system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles
261system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles
262system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles
263system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses)
264system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses)
265system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses)
266system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses)
267system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses)
268system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses)
269system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses)
270system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses)
271system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses
272system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses
273system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses
274system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses
275system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses
276system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses
277system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses
278system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses
279system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses
280system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses
281system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses
282system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses
283system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses
284system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses
285system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency
286system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency
287system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency
288system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency
289system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency
290system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency
291system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency
292system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency
293system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency
294system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency
|
533system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
534system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
535system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
536system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
537system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
538system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
539system.cpu.dcache.fast_writes 0 # number of fast writes performed
540system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 295system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
296system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
297system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
298system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
299system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
300system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
301system.cpu.dcache.fast_writes 0 # number of fast writes performed
302system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
541system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks
542system.cpu.dcache.writebacks::total 596416 # number of writebacks
543system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # number of ReadReq MSHR misses
544system.cpu.dcache.ReadReq_mshr_misses::total 369069 # number of ReadReq MSHR misses
545system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250541 # number of WriteReq MSHR misses
546system.cpu.dcache.WriteReq_mshr_misses::total 250541 # number of WriteReq MSHR misses
547system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses
548system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses
549system.cpu.dcache.demand_mshr_misses::cpu.data 619610 # number of demand (read+write) MSHR misses
550system.cpu.dcache.demand_mshr_misses::total 619610 # number of demand (read+write) MSHR misses
551system.cpu.dcache.overall_mshr_misses::cpu.data 619610 # number of overall MSHR misses
552system.cpu.dcache.overall_mshr_misses::total 619610 # number of overall MSHR misses
553system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4633803000 # number of ReadReq MSHR miss cycles
554system.cpu.dcache.ReadReq_mshr_miss_latency::total 4633803000 # number of ReadReq MSHR miss cycles
555system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509109000 # number of WriteReq MSHR miss cycles
556system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509109000 # number of WriteReq MSHR miss cycles
557system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136482000 # number of LoadLockedReq MSHR miss cycles
558system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136482000 # number of LoadLockedReq MSHR miss cycles
559system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13142912000 # number of demand (read+write) MSHR miss cycles
560system.cpu.dcache.demand_mshr_miss_latency::total 13142912000 # number of demand (read+write) MSHR miss cycles
561system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13142912000 # number of overall MSHR miss cycles
562system.cpu.dcache.overall_mshr_miss_latency::total 13142912000 # number of overall MSHR miss cycles
563system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500 # number of ReadReq MSHR uncacheable cycles
564system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500 # number of ReadReq MSHR uncacheable cycles
565system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41013343500 # number of WriteReq MSHR uncacheable cycles
566system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41013343500 # number of WriteReq MSHR uncacheable cycles
567system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000 # number of overall MSHR uncacheable cycles
568system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000 # number of overall MSHR uncacheable cycles
569system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027206 # mshr miss rate for ReadReq accesses
570system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027206 # mshr miss rate for ReadReq accesses
571system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses
572system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses
573system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046333 # mshr miss rate for LoadLockedReq accesses
574system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046333 # mshr miss rate for LoadLockedReq accesses
575system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for demand accesses
576system.cpu.dcache.demand_mshr_miss_rate::total 0.026045 # mshr miss rate for demand accesses
577system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for overall accesses
578system.cpu.dcache.overall_mshr_miss_rate::total 0.026045 # mshr miss rate for overall accesses
579system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953 # average ReadReq mshr miss latency
580system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency
581system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency
582system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency
583system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency
584system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency
585system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency
586system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency
587system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency
588system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency
| 303system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks
304system.cpu.dcache.writebacks::total 595968 # number of writebacks
305system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses
306system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses
307system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses
308system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
309system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses
310system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses
311system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses
312system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses
313system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses
314system.cpu.dcache.overall_mshr_misses::total 619213 # number of overall MSHR misses
315system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463674500 # number of ReadReq MSHR miss cycles
316system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463674500 # number of ReadReq MSHR miss cycles
317system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8475687500 # number of WriteReq MSHR miss cycles
318system.cpu.dcache.WriteReq_mshr_miss_latency::total 8475687500 # number of WriteReq MSHR miss cycles
319system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles
320system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles
321system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939362000 # number of demand (read+write) MSHR miss cycles
322system.cpu.dcache.demand_mshr_miss_latency::total 12939362000 # number of demand (read+write) MSHR miss cycles
323system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939362000 # number of overall MSHR miss cycles
324system.cpu.dcache.overall_mshr_miss_latency::total 12939362000 # number of overall MSHR miss cycles
325system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles
326system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles
327system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles
328system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles
329system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles
330system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles
331system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses
332system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses
333system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses
334system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024501 # mshr miss rate for WriteReq accesses
335system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046025 # mshr miss rate for LoadLockedReq accesses
336system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046025 # mshr miss rate for LoadLockedReq accesses
337system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for demand accesses
338system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses
339system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses
340system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses
341system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.423056 # average ReadReq mshr miss latency
342system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.423056 # average ReadReq mshr miss latency
343system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33833.729192 # average WriteReq mshr miss latency
344system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency
345system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency
346system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency
347system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency
348system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency
349system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency
350system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency
|
589system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
590system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
591system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
592system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
593system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
594system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
595system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 351system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
352system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
353system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
354system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
355system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
356system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
357system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
| 358system.cpu.l2cache.replacements 61913 # number of replacements
359system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use
360system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks.
361system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks.
362system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks.
363system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit.
364system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor
365system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor
366system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor
367system.cpu.l2cache.occ_blocks::cpu.inst 6985.667758 # Average occupied blocks per requestor
368system.cpu.l2cache.occ_blocks::cpu.data 6014.098399 # Average occupied blocks per requestor
369system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy
370system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
371system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
372system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy
373system.cpu.l2cache.occ_percent::cpu.data 0.091768 # Average percentage of cache occupancy
374system.cpu.l2cache.occ_percent::total 0.776184 # Average percentage of cache occupancy
375system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits
376system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits
377system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits
378system.cpu.l2cache.ReadReq_hits::cpu.data 370245 # number of ReadReq hits
379system.cpu.l2cache.ReadReq_hits::total 1226697 # number of ReadReq hits
380system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits
381system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits
382system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
383system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
384system.cpu.l2cache.ReadExReq_hits::cpu.data 114435 # number of ReadExReq hits
385system.cpu.l2cache.ReadExReq_hits::total 114435 # number of ReadExReq hits
386system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits
387system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits
388system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits
389system.cpu.l2cache.demand_hits::cpu.data 484680 # number of demand (read+write) hits
390system.cpu.l2cache.demand_hits::total 1341132 # number of demand (read+write) hits
391system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits
392system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits
393system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits
394system.cpu.l2cache.overall_hits::cpu.data 484680 # number of overall hits
395system.cpu.l2cache.overall_hits::total 1341132 # number of overall hits
396system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
397system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
398system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses
399system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses
400system.cpu.l2cache.ReadReq_misses::total 20481 # number of ReadReq misses
401system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses
402system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses
403system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses
404system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses
405system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
406system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
407system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses
408system.cpu.l2cache.demand_misses::cpu.data 143034 # number of demand (read+write) misses
409system.cpu.l2cache.demand_misses::total 153657 # number of demand (read+write) misses
410system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
411system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
412system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses
413system.cpu.l2cache.overall_misses::cpu.data 143034 # number of overall misses
414system.cpu.l2cache.overall_misses::total 153657 # number of overall misses
415system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles
416system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles
417system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553303500 # number of ReadReq miss cycles
418system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513115500 # number of ReadReq miss cycles
419system.cpu.l2cache.ReadReq_miss_latency::total 1066836500 # number of ReadReq miss cycles
420system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
421system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
422system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6933900000 # number of ReadExReq miss cycles
423system.cpu.l2cache.ReadExReq_miss_latency::total 6933900000 # number of ReadExReq miss cycles
424system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles
425system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles
426system.cpu.l2cache.demand_miss_latency::cpu.inst 553303500 # number of demand (read+write) miss cycles
427system.cpu.l2cache.demand_miss_latency::cpu.data 7447015500 # number of demand (read+write) miss cycles
428system.cpu.l2cache.demand_miss_latency::total 8000736500 # number of demand (read+write) miss cycles
429system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles
430system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles
431system.cpu.l2cache.overall_miss_latency::cpu.inst 553303500 # number of overall miss cycles
432system.cpu.l2cache.overall_miss_latency::cpu.data 7447015500 # number of overall miss cycles
433system.cpu.l2cache.overall_miss_latency::total 8000736500 # number of overall miss cycles
434system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses)
435system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses)
436system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses)
437system.cpu.l2cache.ReadReq_accesses::cpu.data 380103 # number of ReadReq accesses(hits+misses)
438system.cpu.l2cache.ReadReq_accesses::total 1247178 # number of ReadReq accesses(hits+misses)
439system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses)
440system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses)
441system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses)
442system.cpu.l2cache.UpgradeReq_accesses::total 2899 # number of UpgradeReq accesses(hits+misses)
443system.cpu.l2cache.ReadExReq_accesses::cpu.data 247611 # number of ReadExReq accesses(hits+misses)
444system.cpu.l2cache.ReadExReq_accesses::total 247611 # number of ReadExReq accesses(hits+misses)
445system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses
446system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses
447system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses
448system.cpu.l2cache.demand_accesses::cpu.data 627714 # number of demand (read+write) accesses
449system.cpu.l2cache.demand_accesses::total 1494789 # number of demand (read+write) accesses
450system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses
451system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses
452system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses
453system.cpu.l2cache.overall_accesses::cpu.data 627714 # number of overall (read+write) accesses
454system.cpu.l2cache.overall_accesses::total 1494789 # number of overall (read+write) accesses
455system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses
456system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses
457system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses
458system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025935 # miss rate for ReadReq accesses
459system.cpu.l2cache.ReadReq_miss_rate::total 0.016422 # miss rate for ReadReq accesses
460system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991031 # miss rate for UpgradeReq accesses
461system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991031 # miss rate for UpgradeReq accesses
462system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537844 # miss rate for ReadExReq accesses
463system.cpu.l2cache.ReadExReq_miss_rate::total 0.537844 # miss rate for ReadExReq accesses
464system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000570 # miss rate for demand accesses
465system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000844 # miss rate for demand accesses
466system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012419 # miss rate for demand accesses
467system.cpu.l2cache.demand_miss_rate::cpu.data 0.227865 # miss rate for demand accesses
468system.cpu.l2cache.demand_miss_rate::total 0.102795 # miss rate for demand accesses
469system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000570 # miss rate for overall accesses
470system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000844 # miss rate for overall accesses
471system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012419 # miss rate for overall accesses
472system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865 # miss rate for overall accesses
473system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses
474system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency
475system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
476system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52124.682054 # average ReadReq miss latency
477system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52050.669507 # average ReadReq miss latency
478system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.082564 # average ReadReq miss latency
479system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency
480system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency
481system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52065.687511 # average ReadExReq miss latency
482system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52065.687511 # average ReadExReq miss latency
483system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency
484system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
485system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency
486system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency
487system.cpu.l2cache.demand_avg_miss_latency::total 52068.805847 # average overall miss latency
488system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency
489system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
490system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency
491system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency
492system.cpu.l2cache.overall_avg_miss_latency::total 52068.805847 # average overall miss latency
493system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
494system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
495system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
496system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
497system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
498system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
499system.cpu.l2cache.fast_writes 0 # number of fast writes performed
500system.cpu.l2cache.cache_copies 0 # number of cache copies performed
501system.cpu.l2cache.writebacks::writebacks 57452 # number of writebacks
502system.cpu.l2cache.writebacks::total 57452 # number of writebacks
503system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
504system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
505system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses
506system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses
507system.cpu.l2cache.ReadReq_mshr_misses::total 20481 # number of ReadReq MSHR misses
508system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses
509system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses
510system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses
511system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses
512system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
513system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
514system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses
515system.cpu.l2cache.demand_mshr_misses::cpu.data 143034 # number of demand (read+write) MSHR misses
516system.cpu.l2cache.demand_mshr_misses::total 153657 # number of demand (read+write) MSHR misses
517system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
518system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
519system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses
520system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 # number of overall MSHR misses
521system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses
522system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles
523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles
524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425853000 # number of ReadReq MSHR miss cycles
525system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394738000 # number of ReadReq MSHR miss cycles
526system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820911000 # number of ReadReq MSHR miss cycles
527system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115017000 # number of UpgradeReq MSHR miss cycles
528system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115017000 # number of UpgradeReq MSHR miss cycles
529system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5335717000 # number of ReadExReq MSHR miss cycles
530system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5335717000 # number of ReadExReq MSHR miss cycles
531system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles
532system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles
533system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425853000 # number of demand (read+write) MSHR miss cycles
534system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5730455000 # number of demand (read+write) MSHR miss cycles
535system.cpu.l2cache.demand_mshr_miss_latency::total 6156628000 # number of demand (read+write) MSHR miss cycles
536system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles
537system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles
538system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles
539system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles
540system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles
541system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
542system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles
543system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles
544system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles
545system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles
546system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
547system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles
548system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles
549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses
550system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses
551system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses
552system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses
553system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses
554system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses
555system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses
556system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses
557system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses
558system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses
559system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses
560system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses
561system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses
562system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses
563system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses
564system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses
565system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses
566system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses
567system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses
568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency
571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency
572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency
573system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency
574system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency
575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency
576system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency
577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
578system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
579system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency
580system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency
581system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency
582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency
585system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency
586system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency
587system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
588system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
589system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
590system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
591system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
592system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
593system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
594system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
596system.iocache.replacements 0 # number of replacements
597system.iocache.tagsinuse 0 # Cycle average of tags in use
598system.iocache.total_refs 0 # Total number of references to valid blocks.
599system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
600system.iocache.avg_refs nan # Average number of references to valid blocks.
601system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
602system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
603system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
604system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
605system.iocache.blocked::no_targets 0 # number of cycles access was blocked
606system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
607system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
608system.iocache.fast_writes 0 # number of fast writes performed
609system.iocache.cache_copies 0 # number of cache copies performed
| 596system.iocache.replacements 0 # number of replacements
597system.iocache.tagsinuse 0 # Cycle average of tags in use
598system.iocache.total_refs 0 # Total number of references to valid blocks.
599system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
600system.iocache.avg_refs nan # Average number of references to valid blocks.
601system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
602system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
603system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
604system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
605system.iocache.blocked::no_targets 0 # number of cycles access was blocked
606system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
607system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
608system.iocache.fast_writes 0 # number of fast writes performed
609system.iocache.cache_copies 0 # number of cache copies performed
|
610system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles
611system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles
612system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles
613system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles
| 610system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles
611system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles
612system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles
613system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles
|
614system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
615system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
616system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
617system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
618system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
619
620---------- End Simulation Statistics ----------
| 614system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
615system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
616system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
617system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
618system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
619
620---------- End Simulation Statistics ----------
|