| stats.txt (9265:8fe936e937bd) | stats.txt (9283:490958b032d6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.629150 # Number of seconds simulated 4sim_ticks 2629149747000 # Number of ticks simulated 5final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 556259 # Simulator instruction rate (inst/s) 8host_op_rate 707830 # Simulator op (including micro ops) rate (op/s) --- 47 unchanged lines hidden (view full) --- 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.629150 # Number of seconds simulated 4sim_ticks 2629149747000 # Number of ticks simulated 5final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 556259 # Simulator instruction rate (inst/s) 8host_op_rate 707830 # Simulator op (including micro ops) rate (op/s) --- 47 unchanged lines hidden (view full) --- 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) |
| 64system.l2c.replacements 62933 # number of replacements 65system.l2c.tagsinuse 51862.510726 # Cycle average of tags in use 66system.l2c.total_refs 1683379 # Total number of references to valid blocks. 67system.l2c.sampled_refs 128318 # Sample count of references to valid blocks. 68system.l2c.avg_refs 13.118806 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy 77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 78system.l2c.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.791359 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 370308 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1226888 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 596416 # number of Writeback hits 87system.l2c.Writeback_hits::total 596416 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits 90system.l2c.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits 91system.l2c.ReadExReq_hits::total 113846 # number of ReadExReq hits 92system.l2c.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits 93system.l2c.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits 94system.l2c.demand_hits::cpu.inst 844195 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.data 484154 # number of demand (read+write) hits 96system.l2c.demand_hits::total 1340734 # number of demand (read+write) hits 97system.l2c.overall_hits::cpu.dtb.walker 8836 # number of overall hits 98system.l2c.overall_hits::cpu.itb.walker 3549 # number of overall hits 99system.l2c.overall_hits::cpu.inst 844195 # number of overall hits 100system.l2c.overall_hits::cpu.data 484154 # number of overall hits 101system.l2c.overall_hits::total 1340734 # number of overall hits 102system.l2c.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses 103system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 104system.l2c.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses 105system.l2c.ReadReq_misses::cpu.data 10261 # number of ReadReq misses 106system.l2c.ReadReq_misses::total 20880 # number of ReadReq misses 107system.l2c.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses 108system.l2c.UpgradeReq_misses::total 2845 # number of UpgradeReq misses 109system.l2c.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses 110system.l2c.ReadExReq_misses::total 133824 # number of ReadExReq misses 111system.l2c.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses 112system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 113system.l2c.demand_misses::cpu.inst 10613 # number of demand (read+write) misses 114system.l2c.demand_misses::cpu.data 144085 # number of demand (read+write) misses 115system.l2c.demand_misses::total 154704 # number of demand (read+write) misses 116system.l2c.overall_misses::cpu.dtb.walker 4 # number of overall misses 117system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses 118system.l2c.overall_misses::cpu.inst 10613 # number of overall misses 119system.l2c.overall_misses::cpu.data 144085 # number of overall misses 120system.l2c.overall_misses::total 154704 # number of overall misses 121system.l2c.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles 123system.l2c.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles 124system.l2c.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles 125system.l2c.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles 126system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles 127system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles 128system.l2c.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles 129system.l2c.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles 130system.l2c.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles 131system.l2c.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles 132system.l2c.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles 135system.l2c.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles 136system.l2c.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles 137system.l2c.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles 139system.l2c.overall_miss_latency::total 8049111500 # number of overall miss cycles 140system.l2c.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) 141system.l2c.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) 142system.l2c.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) 145system.l2c.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) 146system.l2c.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) 147system.l2c.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) 148system.l2c.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) 149system.l2c.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) 150system.l2c.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) 151system.l2c.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses 152system.l2c.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses 153system.l2c.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses 154system.l2c.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses 155system.l2c.demand_accesses::total 1495438 # number of demand (read+write) accesses 156system.l2c.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses 157system.l2c.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses 158system.l2c.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses 159system.l2c.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses 160system.l2c.overall_accesses::total 1495438 # number of overall (read+write) accesses 161system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses 162system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses 163system.l2c.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses 164system.l2c.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses 165system.l2c.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses 166system.l2c.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses 167system.l2c.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses 168system.l2c.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses 169system.l2c.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses 170system.l2c.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses 171system.l2c.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses 172system.l2c.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses 173system.l2c.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses 174system.l2c.demand_miss_rate::total 0.103451 # miss rate for demand accesses 175system.l2c.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses 176system.l2c.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses 177system.l2c.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses 178system.l2c.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses 179system.l2c.overall_miss_rate::total 0.103451 # miss rate for overall accesses 180system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency 181system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 182system.l2c.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency 183system.l2c.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency 184system.l2c.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency 185system.l2c.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency 186system.l2c.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency 187system.l2c.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency 188system.l2c.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency 189system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 190system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 191system.l2c.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency 192system.l2c.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency 193system.l2c.demand_avg_miss_latency::total 52029.110430 # average overall miss latency 194system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 195system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 196system.l2c.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency 197system.l2c.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency 198system.l2c.overall_avg_miss_latency::total 52029.110430 # average overall miss latency 199system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 200system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 201system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 202system.l2c.blocked::no_targets 0 # number of cycles access was blocked 203system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 204system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 205system.l2c.fast_writes 0 # number of fast writes performed 206system.l2c.cache_copies 0 # number of cache copies performed 207system.l2c.writebacks::writebacks 58379 # number of writebacks 208system.l2c.writebacks::total 58379 # number of writebacks 209system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses 210system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 211system.l2c.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses 212system.l2c.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses 213system.l2c.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses 214system.l2c.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses 215system.l2c.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses 216system.l2c.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses 217system.l2c.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses 218system.l2c.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses 219system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 220system.l2c.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses 221system.l2c.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses 222system.l2c.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses 223system.l2c.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses 224system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 225system.l2c.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses 226system.l2c.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses 227system.l2c.overall_mshr_misses::total 154704 # number of overall MSHR misses 228system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles 229system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles 230system.l2c.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles 231system.l2c.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles 232system.l2c.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles 233system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles 234system.l2c.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles 235system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles 236system.l2c.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles 237system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles 238system.l2c.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 239system.l2c.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles 240system.l2c.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles 241system.l2c.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles 242system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles 243system.l2c.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles 244system.l2c.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles 245system.l2c.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles 246system.l2c.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles 247system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles 248system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles 249system.l2c.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles 250system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles 251system.l2c.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles 252system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles 253system.l2c.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles 254system.l2c.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles 255system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses 256system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses 257system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses 258system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses 259system.l2c.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses 260system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses 262system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses 263system.l2c.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses 264system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses 265system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses 266system.l2c.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses 267system.l2c.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses 268system.l2c.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses 269system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses 270system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses 271system.l2c.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses 272system.l2c.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses 273system.l2c.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses 274system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 275system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 276system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency 277system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency 278system.l2c.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency 279system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency 280system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency 281system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency 282system.l2c.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency 283system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 284system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 285system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency 286system.l2c.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency 287system.l2c.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency 288system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 289system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 290system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency 291system.l2c.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency 292system.l2c.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency 293system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 294system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 295system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 296system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 297system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 298system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 299system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 300system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 301system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 64system.cpu.l2cache.replacements 62933 # number of replacements 65system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use 66system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks. 67system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks. 68system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks. 69system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. 70system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor 71system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor 72system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor 73system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor 74system.cpu.l2cache.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor 75system.cpu.l2cache.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy 76system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy 77system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 78system.cpu.l2cache.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy 79system.cpu.l2cache.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy 80system.cpu.l2cache.occ_percent::total 0.791359 # Average percentage of cache occupancy 81system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits 82system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits 83system.cpu.l2cache.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits 84system.cpu.l2cache.ReadReq_hits::cpu.data 370308 # number of ReadReq hits 85system.cpu.l2cache.ReadReq_hits::total 1226888 # number of ReadReq hits 86system.cpu.l2cache.Writeback_hits::writebacks 596416 # number of Writeback hits 87system.cpu.l2cache.Writeback_hits::total 596416 # number of Writeback hits 88system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 89system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 90system.cpu.l2cache.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits 91system.cpu.l2cache.ReadExReq_hits::total 113846 # number of ReadExReq hits 92system.cpu.l2cache.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits 93system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits 94system.cpu.l2cache.demand_hits::cpu.inst 844195 # number of demand (read+write) hits 95system.cpu.l2cache.demand_hits::cpu.data 484154 # number of demand (read+write) hits 96system.cpu.l2cache.demand_hits::total 1340734 # number of demand (read+write) hits 97system.cpu.l2cache.overall_hits::cpu.dtb.walker 8836 # number of overall hits 98system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits 99system.cpu.l2cache.overall_hits::cpu.inst 844195 # number of overall hits 100system.cpu.l2cache.overall_hits::cpu.data 484154 # number of overall hits 101system.cpu.l2cache.overall_hits::total 1340734 # number of overall hits 102system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses 103system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 104system.cpu.l2cache.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses 105system.cpu.l2cache.ReadReq_misses::cpu.data 10261 # number of ReadReq misses 106system.cpu.l2cache.ReadReq_misses::total 20880 # number of ReadReq misses 107system.cpu.l2cache.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses 108system.cpu.l2cache.UpgradeReq_misses::total 2845 # number of UpgradeReq misses 109system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses 110system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses 111system.cpu.l2cache.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses 112system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 113system.cpu.l2cache.demand_misses::cpu.inst 10613 # number of demand (read+write) misses 114system.cpu.l2cache.demand_misses::cpu.data 144085 # number of demand (read+write) misses 115system.cpu.l2cache.demand_misses::total 154704 # number of demand (read+write) misses 116system.cpu.l2cache.overall_misses::cpu.dtb.walker 4 # number of overall misses 117system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 118system.cpu.l2cache.overall_misses::cpu.inst 10613 # number of overall misses 119system.cpu.l2cache.overall_misses::cpu.data 144085 # number of overall misses 120system.cpu.l2cache.overall_misses::total 154704 # number of overall misses 121system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles 122system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles 123system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles 124system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles 125system.cpu.l2cache.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles 126system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles 127system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles 128system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles 129system.cpu.l2cache.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles 130system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles 131system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles 132system.cpu.l2cache.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles 133system.cpu.l2cache.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles 134system.cpu.l2cache.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles 135system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles 136system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles 137system.cpu.l2cache.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles 138system.cpu.l2cache.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles 139system.cpu.l2cache.overall_miss_latency::total 8049111500 # number of overall miss cycles 140system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) 141system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) 142system.cpu.l2cache.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) 143system.cpu.l2cache.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) 144system.cpu.l2cache.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) 145system.cpu.l2cache.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) 146system.cpu.l2cache.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) 147system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) 148system.cpu.l2cache.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) 149system.cpu.l2cache.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) 150system.cpu.l2cache.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) 151system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses 152system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses 153system.cpu.l2cache.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses 154system.cpu.l2cache.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses 155system.cpu.l2cache.demand_accesses::total 1495438 # number of demand (read+write) accesses 156system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses 157system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses 158system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses 159system.cpu.l2cache.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses 160system.cpu.l2cache.overall_accesses::total 1495438 # number of overall (read+write) accesses 161system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses 162system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses 163system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses 164system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses 165system.cpu.l2cache.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses 166system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses 167system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses 168system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses 169system.cpu.l2cache.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses 170system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses 171system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses 172system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses 173system.cpu.l2cache.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses 174system.cpu.l2cache.demand_miss_rate::total 0.103451 # miss rate for demand accesses 175system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses 176system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses 177system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses 178system.cpu.l2cache.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses 179system.cpu.l2cache.overall_miss_rate::total 0.103451 # miss rate for overall accesses 180system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency 181system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 182system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency 183system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency 184system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency 185system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency 186system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency 187system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency 188system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency 189system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 190system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 191system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency 192system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency 193system.cpu.l2cache.demand_avg_miss_latency::total 52029.110430 # average overall miss latency 194system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 195system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 196system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency 197system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency 198system.cpu.l2cache.overall_avg_miss_latency::total 52029.110430 # average overall miss latency 199system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 200system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 201system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 202system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 203system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 204system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 205system.cpu.l2cache.fast_writes 0 # number of fast writes performed 206system.cpu.l2cache.cache_copies 0 # number of cache copies performed 207system.cpu.l2cache.writebacks::writebacks 58379 # number of writebacks 208system.cpu.l2cache.writebacks::total 58379 # number of writebacks 209system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses 210system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 211system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses 212system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses 213system.cpu.l2cache.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses 214system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses 215system.cpu.l2cache.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses 216system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses 217system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses 218system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses 219system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 220system.cpu.l2cache.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses 221system.cpu.l2cache.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses 222system.cpu.l2cache.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses 223system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses 224system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 225system.cpu.l2cache.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses 226system.cpu.l2cache.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses 227system.cpu.l2cache.overall_mshr_misses::total 154704 # number of overall MSHR misses 228system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles 229system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles 230system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles 231system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles 232system.cpu.l2cache.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles 233system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles 234system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles 235system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles 236system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles 237system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles 238system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 239system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles 240system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles 241system.cpu.l2cache.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles 242system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles 243system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles 244system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles 245system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles 246system.cpu.l2cache.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles 247system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles 248system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles 249system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles 250system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles 251system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles 252system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles 253system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles 254system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles 255system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses 256system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses 257system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses 258system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses 259system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses 260system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses 261system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses 262system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses 263system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses 264system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses 265system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses 266system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses 267system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses 268system.cpu.l2cache.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses 269system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses 270system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses 271system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses 272system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses 273system.cpu.l2cache.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses 274system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 275system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 276system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency 277system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency 278system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency 279system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency 280system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency 281system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency 282system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency 283system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 284system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 285system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency 286system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency 287system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency 288system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 289system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 290system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency 291system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency 292system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency 293system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 294system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 295system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 296system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 297system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 298system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 299system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 300system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 301system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 302system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 303system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 304system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 305system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 306system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 307system.cf0.dma_write_txs 0 # Number of DMA write transactions. 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses --- 311 unchanged lines hidden --- | 302system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 303system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 304system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 305system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 306system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 307system.cf0.dma_write_txs 0 # Number of DMA write transactions. 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses --- 311 unchanged lines hidden --- |