| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.591442 # Number of seconds simulated 4sim_ticks 2591441692000 # Number of ticks simulated 5final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.591442 # Number of seconds simulated 4sim_ticks 2591441692000 # Number of ticks simulated 5final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 879685 # Simulator instruction rate (inst/s) 8host_op_rate 1123921 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38588641896 # Simulator tick rate (ticks/s) 10host_mem_usage 377580 # Number of bytes of host memory used 11host_seconds 67.16 # Real time elapsed on the host | 7host_inst_rate 302887 # Simulator instruction rate (inst/s) 8host_op_rate 386981 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13286578938 # Simulator tick rate (ticks/s) 10host_mem_usage 384192 # Number of bytes of host memory used 11host_seconds 195.04 # Real time elapsed on the host |
| 12sim_insts 59075703 # Number of instructions simulated 13sim_ops 75477535 # Number of ops (including micro ops) simulated | 12sim_insts 59075703 # Number of instructions simulated 13sim_ops 75477535 # Number of ops (including micro ops) simulated |
| 14system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s) 22system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s) | |
| 23system.physmem.bytes_read 133655408 # Number of bytes read from this memory 24system.physmem.bytes_inst_read 949920 # Number of instructions bytes read from this memory 25system.physmem.bytes_written 9634312 # Number of bytes written to this memory 26system.physmem.num_reads 15513098 # Number of read requests responded to by this memory 27system.physmem.num_writes 857428 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 51575696 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 366560 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read 133655408 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 949920 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 9634312 # Number of bytes written to this memory 17system.physmem.num_reads 15513098 # Number of read requests responded to by this memory 18system.physmem.num_writes 857428 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 51575696 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 366560 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s) |
| 24system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s) |
|
| 33system.l2c.replacements 117809 # number of replacements 34system.l2c.tagsinuse 24929.234619 # Cycle average of tags in use 35system.l2c.total_refs 1535239 # Total number of references to valid blocks. 36system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. 37system.l2c.avg_refs 10.464518 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 14588.908290 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor --- 113 unchanged lines hidden (view full) --- 154system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency 155system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 156system.l2c.overall_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency 157system.l2c.overall_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency 158system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 160system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 161system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 33system.l2c.replacements 117809 # number of replacements 34system.l2c.tagsinuse 24929.234619 # Cycle average of tags in use 35system.l2c.total_refs 1535239 # Total number of references to valid blocks. 36system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. 37system.l2c.avg_refs 10.464518 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 14588.908290 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor --- 113 unchanged lines hidden (view full) --- 154system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency 155system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 156system.l2c.overall_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency 157system.l2c.overall_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency 158system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 160system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 161system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 162system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 163system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 162system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 163system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 164system.l2c.fast_writes 0 # number of fast writes performed 165system.l2c.cache_copies 0 # number of cache copies performed 166system.l2c.writebacks::writebacks 103410 # number of writebacks 167system.l2c.writebacks::total 103410 # number of writebacks 168system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 24 # number of ReadReq MSHR misses 169system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses 170system.l2c.ReadReq_mshr_misses::cpu.inst 14429 # number of ReadReq MSHR misses 171system.l2c.ReadReq_mshr_misses::cpu.data 17256 # number of ReadReq MSHR misses --- 183 unchanged lines hidden (view full) --- 355system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses 356system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14701.087192 # average ReadReq miss latency 357system.cpu.icache.demand_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency 358system.cpu.icache.overall_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency 359system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 164system.l2c.fast_writes 0 # number of fast writes performed 165system.l2c.cache_copies 0 # number of cache copies performed 166system.l2c.writebacks::writebacks 103410 # number of writebacks 167system.l2c.writebacks::total 103410 # number of writebacks 168system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 24 # number of ReadReq MSHR misses 169system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses 170system.l2c.ReadReq_mshr_misses::cpu.inst 14429 # number of ReadReq MSHR misses 171system.l2c.ReadReq_mshr_misses::cpu.data 17256 # number of ReadReq MSHR misses --- 183 unchanged lines hidden (view full) --- 355system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses 356system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14701.087192 # average ReadReq miss latency 357system.cpu.icache.demand_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency 358system.cpu.icache.overall_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency 359system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 363system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 364system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 363system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 365system.cpu.icache.fast_writes 0 # number of fast writes performed 366system.cpu.icache.cache_copies 0 # number of cache copies performed 367system.cpu.icache.writebacks::writebacks 45661 # number of writebacks 368system.cpu.icache.writebacks::total 45661 # number of writebacks 369system.cpu.icache.ReadReq_mshr_misses::cpu.inst 853483 # number of ReadReq MSHR misses 370system.cpu.icache.ReadReq_mshr_misses::total 853483 # number of ReadReq MSHR misses 371system.cpu.icache.demand_mshr_misses::cpu.inst 853483 # number of demand (read+write) MSHR misses 372system.cpu.icache.demand_mshr_misses::total 853483 # number of demand (read+write) MSHR misses --- 80 unchanged lines hidden (view full) --- 453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428 # average WriteReq miss latency 454system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511 # average LoadLockedReq miss latency 455system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency 456system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency 457system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 458system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 459system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 460system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 365system.cpu.icache.fast_writes 0 # number of fast writes performed 366system.cpu.icache.cache_copies 0 # number of cache copies performed 367system.cpu.icache.writebacks::writebacks 45661 # number of writebacks 368system.cpu.icache.writebacks::total 45661 # number of writebacks 369system.cpu.icache.ReadReq_mshr_misses::cpu.inst 853483 # number of ReadReq MSHR misses 370system.cpu.icache.ReadReq_mshr_misses::total 853483 # number of ReadReq MSHR misses 371system.cpu.icache.demand_mshr_misses::cpu.inst 853483 # number of demand (read+write) MSHR misses 372system.cpu.icache.demand_mshr_misses::total 853483 # number of demand (read+write) MSHR misses --- 80 unchanged lines hidden (view full) --- 453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428 # average WriteReq miss latency 454system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511 # average LoadLockedReq miss latency 455system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency 456system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency 457system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 458system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 459system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 460system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 461system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 462system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 461system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 462system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 463system.cpu.dcache.fast_writes 0 # number of fast writes performed 464system.cpu.dcache.cache_copies 0 # number of cache copies performed 465system.cpu.dcache.writebacks::writebacks 564388 # number of writebacks 466system.cpu.dcache.writebacks::total 564388 # number of writebacks 467system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368563 # number of ReadReq MSHR misses 468system.cpu.dcache.ReadReq_mshr_misses::total 368563 # number of ReadReq MSHR misses 469system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250302 # number of WriteReq MSHR misses 470system.cpu.dcache.WriteReq_mshr_misses::total 250302 # number of WriteReq MSHR misses --- 32 unchanged lines hidden (view full) --- 503system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 504system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 505system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 506system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 507system.iocache.replacements 0 # number of replacements 508system.iocache.tagsinuse 0 # Cycle average of tags in use 509system.iocache.total_refs 0 # Total number of references to valid blocks. 510system.iocache.sampled_refs 0 # Sample count of references to valid blocks. | 463system.cpu.dcache.fast_writes 0 # number of fast writes performed 464system.cpu.dcache.cache_copies 0 # number of cache copies performed 465system.cpu.dcache.writebacks::writebacks 564388 # number of writebacks 466system.cpu.dcache.writebacks::total 564388 # number of writebacks 467system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368563 # number of ReadReq MSHR misses 468system.cpu.dcache.ReadReq_mshr_misses::total 368563 # number of ReadReq MSHR misses 469system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250302 # number of WriteReq MSHR misses 470system.cpu.dcache.WriteReq_mshr_misses::total 250302 # number of WriteReq MSHR misses --- 32 unchanged lines hidden (view full) --- 503system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 504system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 505system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 506system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 507system.iocache.replacements 0 # number of replacements 508system.iocache.tagsinuse 0 # Cycle average of tags in use 509system.iocache.total_refs 0 # Total number of references to valid blocks. 510system.iocache.sampled_refs 0 # Sample count of references to valid blocks. |
| 511system.iocache.avg_refs no_value # Average number of references to valid blocks. | 511system.iocache.avg_refs nan # Average number of references to valid blocks. |
| 512system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 513system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 512system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 513system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 517system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 518system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 517system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 519system.iocache.fast_writes 0 # number of fast writes performed 520system.iocache.cache_copies 0 # number of cache copies performed 521system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of ReadReq MSHR uncacheable cycles 522system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938 # number of ReadReq MSHR uncacheable cycles 523system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of overall MSHR uncacheable cycles 524system.iocache.overall_mshr_uncacheable_latency::total 1341941439938 # number of overall MSHR uncacheable cycles 525system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 526system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 527system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 528 529---------- End Simulation Statistics ---------- | 519system.iocache.fast_writes 0 # number of fast writes performed 520system.iocache.cache_copies 0 # number of cache copies performed 521system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of ReadReq MSHR uncacheable cycles 522system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938 # number of ReadReq MSHR uncacheable cycles 523system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of overall MSHR uncacheable cycles 524system.iocache.overall_mshr_uncacheable_latency::total 1341941439938 # number of overall MSHR uncacheable cycles 525system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 526system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 527system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 528 529---------- End Simulation Statistics ---------- |