| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.903737 # Number of seconds simulated 4sim_ticks 2903736790500 # Number of ticks simulated 5final_tick 2903736790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.905298 # Number of seconds simulated 4sim_ticks 2905297782500 # Number of ticks simulated 5final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 515424 # Simulator instruction rate (inst/s) 8host_op_rate 621448 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13306386787 # Simulator tick rate (ticks/s) 10host_mem_usage 582748 # Number of bytes of host memory used 11host_seconds 218.22 # Real time elapsed on the host 12sim_insts 112476413 # Number of instructions simulated 13sim_ops 135613231 # Number of ops (including micro ops) simulated | 7host_inst_rate 483331 # Simulator instruction rate (inst/s) 8host_op_rate 582745 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12486239543 # Simulator tick rate (ticks/s) 10host_mem_usage 580500 # Number of bytes of host memory used 11host_seconds 232.68 # Real time elapsed on the host 12sim_insts 112461365 # Number of instructions simulated 13sim_ops 135593151 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 512 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 1188964 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9028260 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu.inst 1184612 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 8933156 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 10218824 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1188964 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1188964 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7618752 # Number of bytes written to this memory | 22system.physmem.bytes_read::total 10119304 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1184612 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1184612 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7531136 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::total 7636276 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 8 # Number of read requests responded to by this memory | 27system.physmem.bytes_written::total 7548660 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 27031 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141586 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 26963 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 140100 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 168642 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 119043 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 167087 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 117674 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::total 123424 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 176 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.num_writes::total 122055 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 409460 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3109187 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3519198 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 409460 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 409460 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2623775 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2629810 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2623775 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 176 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 407742 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3074782 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3483052 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 407742 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 407742 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2592208 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2598240 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2592208 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) | 50system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 409460 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3115222 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6149008 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 168642 # Number of read requests accepted 56system.physmem.writeReqs 123424 # Number of write requests accepted 57system.physmem.readBursts 168642 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 123424 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10783744 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7648256 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10218824 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7636276 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one | 51system.physmem.bw_total::cpu.inst 407742 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3080813 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6081292 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 167087 # Number of read requests accepted 56system.physmem.writeReqs 122055 # Number of write requests accepted 57system.physmem.readBursts 167087 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 122055 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10685312 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7561344 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10119304 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7548660 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one |
| 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 67system.physmem.perBankRdBursts::0 9943 # Per bank write bursts 68system.physmem.perBankRdBursts::1 9648 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10560 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10245 # Per bank write bursts 71system.physmem.perBankRdBursts::4 18706 # Per bank write bursts 72system.physmem.perBankRdBursts::5 9867 # Per bank write bursts 73system.physmem.perBankRdBursts::6 9999 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10271 # Per bank write bursts 75system.physmem.perBankRdBursts::8 9694 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10419 # Per bank write bursts 77system.physmem.perBankRdBursts::10 9828 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9028 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10140 # Per bank write bursts 80system.physmem.perBankRdBursts::13 10489 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10151 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9508 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7397 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7199 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8385 # Per bank write bursts 86system.physmem.perBankWrBursts::3 7801 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7213 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7134 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7314 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7590 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7388 # Per bank write bursts 92system.physmem.perBankWrBursts::9 8015 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7407 # Per bank write bursts 94system.physmem.perBankWrBursts::11 6899 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7622 # Per bank write bursts 96system.physmem.perBankWrBursts::13 7751 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7507 # Per bank write bursts 98system.physmem.perBankWrBursts::15 6882 # Per bank write bursts | 67system.physmem.perBankRdBursts::0 9954 # Per bank write bursts 68system.physmem.perBankRdBursts::1 9813 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10094 # Per bank write bursts 70system.physmem.perBankRdBursts::3 9518 # Per bank write bursts 71system.physmem.perBankRdBursts::4 18811 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10188 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10467 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10858 # Per bank write bursts 75system.physmem.perBankRdBursts::8 9262 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10094 # Per bank write bursts 77system.physmem.perBankRdBursts::10 9505 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9184 # Per bank write bursts 79system.physmem.perBankRdBursts::12 9983 # Per bank write bursts 80system.physmem.perBankRdBursts::13 9847 # Per bank write bursts 81system.physmem.perBankRdBursts::14 9958 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9422 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7103 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7218 # Per bank write bursts 85system.physmem.perBankWrBursts::2 7869 # Per bank write bursts 86system.physmem.perBankWrBursts::3 7374 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7424 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7558 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7579 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7921 # Per bank write bursts 91system.physmem.perBankWrBursts::8 6916 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7516 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7047 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7122 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7779 # Per bank write bursts 96system.physmem.perBankWrBursts::13 7383 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7451 # Per bank write bursts 98system.physmem.perBankWrBursts::15 6886 # Per bank write bursts |
| 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 100system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 101system.physmem.totGap 2903736355000 # Total gap between requests | 100system.physmem.numWrRetry 65 # Number of times write queue was full causing retry 101system.physmem.totGap 2905297420500 # Total gap between requests |
| 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 9558 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) | 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 9558 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 108system.physmem.readPktSize::6 159070 # Read request sizes (log2) | 108system.physmem.readPktSize::6 157515 # Read request sizes (log2) |
| 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) | 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 115system.physmem.writePktSize::6 119043 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 167708 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 529 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 247 # What read queue length does an incoming req see | 115system.physmem.writePktSize::6 117674 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 166128 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 554 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 163system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2984 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 6117 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6096 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6314 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6034 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6526 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6858 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7572 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8704 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8960 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7233 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 6955 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 6927 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6384 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6223 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 148 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 138 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 168 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 106 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 130 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 60 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 58618 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 314.441571 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 184.322128 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 334.751512 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 21316 36.36% 36.36% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14773 25.20% 61.57% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 5607 9.57% 71.13% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3267 5.57% 76.71% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2505 4.27% 80.98% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1471 2.51% 83.49% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1045 1.78% 85.27% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1040 1.77% 87.04% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7594 12.96% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 58618 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 5878 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 28.661279 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 584.674226 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 5877 99.98% 99.98% # Reads before turning the bus around for writes | 163system.physmem.wrQLenPdf::15 1886 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2786 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 5910 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 5857 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 5767 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6250 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6643 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7263 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7223 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8271 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8725 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7065 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 6628 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 6527 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6281 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6129 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6179 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 401 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 376 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 293 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 238 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 238 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 204 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 193 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 229 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 186 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 214 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 196 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 206 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 246 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 234 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 180 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 57323 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 318.311882 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 186.988870 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 336.470779 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 20402 35.59% 35.59% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14531 25.35% 60.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 5716 9.97% 70.91% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3104 5.41% 76.33% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2370 4.13% 80.46% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1421 2.48% 82.94% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1241 2.16% 85.11% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 946 1.65% 86.76% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7592 13.24% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 57323 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 5761 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 28.979865 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 590.542998 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 5760 99.98% 99.98% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes | 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 231system.physmem.rdPerTurnAround::total 5878 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5878 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.330725 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.604611 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 13.460490 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5095 86.68% 86.68% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 41 0.70% 87.38% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 85 1.45% 88.82% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 37 0.63% 89.45% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 285 4.85% 94.30% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 59 1.00% 95.30% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 13 0.22% 95.53% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 14 0.24% 95.76% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 4 0.07% 95.99% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 6 0.10% 96.09% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 8 0.14% 96.22% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 168 2.86% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 3 0.05% 99.13% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 2 0.03% 99.17% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 6 0.10% 99.27% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 7 0.12% 99.39% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.40% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 1 0.02% 99.42% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 2 0.03% 99.46% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 2 0.03% 99.49% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 5 0.09% 99.57% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 11 0.19% 99.78% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::136-139 1 0.02% 99.80% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::140-143 1 0.02% 99.81% # Writes before turning the bus around for reads | 231system.physmem.rdPerTurnAround::total 5761 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5761 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.507898 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.546505 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 15.055833 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5040 87.48% 87.48% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 23 0.40% 87.88% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 68 1.18% 89.06% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 38 0.66% 89.72% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 294 5.10% 94.83% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 33 0.57% 95.40% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 2 0.03% 95.43% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 7 0.12% 95.56% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 6 0.10% 95.66% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 3 0.05% 95.71% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 2 0.03% 95.75% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 5 0.09% 95.83% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 158 2.74% 98.58% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 4 0.07% 98.65% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 6 0.10% 98.75% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 3 0.05% 98.80% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 10 0.17% 98.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 2 0.03% 99.01% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 2 0.03% 99.05% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 1 0.02% 99.06% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 11 0.19% 99.29% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 2 0.03% 99.32% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::124-127 3 0.05% 99.39% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 8 0.14% 99.53% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::132-135 7 0.12% 99.65% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::136-139 4 0.07% 99.72% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::140-143 4 0.07% 99.79% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads |
| 262system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads | 266system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads |
| 263system.physmem.wrPerTurnAround::156-159 1 0.02% 99.85% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::160-163 6 0.10% 99.95% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 5878 # Writes before turning the bus around for reads 269system.physmem.totQLat 1493636250 # Total ticks spent queuing 270system.physmem.totMemAccLat 4652936250 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 842480000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 8864.52 # Average queueing delay per DRAM burst | 267system.physmem.wrPerTurnAround::156-159 2 0.03% 99.86% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::172-175 3 0.05% 99.91% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 5761 # Writes before turning the bus around for reads 274system.physmem.totQLat 4504540500 # Total ticks spent queuing 275system.physmem.totMemAccLat 7635003000 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 834790000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 26980.08 # Average queueing delay per DRAM burst |
| 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 274system.physmem.avgMemAccLat 27614.52 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s | 279system.physmem.avgMemAccLat 45730.08 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 3.68 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 3.48 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s |
| 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 280system.physmem.busUtil 0.05 # Data bus utilization in percentage 281system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 282system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.05 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 284system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing 285system.physmem.readRowHits 138583 # Number of row buffer hits during reads 286system.physmem.writeRowHits 90798 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes 289system.physmem.avgGap 9942055.41 # Average gap between requests 290system.physmem.pageHitRate 79.64 # Row buffer hit rate, read and write combined 291system.physmem_0.actEnergy 226187640 # Energy for activate commands per rank (pJ) 292system.physmem_0.preEnergy 123415875 # Energy for precharge commands per rank (pJ) 293system.physmem_0.readEnergy 696064200 # Energy for read commands per rank (pJ) 294system.physmem_0.writeEnergy 389013840 # Energy for write commands per rank (pJ) 295system.physmem_0.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) 296system.physmem_0.actBackEnergy 86978464290 # Energy for active background per rank (pJ) 297system.physmem_0.preBackEnergy 1665943648500 # Energy for precharge background per rank (pJ) 298system.physmem_0.totalEnergy 1944014583705 # Total energy per rank (pJ) 299system.physmem_0.averagePower 669.487777 # Core power per rank (mW) 300system.physmem_0.memoryStateTime::IDLE 2771286006000 # Time in different power states 301system.physmem_0.memoryStateTime::REF 96962060000 # Time in different power states 302system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 303system.physmem_0.memoryStateTime::ACT 35486192750 # Time in different power states 304system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 305system.physmem_1.actEnergy 216964440 # Energy for activate commands per rank (pJ) 306system.physmem_1.preEnergy 118383375 # Energy for precharge commands per rank (pJ) 307system.physmem_1.readEnergy 618196800 # Energy for read commands per rank (pJ) 308system.physmem_1.writeEnergy 385372080 # Energy for write commands per rank (pJ) 309system.physmem_1.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) 310system.physmem_1.actBackEnergy 85605070095 # Energy for active background per rank (pJ) 311system.physmem_1.preBackEnergy 1667148388500 # Energy for precharge background per rank (pJ) 312system.physmem_1.totalEnergy 1943750164650 # Total energy per rank (pJ) 313system.physmem_1.averagePower 669.396712 # Core power per rank (mW) 314system.physmem_1.memoryStateTime::IDLE 2773305848750 # Time in different power states 315system.physmem_1.memoryStateTime::REF 96962060000 # Time in different power states 316system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 317system.physmem_1.memoryStateTime::ACT 33468782750 # Time in different power states 318system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 319system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 289system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing 290system.physmem.readRowHits 138094 # Number of row buffer hits during reads 291system.physmem.writeRowHits 89686 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 82.71 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes 294system.physmem.avgGap 10047995.17 # Average gap between requests 295system.physmem.pageHitRate 79.89 # Row buffer hit rate, read and write combined 296system.physmem_0.actEnergy 210115920 # Energy for activate commands per rank (pJ) 297system.physmem_0.preEnergy 111679260 # Energy for precharge commands per rank (pJ) 298system.physmem_0.readEnergy 640479420 # Energy for read commands per rank (pJ) 299system.physmem_0.writeEnergy 313440120 # Energy for write commands per rank (pJ) 300system.physmem_0.refreshEnergy 6609223920.000002 # Energy for refresh commands per rank (pJ) 301system.physmem_0.actBackEnergy 4735061820 # Energy for active background per rank (pJ) 302system.physmem_0.preBackEnergy 414343200 # Energy for precharge background per rank (pJ) 303system.physmem_0.actPowerDownEnergy 13903412640 # Energy for active power-down per rank (pJ) 304system.physmem_0.prePowerDownEnergy 9310120320 # Energy for precharge power-down per rank (pJ) 305system.physmem_0.selfRefreshEnergy 682719565725 # Energy for self refresh per rank (pJ) 306system.physmem_0.totalEnergy 718969243965 # Total energy per rank (pJ) 307system.physmem_0.averagePower 247.468348 # Core power per rank (mW) 308system.physmem_0.totalIdleTime 2893307612500 # Total Idle time Per DRAM Rank 309system.physmem_0.memoryStateTime::IDLE 778413000 # Time in different power states 310system.physmem_0.memoryStateTime::REF 2810438000 # Time in different power states 311system.physmem_0.memoryStateTime::SREF 2839095824500 # Time in different power states 312system.physmem_0.memoryStateTime::PRE_PDN 24245244750 # Time in different power states 313system.physmem_0.memoryStateTime::ACT 7877734000 # Time in different power states 314system.physmem_0.memoryStateTime::ACT_PDN 30490128250 # Time in different power states 315system.physmem_1.actEnergy 199177440 # Energy for activate commands per rank (pJ) 316system.physmem_1.preEnergy 105861525 # Energy for precharge commands per rank (pJ) 317system.physmem_1.readEnergy 551600700 # Energy for read commands per rank (pJ) 318system.physmem_1.writeEnergy 303282000 # Energy for write commands per rank (pJ) 319system.physmem_1.refreshEnergy 6621516720.000002 # Energy for refresh commands per rank (pJ) 320system.physmem_1.actBackEnergy 4536550200 # Energy for active background per rank (pJ) 321system.physmem_1.preBackEnergy 409678080 # Energy for precharge background per rank (pJ) 322system.physmem_1.actPowerDownEnergy 13514783790 # Energy for active power-down per rank (pJ) 323system.physmem_1.prePowerDownEnergy 9490661760 # Energy for precharge power-down per rank (pJ) 324system.physmem_1.selfRefreshEnergy 682993594335 # Energy for self refresh per rank (pJ) 325system.physmem_1.totalEnergy 718728215280 # Total energy per rank (pJ) 326system.physmem_1.averagePower 247.385386 # Core power per rank (mW) 327system.physmem_1.totalIdleTime 2894278953000 # Total Idle time Per DRAM Rank 328system.physmem_1.memoryStateTime::IDLE 777246000 # Time in different power states 329system.physmem_1.memoryStateTime::REF 2816412000 # Time in different power states 330system.physmem_1.memoryStateTime::SREF 2839926040500 # Time in different power states 331system.physmem_1.memoryStateTime::PRE_PDN 24715420500 # Time in different power states 332system.physmem_1.memoryStateTime::ACT 7425105000 # Time in different power states 333system.physmem_1.memoryStateTime::ACT_PDN 29637558500 # Time in different power states 334system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 320system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 321system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 322system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 323system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 324system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 325system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 326system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 331system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) | 335system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 336system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 337system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 338system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 339system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 340system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 341system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) |
| 332system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 333system.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 334system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 347system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 348system.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 349system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 335system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 336system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 337system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 338system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 339system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 340system.cf0.dma_write_txs 631 # Number of DMA write transactions. 341system.cpu_clk_domain.clock 500 # Clock period in ticks | 350system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 351system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 352system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 353system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 354system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 355system.cf0.dma_write_txs 631 # Number of DMA write transactions. 356system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 342system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 357system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 343system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 364system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 367system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 368system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 369system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 370system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 371system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 358system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 379system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 380system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 382system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 383system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 384system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 385system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 386system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 372system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 373system.cpu.dtb.walker.walks 9520 # Table walker walks requested 374system.cpu.dtb.walker.walksShort 9520 # Table walker walks initiated with short descriptors 375system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1252 # Level at which table walker walks with short descriptors terminate 376system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8268 # Level at which table walker walks with short descriptors terminate 377system.cpu.dtb.walker.walkWaitTime::samples 9520 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::0 9520 100.00% 100.00% # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::total 9520 # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkCompletionTime::samples 7356 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::gmean 8514.979061 # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::stdev 6541.334463 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::0-16383 6558 89.15% 89.15% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::16384-32767 793 10.78% 99.93% # Table walker service (enqueue to completion) latency | 387system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 388system.cpu.dtb.walker.walks 9547 # Table walker walks requested 389system.cpu.dtb.walker.walksShort 9547 # Table walker walks initiated with short descriptors 390system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1253 # Level at which table walker walks with short descriptors terminate 391system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8294 # Level at which table walker walks with short descriptors terminate 392system.cpu.dtb.walker.walkWaitTime::samples 9547 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::0 9547 100.00% 100.00% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::total 9547 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkCompletionTime::samples 7383 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::mean 9942.435324 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::gmean 8397.692517 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::stdev 6587.109188 # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::0-16383 6605 89.46% 89.46% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::16384-32767 773 10.47% 99.93% # Table walker service (enqueue to completion) latency |
| 386system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency | 401system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency |
| 388system.cpu.dtb.walker.walkCompletionTime::total 7356 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution 390system.cpu.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution 391system.cpu.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution 392system.cpu.dtb.walker.walkPageSizes::4K 6151 83.62% 83.62% # Table walker page sizes translated 393system.cpu.dtb.walker.walkPageSizes::1M 1205 16.38% 100.00% # Table walker page sizes translated 394system.cpu.dtb.walker.walkPageSizes::total 7356 # Table walker page sizes translated 395system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9520 # Table walker requests started/completed, data/inst | 403system.cpu.dtb.walker.walkCompletionTime::total 7383 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution 405system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution 407system.cpu.dtb.walker.walkPageSizes::4K 6177 83.67% 83.67% # Table walker page sizes translated 408system.cpu.dtb.walker.walkPageSizes::1M 1206 16.33% 100.00% # Table walker page sizes translated 409system.cpu.dtb.walker.walkPageSizes::total 7383 # Table walker page sizes translated 410system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9547 # Table walker requests started/completed, data/inst |
| 396system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 411system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 397system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9520 # Table walker requests started/completed, data/inst 398system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7356 # Table walker requests started/completed, data/inst | 412system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9547 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7383 # Table walker requests started/completed, data/inst |
| 399system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 414system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 400system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7356 # Table walker requests started/completed, data/inst 401system.cpu.dtb.walker.walkRequestOrigin::total 16876 # Table walker requests started/completed, data/inst | 415system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7383 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin::total 16930 # Table walker requests started/completed, data/inst |
| 402system.cpu.dtb.inst_hits 0 # ITB inst hits 403system.cpu.dtb.inst_misses 0 # ITB inst misses | 417system.cpu.dtb.inst_hits 0 # ITB inst hits 418system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 404system.cpu.dtb.read_hits 24525489 # DTB read hits 405system.cpu.dtb.read_misses 8109 # DTB read misses 406system.cpu.dtb.write_hits 19608938 # DTB write hits 407system.cpu.dtb.write_misses 1411 # DTB write misses | 419system.cpu.dtb.read_hits 24520121 # DTB read hits 420system.cpu.dtb.read_misses 8133 # DTB read misses 421system.cpu.dtb.write_hits 19605715 # DTB write hits 422system.cpu.dtb.write_misses 1414 # DTB write misses |
| 408system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 409system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 410system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 411system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 423system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 424system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 425system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 426system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 412system.cpu.dtb.flush_entries 4199 # Number of entries that have been flushed from TLB | 427system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB |
| 413system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 428system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 414system.cpu.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch | 429system.cpu.dtb.prefetch_faults 1628 # Number of TLB faults due to prefetch |
| 415system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions | 430system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 431system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions |
| 417system.cpu.dtb.read_accesses 24533598 # DTB read accesses 418system.cpu.dtb.write_accesses 19610349 # DTB write accesses | 432system.cpu.dtb.read_accesses 24528254 # DTB read accesses 433system.cpu.dtb.write_accesses 19607129 # DTB write accesses |
| 419system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 434system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 420system.cpu.dtb.hits 44134427 # DTB hits 421system.cpu.dtb.misses 9520 # DTB misses 422system.cpu.dtb.accesses 44143947 # DTB accesses 423system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 435system.cpu.dtb.hits 44125836 # DTB hits 436system.cpu.dtb.misses 9547 # DTB misses 437system.cpu.dtb.accesses 44135383 # DTB accesses 438system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 424system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 445system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 446system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 447system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 448system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 449system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 450system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 451system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 452system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 439system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 460system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 461system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 462system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 463system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 464system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 465system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 466system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 467system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 453system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 454system.cpu.itb.walker.walks 4762 # Table walker walks requested 455system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 456system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate | 468system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 469system.cpu.itb.walker.walks 4763 # Table walker walks requested 470system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors 471system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate |
| 457system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate | 472system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate |
| 458system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 459system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 460system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 461system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::mean 10273.897650 # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::gmean 8288.299297 # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walkCompletionTime::stdev 7346.561217 # Table walker service (enqueue to completion) latency 465system.cpu.itb.walker.walkCompletionTime::0-8191 1812 58.32% 58.32% # Table walker service (enqueue to completion) latency 466system.cpu.itb.walker.walkCompletionTime::8192-16383 745 23.98% 82.30% # Table walker service (enqueue to completion) latency 467system.cpu.itb.walker.walkCompletionTime::16384-24575 548 17.64% 99.94% # Table walker service (enqueue to completion) latency 468system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency 469system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 470system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency 471system.cpu.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution 472system.cpu.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution 473system.cpu.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution 474system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 475system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 476system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated | 473system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency 474system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency 475system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency 476system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::mean 10156.853282 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::gmean 8221.468352 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::stdev 7284.204444 # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::8192-16383 769 24.74% 83.33% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::16384-24575 516 16.60% 99.94% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution 487system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution 488system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution 489system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated 490system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated 491system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated |
| 477system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 492system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 478system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 479system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst | 493system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst 494system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst |
| 480system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 495system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 481system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 482system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 483system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 484system.cpu.itb.inst_hits 115574516 # ITB inst hits 485system.cpu.itb.inst_misses 4762 # ITB inst misses | 496system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst 499system.cpu.itb.inst_hits 115559307 # ITB inst hits 500system.cpu.itb.inst_misses 4763 # ITB inst misses |
| 486system.cpu.itb.read_hits 0 # DTB read hits 487system.cpu.itb.read_misses 0 # DTB read misses 488system.cpu.itb.write_hits 0 # DTB write hits 489system.cpu.itb.write_misses 0 # DTB write misses 490system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 491system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 492system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 493system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 494system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 495system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 496system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 497system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 498system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 499system.cpu.itb.read_accesses 0 # DTB read accesses 500system.cpu.itb.write_accesses 0 # DTB write accesses | 501system.cpu.itb.read_hits 0 # DTB read hits 502system.cpu.itb.read_misses 0 # DTB read misses 503system.cpu.itb.write_hits 0 # DTB write hits 504system.cpu.itb.write_misses 0 # DTB write misses 505system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 506system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 507system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 508system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 509system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 510system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 511system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 512system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 513system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 514system.cpu.itb.read_accesses 0 # DTB read accesses 515system.cpu.itb.write_accesses 0 # DTB write accesses |
| 501system.cpu.itb.inst_accesses 115579278 # ITB inst accesses 502system.cpu.itb.hits 115574516 # DTB hits 503system.cpu.itb.misses 4762 # DTB misses 504system.cpu.itb.accesses 115579278 # DTB accesses 505system.cpu.numPwrStateTransitions 6062 # Number of power state transitions 506system.cpu.pwrStateClkGateDist::samples 3031 # Distribution of time spent in the clock gated state 507system.cpu.pwrStateClkGateDist::mean 888232478.174860 # Distribution of time spent in the clock gated state 508system.cpu.pwrStateClkGateDist::stdev 17469824950.226959 # Distribution of time spent in the clock gated state 509system.cpu.pwrStateClkGateDist::underflows 2968 97.92% 97.92% # Distribution of time spent in the clock gated state 510system.cpu.pwrStateClkGateDist::1000-5e+10 57 1.88% 99.80% # Distribution of time spent in the clock gated state | 516system.cpu.itb.inst_accesses 115564070 # ITB inst accesses 517system.cpu.itb.hits 115559307 # DTB hits 518system.cpu.itb.misses 4763 # DTB misses 519system.cpu.itb.accesses 115564070 # DTB accesses 520system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 521system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state 522system.cpu.pwrStateClkGateDist::mean 887205638.526871 # Distribution of time spent in the clock gated state 523system.cpu.pwrStateClkGateDist::stdev 17463817933.974155 # Distribution of time spent in the clock gated state 524system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state 525system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state |
| 511system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 512system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 513system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 514system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 515system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 526system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 527system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 528system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 529system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 530system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 516system.cpu.pwrStateClkGateDist::max_value 499964073052 # Distribution of time spent in the clock gated state 517system.cpu.pwrStateClkGateDist::total 3031 # Distribution of time spent in the clock gated state 518system.cpu.pwrStateResidencyTicks::ON 211504149152 # Cumulative time (in ticks) in various power states 519system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348 # Cumulative time (in ticks) in various power states 520system.cpu.numCycles 5807473581 # number of cpu cycles simulated | 531system.cpu.pwrStateClkGateDist::max_value 499962880972 # Distribution of time spent in the clock gated state 532system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state 533system.cpu.pwrStateResidencyTicks::ON 214403080848 # Cumulative time (in ticks) in various power states 534system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652 # Cumulative time (in ticks) in various power states 535system.cpu.numCycles 5810595565 # number of cpu cycles simulated |
| 521system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 522system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 523system.cpu.kern.inst.arm 0 # number of arm instructions executed | 536system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 537system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 538system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 524system.cpu.kern.inst.quiesce 3031 # number of quiesce instructions executed 525system.cpu.committedInsts 112476413 # Number of instructions committed 526system.cpu.committedOps 135613231 # Number of ops (including micro ops) committed 527system.cpu.num_int_alu_accesses 119916333 # Number of integer alu accesses 528system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 529system.cpu.num_func_calls 9896179 # number of times a function call or return occured 530system.cpu.num_conditional_control_insts 15232917 # number of instructions that are conditional controls 531system.cpu.num_int_insts 119916333 # number of integer instructions 532system.cpu.num_fp_insts 11161 # number of float instructions 533system.cpu.num_int_register_reads 218092554 # number of times the integer registers were read 534system.cpu.num_int_register_writes 82663252 # number of times the integer registers were written 535system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read | 539system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 540system.cpu.committedInsts 112461365 # Number of instructions committed 541system.cpu.committedOps 135593151 # Number of ops (including micro ops) committed 542system.cpu.num_int_alu_accesses 119897812 # Number of integer alu accesses 543system.cpu.num_fp_alu_accesses 11226 # Number of float alu accesses 544system.cpu.num_func_calls 9894928 # number of times a function call or return occured 545system.cpu.num_conditional_control_insts 15231225 # number of instructions that are conditional controls 546system.cpu.num_int_insts 119897812 # number of integer instructions 547system.cpu.num_fp_insts 11226 # number of float instructions 548system.cpu.num_int_register_reads 218061607 # number of times the integer registers were read 549system.cpu.num_int_register_writes 82648736 # number of times the integer registers were written 550system.cpu.num_fp_register_reads 8514 # number of times the floating registers were read |
| 536system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written | 551system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written |
| 537system.cpu.num_cc_register_reads 489835813 # number of times the CC registers were read 538system.cpu.num_cc_register_writes 51902110 # number of times the CC registers were written 539system.cpu.num_mem_refs 45414800 # number of memory refs 540system.cpu.num_load_insts 24847736 # Number of load instructions 541system.cpu.num_store_insts 20567064 # Number of store instructions 542system.cpu.num_idle_cycles 5384465282.694146 # Number of idle cycles 543system.cpu.num_busy_cycles 423008298.305854 # Number of busy cycles 544system.cpu.not_idle_fraction 0.072839 # Percentage of non-idle cycles 545system.cpu.idle_fraction 0.927161 # Percentage of idle cycles 546system.cpu.Branches 25923023 # Number of branches fetched | 552system.cpu.num_cc_register_reads 489758493 # number of times the CC registers were read 553system.cpu.num_cc_register_writes 51897030 # number of times the CC registers were written 554system.cpu.num_mem_refs 45406070 # number of memory refs 555system.cpu.num_load_insts 24842315 # Number of load instructions 556system.cpu.num_store_insts 20563755 # Number of store instructions 557system.cpu.num_idle_cycles 5381789403.302147 # Number of idle cycles 558system.cpu.num_busy_cycles 428806161.697852 # Number of busy cycles 559system.cpu.not_idle_fraction 0.073797 # Percentage of non-idle cycles 560system.cpu.idle_fraction 0.926203 # Percentage of idle cycles 561system.cpu.Branches 25920117 # Number of branches fetched |
| 547system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction | 562system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction |
| 548system.cpu.op_class::IntAlu 93194210 67.17% 67.18% # Class of executed instruction 549system.cpu.op_class::IntMult 114540 0.08% 67.26% # Class of executed instruction | 563system.cpu.op_class::IntAlu 93182494 67.18% 67.18% # Class of executed instruction 564system.cpu.op_class::IntMult 114558 0.08% 67.26% # Class of executed instruction |
| 550system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 551system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 552system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 553system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 554system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 555system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 556system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 557system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 565system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 566system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 567system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 568system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 569system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 570system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 571system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 572system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction | 565system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 566system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 567system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 568system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 569system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 570system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 571system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 572system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 580system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 581system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 582system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 583system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 584system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 585system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 586system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 587system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction |
| 573system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction 574system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 575system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 576system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 577system.cpu.op_class::MemRead 24847736 17.91% 85.18% # Class of executed instruction 578system.cpu.op_class::MemWrite 20567064 14.82% 100.00% # Class of executed instruction | 588system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Class of executed instruction 589system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction 590system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction 591system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction 592system.cpu.op_class::MemRead 24842315 17.91% 85.18% # Class of executed instruction 593system.cpu.op_class::MemWrite 20563755 14.82% 100.00% # Class of executed instruction |
| 579system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 580system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 594system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 595system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 581system.cpu.op_class::total 138734340 # Class of executed instruction 582system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 583system.cpu.dcache.tags.replacements 819770 # number of replacements 584system.cpu.dcache.tags.tagsinuse 511.827215 # Cycle average of tags in use 585system.cpu.dcache.tags.total_refs 43243016 # Total number of references to valid blocks. 586system.cpu.dcache.tags.sampled_refs 820282 # Sample count of references to valid blocks. 587system.cpu.dcache.tags.avg_refs 52.717256 # Average number of references to valid blocks. 588system.cpu.dcache.tags.warmup_cycle 1013099500 # Cycle when the warmup percentage was hit. 589system.cpu.dcache.tags.occ_blocks::cpu.data 511.827215 # Average occupied blocks per requestor 590system.cpu.dcache.tags.occ_percent::cpu.data 0.999663 # Average percentage of cache occupancy 591system.cpu.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy | 596system.cpu.op_class::total 138713890 # Class of executed instruction 597system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 598system.cpu.dcache.tags.replacements 821351 # number of replacements 599system.cpu.dcache.tags.tagsinuse 511.816254 # Cycle average of tags in use 600system.cpu.dcache.tags.total_refs 43232645 # Total number of references to valid blocks. 601system.cpu.dcache.tags.sampled_refs 821863 # Sample count of references to valid blocks. 602system.cpu.dcache.tags.avg_refs 52.603226 # Average number of references to valid blocks. 603system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit. 604system.cpu.dcache.tags.occ_blocks::cpu.data 511.816254 # Average occupied blocks per requestor 605system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy 606system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy |
| 592system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 607system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 593system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 594system.cpu.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id 595system.cpu.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id 596system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 608system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 609system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
| 597system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 612system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 598system.cpu.dcache.tags.tag_accesses 177141047 # Number of tag accesses 599system.cpu.dcache.tags.data_accesses 177141047 # Number of data accesses 600system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 601system.cpu.dcache.ReadReq_hits::cpu.data 23117557 # number of ReadReq hits 602system.cpu.dcache.ReadReq_hits::total 23117557 # number of ReadReq hits 603system.cpu.dcache.WriteReq_hits::cpu.data 18826251 # number of WriteReq hits 604system.cpu.dcache.WriteReq_hits::total 18826251 # number of WriteReq hits 605system.cpu.dcache.SoftPFReq_hits::cpu.data 392764 # number of SoftPFReq hits 606system.cpu.dcache.SoftPFReq_hits::total 392764 # number of SoftPFReq hits 607system.cpu.dcache.LoadLockedReq_hits::cpu.data 443415 # number of LoadLockedReq hits 608system.cpu.dcache.LoadLockedReq_hits::total 443415 # number of LoadLockedReq hits 609system.cpu.dcache.StoreCondReq_hits::cpu.data 460277 # number of StoreCondReq hits 610system.cpu.dcache.StoreCondReq_hits::total 460277 # number of StoreCondReq hits 611system.cpu.dcache.demand_hits::cpu.data 41943808 # number of demand (read+write) hits 612system.cpu.dcache.demand_hits::total 41943808 # number of demand (read+write) hits 613system.cpu.dcache.overall_hits::cpu.data 42336572 # number of overall hits 614system.cpu.dcache.overall_hits::total 42336572 # number of overall hits 615system.cpu.dcache.ReadReq_misses::cpu.data 400061 # number of ReadReq misses 616system.cpu.dcache.ReadReq_misses::total 400061 # number of ReadReq misses 617system.cpu.dcache.WriteReq_misses::cpu.data 298752 # number of WriteReq misses 618system.cpu.dcache.WriteReq_misses::total 298752 # number of WriteReq misses 619system.cpu.dcache.SoftPFReq_misses::cpu.data 118460 # number of SoftPFReq misses 620system.cpu.dcache.SoftPFReq_misses::total 118460 # number of SoftPFReq misses 621system.cpu.dcache.LoadLockedReq_misses::cpu.data 22645 # number of LoadLockedReq misses 622system.cpu.dcache.LoadLockedReq_misses::total 22645 # number of LoadLockedReq misses | 613system.cpu.dcache.tags.tag_accesses 177108261 # Number of tag accesses 614system.cpu.dcache.tags.data_accesses 177108261 # Number of data accesses 615system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 616system.cpu.dcache.ReadReq_hits::cpu.data 23111024 # number of ReadReq hits 617system.cpu.dcache.ReadReq_hits::total 23111024 # number of ReadReq hits 618system.cpu.dcache.WriteReq_hits::cpu.data 18823159 # number of WriteReq hits 619system.cpu.dcache.WriteReq_hits::total 18823159 # number of WriteReq hits 620system.cpu.dcache.SoftPFReq_hits::cpu.data 392414 # number of SoftPFReq hits 621system.cpu.dcache.SoftPFReq_hits::total 392414 # number of SoftPFReq hits 622system.cpu.dcache.LoadLockedReq_hits::cpu.data 443071 # number of LoadLockedReq hits 623system.cpu.dcache.LoadLockedReq_hits::total 443071 # number of LoadLockedReq hits 624system.cpu.dcache.StoreCondReq_hits::cpu.data 460161 # number of StoreCondReq hits 625system.cpu.dcache.StoreCondReq_hits::total 460161 # number of StoreCondReq hits 626system.cpu.dcache.demand_hits::cpu.data 41934183 # number of demand (read+write) hits 627system.cpu.dcache.demand_hits::total 41934183 # number of demand (read+write) hits 628system.cpu.dcache.overall_hits::cpu.data 42326597 # number of overall hits 629system.cpu.dcache.overall_hits::total 42326597 # number of overall hits 630system.cpu.dcache.ReadReq_misses::cpu.data 401452 # number of ReadReq misses 631system.cpu.dcache.ReadReq_misses::total 401452 # number of ReadReq misses 632system.cpu.dcache.WriteReq_misses::cpu.data 298737 # number of WriteReq misses 633system.cpu.dcache.WriteReq_misses::total 298737 # number of WriteReq misses 634system.cpu.dcache.SoftPFReq_misses::cpu.data 118712 # number of SoftPFReq misses 635system.cpu.dcache.SoftPFReq_misses::total 118712 # number of SoftPFReq misses 636system.cpu.dcache.LoadLockedReq_misses::cpu.data 22861 # number of LoadLockedReq misses 637system.cpu.dcache.LoadLockedReq_misses::total 22861 # number of LoadLockedReq misses |
| 623system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 624system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 638system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 639system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 625system.cpu.dcache.demand_misses::cpu.data 698813 # number of demand (read+write) misses 626system.cpu.dcache.demand_misses::total 698813 # number of demand (read+write) misses 627system.cpu.dcache.overall_misses::cpu.data 817273 # number of overall misses 628system.cpu.dcache.overall_misses::total 817273 # number of overall misses 629system.cpu.dcache.ReadReq_miss_latency::cpu.data 5967732500 # number of ReadReq miss cycles 630system.cpu.dcache.ReadReq_miss_latency::total 5967732500 # number of ReadReq miss cycles 631system.cpu.dcache.WriteReq_miss_latency::cpu.data 12596392000 # number of WriteReq miss cycles 632system.cpu.dcache.WriteReq_miss_latency::total 12596392000 # number of WriteReq miss cycles 633system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280149500 # number of LoadLockedReq miss cycles 634system.cpu.dcache.LoadLockedReq_miss_latency::total 280149500 # number of LoadLockedReq miss cycles | 640system.cpu.dcache.demand_misses::cpu.data 700189 # number of demand (read+write) misses 641system.cpu.dcache.demand_misses::total 700189 # number of demand (read+write) misses 642system.cpu.dcache.overall_misses::cpu.data 818901 # number of overall misses 643system.cpu.dcache.overall_misses::total 818901 # number of overall misses 644system.cpu.dcache.ReadReq_miss_latency::cpu.data 6440957000 # number of ReadReq miss cycles 645system.cpu.dcache.ReadReq_miss_latency::total 6440957000 # number of ReadReq miss cycles 646system.cpu.dcache.WriteReq_miss_latency::cpu.data 14361709000 # number of WriteReq miss cycles 647system.cpu.dcache.WriteReq_miss_latency::total 14361709000 # number of WriteReq miss cycles 648system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 300793500 # number of LoadLockedReq miss cycles 649system.cpu.dcache.LoadLockedReq_miss_latency::total 300793500 # number of LoadLockedReq miss cycles |
| 635system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles 636system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles | 650system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles 651system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles |
| 637system.cpu.dcache.demand_miss_latency::cpu.data 18564124500 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 18564124500 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 18564124500 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 18564124500 # number of overall miss cycles 641system.cpu.dcache.ReadReq_accesses::cpu.data 23517618 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 23517618 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::cpu.data 19125003 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 19125003 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.SoftPFReq_accesses::cpu.data 511224 # number of SoftPFReq accesses(hits+misses) 646system.cpu.dcache.SoftPFReq_accesses::total 511224 # number of SoftPFReq accesses(hits+misses) 647system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466060 # number of LoadLockedReq accesses(hits+misses) 648system.cpu.dcache.LoadLockedReq_accesses::total 466060 # number of LoadLockedReq accesses(hits+misses) 649system.cpu.dcache.StoreCondReq_accesses::cpu.data 460279 # number of StoreCondReq accesses(hits+misses) 650system.cpu.dcache.StoreCondReq_accesses::total 460279 # number of StoreCondReq accesses(hits+misses) 651system.cpu.dcache.demand_accesses::cpu.data 42642621 # number of demand (read+write) accesses 652system.cpu.dcache.demand_accesses::total 42642621 # number of demand (read+write) accesses 653system.cpu.dcache.overall_accesses::cpu.data 43153845 # number of overall (read+write) accesses 654system.cpu.dcache.overall_accesses::total 43153845 # number of overall (read+write) accesses 655system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017011 # miss rate for ReadReq accesses 656system.cpu.dcache.ReadReq_miss_rate::total 0.017011 # miss rate for ReadReq accesses 657system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015621 # miss rate for WriteReq accesses 658system.cpu.dcache.WriteReq_miss_rate::total 0.015621 # miss rate for WriteReq accesses 659system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231718 # miss rate for SoftPFReq accesses 660system.cpu.dcache.SoftPFReq_miss_rate::total 0.231718 # miss rate for SoftPFReq accesses 661system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048588 # miss rate for LoadLockedReq accesses 662system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048588 # miss rate for LoadLockedReq accesses | 652system.cpu.dcache.demand_miss_latency::cpu.data 20802666000 # number of demand (read+write) miss cycles 653system.cpu.dcache.demand_miss_latency::total 20802666000 # number of demand (read+write) miss cycles 654system.cpu.dcache.overall_miss_latency::cpu.data 20802666000 # number of overall miss cycles 655system.cpu.dcache.overall_miss_latency::total 20802666000 # number of overall miss cycles 656system.cpu.dcache.ReadReq_accesses::cpu.data 23512476 # number of ReadReq accesses(hits+misses) 657system.cpu.dcache.ReadReq_accesses::total 23512476 # number of ReadReq accesses(hits+misses) 658system.cpu.dcache.WriteReq_accesses::cpu.data 19121896 # number of WriteReq accesses(hits+misses) 659system.cpu.dcache.WriteReq_accesses::total 19121896 # number of WriteReq accesses(hits+misses) 660system.cpu.dcache.SoftPFReq_accesses::cpu.data 511126 # number of SoftPFReq accesses(hits+misses) 661system.cpu.dcache.SoftPFReq_accesses::total 511126 # number of SoftPFReq accesses(hits+misses) 662system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465932 # number of LoadLockedReq accesses(hits+misses) 663system.cpu.dcache.LoadLockedReq_accesses::total 465932 # number of LoadLockedReq accesses(hits+misses) 664system.cpu.dcache.StoreCondReq_accesses::cpu.data 460163 # number of StoreCondReq accesses(hits+misses) 665system.cpu.dcache.StoreCondReq_accesses::total 460163 # number of StoreCondReq accesses(hits+misses) 666system.cpu.dcache.demand_accesses::cpu.data 42634372 # number of demand (read+write) accesses 667system.cpu.dcache.demand_accesses::total 42634372 # number of demand (read+write) accesses 668system.cpu.dcache.overall_accesses::cpu.data 43145498 # number of overall (read+write) accesses 669system.cpu.dcache.overall_accesses::total 43145498 # number of overall (read+write) accesses 670system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017074 # miss rate for ReadReq accesses 671system.cpu.dcache.ReadReq_miss_rate::total 0.017074 # miss rate for ReadReq accesses 672system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015623 # miss rate for WriteReq accesses 673system.cpu.dcache.WriteReq_miss_rate::total 0.015623 # miss rate for WriteReq accesses 674system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232256 # miss rate for SoftPFReq accesses 675system.cpu.dcache.SoftPFReq_miss_rate::total 0.232256 # miss rate for SoftPFReq accesses 676system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.049065 # miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_miss_rate::total 0.049065 # miss rate for LoadLockedReq accesses |
| 663system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 664system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses | 678system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 679system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses |
| 665system.cpu.dcache.demand_miss_rate::cpu.data 0.016388 # miss rate for demand accesses 666system.cpu.dcache.demand_miss_rate::total 0.016388 # miss rate for demand accesses 667system.cpu.dcache.overall_miss_rate::cpu.data 0.018939 # miss rate for overall accesses 668system.cpu.dcache.overall_miss_rate::total 0.018939 # miss rate for overall accesses 669system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399 # average ReadReq miss latency 670system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399 # average ReadReq miss latency 671system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965 # average WriteReq miss latency 672system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965 # average WriteReq miss latency 673system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332 # average LoadLockedReq miss latency 674system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332 # average LoadLockedReq miss latency | 680system.cpu.dcache.demand_miss_rate::cpu.data 0.016423 # miss rate for demand accesses 681system.cpu.dcache.demand_miss_rate::total 0.016423 # miss rate for demand accesses 682system.cpu.dcache.overall_miss_rate::cpu.data 0.018980 # miss rate for overall accesses 683system.cpu.dcache.overall_miss_rate::total 0.018980 # miss rate for overall accesses 684system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16044.152227 # average ReadReq miss latency 685system.cpu.dcache.ReadReq_avg_miss_latency::total 16044.152227 # average ReadReq miss latency 686system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48074.758065 # average WriteReq miss latency 687system.cpu.dcache.WriteReq_avg_miss_latency::total 48074.758065 # average WriteReq miss latency 688system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13157.495298 # average LoadLockedReq miss latency 689system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13157.495298 # average LoadLockedReq miss latency |
| 675system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 676system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency | 690system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 691system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency |
| 677system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.224888 # average overall miss latency 678system.cpu.dcache.demand_avg_miss_latency::total 26565.224888 # average overall miss latency 679system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502 # average overall miss latency 680system.cpu.dcache.overall_avg_miss_latency::total 22714.716502 # average overall miss latency | 692system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566 # average overall miss latency 693system.cpu.dcache.demand_avg_miss_latency::total 29710.072566 # average overall miss latency 694system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297 # average overall miss latency 695system.cpu.dcache.overall_avg_miss_latency::total 25403.151297 # average overall miss latency |
| 681system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked 682system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 683system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked 684system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 685system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked 686system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 696system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked 697system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 698system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked 699system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 700system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked 701system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 687system.cpu.dcache.writebacks::writebacks 683946 # number of writebacks 688system.cpu.dcache.writebacks::total 683946 # number of writebacks 689system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits 690system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits 691system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14146 # number of LoadLockedReq MSHR hits 692system.cpu.dcache.LoadLockedReq_mshr_hits::total 14146 # number of LoadLockedReq MSHR hits 693system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits 694system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits 695system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits 696system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits 697system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399381 # number of ReadReq MSHR misses 698system.cpu.dcache.ReadReq_mshr_misses::total 399381 # number of ReadReq MSHR misses 699system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298752 # number of WriteReq MSHR misses 700system.cpu.dcache.WriteReq_mshr_misses::total 298752 # number of WriteReq MSHR misses 701system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116429 # number of SoftPFReq MSHR misses 702system.cpu.dcache.SoftPFReq_mshr_misses::total 116429 # number of SoftPFReq MSHR misses 703system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8499 # number of LoadLockedReq MSHR misses 704system.cpu.dcache.LoadLockedReq_mshr_misses::total 8499 # number of LoadLockedReq MSHR misses | 702system.cpu.dcache.writebacks::writebacks 685561 # number of writebacks 703system.cpu.dcache.writebacks::total 685561 # number of writebacks 704system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705 # number of ReadReq MSHR hits 705system.cpu.dcache.ReadReq_mshr_hits::total 705 # number of ReadReq MSHR hits 706system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14335 # number of LoadLockedReq MSHR hits 707system.cpu.dcache.LoadLockedReq_mshr_hits::total 14335 # number of LoadLockedReq MSHR hits 708system.cpu.dcache.demand_mshr_hits::cpu.data 705 # number of demand (read+write) MSHR hits 709system.cpu.dcache.demand_mshr_hits::total 705 # number of demand (read+write) MSHR hits 710system.cpu.dcache.overall_mshr_hits::cpu.data 705 # number of overall MSHR hits 711system.cpu.dcache.overall_mshr_hits::total 705 # number of overall MSHR hits 712system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400747 # number of ReadReq MSHR misses 713system.cpu.dcache.ReadReq_mshr_misses::total 400747 # number of ReadReq MSHR misses 714system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298737 # number of WriteReq MSHR misses 715system.cpu.dcache.WriteReq_mshr_misses::total 298737 # number of WriteReq MSHR misses 716system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116693 # number of SoftPFReq MSHR misses 717system.cpu.dcache.SoftPFReq_mshr_misses::total 116693 # number of SoftPFReq MSHR misses 718system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8526 # number of LoadLockedReq MSHR misses 719system.cpu.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses |
| 705system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 706system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 720system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 721system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 707system.cpu.dcache.demand_mshr_misses::cpu.data 698133 # number of demand (read+write) MSHR misses 708system.cpu.dcache.demand_mshr_misses::total 698133 # number of demand (read+write) MSHR misses 709system.cpu.dcache.overall_mshr_misses::cpu.data 814562 # number of overall MSHR misses 710system.cpu.dcache.overall_mshr_misses::total 814562 # number of overall MSHR misses | 722system.cpu.dcache.demand_mshr_misses::cpu.data 699484 # number of demand (read+write) MSHR misses 723system.cpu.dcache.demand_mshr_misses::total 699484 # number of demand (read+write) MSHR misses 724system.cpu.dcache.overall_mshr_misses::cpu.data 816177 # number of overall MSHR misses 725system.cpu.dcache.overall_mshr_misses::total 816177 # number of overall MSHR misses |
| 711system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 712system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable 713system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 714system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 715system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 716system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses | 726system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 727system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable 728system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 729system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 730system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 731system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses |
| 717system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5555392000 # number of ReadReq MSHR miss cycles 718system.cpu.dcache.ReadReq_mshr_miss_latency::total 5555392000 # number of ReadReq MSHR miss cycles 719system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12297640000 # number of WriteReq MSHR miss cycles 720system.cpu.dcache.WriteReq_mshr_miss_latency::total 12297640000 # number of WriteReq MSHR miss cycles 721system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1530002500 # number of SoftPFReq MSHR miss cycles 722system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1530002500 # number of SoftPFReq MSHR miss cycles 723system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 108858500 # number of LoadLockedReq MSHR miss cycles 724system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108858500 # number of LoadLockedReq MSHR miss cycles | 732system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015919500 # number of ReadReq MSHR miss cycles 733system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015919500 # number of ReadReq MSHR miss cycles 734system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14062972000 # number of WriteReq MSHR miss cycles 735system.cpu.dcache.WriteReq_mshr_miss_latency::total 14062972000 # number of WriteReq MSHR miss cycles 736system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1582474000 # number of SoftPFReq MSHR miss cycles 737system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1582474000 # number of SoftPFReq MSHR miss cycles 738system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 120274000 # number of LoadLockedReq MSHR miss cycles 739system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 120274000 # number of LoadLockedReq MSHR miss cycles |
| 725system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles 726system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles | 740system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles 741system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles |
| 727system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17853032000 # number of demand (read+write) MSHR miss cycles 728system.cpu.dcache.demand_mshr_miss_latency::total 17853032000 # number of demand (read+write) MSHR miss cycles 729system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19383034500 # number of overall MSHR miss cycles 730system.cpu.dcache.overall_mshr_miss_latency::total 19383034500 # number of overall MSHR miss cycles 731system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281205500 # number of ReadReq MSHR uncacheable cycles 732system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281205500 # number of ReadReq MSHR uncacheable cycles 733system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281205500 # number of overall MSHR uncacheable cycles 734system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281205500 # number of overall MSHR uncacheable cycles 735system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016982 # mshr miss rate for ReadReq accesses 736system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016982 # mshr miss rate for ReadReq accesses 737system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses 738system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses 739system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227746 # mshr miss rate for SoftPFReq accesses 740system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227746 # mshr miss rate for SoftPFReq accesses 741system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018236 # mshr miss rate for LoadLockedReq accesses 742system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018236 # mshr miss rate for LoadLockedReq accesses | 742system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20078891500 # number of demand (read+write) MSHR miss cycles 743system.cpu.dcache.demand_mshr_miss_latency::total 20078891500 # number of demand (read+write) MSHR miss cycles 744system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21661365500 # number of overall MSHR miss cycles 745system.cpu.dcache.overall_mshr_miss_latency::total 21661365500 # number of overall MSHR miss cycles 746system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284842500 # number of ReadReq MSHR uncacheable cycles 747system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284842500 # number of ReadReq MSHR uncacheable cycles 748system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284842500 # number of overall MSHR uncacheable cycles 749system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284842500 # number of overall MSHR uncacheable cycles 750system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017044 # mshr miss rate for ReadReq accesses 751system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017044 # mshr miss rate for ReadReq accesses 752system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses 753system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses 754system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228306 # mshr miss rate for SoftPFReq accesses 755system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228306 # mshr miss rate for SoftPFReq accesses 756system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018299 # mshr miss rate for LoadLockedReq accesses 757system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018299 # mshr miss rate for LoadLockedReq accesses |
| 743system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 744system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses | 758system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 759system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses |
| 745system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016372 # mshr miss rate for demand accesses 746system.cpu.dcache.demand_mshr_miss_rate::total 0.016372 # mshr miss rate for demand accesses 747system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018876 # mshr miss rate for overall accesses 748system.cpu.dcache.overall_mshr_miss_rate::total 0.018876 # mshr miss rate for overall accesses 749system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13910.005734 # average ReadReq mshr miss latency 750system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734 # average ReadReq mshr miss latency 751system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965 # average WriteReq mshr miss latency 752system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965 # average WriteReq mshr miss latency 753system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395 # average SoftPFReq mshr miss latency 754system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395 # average SoftPFReq mshr miss latency 755system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222 # average LoadLockedReq mshr miss latency 756system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222 # average LoadLockedReq mshr miss latency | 760system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016407 # mshr miss rate for demand accesses 761system.cpu.dcache.demand_mshr_miss_rate::total 0.016407 # mshr miss rate for demand accesses 762system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018917 # mshr miss rate for overall accesses 763system.cpu.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses 764system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15011.764280 # average ReadReq mshr miss latency 765system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15011.764280 # average ReadReq mshr miss latency 766system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47074.758065 # average WriteReq mshr miss latency 767system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47074.758065 # average WriteReq mshr miss latency 768system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13561.001945 # average SoftPFReq mshr miss latency 769system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13561.001945 # average SoftPFReq mshr miss latency 770system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14106.732348 # average LoadLockedReq mshr miss latency 771system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14106.732348 # average LoadLockedReq mshr miss latency |
| 757system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 758system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency | 772system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 773system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency |
| 759system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25572.537038 # average overall mshr miss latency 760system.cpu.dcache.demand_avg_mshr_miss_latency::total 25572.537038 # average overall mshr miss latency 761system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23795.652756 # average overall mshr miss latency 762system.cpu.dcache.overall_avg_mshr_miss_latency::total 23795.652756 # average overall mshr miss latency 763system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201721.546021 # average ReadReq mshr uncacheable latency 764system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.546021 # average ReadReq mshr uncacheable latency 765system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310 # average overall mshr uncacheable latency 766system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310 # average overall mshr uncacheable latency 767system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 768system.cpu.icache.tags.replacements 1698000 # number of replacements 769system.cpu.icache.tags.tagsinuse 510.728664 # Cycle average of tags in use 770system.cpu.icache.tags.total_refs 113875998 # Total number of references to valid blocks. 771system.cpu.icache.tags.sampled_refs 1698512 # Sample count of references to valid blocks. 772system.cpu.icache.tags.avg_refs 67.044565 # Average number of references to valid blocks. 773system.cpu.icache.tags.warmup_cycle 25832791500 # Cycle when the warmup percentage was hit. 774system.cpu.icache.tags.occ_blocks::cpu.inst 510.728664 # Average occupied blocks per requestor 775system.cpu.icache.tags.occ_percent::cpu.inst 0.997517 # Average percentage of cache occupancy 776system.cpu.icache.tags.occ_percent::total 0.997517 # Average percentage of cache occupancy | 774system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28705.290614 # average overall mshr miss latency 775system.cpu.dcache.demand_avg_mshr_miss_latency::total 28705.290614 # average overall mshr miss latency 776system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26540.034208 # average overall mshr miss latency 777system.cpu.dcache.overall_avg_mshr_miss_latency::total 26540.034208 # average overall mshr miss latency 778system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201838.348642 # average ReadReq mshr uncacheable latency 779system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201838.348642 # average ReadReq mshr uncacheable latency 780system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.938938 # average overall mshr uncacheable latency 781system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.938938 # average overall mshr uncacheable latency 782system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 783system.cpu.icache.tags.replacements 1700003 # number of replacements 784system.cpu.icache.tags.tagsinuse 510.693079 # Cycle average of tags in use 785system.cpu.icache.tags.total_refs 113858786 # Total number of references to valid blocks. 786system.cpu.icache.tags.sampled_refs 1700515 # Sample count of references to valid blocks. 787system.cpu.icache.tags.avg_refs 66.955473 # Average number of references to valid blocks. 788system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit. 789system.cpu.icache.tags.occ_blocks::cpu.inst 510.693079 # Average occupied blocks per requestor 790system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy 791system.cpu.icache.tags.occ_percent::total 0.997447 # Average percentage of cache occupancy |
| 777system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 792system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 778system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 779system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 780system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 781system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id | 793system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 794system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id 795system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id 796system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id |
| 782system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 797system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 783system.cpu.icache.tags.tag_accesses 117273034 # Number of tag accesses 784system.cpu.icache.tags.data_accesses 117273034 # Number of data accesses 785system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 786system.cpu.icache.ReadReq_hits::cpu.inst 113875998 # number of ReadReq hits 787system.cpu.icache.ReadReq_hits::total 113875998 # number of ReadReq hits 788system.cpu.icache.demand_hits::cpu.inst 113875998 # number of demand (read+write) hits 789system.cpu.icache.demand_hits::total 113875998 # number of demand (read+write) hits 790system.cpu.icache.overall_hits::cpu.inst 113875998 # number of overall hits 791system.cpu.icache.overall_hits::total 113875998 # number of overall hits 792system.cpu.icache.ReadReq_misses::cpu.inst 1698518 # number of ReadReq misses 793system.cpu.icache.ReadReq_misses::total 1698518 # number of ReadReq misses 794system.cpu.icache.demand_misses::cpu.inst 1698518 # number of demand (read+write) misses 795system.cpu.icache.demand_misses::total 1698518 # number of demand (read+write) misses 796system.cpu.icache.overall_misses::cpu.inst 1698518 # number of overall misses 797system.cpu.icache.overall_misses::total 1698518 # number of overall misses 798system.cpu.icache.ReadReq_miss_latency::cpu.inst 23414403500 # number of ReadReq miss cycles 799system.cpu.icache.ReadReq_miss_latency::total 23414403500 # number of ReadReq miss cycles 800system.cpu.icache.demand_miss_latency::cpu.inst 23414403500 # number of demand (read+write) miss cycles 801system.cpu.icache.demand_miss_latency::total 23414403500 # number of demand (read+write) miss cycles 802system.cpu.icache.overall_miss_latency::cpu.inst 23414403500 # number of overall miss cycles 803system.cpu.icache.overall_miss_latency::total 23414403500 # number of overall miss cycles 804system.cpu.icache.ReadReq_accesses::cpu.inst 115574516 # number of ReadReq accesses(hits+misses) 805system.cpu.icache.ReadReq_accesses::total 115574516 # number of ReadReq accesses(hits+misses) 806system.cpu.icache.demand_accesses::cpu.inst 115574516 # number of demand (read+write) accesses 807system.cpu.icache.demand_accesses::total 115574516 # number of demand (read+write) accesses 808system.cpu.icache.overall_accesses::cpu.inst 115574516 # number of overall (read+write) accesses 809system.cpu.icache.overall_accesses::total 115574516 # number of overall (read+write) accesses 810system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014696 # miss rate for ReadReq accesses 811system.cpu.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses 812system.cpu.icache.demand_miss_rate::cpu.inst 0.014696 # miss rate for demand accesses 813system.cpu.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses 814system.cpu.icache.overall_miss_rate::cpu.inst 0.014696 # miss rate for overall accesses 815system.cpu.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses 816system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977 # average ReadReq miss latency 817system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977 # average ReadReq miss latency 818system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency 819system.cpu.icache.demand_avg_miss_latency::total 13785.195977 # average overall miss latency 820system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency 821system.cpu.icache.overall_avg_miss_latency::total 13785.195977 # average overall miss latency | 798system.cpu.icache.tags.tag_accesses 117259828 # Number of tag accesses 799system.cpu.icache.tags.data_accesses 117259828 # Number of data accesses 800system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 801system.cpu.icache.ReadReq_hits::cpu.inst 113858786 # number of ReadReq hits 802system.cpu.icache.ReadReq_hits::total 113858786 # number of ReadReq hits 803system.cpu.icache.demand_hits::cpu.inst 113858786 # number of demand (read+write) hits 804system.cpu.icache.demand_hits::total 113858786 # number of demand (read+write) hits 805system.cpu.icache.overall_hits::cpu.inst 113858786 # number of overall hits 806system.cpu.icache.overall_hits::total 113858786 # number of overall hits 807system.cpu.icache.ReadReq_misses::cpu.inst 1700521 # number of ReadReq misses 808system.cpu.icache.ReadReq_misses::total 1700521 # number of ReadReq misses 809system.cpu.icache.demand_misses::cpu.inst 1700521 # number of demand (read+write) misses 810system.cpu.icache.demand_misses::total 1700521 # number of demand (read+write) misses 811system.cpu.icache.overall_misses::cpu.inst 1700521 # number of overall misses 812system.cpu.icache.overall_misses::total 1700521 # number of overall misses 813system.cpu.icache.ReadReq_miss_latency::cpu.inst 24021238000 # number of ReadReq miss cycles 814system.cpu.icache.ReadReq_miss_latency::total 24021238000 # number of ReadReq miss cycles 815system.cpu.icache.demand_miss_latency::cpu.inst 24021238000 # number of demand (read+write) miss cycles 816system.cpu.icache.demand_miss_latency::total 24021238000 # number of demand (read+write) miss cycles 817system.cpu.icache.overall_miss_latency::cpu.inst 24021238000 # number of overall miss cycles 818system.cpu.icache.overall_miss_latency::total 24021238000 # number of overall miss cycles 819system.cpu.icache.ReadReq_accesses::cpu.inst 115559307 # number of ReadReq accesses(hits+misses) 820system.cpu.icache.ReadReq_accesses::total 115559307 # number of ReadReq accesses(hits+misses) 821system.cpu.icache.demand_accesses::cpu.inst 115559307 # number of demand (read+write) accesses 822system.cpu.icache.demand_accesses::total 115559307 # number of demand (read+write) accesses 823system.cpu.icache.overall_accesses::cpu.inst 115559307 # number of overall (read+write) accesses 824system.cpu.icache.overall_accesses::total 115559307 # number of overall (read+write) accesses 825system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses 826system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses 827system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses 828system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses 829system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses 830system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses 831system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854 # average ReadReq miss latency 832system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854 # average ReadReq miss latency 833system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency 834system.cpu.icache.demand_avg_miss_latency::total 14125.810854 # average overall miss latency 835system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency 836system.cpu.icache.overall_avg_miss_latency::total 14125.810854 # average overall miss latency |
| 822system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 823system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 824system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 825system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 826system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 827system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 837system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 828system.cpu.icache.writebacks::writebacks 1698000 # number of writebacks 829system.cpu.icache.writebacks::total 1698000 # number of writebacks 830system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1698518 # number of ReadReq MSHR misses 831system.cpu.icache.ReadReq_mshr_misses::total 1698518 # number of ReadReq MSHR misses 832system.cpu.icache.demand_mshr_misses::cpu.inst 1698518 # number of demand (read+write) MSHR misses 833system.cpu.icache.demand_mshr_misses::total 1698518 # number of demand (read+write) MSHR misses 834system.cpu.icache.overall_mshr_misses::cpu.inst 1698518 # number of overall MSHR misses 835system.cpu.icache.overall_mshr_misses::total 1698518 # number of overall MSHR misses | 843system.cpu.icache.writebacks::writebacks 1700003 # number of writebacks 844system.cpu.icache.writebacks::total 1700003 # number of writebacks 845system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700521 # number of ReadReq MSHR misses 846system.cpu.icache.ReadReq_mshr_misses::total 1700521 # number of ReadReq MSHR misses 847system.cpu.icache.demand_mshr_misses::cpu.inst 1700521 # number of demand (read+write) MSHR misses 848system.cpu.icache.demand_mshr_misses::total 1700521 # number of demand (read+write) MSHR misses 849system.cpu.icache.overall_mshr_misses::cpu.inst 1700521 # number of overall MSHR misses 850system.cpu.icache.overall_mshr_misses::total 1700521 # number of overall MSHR misses |
| 836system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 837system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 838system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 839system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses | 851system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 852system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 853system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 854system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses |
| 840system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21715885500 # number of ReadReq MSHR miss cycles 841system.cpu.icache.ReadReq_mshr_miss_latency::total 21715885500 # number of ReadReq MSHR miss cycles 842system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21715885500 # number of demand (read+write) MSHR miss cycles 843system.cpu.icache.demand_mshr_miss_latency::total 21715885500 # number of demand (read+write) MSHR miss cycles 844system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21715885500 # number of overall MSHR miss cycles 845system.cpu.icache.overall_mshr_miss_latency::total 21715885500 # number of overall MSHR miss cycles 846system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 687287000 # number of ReadReq MSHR uncacheable cycles 847system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles 848system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 687287000 # number of overall MSHR uncacheable cycles 849system.cpu.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles 850system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for ReadReq accesses 851system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses 852system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for demand accesses 853system.cpu.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses 854system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for overall accesses 855system.cpu.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses 856system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977 # average ReadReq mshr miss latency 857system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977 # average ReadReq mshr miss latency 858system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency 859system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency 860system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency 861system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency 862system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average ReadReq mshr uncacheable latency 863system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency 864system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average overall mshr uncacheable latency 865system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency 866system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 867system.cpu.l2cache.tags.replacements 89464 # number of replacements 868system.cpu.l2cache.tags.tagsinuse 65017.694965 # Cycle average of tags in use 869system.cpu.l2cache.tags.total_refs 4847707 # Total number of references to valid blocks. 870system.cpu.l2cache.tags.sampled_refs 154877 # Sample count of references to valid blocks. 871system.cpu.l2cache.tags.avg_refs 31.300367 # Average number of references to valid blocks. 872system.cpu.l2cache.tags.warmup_cycle 144041988000 # Cycle when the warmup percentage was hit. 873system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.877834 # Average occupied blocks per requestor 874system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.040783 # Average occupied blocks per requestor 875system.cpu.l2cache.tags.occ_blocks::cpu.inst 9524.120186 # Average occupied blocks per requestor 876system.cpu.l2cache.tags.occ_blocks::cpu.data 55489.656162 # Average occupied blocks per requestor 877system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy | 855system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22320717000 # number of ReadReq MSHR miss cycles 856system.cpu.icache.ReadReq_mshr_miss_latency::total 22320717000 # number of ReadReq MSHR miss cycles 857system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22320717000 # number of demand (read+write) MSHR miss cycles 858system.cpu.icache.demand_mshr_miss_latency::total 22320717000 # number of demand (read+write) MSHR miss cycles 859system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22320717000 # number of overall MSHR miss cycles 860system.cpu.icache.overall_mshr_miss_latency::total 22320717000 # number of overall MSHR miss cycles 861system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles 862system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles 863system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles 864system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 # number of overall MSHR uncacheable cycles 865system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for ReadReq accesses 866system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014716 # mshr miss rate for ReadReq accesses 867system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for demand accesses 868system.cpu.icache.demand_mshr_miss_rate::total 0.014716 # mshr miss rate for demand accesses 869system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for overall accesses 870system.cpu.icache.overall_mshr_miss_rate::total 0.014716 # mshr miss rate for overall accesses 871system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13125.810854 # average ReadReq mshr miss latency 872system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13125.810854 # average ReadReq mshr miss latency 873system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency 874system.cpu.icache.demand_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency 875system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency 876system.cpu.icache.overall_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency 877system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency 878system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency 879system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency 880system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency 881system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 882system.cpu.l2cache.tags.replacements 88035 # number of replacements 883system.cpu.l2cache.tags.tagsinuse 65011.446283 # Cycle average of tags in use 884system.cpu.l2cache.tags.total_refs 4854285 # Total number of references to valid blocks. 885system.cpu.l2cache.tags.sampled_refs 153426 # Sample count of references to valid blocks. 886system.cpu.l2cache.tags.avg_refs 31.639259 # Average number of references to valid blocks. 887system.cpu.l2cache.tags.warmup_cycle 146352515000 # Cycle when the warmup percentage was hit. 888system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050747 # Average occupied blocks per requestor 889system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041160 # Average occupied blocks per requestor 890system.cpu.l2cache.tags.occ_blocks::cpu.inst 9651.725117 # Average occupied blocks per requestor 891system.cpu.l2cache.tags.occ_blocks::cpu.data 55356.629260 # Average occupied blocks per requestor 892system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy |
| 878system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy | 893system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy |
| 879system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145327 # Average percentage of cache occupancy 880system.cpu.l2cache.tags.occ_percent::cpu.data 0.846705 # Average percentage of cache occupancy 881system.cpu.l2cache.tags.occ_percent::total 0.992091 # Average percentage of cache occupancy 882system.cpu.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 883system.cpu.l2cache.tags.occ_task_id_blocks::1024 65407 # Occupied blocks per task id 884system.cpu.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 885system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 886system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 887system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4600 # Occupied blocks per task id 888system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60798 # Occupied blocks per task id 889system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 890system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998032 # Percentage of cache occupancy per task id 891system.cpu.l2cache.tags.tag_accesses 40230644 # Number of tag accesses 892system.cpu.l2cache.tags.data_accesses 40230644 # Number of data accesses 893system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 894system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5114 # number of ReadReq hits 895system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2743 # number of ReadReq hits 896system.cpu.l2cache.ReadReq_hits::total 7857 # number of ReadReq hits 897system.cpu.l2cache.WritebackDirty_hits::writebacks 683946 # number of WritebackDirty hits 898system.cpu.l2cache.WritebackDirty_hits::total 683946 # number of WritebackDirty hits 899system.cpu.l2cache.WritebackClean_hits::writebacks 1666952 # number of WritebackClean hits 900system.cpu.l2cache.WritebackClean_hits::total 1666952 # number of WritebackClean hits 901system.cpu.l2cache.UpgradeReq_hits::cpu.data 2730 # number of UpgradeReq hits 902system.cpu.l2cache.UpgradeReq_hits::total 2730 # number of UpgradeReq hits 903system.cpu.l2cache.ReadExReq_hits::cpu.data 166687 # number of ReadExReq hits 904system.cpu.l2cache.ReadExReq_hits::total 166687 # number of ReadExReq hits 905system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1680478 # number of ReadCleanReq hits 906system.cpu.l2cache.ReadCleanReq_hits::total 1680478 # number of ReadCleanReq hits 907system.cpu.l2cache.ReadSharedReq_hits::cpu.data 512210 # number of ReadSharedReq hits 908system.cpu.l2cache.ReadSharedReq_hits::total 512210 # number of ReadSharedReq hits 909system.cpu.l2cache.demand_hits::cpu.dtb.walker 5114 # number of demand (read+write) hits 910system.cpu.l2cache.demand_hits::cpu.itb.walker 2743 # number of demand (read+write) hits 911system.cpu.l2cache.demand_hits::cpu.inst 1680478 # number of demand (read+write) hits 912system.cpu.l2cache.demand_hits::cpu.data 678897 # number of demand (read+write) hits 913system.cpu.l2cache.demand_hits::total 2367232 # number of demand (read+write) hits 914system.cpu.l2cache.overall_hits::cpu.dtb.walker 5114 # number of overall hits 915system.cpu.l2cache.overall_hits::cpu.itb.walker 2743 # number of overall hits 916system.cpu.l2cache.overall_hits::cpu.inst 1680478 # number of overall hits 917system.cpu.l2cache.overall_hits::cpu.data 678897 # number of overall hits 918system.cpu.l2cache.overall_hits::total 2367232 # number of overall hits 919system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 8 # number of ReadReq misses | 894system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147274 # Average percentage of cache occupancy 895system.cpu.l2cache.tags.occ_percent::cpu.data 0.844675 # Average percentage of cache occupancy 896system.cpu.l2cache.tags.occ_percent::total 0.991996 # Average percentage of cache occupancy 897system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 898system.cpu.l2cache.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id 899system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 900system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 901system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 902system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4355 # Occupied blocks per task id 903system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60952 # Occupied blocks per task id 904system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 905system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id 906system.cpu.l2cache.tags.tag_accesses 40277345 # Number of tag accesses 907system.cpu.l2cache.tags.data_accesses 40277345 # Number of data accesses 908system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 909system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 4991 # number of ReadReq hits 910system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2669 # number of ReadReq hits 911system.cpu.l2cache.ReadReq_hits::total 7660 # number of ReadReq hits 912system.cpu.l2cache.WritebackDirty_hits::writebacks 685561 # number of WritebackDirty hits 913system.cpu.l2cache.WritebackDirty_hits::total 685561 # number of WritebackDirty hits 914system.cpu.l2cache.WritebackClean_hits::writebacks 1667726 # number of WritebackClean hits 915system.cpu.l2cache.WritebackClean_hits::total 1667726 # number of WritebackClean hits 916system.cpu.l2cache.UpgradeReq_hits::cpu.data 2795 # number of UpgradeReq hits 917system.cpu.l2cache.UpgradeReq_hits::total 2795 # number of UpgradeReq hits 918system.cpu.l2cache.ReadExReq_hits::cpu.data 168131 # number of ReadExReq hits 919system.cpu.l2cache.ReadExReq_hits::total 168131 # number of ReadExReq hits 920system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682557 # number of ReadCleanReq hits 921system.cpu.l2cache.ReadCleanReq_hits::total 1682557 # number of ReadCleanReq hits 922system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513829 # number of ReadSharedReq hits 923system.cpu.l2cache.ReadSharedReq_hits::total 513829 # number of ReadSharedReq hits 924system.cpu.l2cache.demand_hits::cpu.dtb.walker 4991 # number of demand (read+write) hits 925system.cpu.l2cache.demand_hits::cpu.itb.walker 2669 # number of demand (read+write) hits 926system.cpu.l2cache.demand_hits::cpu.inst 1682557 # number of demand (read+write) hits 927system.cpu.l2cache.demand_hits::cpu.data 681960 # number of demand (read+write) hits 928system.cpu.l2cache.demand_hits::total 2372177 # number of demand (read+write) hits 929system.cpu.l2cache.overall_hits::cpu.dtb.walker 4991 # number of overall hits 930system.cpu.l2cache.overall_hits::cpu.itb.walker 2669 # number of overall hits 931system.cpu.l2cache.overall_hits::cpu.inst 1682557 # number of overall hits 932system.cpu.l2cache.overall_hits::cpu.data 681960 # number of overall hits 933system.cpu.l2cache.overall_hits::total 2372177 # number of overall hits 934system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses |
| 920system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 935system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 921system.cpu.l2cache.ReadReq_misses::total 10 # number of ReadReq misses 922system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses 923system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses | 936system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses 937system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses 938system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses |
| 924system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 925system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 939system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 940system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 926system.cpu.l2cache.ReadExReq_misses::cpu.data 129315 # number of ReadExReq misses 927system.cpu.l2cache.ReadExReq_misses::total 129315 # number of ReadExReq misses 928system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18016 # number of ReadCleanReq misses 929system.cpu.l2cache.ReadCleanReq_misses::total 18016 # number of ReadCleanReq misses 930system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12099 # number of ReadSharedReq misses 931system.cpu.l2cache.ReadSharedReq_misses::total 12099 # number of ReadSharedReq misses 932system.cpu.l2cache.demand_misses::cpu.dtb.walker 8 # number of demand (read+write) misses | 941system.cpu.l2cache.ReadExReq_misses::cpu.data 127792 # number of ReadExReq misses 942system.cpu.l2cache.ReadExReq_misses::total 127792 # number of ReadExReq misses 943system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17948 # number of ReadCleanReq misses 944system.cpu.l2cache.ReadCleanReq_misses::total 17948 # number of ReadCleanReq misses 945system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12137 # number of ReadSharedReq misses 946system.cpu.l2cache.ReadSharedReq_misses::total 12137 # number of ReadSharedReq misses 947system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses |
| 933system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 948system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 934system.cpu.l2cache.demand_misses::cpu.inst 18016 # number of demand (read+write) misses 935system.cpu.l2cache.demand_misses::cpu.data 141414 # number of demand (read+write) misses 936system.cpu.l2cache.demand_misses::total 159440 # number of demand (read+write) misses 937system.cpu.l2cache.overall_misses::cpu.dtb.walker 8 # number of overall misses | 949system.cpu.l2cache.demand_misses::cpu.inst 17948 # number of demand (read+write) misses 950system.cpu.l2cache.demand_misses::cpu.data 139929 # number of demand (read+write) misses 951system.cpu.l2cache.demand_misses::total 157886 # number of demand (read+write) misses 952system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses |
| 938system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 953system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 939system.cpu.l2cache.overall_misses::cpu.inst 18016 # number of overall misses 940system.cpu.l2cache.overall_misses::cpu.data 141414 # number of overall misses 941system.cpu.l2cache.overall_misses::total 159440 # number of overall misses 942system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 829500 # number of ReadReq miss cycles 943system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 168000 # number of ReadReq miss cycles 944system.cpu.l2cache.ReadReq_miss_latency::total 997500 # number of ReadReq miss cycles 945system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581000 # number of UpgradeReq miss cycles 946system.cpu.l2cache.UpgradeReq_miss_latency::total 581000 # number of UpgradeReq miss cycles | 954system.cpu.l2cache.overall_misses::cpu.inst 17948 # number of overall misses 955system.cpu.l2cache.overall_misses::cpu.data 139929 # number of overall misses 956system.cpu.l2cache.overall_misses::total 157886 # number of overall misses 957system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154500 # number of ReadReq miss cycles 958system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles 959system.cpu.l2cache.ReadReq_miss_latency::total 1334500 # number of ReadReq miss cycles 960system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 555500 # number of UpgradeReq miss cycles 961system.cpu.l2cache.UpgradeReq_miss_latency::total 555500 # number of UpgradeReq miss cycles |
| 947system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles 948system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles | 962system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles 963system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles |
| 949system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10066469000 # number of ReadExReq miss cycles 950system.cpu.l2cache.ReadExReq_miss_latency::total 10066469000 # number of ReadExReq miss cycles 951system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1464060500 # number of ReadCleanReq miss cycles 952system.cpu.l2cache.ReadCleanReq_miss_latency::total 1464060500 # number of ReadCleanReq miss cycles 953system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1012302000 # number of ReadSharedReq miss cycles 954system.cpu.l2cache.ReadSharedReq_miss_latency::total 1012302000 # number of ReadSharedReq miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 829500 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 168000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.demand_miss_latency::cpu.inst 1464060500 # number of demand (read+write) miss cycles 958system.cpu.l2cache.demand_miss_latency::cpu.data 11078771000 # number of demand (read+write) miss cycles 959system.cpu.l2cache.demand_miss_latency::total 12543829000 # number of demand (read+write) miss cycles 960system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 829500 # number of overall miss cycles 961system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 168000 # number of overall miss cycles 962system.cpu.l2cache.overall_miss_latency::cpu.inst 1464060500 # number of overall miss cycles 963system.cpu.l2cache.overall_miss_latency::cpu.data 11078771000 # number of overall miss cycles 964system.cpu.l2cache.overall_miss_latency::total 12543829000 # number of overall miss cycles 965system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5122 # number of ReadReq accesses(hits+misses) 966system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2745 # number of ReadReq accesses(hits+misses) 967system.cpu.l2cache.ReadReq_accesses::total 7867 # number of ReadReq accesses(hits+misses) 968system.cpu.l2cache.WritebackDirty_accesses::writebacks 683946 # number of WritebackDirty accesses(hits+misses) 969system.cpu.l2cache.WritebackDirty_accesses::total 683946 # number of WritebackDirty accesses(hits+misses) 970system.cpu.l2cache.WritebackClean_accesses::writebacks 1666952 # number of WritebackClean accesses(hits+misses) 971system.cpu.l2cache.WritebackClean_accesses::total 1666952 # number of WritebackClean accesses(hits+misses) 972system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2750 # number of UpgradeReq accesses(hits+misses) 973system.cpu.l2cache.UpgradeReq_accesses::total 2750 # number of UpgradeReq accesses(hits+misses) | 964system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11816022500 # number of ReadExReq miss cycles 965system.cpu.l2cache.ReadExReq_miss_latency::total 11816022500 # number of ReadExReq miss cycles 966system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2043061500 # number of ReadCleanReq miss cycles 967system.cpu.l2cache.ReadCleanReq_miss_latency::total 2043061500 # number of ReadCleanReq miss cycles 968system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1517166500 # number of ReadSharedReq miss cycles 969system.cpu.l2cache.ReadSharedReq_miss_latency::total 1517166500 # number of ReadSharedReq miss cycles 970system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154500 # number of demand (read+write) miss cycles 971system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles 972system.cpu.l2cache.demand_miss_latency::cpu.inst 2043061500 # number of demand (read+write) miss cycles 973system.cpu.l2cache.demand_miss_latency::cpu.data 13333189000 # number of demand (read+write) miss cycles 974system.cpu.l2cache.demand_miss_latency::total 15377585000 # number of demand (read+write) miss cycles 975system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154500 # number of overall miss cycles 976system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles 977system.cpu.l2cache.overall_miss_latency::cpu.inst 2043061500 # number of overall miss cycles 978system.cpu.l2cache.overall_miss_latency::cpu.data 13333189000 # number of overall miss cycles 979system.cpu.l2cache.overall_miss_latency::total 15377585000 # number of overall miss cycles 980system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 4998 # number of ReadReq accesses(hits+misses) 981system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2671 # number of ReadReq accesses(hits+misses) 982system.cpu.l2cache.ReadReq_accesses::total 7669 # number of ReadReq accesses(hits+misses) 983system.cpu.l2cache.WritebackDirty_accesses::writebacks 685561 # number of WritebackDirty accesses(hits+misses) 984system.cpu.l2cache.WritebackDirty_accesses::total 685561 # number of WritebackDirty accesses(hits+misses) 985system.cpu.l2cache.WritebackClean_accesses::writebacks 1667726 # number of WritebackClean accesses(hits+misses) 986system.cpu.l2cache.WritebackClean_accesses::total 1667726 # number of WritebackClean accesses(hits+misses) 987system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2814 # number of UpgradeReq accesses(hits+misses) 988system.cpu.l2cache.UpgradeReq_accesses::total 2814 # number of UpgradeReq accesses(hits+misses) |
| 974system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 975system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 989system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 990system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 976system.cpu.l2cache.ReadExReq_accesses::cpu.data 296002 # number of ReadExReq accesses(hits+misses) 977system.cpu.l2cache.ReadExReq_accesses::total 296002 # number of ReadExReq accesses(hits+misses) 978system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1698494 # number of ReadCleanReq accesses(hits+misses) 979system.cpu.l2cache.ReadCleanReq_accesses::total 1698494 # number of ReadCleanReq accesses(hits+misses) 980system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 524309 # number of ReadSharedReq accesses(hits+misses) 981system.cpu.l2cache.ReadSharedReq_accesses::total 524309 # number of ReadSharedReq accesses(hits+misses) 982system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5122 # number of demand (read+write) accesses 983system.cpu.l2cache.demand_accesses::cpu.itb.walker 2745 # number of demand (read+write) accesses 984system.cpu.l2cache.demand_accesses::cpu.inst 1698494 # number of demand (read+write) accesses 985system.cpu.l2cache.demand_accesses::cpu.data 820311 # number of demand (read+write) accesses 986system.cpu.l2cache.demand_accesses::total 2526672 # number of demand (read+write) accesses 987system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5122 # number of overall (read+write) accesses 988system.cpu.l2cache.overall_accesses::cpu.itb.walker 2745 # number of overall (read+write) accesses 989system.cpu.l2cache.overall_accesses::cpu.inst 1698494 # number of overall (read+write) accesses 990system.cpu.l2cache.overall_accesses::cpu.data 820311 # number of overall (read+write) accesses 991system.cpu.l2cache.overall_accesses::total 2526672 # number of overall (read+write) accesses 992system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001562 # miss rate for ReadReq accesses 993system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000729 # miss rate for ReadReq accesses 994system.cpu.l2cache.ReadReq_miss_rate::total 0.001271 # miss rate for ReadReq accesses 995system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.007273 # miss rate for UpgradeReq accesses 996system.cpu.l2cache.UpgradeReq_miss_rate::total 0.007273 # miss rate for UpgradeReq accesses | 991system.cpu.l2cache.ReadExReq_accesses::cpu.data 295923 # number of ReadExReq accesses(hits+misses) 992system.cpu.l2cache.ReadExReq_accesses::total 295923 # number of ReadExReq accesses(hits+misses) 993system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700505 # number of ReadCleanReq accesses(hits+misses) 994system.cpu.l2cache.ReadCleanReq_accesses::total 1700505 # number of ReadCleanReq accesses(hits+misses) 995system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525966 # number of ReadSharedReq accesses(hits+misses) 996system.cpu.l2cache.ReadSharedReq_accesses::total 525966 # number of ReadSharedReq accesses(hits+misses) 997system.cpu.l2cache.demand_accesses::cpu.dtb.walker 4998 # number of demand (read+write) accesses 998system.cpu.l2cache.demand_accesses::cpu.itb.walker 2671 # number of demand (read+write) accesses 999system.cpu.l2cache.demand_accesses::cpu.inst 1700505 # number of demand (read+write) accesses 1000system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses 1001system.cpu.l2cache.demand_accesses::total 2530063 # number of demand (read+write) accesses 1002system.cpu.l2cache.overall_accesses::cpu.dtb.walker 4998 # number of overall (read+write) accesses 1003system.cpu.l2cache.overall_accesses::cpu.itb.walker 2671 # number of overall (read+write) accesses 1004system.cpu.l2cache.overall_accesses::cpu.inst 1700505 # number of overall (read+write) accesses 1005system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses 1006system.cpu.l2cache.overall_accesses::total 2530063 # number of overall (read+write) accesses 1007system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001401 # miss rate for ReadReq accesses 1008system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000749 # miss rate for ReadReq accesses 1009system.cpu.l2cache.ReadReq_miss_rate::total 0.001174 # miss rate for ReadReq accesses 1010system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006752 # miss rate for UpgradeReq accesses 1011system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006752 # miss rate for UpgradeReq accesses |
| 997system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 998system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1012system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1013system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 999system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436872 # miss rate for ReadExReq accesses 1000system.cpu.l2cache.ReadExReq_miss_rate::total 0.436872 # miss rate for ReadExReq accesses 1001system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadCleanReq accesses 1002system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010607 # miss rate for ReadCleanReq accesses | 1014system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.431842 # miss rate for ReadExReq accesses 1015system.cpu.l2cache.ReadExReq_miss_rate::total 0.431842 # miss rate for ReadExReq accesses 1016system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010555 # miss rate for ReadCleanReq accesses 1017system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010555 # miss rate for ReadCleanReq accesses |
| 1003system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses 1004system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses | 1018system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses 1019system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses |
| 1005system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001562 # miss rate for demand accesses 1006system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000729 # miss rate for demand accesses 1007system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses 1008system.cpu.l2cache.demand_miss_rate::cpu.data 0.172391 # miss rate for demand accesses 1009system.cpu.l2cache.demand_miss_rate::total 0.063103 # miss rate for demand accesses 1010system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001562 # miss rate for overall accesses 1011system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000729 # miss rate for overall accesses 1012system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses 1013system.cpu.l2cache.overall_miss_rate::cpu.data 0.172391 # miss rate for overall accesses 1014system.cpu.l2cache.overall_miss_rate::total 0.063103 # miss rate for overall accesses 1015system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103687.500000 # average ReadReq miss latency 1016system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84000 # average ReadReq miss latency 1017system.cpu.l2cache.ReadReq_avg_miss_latency::total 99750 # average ReadReq miss latency 1018system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29050 # average UpgradeReq miss latency 1019system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29050 # average UpgradeReq miss latency | 1020system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001401 # miss rate for demand accesses 1021system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000749 # miss rate for demand accesses 1022system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010555 # miss rate for demand accesses 1023system.cpu.l2cache.demand_miss_rate::cpu.data 0.170253 # miss rate for demand accesses 1024system.cpu.l2cache.demand_miss_rate::total 0.062404 # miss rate for demand accesses 1025system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001401 # miss rate for overall accesses 1026system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000749 # miss rate for overall accesses 1027system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010555 # miss rate for overall accesses 1028system.cpu.l2cache.overall_miss_rate::cpu.data 0.170253 # miss rate for overall accesses 1029system.cpu.l2cache.overall_miss_rate::total 0.062404 # miss rate for overall accesses 1030system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164928.571429 # average ReadReq miss latency 1031system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency 1032system.cpu.l2cache.ReadReq_avg_miss_latency::total 148277.777778 # average ReadReq miss latency 1033system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29236.842105 # average UpgradeReq miss latency 1034system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29236.842105 # average UpgradeReq miss latency |
| 1020system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 1021system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency | 1035system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 1036system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency |
| 1022system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77844.557863 # average ReadExReq miss latency 1023system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77844.557863 # average ReadExReq miss latency 1024system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81264.459369 # average ReadCleanReq miss latency 1025system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81264.459369 # average ReadCleanReq miss latency 1026system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83668.237044 # average ReadSharedReq miss latency 1027system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83668.237044 # average ReadSharedReq miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency 1029system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency 1030system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency 1031system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency 1032system.cpu.l2cache.demand_avg_miss_latency::total 78674.291269 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency 1037system.cpu.l2cache.overall_avg_miss_latency::total 78674.291269 # average overall miss latency | 1037system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92462.928039 # average ReadExReq miss latency 1038system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92462.928039 # average ReadExReq miss latency 1039system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 113832.265433 # average ReadCleanReq miss latency 1040system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 113832.265433 # average ReadCleanReq miss latency 1041system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125003.419296 # average ReadSharedReq miss latency 1042system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125003.419296 # average ReadSharedReq miss latency 1043system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency 1044system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency 1045system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency 1046system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency 1047system.cpu.l2cache.demand_avg_miss_latency::total 97396.760954 # average overall miss latency 1048system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency 1049system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency 1050system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency 1051system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::total 97396.760954 # average overall miss latency |
| 1038system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1041system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1043system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1053system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1054system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1055system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1057system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1058system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1044system.cpu.l2cache.writebacks::writebacks 82853 # number of writebacks 1045system.cpu.l2cache.writebacks::total 82853 # number of writebacks 1046system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 8 # number of ReadReq MSHR misses | 1059system.cpu.l2cache.writebacks::writebacks 81484 # number of writebacks 1060system.cpu.l2cache.writebacks::total 81484 # number of writebacks 1061system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses |
| 1047system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 1062system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 1048system.cpu.l2cache.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses 1049system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses 1050system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses | 1063system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses 1064system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses 1065system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses |
| 1051system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1052system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1066system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1067system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1053system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129315 # number of ReadExReq MSHR misses 1054system.cpu.l2cache.ReadExReq_mshr_misses::total 129315 # number of ReadExReq MSHR misses 1055system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 18016 # number of ReadCleanReq MSHR misses 1056system.cpu.l2cache.ReadCleanReq_mshr_misses::total 18016 # number of ReadCleanReq MSHR misses 1057system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12099 # number of ReadSharedReq MSHR misses 1058system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12099 # number of ReadSharedReq MSHR misses 1059system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 8 # number of demand (read+write) MSHR misses | 1068system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127792 # number of ReadExReq MSHR misses 1069system.cpu.l2cache.ReadExReq_mshr_misses::total 127792 # number of ReadExReq MSHR misses 1070system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17948 # number of ReadCleanReq MSHR misses 1071system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17948 # number of ReadCleanReq MSHR misses 1072system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12137 # number of ReadSharedReq MSHR misses 1073system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12137 # number of ReadSharedReq MSHR misses 1074system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses |
| 1060system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 1075system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 1061system.cpu.l2cache.demand_mshr_misses::cpu.inst 18016 # number of demand (read+write) MSHR misses 1062system.cpu.l2cache.demand_mshr_misses::cpu.data 141414 # number of demand (read+write) MSHR misses 1063system.cpu.l2cache.demand_mshr_misses::total 159440 # number of demand (read+write) MSHR misses 1064system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 8 # number of overall MSHR misses | 1076system.cpu.l2cache.demand_mshr_misses::cpu.inst 17948 # number of demand (read+write) MSHR misses 1077system.cpu.l2cache.demand_mshr_misses::cpu.data 139929 # number of demand (read+write) MSHR misses 1078system.cpu.l2cache.demand_mshr_misses::total 157886 # number of demand (read+write) MSHR misses 1079system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses |
| 1065system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 1080system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 1066system.cpu.l2cache.overall_mshr_misses::cpu.inst 18016 # number of overall MSHR misses 1067system.cpu.l2cache.overall_mshr_misses::cpu.data 141414 # number of overall MSHR misses 1068system.cpu.l2cache.overall_mshr_misses::total 159440 # number of overall MSHR misses | 1081system.cpu.l2cache.overall_mshr_misses::cpu.inst 17948 # number of overall MSHR misses 1082system.cpu.l2cache.overall_mshr_misses::cpu.data 139929 # number of overall MSHR misses 1083system.cpu.l2cache.overall_mshr_misses::total 157886 # number of overall MSHR misses |
| 1069system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 1070system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 1071system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable 1072system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 1073system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 1074system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 1075system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 1076system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses | 1084system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 1085system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 1086system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable 1087system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 1088system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 1089system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 1090system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 1091system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses |
| 1077system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 749500 # number of ReadReq MSHR miss cycles 1078system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 148000 # number of ReadReq MSHR miss cycles 1079system.cpu.l2cache.ReadReq_mshr_miss_latency::total 897500 # number of ReadReq MSHR miss cycles 1080system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 381000 # number of UpgradeReq MSHR miss cycles 1081system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 381000 # number of UpgradeReq MSHR miss cycles | 1092system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084500 # number of ReadReq MSHR miss cycles 1093system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 # number of ReadReq MSHR miss cycles 1094system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244500 # number of ReadReq MSHR miss cycles 1095system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 365500 # number of UpgradeReq MSHR miss cycles 1096system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 365500 # number of UpgradeReq MSHR miss cycles |
| 1082system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles 1083system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles | 1097system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles 1098system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles |
| 1084system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8773319000 # number of ReadExReq MSHR miss cycles 1085system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8773319000 # number of ReadExReq MSHR miss cycles 1086system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1283900500 # number of ReadCleanReq MSHR miss cycles 1087system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1283900500 # number of ReadCleanReq MSHR miss cycles 1088system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 891312000 # number of ReadSharedReq MSHR miss cycles 1089system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 891312000 # number of ReadSharedReq MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 749500 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 148000 # number of demand (read+write) MSHR miss cycles 1092system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1283900500 # number of demand (read+write) MSHR miss cycles 1093system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9664631000 # number of demand (read+write) MSHR miss cycles 1094system.cpu.l2cache.demand_mshr_miss_latency::total 10949429000 # number of demand (read+write) MSHR miss cycles 1095system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 749500 # number of overall MSHR miss cycles 1096system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 148000 # number of overall MSHR miss cycles 1097system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1283900500 # number of overall MSHR miss cycles 1098system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9664631000 # number of overall MSHR miss cycles 1099system.cpu.l2cache.overall_mshr_miss_latency::total 10949429000 # number of overall MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 574512000 # number of ReadReq MSHR uncacheable cycles 1101system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5891860500 # number of ReadReq MSHR uncacheable cycles 1102system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6466372500 # number of ReadReq MSHR uncacheable cycles 1103system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 574512000 # number of overall MSHR uncacheable cycles 1104system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5891860500 # number of overall MSHR uncacheable cycles 1105system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6466372500 # number of overall MSHR uncacheable cycles 1106system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for ReadReq accesses 1107system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for ReadReq accesses 1108system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001271 # mshr miss rate for ReadReq accesses 1109system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.007273 # mshr miss rate for UpgradeReq accesses 1110system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.007273 # mshr miss rate for UpgradeReq accesses | 1099system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10538102500 # number of ReadExReq MSHR miss cycles 1100system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10538102500 # number of ReadExReq MSHR miss cycles 1101system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1863581500 # number of ReadCleanReq MSHR miss cycles 1102system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1863581500 # number of ReadCleanReq MSHR miss cycles 1103system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1395796500 # number of ReadSharedReq MSHR miss cycles 1104system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1395796500 # number of ReadSharedReq MSHR miss cycles 1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084500 # number of demand (read+write) MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1863581500 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11933899000 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::total 13798725000 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084500 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1863581500 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11933899000 # number of overall MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::total 13798725000 # number of overall MSHR miss cycles 1115system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles 1116system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895497500 # number of ReadReq MSHR uncacheable cycles 1117system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527925500 # number of ReadReq MSHR uncacheable cycles 1118system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 # number of overall MSHR uncacheable cycles 1119system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895497500 # number of overall MSHR uncacheable cycles 1120system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527925500 # number of overall MSHR uncacheable cycles 1121system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for ReadReq accesses 1122system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for ReadReq accesses 1123system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001174 # mshr miss rate for ReadReq accesses 1124system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006752 # mshr miss rate for UpgradeReq accesses 1125system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006752 # mshr miss rate for UpgradeReq accesses |
| 1111system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1112system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1126system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1127system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1113system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436872 # mshr miss rate for ReadExReq accesses 1114system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436872 # mshr miss rate for ReadExReq accesses 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadCleanReq accesses 1116system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010607 # mshr miss rate for ReadCleanReq accesses | 1128system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.431842 # mshr miss rate for ReadExReq accesses 1129system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.431842 # mshr miss rate for ReadExReq accesses 1130system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for ReadCleanReq accesses 1131system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010555 # mshr miss rate for ReadCleanReq accesses |
| 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses 1118system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses | 1132system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses 1133system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses |
| 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses 1122system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for demand accesses 1123system.cpu.l2cache.demand_mshr_miss_rate::total 0.063103 # mshr miss rate for demand accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for overall accesses 1126system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for overall accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::total 0.063103 # mshr miss rate for overall accesses 1129system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average ReadReq mshr miss latency 1130system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74000 # average ReadReq mshr miss latency 1131system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 89750 # average ReadReq mshr miss latency 1132system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19050 # average UpgradeReq mshr miss latency 1133system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19050 # average UpgradeReq mshr miss latency | 1134system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for demand accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for demand accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for demand accesses 1138system.cpu.l2cache.demand_mshr_miss_rate::total 0.062404 # mshr miss rate for demand accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for overall accesses 1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for overall accesses 1142system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for overall accesses 1143system.cpu.l2cache.overall_mshr_miss_rate::total 0.062404 # mshr miss rate for overall accesses 1144system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average ReadReq mshr miss latency 1145system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency 1146system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778 # average ReadReq mshr miss latency 1147system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105 # average UpgradeReq mshr miss latency 1148system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105 # average UpgradeReq mshr miss latency |
| 1134system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1135system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency | 1149system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1150system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency |
| 1136system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863 # average ReadExReq mshr miss latency 1137system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863 # average ReadExReq mshr miss latency 1138system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369 # average ReadCleanReq mshr miss latency 1139system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369 # average ReadCleanReq mshr miss latency 1140system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044 # average ReadSharedReq mshr miss latency 1141system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044 # average ReadSharedReq mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency 1143system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency 1144system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency 1145system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency 1152system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average ReadReq mshr uncacheable latency 1153system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209 # average ReadReq mshr uncacheable latency 1154system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494 # average ReadReq mshr uncacheable latency 1155system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average overall mshr uncacheable latency 1156system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899 # average overall mshr uncacheable latency 1157system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343 # average overall mshr uncacheable latency 1158system.cpu.toL2Bus.snoop_filter.tot_requests 5058492 # Total number of requests made to the snoop filter. 1159system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539687 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1160system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38280 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1161system.cpu.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. 1162system.cpu.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039 # average ReadExReq mshr miss latency 1152system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039 # average ReadExReq mshr miss latency 1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433 # average ReadCleanReq mshr miss latency 1154system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433 # average ReadCleanReq mshr miss latency 1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296 # average ReadSharedReq mshr miss latency 1156system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296 # average ReadSharedReq mshr miss latency 1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency 1167system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency 1168system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829 # average ReadReq mshr uncacheable latency 1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717 # average ReadReq mshr uncacheable latency 1170system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency 1171system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527 # average overall mshr uncacheable latency 1172system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119 # average overall mshr uncacheable latency 1173system.cpu.toL2Bus.snoop_filter.tot_requests 5065968 # Total number of requests made to the snoop filter. 1174system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543576 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1175system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1176system.cpu.toL2Bus.snoop_filter.tot_snoops 219 # Total number of snoops made to the snoop filter. 1177system.cpu.toL2Bus.snoop_filter.hit_single_snoops 219 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1163system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1178system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1164system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1165system.cpu.toL2Bus.trans_dist::ReadReq 67163 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadResp 2290209 # Transaction distribution | 1179system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1180system.cpu.toL2Bus.trans_dist::ReadReq 67217 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::ReadResp 2293895 # Transaction distribution |
| 1167system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution | 1182system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution |
| 1169system.cpu.toL2Bus.trans_dist::WritebackDirty 766799 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::WritebackClean 1698000 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::CleanEvict 142435 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::UpgradeReq 2750 # Transaction distribution | 1184system.cpu.toL2Bus.trans_dist::WritebackDirty 767045 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::WritebackClean 1700003 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::CleanEvict 142341 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::UpgradeReq 2814 # Transaction distribution |
| 1173system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1188system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1174system.cpu.toL2Bus.trans_dist::UpgradeResp 2752 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::ReadExReq 296002 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::ReadExResp 296002 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::ReadCleanReq 1698518 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::ReadSharedReq 524530 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::InvalidateReq 4455 # Transaction distribution 1180system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5113056 # Packet count per connected master and slave (bytes) 1181system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2583569 # Packet count per connected master and slave (bytes) 1182system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11960 # Packet count per connected master and slave (bytes) 1183system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22910 # Packet count per connected master and slave (bytes) 1184system.cpu.toL2Bus.pkt_count::total 7731495 # Packet count per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217411704 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96469597 # Cumulative packet size per connected master and slave (bytes) 1187system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10980 # Cumulative packet size per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20488 # Cumulative packet size per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_size::total 313912769 # Cumulative packet size per connected master and slave (bytes) 1190system.cpu.toL2Bus.snoops 113519 # Total snoops (count) 1191system.cpu.toL2Bus.snoopTraffic 5394688 # Total snoop traffic (bytes) 1192system.cpu.toL2Bus.snoop_fanout::samples 2710473 # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::mean 0.021286 # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::stdev 0.144336 # Request fanout histogram | 1189system.cpu.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::ReadExReq 295923 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::ReadExResp 295923 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700521 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::ReadSharedReq 526163 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution 1195system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119073 # Packet count per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2588406 # Packet count per connected master and slave (bytes) 1197system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11887 # Packet count per connected master and slave (bytes) 1198system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22839 # Packet count per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_count::total 7742205 # Packet count per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217668600 # Cumulative packet size per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96672157 # Cumulative packet size per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10684 # Cumulative packet size per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 19992 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_size::total 314371433 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu.toL2Bus.snoops 112178 # Total snoops (count) 1206system.cpu.toL2Bus.snoopTraffic 5305776 # Total snoop traffic (bytes) 1207system.cpu.toL2Bus.snoop_fanout::samples 2712615 # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::mean 0.021718 # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::stdev 0.145761 # Request fanout histogram |
| 1195system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1210system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1196system.cpu.toL2Bus.snoop_fanout::0 2652778 97.87% 97.87% # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::1 57695 2.13% 100.00% # Request fanout histogram | 1211system.cpu.toL2Bus.snoop_fanout::0 2653703 97.83% 97.83% # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::1 58912 2.17% 100.00% # Request fanout histogram |
| 1198system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1213system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1202system.cpu.toL2Bus.snoop_fanout::total 2710473 # Request fanout histogram 1203system.cpu.toL2Bus.reqLayer0.occupancy 4962792000 # Layer occupancy (ticks) | 1217system.cpu.toL2Bus.snoop_fanout::total 2712615 # Request fanout histogram 1218system.cpu.toL2Bus.reqLayer0.occupancy 4970051500 # Layer occupancy (ticks) |
| 1204system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1219system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1205system.cpu.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) | 1220system.cpu.toL2Bus.snoopLayer0.occupancy 347876 # Layer occupancy (ticks) |
| 1206system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1221system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1207system.cpu.toL2Bus.respLayer0.occupancy 2556799000 # Layer occupancy (ticks) | 1222system.cpu.toL2Bus.respLayer0.occupancy 2559803500 # Layer occupancy (ticks) |
| 1208system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1223system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1209system.cpu.toL2Bus.respLayer1.occupancy 1276777495 # Layer occupancy (ticks) | 1224system.cpu.toL2Bus.respLayer1.occupancy 1279174000 # Layer occupancy (ticks) |
| 1210system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1225system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1211system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) | 1226system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) |
| 1212system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1227system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1213system.cpu.toL2Bus.respLayer3.occupancy 17788000 # Layer occupancy (ticks) | 1228system.cpu.toL2Bus.respLayer3.occupancy 17841000 # Layer occupancy (ticks) |
| 1214system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1229system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1215system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1216system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1217system.iobus.trans_dist::ReadResp 30183 # Transaction distribution | 1230system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1231system.iobus.trans_dist::ReadReq 30159 # Transaction distribution 1232system.iobus.trans_dist::ReadResp 30159 # Transaction distribution |
| 1218system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1219system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1220system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1223system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1224system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1225system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1232system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) | 1233system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1234system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1235system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1240system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1247system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1252system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1253system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1254system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) |
| 1240system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1241system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) | 1255system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes) 1256system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes) 1257system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes) |
| 1243system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1244system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1245system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1246system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1247system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1248system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1249system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1250system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1255system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) | 1258system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1270system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1273system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1274system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1275system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1276system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1277system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) |
| 1263system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) | 1278system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes) 1279system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes) 1280system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes) 1281system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) |
| 1267system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1268system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) 1269system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1282system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1283system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) 1284system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1270system.iobus.reqLayer2.occupancy 338500 # Layer occupancy (ticks) | 1285system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) |
| 1271system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1272system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) 1273system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1274system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 1275system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 1286system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1287system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) 1288system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1289system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 1290system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 1276system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) | 1291system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) |
| 1277system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1292system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1278system.iobus.reqLayer8.occupancy 642000 # Layer occupancy (ticks) | 1293system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks) |
| 1279system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1280system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1281system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1282system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 1283system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1284system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 1285system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1286system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1292system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 1293system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1294system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1295system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1296system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1297system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1298system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 1299system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1294system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1295system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1296system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 1298system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 1300system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1301system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1307system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 1308system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1309system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1310system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1311system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1312system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1313system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 1314system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1300system.iobus.reqLayer23.occupancy 6273000 # Layer occupancy (ticks) | 1315system.iobus.reqLayer23.occupancy 6292000 # Layer occupancy (ticks) |
| 1301system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1302system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) 1303system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1316system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1317system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) 1318system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1304system.iobus.reqLayer25.occupancy 187671849 # Layer occupancy (ticks) | 1319system.iobus.reqLayer25.occupancy 187581870 # Layer occupancy (ticks) |
| 1305system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1306system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1307system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1320system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1321system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1322system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1308system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) | 1323system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks) |
| 1309system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1324system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1310system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1311system.iocache.tags.replacements 36424 # number of replacements 1312system.iocache.tags.tagsinuse 1.078594 # Cycle average of tags in use | 1325system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1326system.iocache.tags.replacements 36400 # number of replacements 1327system.iocache.tags.tagsinuse 1.079755 # Cycle average of tags in use |
| 1313system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1328system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1314system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. | 1329system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks. |
| 1315system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1330system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1316system.iocache.tags.warmup_cycle 309373303000 # Cycle when the warmup percentage was hit. 1317system.iocache.tags.occ_blocks::realview.ide 1.078594 # Average occupied blocks per requestor 1318system.iocache.tags.occ_percent::realview.ide 0.067412 # Average percentage of cache occupancy 1319system.iocache.tags.occ_percent::total 0.067412 # Average percentage of cache occupancy | 1331system.iocache.tags.warmup_cycle 310620847000 # Cycle when the warmup percentage was hit. 1332system.iocache.tags.occ_blocks::realview.ide 1.079755 # Average occupied blocks per requestor 1333system.iocache.tags.occ_percent::realview.ide 0.067485 # Average percentage of cache occupancy 1334system.iocache.tags.occ_percent::total 0.067485 # Average percentage of cache occupancy |
| 1320system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1321system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1322system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1335system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1336system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1337system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1323system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1324system.iocache.tags.data_accesses 328122 # Number of data accesses 1325system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1326system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1327system.iocache.ReadReq_misses::total 234 # number of ReadReq misses | 1338system.iocache.tags.tag_accesses 327906 # Number of tag accesses 1339system.iocache.tags.data_accesses 327906 # Number of data accesses 1340system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1341system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses 1342system.iocache.ReadReq_misses::total 210 # number of ReadReq misses |
| 1328system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1329system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses | 1343system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1344system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
| 1330system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1331system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1332system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1333system.iocache.overall_misses::total 36458 # number of overall misses 1334system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles 1335system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles 1336system.iocache.WriteLineReq_miss_latency::realview.ide 4278807472 # number of WriteLineReq miss cycles 1337system.iocache.WriteLineReq_miss_latency::total 4278807472 # number of WriteLineReq miss cycles 1338system.iocache.demand_miss_latency::realview.ide 4307704849 # number of demand (read+write) miss cycles 1339system.iocache.demand_miss_latency::total 4307704849 # number of demand (read+write) miss cycles 1340system.iocache.overall_miss_latency::realview.ide 4307704849 # number of overall miss cycles 1341system.iocache.overall_miss_latency::total 4307704849 # number of overall miss cycles 1342system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1343system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) | 1345system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses 1346system.iocache.demand_misses::total 36434 # number of demand (read+write) misses 1347system.iocache.overall_misses::realview.ide 36434 # number of overall misses 1348system.iocache.overall_misses::total 36434 # number of overall misses 1349system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles 1350system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles 1351system.iocache.WriteLineReq_miss_latency::realview.ide 4367688494 # number of WriteLineReq miss cycles 1352system.iocache.WriteLineReq_miss_latency::total 4367688494 # number of WriteLineReq miss cycles 1353system.iocache.demand_miss_latency::realview.ide 4401754870 # number of demand (read+write) miss cycles 1354system.iocache.demand_miss_latency::total 4401754870 # number of demand (read+write) miss cycles 1355system.iocache.overall_miss_latency::realview.ide 4401754870 # number of overall miss cycles 1356system.iocache.overall_miss_latency::total 4401754870 # number of overall miss cycles 1357system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses) 1358system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses) |
| 1344system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1345system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) | 1359system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1360system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
| 1346system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1347system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1348system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1349system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses | 1361system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses 1362system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses 1363system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses 1364system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses |
| 1350system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1351system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1352system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1353system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1354system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1355system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1356system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1357system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1365system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1366system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1367system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1368system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1369system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1370system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1371system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1372system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1358system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency 1359system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency 1360system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311 # average WriteLineReq miss latency 1361system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311 # average WriteLineReq miss latency 1362system.iocache.demand_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency 1363system.iocache.demand_avg_miss_latency::total 118155.270421 # average overall miss latency 1364system.iocache.overall_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency 1365system.iocache.overall_avg_miss_latency::total 118155.270421 # average overall miss latency | 1373system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency 1374system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency 1375system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432 # average WriteLineReq miss latency 1376system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432 # average WriteLineReq miss latency 1377system.iocache.demand_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency 1378system.iocache.demand_avg_miss_latency::total 120814.482901 # average overall miss latency 1379system.iocache.overall_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency 1380system.iocache.overall_avg_miss_latency::total 120814.482901 # average overall miss latency |
| 1366system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1367system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1368system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1369system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1370system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1371system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1372system.iocache.writebacks::writebacks 36190 # number of writebacks 1373system.iocache.writebacks::total 36190 # number of writebacks | 1381system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1382system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1383system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1384system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1385system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1386system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1387system.iocache.writebacks::writebacks 36190 # number of writebacks 1388system.iocache.writebacks::total 36190 # number of writebacks |
| 1374system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1375system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses | 1389system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses 1390system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses |
| 1376system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1377system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses | 1391system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1392system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses |
| 1378system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1379system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1380system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1381system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses 1382system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles 1383system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles 1384system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465502723 # number of WriteLineReq MSHR miss cycles 1385system.iocache.WriteLineReq_mshr_miss_latency::total 2465502723 # number of WriteLineReq MSHR miss cycles 1386system.iocache.demand_mshr_miss_latency::realview.ide 2482700100 # number of demand (read+write) MSHR miss cycles 1387system.iocache.demand_mshr_miss_latency::total 2482700100 # number of demand (read+write) MSHR miss cycles 1388system.iocache.overall_mshr_miss_latency::realview.ide 2482700100 # number of overall MSHR miss cycles 1389system.iocache.overall_mshr_miss_latency::total 2482700100 # number of overall MSHR miss cycles | 1393system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses 1394system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses 1395system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses 1396system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses 1397system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles 1398system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles 1399system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2554457612 # number of WriteLineReq MSHR miss cycles 1400system.iocache.WriteLineReq_mshr_miss_latency::total 2554457612 # number of WriteLineReq MSHR miss cycles 1401system.iocache.demand_mshr_miss_latency::realview.ide 2578023988 # number of demand (read+write) MSHR miss cycles 1402system.iocache.demand_mshr_miss_latency::total 2578023988 # number of demand (read+write) MSHR miss cycles 1403system.iocache.overall_mshr_miss_latency::realview.ide 2578023988 # number of overall MSHR miss cycles 1404system.iocache.overall_mshr_miss_latency::total 2578023988 # number of overall MSHR miss cycles |
| 1390system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1391system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1392system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1393system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1394system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1395system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1396system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1397system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1405system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1406system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1407system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1408system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1409system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1410system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1411system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1412system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1398system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency 1399system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency 1400system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595 # average WriteLineReq mshr miss latency 1401system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595 # average WriteLineReq mshr miss latency 1402system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency 1403system.iocache.demand_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency 1404system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency 1405system.iocache.overall_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency 1406system.membus.snoop_filter.tot_requests 321817 # Total number of requests made to the snoop filter. 1407system.membus.snoop_filter.hit_single_requests 130498 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1408system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1413system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency 1414system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency 1415system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890 # average WriteLineReq mshr miss latency 1416system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890 # average WriteLineReq mshr miss latency 1417system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency 1418system.iocache.demand_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency 1419system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency 1420system.iocache.overall_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency 1421system.membus.snoop_filter.tot_requests 318841 # Total number of requests made to the snoop filter. 1422system.membus.snoop_filter.hit_single_requests 128997 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1423system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1409system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1410system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1411system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1424system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1425system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1426system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1412system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 1427system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 1413system.membus.trans_dist::ReadReq 40160 # Transaction distribution | 1428system.membus.trans_dist::ReadReq 40160 # Transaction distribution |
| 1414system.membus.trans_dist::ReadResp 70519 # Transaction distribution | 1429system.membus.trans_dist::ReadResp 70464 # Transaction distribution |
| 1415system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1416system.membus.trans_dist::WriteResp 27589 # Transaction distribution | 1430system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1431system.membus.trans_dist::WriteResp 27589 # Transaction distribution |
| 1417system.membus.trans_dist::WritebackDirty 119043 # Transaction distribution 1418system.membus.trans_dist::CleanEvict 6845 # Transaction distribution | 1432system.membus.trans_dist::WritebackDirty 117674 # Transaction distribution 1433system.membus.trans_dist::CleanEvict 6761 # Transaction distribution |
| 1419system.membus.trans_dist::UpgradeReq 128 # Transaction distribution 1420system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1421system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1434system.membus.trans_dist::UpgradeReq 128 # Transaction distribution 1435system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1436system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1422system.membus.trans_dist::ReadExReq 129207 # Transaction distribution 1423system.membus.trans_dist::ReadExResp 129207 # Transaction distribution 1424system.membus.trans_dist::ReadSharedReq 30359 # Transaction distribution | 1437system.membus.trans_dist::ReadExReq 127683 # Transaction distribution 1438system.membus.trans_dist::ReadExResp 127683 # Transaction distribution 1439system.membus.trans_dist::ReadSharedReq 30304 # Transaction distribution |
| 1425system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1426system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1427system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1428system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) | 1440system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1441system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1442system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1443system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) |
| 1429system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 435887 # Packet count per connected master and slave (bytes) 1430system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543479 # Packet count per connected master and slave (bytes) 1431system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1432system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) 1433system.membus.pkt_count::total 616376 # Packet count per connected master and slave (bytes) | 1444system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431348 # Packet count per connected master and slave (bytes) 1445system.membus.pkt_count_system.cpu.l2cache.mem_side::total 538940 # Packet count per connected master and slave (bytes) 1446system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes) 1447system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes) 1448system.membus.pkt_count::total 611789 # Packet count per connected master and slave (bytes) |
| 1434system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1435system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1436system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) | 1449system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1450system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1451system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) |
| 1437system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15537980 # Cumulative packet size per connected master and slave (bytes) 1438system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15701333 # Cumulative packet size per connected master and slave (bytes) | 1452system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15350844 # Cumulative packet size per connected master and slave (bytes) 1453system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15514197 # Cumulative packet size per connected master and slave (bytes) |
| 1439system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1440system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) | 1454system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1455system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) |
| 1441system.membus.pkt_size::total 18018453 # Cumulative packet size per connected master and slave (bytes) 1442system.membus.snoops 498 # Total snoops (count) 1443system.membus.snoopTraffic 31744 # Total snoop traffic (bytes) 1444system.membus.snoop_fanout::samples 263669 # Request fanout histogram 1445system.membus.snoop_fanout::mean 0.018793 # Request fanout histogram 1446system.membus.snoop_fanout::stdev 0.135792 # Request fanout histogram | 1456system.membus.pkt_size::total 17831317 # Cumulative packet size per connected master and slave (bytes) 1457system.membus.snoops 474 # Total snoops (count) 1458system.membus.snoopTraffic 30208 # Total snoop traffic (bytes) 1459system.membus.snoop_fanout::samples 262090 # Request fanout histogram 1460system.membus.snoop_fanout::mean 0.018417 # Request fanout histogram 1461system.membus.snoop_fanout::stdev 0.134455 # Request fanout histogram |
| 1447system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1462system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1448system.membus.snoop_fanout::0 258714 98.12% 98.12% # Request fanout histogram 1449system.membus.snoop_fanout::1 4955 1.88% 100.00% # Request fanout histogram | 1463system.membus.snoop_fanout::0 257263 98.16% 98.16% # Request fanout histogram 1464system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram |
| 1450system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1451system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1452system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1453system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1465system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1466system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1467system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1468system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1454system.membus.snoop_fanout::total 263669 # Request fanout histogram 1455system.membus.reqLayer0.occupancy 90449000 # Layer occupancy (ticks) | 1469system.membus.snoop_fanout::total 262090 # Request fanout histogram 1470system.membus.reqLayer0.occupancy 90471500 # Layer occupancy (ticks) |
| 1456system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1457system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1458system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1471system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1472system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1473system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1459system.membus.reqLayer2.occupancy 1734500 # Layer occupancy (ticks) | 1474system.membus.reqLayer2.occupancy 1726500 # Layer occupancy (ticks) |
| 1460system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1475system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1461system.membus.reqLayer5.occupancy 828323280 # Layer occupancy (ticks) | 1476system.membus.reqLayer5.occupancy 819732726 # Layer occupancy (ticks) |
| 1462system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1477system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1463system.membus.respLayer2.occupancy 954014500 # Layer occupancy (ticks) | 1478system.membus.respLayer2.occupancy 945419750 # Layer occupancy (ticks) |
| 1464system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1479system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1465system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) | 1480system.membus.respLayer3.occupancy 1085624 # Layer occupancy (ticks) |
| 1466system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1481system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1467system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1468system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1469system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1470system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1471system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1472system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1473system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 1482system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1483system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1484system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1485system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1486system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1487system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1488system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 1474system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1475system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1476system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1477system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1478system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1479system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1489system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1490system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1491system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1492system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1493system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1494system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1480system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1481system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 1495system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1496system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 1482system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1483system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1484system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1485system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1486system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1487system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1488system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1489system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1505system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1506system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1507system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1508system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1509system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1510system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1511system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1512system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1497system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1498system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1499system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1500system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1501system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1502system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1503system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1504system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1520system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1521system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1522system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1523system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1524system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1525system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1526system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1527system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1513system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1514system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1515system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1516system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1517system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1518system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1519system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 1528system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1529system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1530system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1531system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1532system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1533system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1534system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 1520system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1521system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1522system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1523system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1535system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1536system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1537system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1538system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1524system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1525system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1526system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1527system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1528system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1529system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1530system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1531system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1532system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1533system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1534system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1535system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states | 1539system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1540system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1541system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1542system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1543system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1544system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1545system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1546system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1547system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1548system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1549system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states 1550system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states |
| 1536 1537---------- End Simulation Statistics ---------- | 1551 1552---------- End Simulation Statistics ---------- |