| stats.txt (11589:af2f7fef4875) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.909583 # Number of seconds simulated 4sim_ticks 2909582799500 # Number of ticks simulated 5final_tick 2909582799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.903737 # Number of seconds simulated 4sim_ticks 2903736790500 # Number of ticks simulated 5final_tick 2903736790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 722784 # Simulator instruction rate (inst/s) 8host_op_rate 871447 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18699971433 # Simulator tick rate (ticks/s) 10host_mem_usage 573692 # Number of bytes of host memory used 11host_seconds 155.59 # Real time elapsed on the host 12sim_insts 112460013 # Number of instructions simulated 13sim_ops 135590937 # Number of ops (including micro ops) simulated | 7host_inst_rate 515424 # Simulator instruction rate (inst/s) 8host_op_rate 621448 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13306386787 # Simulator tick rate (ticks/s) 10host_mem_usage 582748 # Number of bytes of host memory used 11host_seconds 218.22 # Real time elapsed on the host 12sim_insts 112476413 # Number of instructions simulated 13sim_ops 135613231 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 512 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 8901988 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu.inst 1188964 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9028260 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory | 22system.physmem.bytes_read::total 10218824 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1188964 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1188964 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7618752 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory | 27system.physmem.bytes_written::total 7636276 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 8 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 139613 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 27031 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141586 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 166628 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 168642 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 119043 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.num_writes::total 123424 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 176 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 407757 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3059541 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3467826 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 407757 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 407757 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2581791 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2587814 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2581791 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 409460 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3109187 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3519198 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 409460 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 409460 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2623775 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2629810 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2623775 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 176 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) | 50system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 407757 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3065564 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6055641 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 166628 # Number of read requests accepted 56system.physmem.writeReqs 121755 # Number of write requests accepted 57system.physmem.readBursts 166628 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7542016 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10089928 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue | 51system.physmem.bw_total::cpu.inst 409460 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3115222 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6149008 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 168642 # Number of read requests accepted 56system.physmem.writeReqs 123424 # Number of write requests accepted 57system.physmem.readBursts 168642 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 123424 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10783744 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7648256 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10218824 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7636276 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue |
| 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 67system.physmem.perBankRdBursts::0 10077 # Per bank write bursts 68system.physmem.perBankRdBursts::1 9979 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10695 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10660 # Per bank write bursts 71system.physmem.perBankRdBursts::4 18797 # Per bank write bursts 72system.physmem.perBankRdBursts::5 9659 # Per bank write bursts 73system.physmem.perBankRdBursts::6 9664 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10481 # Per bank write bursts 75system.physmem.perBankRdBursts::8 9276 # Per bank write bursts 76system.physmem.perBankRdBursts::9 9973 # Per bank write bursts 77system.physmem.perBankRdBursts::10 9234 # Per bank write bursts 78system.physmem.perBankRdBursts::11 8678 # Per bank write bursts 79system.physmem.perBankRdBursts::12 9820 # Per bank write bursts 80system.physmem.perBankRdBursts::13 10379 # Per bank write bursts 81system.physmem.perBankRdBursts::14 9723 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9412 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7393 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7263 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8282 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8171 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7489 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7265 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7108 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7659 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7080 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7523 # Per bank write bursts 93system.physmem.perBankWrBursts::10 6697 # Per bank write bursts 94system.physmem.perBankWrBursts::11 6470 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7534 # Per bank write bursts 96system.physmem.perBankWrBursts::13 7859 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7263 # Per bank write bursts 98system.physmem.perBankWrBursts::15 6788 # Per bank write bursts | 67system.physmem.perBankRdBursts::0 9943 # Per bank write bursts 68system.physmem.perBankRdBursts::1 9648 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10560 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10245 # Per bank write bursts 71system.physmem.perBankRdBursts::4 18706 # Per bank write bursts 72system.physmem.perBankRdBursts::5 9867 # Per bank write bursts 73system.physmem.perBankRdBursts::6 9999 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10271 # Per bank write bursts 75system.physmem.perBankRdBursts::8 9694 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10419 # Per bank write bursts 77system.physmem.perBankRdBursts::10 9828 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9028 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10140 # Per bank write bursts 80system.physmem.perBankRdBursts::13 10489 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10151 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9508 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7397 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7199 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8385 # Per bank write bursts 86system.physmem.perBankWrBursts::3 7801 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7213 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7134 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7314 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7590 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7388 # Per bank write bursts 92system.physmem.perBankWrBursts::9 8015 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7407 # Per bank write bursts 94system.physmem.perBankWrBursts::11 6899 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7622 # Per bank write bursts 96system.physmem.perBankWrBursts::13 7751 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7507 # Per bank write bursts 98system.physmem.perBankWrBursts::15 6882 # Per bank write bursts |
| 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 100system.physmem.numWrRetry 6 # Number of times write queue was full causing retry 101system.physmem.totGap 2909582442500 # Total gap between requests | 100system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 101system.physmem.totGap 2903736355000 # Total gap between requests |
| 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 9558 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) | 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 9558 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 108system.physmem.readPktSize::6 157056 # Read request sizes (log2) | 108system.physmem.readPktSize::6 159070 # Read request sizes (log2) |
| 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) | 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 115system.physmem.writePktSize::6 117374 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 165625 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see | 115system.physmem.writePktSize::6 119043 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 167708 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 529 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 247 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 163system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 3088 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 7024 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 5908 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6787 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6069 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 5921 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6073 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 6713 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 6435 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 7005 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 7785 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 6798 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7061 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8461 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6953 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6736 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6741 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1266 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 290 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 126 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 151 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 77 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 93 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 54 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 58757 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 309.723097 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 182.771096 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 329.648637 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 21456 36.52% 36.52% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14672 24.97% 61.49% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6129 10.43% 71.92% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3189 5.43% 77.35% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2542 4.33% 81.67% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1474 2.51% 84.18% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1037 1.76% 85.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1065 1.81% 87.76% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7193 12.24% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 58757 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 5617 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 29.641446 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 597.657190 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 5616 99.98% 99.98% # Reads before turning the bus around for writes | 163system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2984 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 6117 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6096 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6314 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6034 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6526 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6858 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7572 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8704 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8960 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7233 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 6955 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 6927 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6384 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6223 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 148 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 138 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 168 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 106 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 130 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 60 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 58618 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 314.441571 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 184.322128 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 334.751512 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 21316 36.36% 36.36% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14773 25.20% 61.57% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 5607 9.57% 71.13% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3267 5.57% 76.71% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2505 4.27% 80.98% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1471 2.51% 83.49% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1045 1.78% 85.27% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1040 1.77% 87.04% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7594 12.96% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 58618 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 5878 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 28.661279 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 584.674226 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 5877 99.98% 99.98% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes | 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 231system.physmem.rdPerTurnAround::total 5617 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5617 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.979882 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.786754 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 15.023739 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 4951 88.14% 88.14% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 84 1.50% 89.64% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 32 0.57% 90.21% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 37 0.66% 90.87% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 25 0.45% 91.31% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 16 0.28% 91.60% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 42 0.75% 92.34% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 8 0.14% 92.49% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 154 2.74% 95.23% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 13 0.23% 95.46% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 5 0.09% 95.55% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 19 0.34% 95.89% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 65 1.16% 97.04% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 4 0.07% 97.12% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 6 0.11% 97.22% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 28 0.50% 97.72% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 101 1.80% 99.52% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::88-91 1 0.02% 99.54% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::136-139 1 0.02% 99.75% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::140-143 2 0.04% 99.79% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::144-147 7 0.12% 99.91% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::148-151 2 0.04% 99.95% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::156-159 1 0.02% 99.96% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 5617 # Writes before turning the bus around for reads 266system.physmem.totQLat 1616687750 # Total ticks spent queuing 267system.physmem.totMemAccLat 4738694000 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 9709.43 # Average queueing delay per DRAM burst | 231system.physmem.rdPerTurnAround::total 5878 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5878 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.330725 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.604611 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 13.460490 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5095 86.68% 86.68% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 41 0.70% 87.38% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 85 1.45% 88.82% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 37 0.63% 89.45% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 285 4.85% 94.30% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 59 1.00% 95.30% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 13 0.22% 95.53% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 14 0.24% 95.76% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 4 0.07% 95.99% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 6 0.10% 96.09% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 8 0.14% 96.22% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 168 2.86% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 3 0.05% 99.13% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 2 0.03% 99.17% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 6 0.10% 99.27% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 7 0.12% 99.39% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.40% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 1 0.02% 99.42% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 2 0.03% 99.46% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 2 0.03% 99.49% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 5 0.09% 99.57% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 11 0.19% 99.78% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::136-139 1 0.02% 99.80% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::140-143 1 0.02% 99.81% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::156-159 1 0.02% 99.85% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::160-163 6 0.10% 99.95% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 5878 # Writes before turning the bus around for reads 269system.physmem.totQLat 1493636250 # Total ticks spent queuing 270system.physmem.totMemAccLat 4652936250 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 842480000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 8864.52 # Average queueing delay per DRAM burst |
| 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 271system.physmem.avgMemAccLat 28459.43 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s | 274system.physmem.avgMemAccLat 27614.52 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s |
| 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 280system.physmem.busUtil 0.05 # Data bus utilization in percentage 281system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 282system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 281system.physmem.avgWrQLen 27.98 # Average write queue length when enqueuing 282system.physmem.readRowHits 136114 # Number of row buffer hits during reads 283system.physmem.writeRowHits 89479 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 81.75 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 75.92 # Row buffer hit rate for writes 286system.physmem.avgGap 10089299.45 # Average gap between requests 287system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined 288system.physmem_0.actEnergy 230655600 # Energy for activate commands per rank (pJ) 289system.physmem_0.preEnergy 125853750 # Energy for precharge commands per rank (pJ) 290system.physmem_0.readEnergy 702093600 # Energy for read commands per rank (pJ) 291system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ) 292system.physmem_0.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) 293system.physmem_0.actBackEnergy 90278415450 # Energy for active background per rank (pJ) 294system.physmem_0.preBackEnergy 1666557438750 # Energy for precharge background per rank (pJ) 295system.physmem_0.totalEnergy 1948327057470 # Total energy per rank (pJ) 296system.physmem_0.averagePower 669.624450 # Core power per rank (mW) 297system.physmem_0.memoryStateTime::IDLE 2772287034500 # Time in different power states 298system.physmem_0.memoryStateTime::REF 97157320000 # Time in different power states | 284system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing 285system.physmem.readRowHits 138583 # Number of row buffer hits during reads 286system.physmem.writeRowHits 90798 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes 289system.physmem.avgGap 9942055.41 # Average gap between requests 290system.physmem.pageHitRate 79.64 # Row buffer hit rate, read and write combined 291system.physmem_0.actEnergy 226187640 # Energy for activate commands per rank (pJ) 292system.physmem_0.preEnergy 123415875 # Energy for precharge commands per rank (pJ) 293system.physmem_0.readEnergy 696064200 # Energy for read commands per rank (pJ) 294system.physmem_0.writeEnergy 389013840 # Energy for write commands per rank (pJ) 295system.physmem_0.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) 296system.physmem_0.actBackEnergy 86978464290 # Energy for active background per rank (pJ) 297system.physmem_0.preBackEnergy 1665943648500 # Energy for precharge background per rank (pJ) 298system.physmem_0.totalEnergy 1944014583705 # Total energy per rank (pJ) 299system.physmem_0.averagePower 669.487777 # Core power per rank (mW) 300system.physmem_0.memoryStateTime::IDLE 2771286006000 # Time in different power states 301system.physmem_0.memoryStateTime::REF 96962060000 # Time in different power states |
| 299system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 302system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 300system.physmem_0.memoryStateTime::ACT 40137378000 # Time in different power states | 303system.physmem_0.memoryStateTime::ACT 35486192750 # Time in different power states |
| 301system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 304system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.physmem_1.actEnergy 213547320 # Energy for activate commands per rank (pJ) 303system.physmem_1.preEnergy 116518875 # Energy for precharge commands per rank (pJ) 304system.physmem_1.readEnergy 596653200 # Energy for read commands per rank (pJ) 305system.physmem_1.writeEnergy 370746720 # Energy for write commands per rank (pJ) 306system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) 307system.physmem_1.actBackEnergy 88164027810 # Energy for active background per rank (pJ) 308system.physmem_1.preBackEnergy 1668412164750 # Energy for precharge background per rank (pJ) 309system.physmem_1.totalEnergy 1947913376595 # Total energy per rank (pJ) 310system.physmem_1.averagePower 669.482271 # Core power per rank (mW) 311system.physmem_1.memoryStateTime::IDLE 2775395780750 # Time in different power states 312system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states | 305system.physmem_1.actEnergy 216964440 # Energy for activate commands per rank (pJ) 306system.physmem_1.preEnergy 118383375 # Energy for precharge commands per rank (pJ) 307system.physmem_1.readEnergy 618196800 # Energy for read commands per rank (pJ) 308system.physmem_1.writeEnergy 385372080 # Energy for write commands per rank (pJ) 309system.physmem_1.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) 310system.physmem_1.actBackEnergy 85605070095 # Energy for active background per rank (pJ) 311system.physmem_1.preBackEnergy 1667148388500 # Energy for precharge background per rank (pJ) 312system.physmem_1.totalEnergy 1943750164650 # Total energy per rank (pJ) 313system.physmem_1.averagePower 669.396712 # Core power per rank (mW) 314system.physmem_1.memoryStateTime::IDLE 2773305848750 # Time in different power states 315system.physmem_1.memoryStateTime::REF 96962060000 # Time in different power states |
| 313system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 316system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 314system.physmem_1.memoryStateTime::ACT 37029550750 # Time in different power states | 317system.physmem_1.memoryStateTime::ACT 33468782750 # Time in different power states |
| 315system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 318system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 316system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 319system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 317system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 318system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 319system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 320system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 321system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 322system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 323system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 328system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) | 320system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 321system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 322system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 323system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 324system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 325system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 326system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 331system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) |
| 329system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 330system.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 331system.bridge.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 332system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 333system.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 334system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 332system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 333system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 334system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 335system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 336system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 337system.cf0.dma_write_txs 631 # Number of DMA write transactions. 338system.cpu_clk_domain.clock 500 # Clock period in ticks | 335system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 336system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 337system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 338system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 339system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 340system.cf0.dma_write_txs 631 # Number of DMA write transactions. 341system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 339system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 342system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 340system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 343system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 364system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 367system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 368system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 369system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 370system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 371system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 369system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 370system.cpu.dtb.walker.walks 9546 # Table walker walks requested 371system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors 372system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate 373system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate 374system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency 375system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency 377system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency 378system.cpu.dtb.walker.walkCompletionTime::mean 13159.103224 # Table walker service (enqueue to completion) latency 379system.cpu.dtb.walker.walkCompletionTime::gmean 10921.089481 # Table walker service (enqueue to completion) latency 380system.cpu.dtb.walker.walkCompletionTime::stdev 8511.779920 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution 386system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution 387system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution 388system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated 389system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated 390system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated 391system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst | 372system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 373system.cpu.dtb.walker.walks 9520 # Table walker walks requested 374system.cpu.dtb.walker.walksShort 9520 # Table walker walks initiated with short descriptors 375system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1252 # Level at which table walker walks with short descriptors terminate 376system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8268 # Level at which table walker walks with short descriptors terminate 377system.cpu.dtb.walker.walkWaitTime::samples 9520 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::0 9520 100.00% 100.00% # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::total 9520 # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkCompletionTime::samples 7356 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::gmean 8514.979061 # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::stdev 6541.334463 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::0-16383 6558 89.15% 89.15% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::16384-32767 793 10.78% 99.93% # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::total 7356 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution 390system.cpu.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution 391system.cpu.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution 392system.cpu.dtb.walker.walkPageSizes::4K 6151 83.62% 83.62% # Table walker page sizes translated 393system.cpu.dtb.walker.walkPageSizes::1M 1205 16.38% 100.00% # Table walker page sizes translated 394system.cpu.dtb.walker.walkPageSizes::total 7356 # Table walker page sizes translated 395system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9520 # Table walker requests started/completed, data/inst |
| 392system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 396system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 393system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst 394system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst | 397system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9520 # Table walker requests started/completed, data/inst 398system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7356 # Table walker requests started/completed, data/inst |
| 395system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 399system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 396system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst 397system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst | 400system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7356 # Table walker requests started/completed, data/inst 401system.cpu.dtb.walker.walkRequestOrigin::total 16876 # Table walker requests started/completed, data/inst |
| 398system.cpu.dtb.inst_hits 0 # ITB inst hits 399system.cpu.dtb.inst_misses 0 # ITB inst misses | 402system.cpu.dtb.inst_hits 0 # ITB inst hits 403system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 400system.cpu.dtb.read_hits 24520634 # DTB read hits 401system.cpu.dtb.read_misses 8124 # DTB read misses 402system.cpu.dtb.write_hits 19606945 # DTB write hits 403system.cpu.dtb.write_misses 1422 # DTB write misses | 404system.cpu.dtb.read_hits 24525489 # DTB read hits 405system.cpu.dtb.read_misses 8109 # DTB read misses 406system.cpu.dtb.write_hits 19608938 # DTB write hits 407system.cpu.dtb.write_misses 1411 # DTB write misses |
| 404system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 405system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 406system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 407system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 408system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 409system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 410system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 411system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 408system.cpu.dtb.flush_entries 4208 # Number of entries that have been flushed from TLB | 412system.cpu.dtb.flush_entries 4199 # Number of entries that have been flushed from TLB |
| 409system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 413system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 410system.cpu.dtb.prefetch_faults 1649 # Number of TLB faults due to prefetch | 414system.cpu.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch |
| 411system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions | 415system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions |
| 413system.cpu.dtb.read_accesses 24528758 # DTB read accesses 414system.cpu.dtb.write_accesses 19608367 # DTB write accesses | 417system.cpu.dtb.read_accesses 24533598 # DTB read accesses 418system.cpu.dtb.write_accesses 19610349 # DTB write accesses |
| 415system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 419system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 416system.cpu.dtb.hits 44127579 # DTB hits 417system.cpu.dtb.misses 9546 # DTB misses 418system.cpu.dtb.accesses 44137125 # DTB accesses 419system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 420system.cpu.dtb.hits 44134427 # DTB hits 421system.cpu.dtb.misses 9520 # DTB misses 422system.cpu.dtb.accesses 44143947 # DTB accesses 423system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 420system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 421system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 422system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 423system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 424system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 441system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 442system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 443system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 444system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 445system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 446system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 447system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 448system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 424system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 445system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 446system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 447system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 448system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 449system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 450system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 451system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 452system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 449system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 450system.cpu.itb.walker.walks 4763 # Table walker walks requested 451system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors 452system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate | 453system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 454system.cpu.itb.walker.walks 4762 # Table walker walks requested 455system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 456system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate |
| 453system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate | 457system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate |
| 454system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency 455system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency 456system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency 457system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency 458system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency 459system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency 460system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency 461system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency 465system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution 466system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution 467system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution 468system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated 469system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated 470system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated | 458system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 459system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 460system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 461system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::mean 10273.897650 # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::gmean 8288.299297 # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walkCompletionTime::stdev 7346.561217 # Table walker service (enqueue to completion) latency 465system.cpu.itb.walker.walkCompletionTime::0-8191 1812 58.32% 58.32% # Table walker service (enqueue to completion) latency 466system.cpu.itb.walker.walkCompletionTime::8192-16383 745 23.98% 82.30% # Table walker service (enqueue to completion) latency 467system.cpu.itb.walker.walkCompletionTime::16384-24575 548 17.64% 99.94% # Table walker service (enqueue to completion) latency 468system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency 469system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 470system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency 471system.cpu.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution 472system.cpu.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution 473system.cpu.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution 474system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 475system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 476system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated |
| 471system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 477system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 472system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst | 478system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 479system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst |
| 474system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 480system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 475system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst 478system.cpu.itb.inst_hits 115557255 # ITB inst hits 479system.cpu.itb.inst_misses 4763 # ITB inst misses | 481system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 482system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 483system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 484system.cpu.itb.inst_hits 115574516 # ITB inst hits 485system.cpu.itb.inst_misses 4762 # ITB inst misses |
| 480system.cpu.itb.read_hits 0 # DTB read hits 481system.cpu.itb.read_misses 0 # DTB read misses 482system.cpu.itb.write_hits 0 # DTB write hits 483system.cpu.itb.write_misses 0 # DTB write misses 484system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 485system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 488system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 489system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 490system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 491system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 493system.cpu.itb.read_accesses 0 # DTB read accesses 494system.cpu.itb.write_accesses 0 # DTB write accesses | 486system.cpu.itb.read_hits 0 # DTB read hits 487system.cpu.itb.read_misses 0 # DTB read misses 488system.cpu.itb.write_hits 0 # DTB write hits 489system.cpu.itb.write_misses 0 # DTB write misses 490system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 491system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 492system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 493system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 494system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 495system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 496system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 497system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 498system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 499system.cpu.itb.read_accesses 0 # DTB read accesses 500system.cpu.itb.write_accesses 0 # DTB write accesses |
| 495system.cpu.itb.inst_accesses 115562018 # ITB inst accesses 496system.cpu.itb.hits 115557255 # DTB hits 497system.cpu.itb.misses 4763 # DTB misses 498system.cpu.itb.accesses 115562018 # DTB accesses 499system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 500system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state 501system.cpu.pwrStateClkGateDist::mean 886755819.088361 # Distribution of time spent in the clock gated state 502system.cpu.pwrStateClkGateDist::stdev 17463725487.376945 # Distribution of time spent in the clock gated state 503system.cpu.pwrStateClkGateDist::underflows 2967 97.82% 97.82% # Distribution of time spent in the clock gated state 504system.cpu.pwrStateClkGateDist::1000-5e+10 60 1.98% 99.80% # Distribution of time spent in the clock gated state | 501system.cpu.itb.inst_accesses 115579278 # ITB inst accesses 502system.cpu.itb.hits 115574516 # DTB hits 503system.cpu.itb.misses 4762 # DTB misses 504system.cpu.itb.accesses 115579278 # DTB accesses 505system.cpu.numPwrStateTransitions 6062 # Number of power state transitions 506system.cpu.pwrStateClkGateDist::samples 3031 # Distribution of time spent in the clock gated state 507system.cpu.pwrStateClkGateDist::mean 888232478.174860 # Distribution of time spent in the clock gated state 508system.cpu.pwrStateClkGateDist::stdev 17469824950.226959 # Distribution of time spent in the clock gated state 509system.cpu.pwrStateClkGateDist::underflows 2968 97.92% 97.92% # Distribution of time spent in the clock gated state 510system.cpu.pwrStateClkGateDist::1000-5e+10 57 1.88% 99.80% # Distribution of time spent in the clock gated state |
| 505system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 506system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 507system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 508system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 509system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 511system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 512system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 513system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 514system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 515system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 510system.cpu.pwrStateClkGateDist::max_value 499963874372 # Distribution of time spent in the clock gated state 511system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state 512system.cpu.pwrStateResidencyTicks::ON 220052400205 # Cumulative time (in ticks) in various power states 513system.cpu.pwrStateResidencyTicks::CLK_GATED 2689530399295 # Cumulative time (in ticks) in various power states 514system.cpu.numCycles 5819165599 # number of cpu cycles simulated | 516system.cpu.pwrStateClkGateDist::max_value 499964073052 # Distribution of time spent in the clock gated state 517system.cpu.pwrStateClkGateDist::total 3031 # Distribution of time spent in the clock gated state 518system.cpu.pwrStateResidencyTicks::ON 211504149152 # Cumulative time (in ticks) in various power states 519system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348 # Cumulative time (in ticks) in various power states 520system.cpu.numCycles 5807473581 # number of cpu cycles simulated |
| 515system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 516system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 517system.cpu.kern.inst.arm 0 # number of arm instructions executed | 521system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 522system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 523system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 518system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 519system.cpu.committedInsts 112460013 # Number of instructions committed 520system.cpu.committedOps 135590937 # Number of ops (including micro ops) committed 521system.cpu.num_int_alu_accesses 119896152 # Number of integer alu accesses | 524system.cpu.kern.inst.quiesce 3031 # number of quiesce instructions executed 525system.cpu.committedInsts 112476413 # Number of instructions committed 526system.cpu.committedOps 135613231 # Number of ops (including micro ops) committed 527system.cpu.num_int_alu_accesses 119916333 # Number of integer alu accesses |
| 522system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses | 528system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses |
| 523system.cpu.num_func_calls 9892206 # number of times a function call or return occured 524system.cpu.num_conditional_control_insts 15230739 # number of instructions that are conditional controls 525system.cpu.num_int_insts 119896152 # number of integer instructions | 529system.cpu.num_func_calls 9896179 # number of times a function call or return occured 530system.cpu.num_conditional_control_insts 15232917 # number of instructions that are conditional controls 531system.cpu.num_int_insts 119916333 # number of integer instructions |
| 526system.cpu.num_fp_insts 11161 # number of float instructions | 532system.cpu.num_fp_insts 11161 # number of float instructions |
| 527system.cpu.num_int_register_reads 218055319 # number of times the integer registers were read 528system.cpu.num_int_register_writes 82647707 # number of times the integer registers were written | 533system.cpu.num_int_register_reads 218092554 # number of times the integer registers were read 534system.cpu.num_int_register_writes 82663252 # number of times the integer registers were written |
| 529system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 530system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written | 535system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 536system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written |
| 531system.cpu.num_cc_register_reads 489751912 # number of times the CC registers were read 532system.cpu.num_cc_register_writes 51896592 # number of times the CC registers were written 533system.cpu.num_mem_refs 45408087 # number of memory refs 534system.cpu.num_load_insts 24843122 # Number of load instructions 535system.cpu.num_store_insts 20564965 # Number of store instructions 536system.cpu.num_idle_cycles 5379060798.588152 # Number of idle cycles 537system.cpu.num_busy_cycles 440104800.411849 # Number of busy cycles 538system.cpu.not_idle_fraction 0.075630 # Percentage of non-idle cycles 539system.cpu.idle_fraction 0.924370 # Percentage of idle cycles 540system.cpu.Branches 25916957 # Number of branches fetched | 537system.cpu.num_cc_register_reads 489835813 # number of times the CC registers were read 538system.cpu.num_cc_register_writes 51902110 # number of times the CC registers were written 539system.cpu.num_mem_refs 45414800 # number of memory refs 540system.cpu.num_load_insts 24847736 # Number of load instructions 541system.cpu.num_store_insts 20567064 # Number of store instructions 542system.cpu.num_idle_cycles 5384465282.694146 # Number of idle cycles 543system.cpu.num_busy_cycles 423008298.305854 # Number of busy cycles 544system.cpu.not_idle_fraction 0.072839 # Percentage of non-idle cycles 545system.cpu.idle_fraction 0.927161 # Percentage of idle cycles 546system.cpu.Branches 25923023 # Number of branches fetched |
| 541system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction | 547system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction |
| 542system.cpu.op_class::IntAlu 93177665 67.17% 67.18% # Class of executed instruction 543system.cpu.op_class::IntMult 114484 0.08% 67.26% # Class of executed instruction | 548system.cpu.op_class::IntAlu 93194210 67.17% 67.18% # Class of executed instruction 549system.cpu.op_class::IntMult 114540 0.08% 67.26% # Class of executed instruction |
| 544system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 545system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 546system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 547system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 548system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 549system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 550system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 551system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 563system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 564system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 565system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 566system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 567system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction 568system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 569system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 570system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction | 550system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 551system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 552system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 553system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 554system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 555system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 556system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 557system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 569system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 570system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 571system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 572system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 573system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction 574system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 575system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 576system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction |
| 571system.cpu.op_class::MemRead 24843122 17.91% 85.17% # Class of executed instruction 572system.cpu.op_class::MemWrite 20564965 14.83% 100.00% # Class of executed instruction | 577system.cpu.op_class::MemRead 24847736 17.91% 85.18% # Class of executed instruction 578system.cpu.op_class::MemWrite 20567064 14.82% 100.00% # Class of executed instruction |
| 573system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 574system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 579system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 580system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 575system.cpu.op_class::total 138711026 # Class of executed instruction 576system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 577system.cpu.dcache.tags.replacements 819269 # number of replacements 578system.cpu.dcache.tags.tagsinuse 511.702333 # Cycle average of tags in use 579system.cpu.dcache.tags.total_refs 43236296 # Total number of references to valid blocks. 580system.cpu.dcache.tags.sampled_refs 819781 # Sample count of references to valid blocks. 581system.cpu.dcache.tags.avg_refs 52.741276 # Average number of references to valid blocks. 582system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. 583system.cpu.dcache.tags.occ_blocks::cpu.data 511.702333 # Average occupied blocks per requestor 584system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy 585system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy | 581system.cpu.op_class::total 138734340 # Class of executed instruction 582system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 583system.cpu.dcache.tags.replacements 819770 # number of replacements 584system.cpu.dcache.tags.tagsinuse 511.827215 # Cycle average of tags in use 585system.cpu.dcache.tags.total_refs 43243016 # Total number of references to valid blocks. 586system.cpu.dcache.tags.sampled_refs 820282 # Sample count of references to valid blocks. 587system.cpu.dcache.tags.avg_refs 52.717256 # Average number of references to valid blocks. 588system.cpu.dcache.tags.warmup_cycle 1013099500 # Cycle when the warmup percentage was hit. 589system.cpu.dcache.tags.occ_blocks::cpu.data 511.827215 # Average occupied blocks per requestor 590system.cpu.dcache.tags.occ_percent::cpu.data 0.999663 # Average percentage of cache occupancy 591system.cpu.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy |
| 586system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id | 592system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 593system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id |
| 588system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id | 594system.cpu.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id 595system.cpu.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id 596system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id |
| 591system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 597system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 592system.cpu.dcache.tags.tag_accesses 177113149 # Number of tag accesses 593system.cpu.dcache.tags.data_accesses 177113149 # Number of data accesses 594system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 595system.cpu.dcache.ReadReq_hits::cpu.data 23112931 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 23112931 # number of ReadReq hits 597system.cpu.dcache.WriteReq_hits::cpu.data 18824347 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 18824347 # number of WriteReq hits 599system.cpu.dcache.SoftPFReq_hits::cpu.data 392800 # number of SoftPFReq hits 600system.cpu.dcache.SoftPFReq_hits::total 392800 # number of SoftPFReq hits 601system.cpu.dcache.LoadLockedReq_hits::cpu.data 443238 # number of LoadLockedReq hits 602system.cpu.dcache.LoadLockedReq_hits::total 443238 # number of LoadLockedReq hits 603system.cpu.dcache.StoreCondReq_hits::cpu.data 460213 # number of StoreCondReq hits 604system.cpu.dcache.StoreCondReq_hits::total 460213 # number of StoreCondReq hits 605system.cpu.dcache.demand_hits::cpu.data 41937278 # number of demand (read+write) hits 606system.cpu.dcache.demand_hits::total 41937278 # number of demand (read+write) hits 607system.cpu.dcache.overall_hits::cpu.data 42330078 # number of overall hits 608system.cpu.dcache.overall_hits::total 42330078 # number of overall hits 609system.cpu.dcache.ReadReq_misses::cpu.data 399955 # number of ReadReq misses 610system.cpu.dcache.ReadReq_misses::total 399955 # number of ReadReq misses 611system.cpu.dcache.WriteReq_misses::cpu.data 298727 # number of WriteReq misses 612system.cpu.dcache.WriteReq_misses::total 298727 # number of WriteReq misses 613system.cpu.dcache.SoftPFReq_misses::cpu.data 118365 # number of SoftPFReq misses 614system.cpu.dcache.SoftPFReq_misses::total 118365 # number of SoftPFReq misses 615system.cpu.dcache.LoadLockedReq_misses::cpu.data 22758 # number of LoadLockedReq misses 616system.cpu.dcache.LoadLockedReq_misses::total 22758 # number of LoadLockedReq misses | 598system.cpu.dcache.tags.tag_accesses 177141047 # Number of tag accesses 599system.cpu.dcache.tags.data_accesses 177141047 # Number of data accesses 600system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 601system.cpu.dcache.ReadReq_hits::cpu.data 23117557 # number of ReadReq hits 602system.cpu.dcache.ReadReq_hits::total 23117557 # number of ReadReq hits 603system.cpu.dcache.WriteReq_hits::cpu.data 18826251 # number of WriteReq hits 604system.cpu.dcache.WriteReq_hits::total 18826251 # number of WriteReq hits 605system.cpu.dcache.SoftPFReq_hits::cpu.data 392764 # number of SoftPFReq hits 606system.cpu.dcache.SoftPFReq_hits::total 392764 # number of SoftPFReq hits 607system.cpu.dcache.LoadLockedReq_hits::cpu.data 443415 # number of LoadLockedReq hits 608system.cpu.dcache.LoadLockedReq_hits::total 443415 # number of LoadLockedReq hits 609system.cpu.dcache.StoreCondReq_hits::cpu.data 460277 # number of StoreCondReq hits 610system.cpu.dcache.StoreCondReq_hits::total 460277 # number of StoreCondReq hits 611system.cpu.dcache.demand_hits::cpu.data 41943808 # number of demand (read+write) hits 612system.cpu.dcache.demand_hits::total 41943808 # number of demand (read+write) hits 613system.cpu.dcache.overall_hits::cpu.data 42336572 # number of overall hits 614system.cpu.dcache.overall_hits::total 42336572 # number of overall hits 615system.cpu.dcache.ReadReq_misses::cpu.data 400061 # number of ReadReq misses 616system.cpu.dcache.ReadReq_misses::total 400061 # number of ReadReq misses 617system.cpu.dcache.WriteReq_misses::cpu.data 298752 # number of WriteReq misses 618system.cpu.dcache.WriteReq_misses::total 298752 # number of WriteReq misses 619system.cpu.dcache.SoftPFReq_misses::cpu.data 118460 # number of SoftPFReq misses 620system.cpu.dcache.SoftPFReq_misses::total 118460 # number of SoftPFReq misses 621system.cpu.dcache.LoadLockedReq_misses::cpu.data 22645 # number of LoadLockedReq misses 622system.cpu.dcache.LoadLockedReq_misses::total 22645 # number of LoadLockedReq misses |
| 617system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 618system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 623system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 624system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 619system.cpu.dcache.demand_misses::cpu.data 698682 # number of demand (read+write) misses 620system.cpu.dcache.demand_misses::total 698682 # number of demand (read+write) misses 621system.cpu.dcache.overall_misses::cpu.data 817047 # number of overall misses 622system.cpu.dcache.overall_misses::total 817047 # number of overall misses 623system.cpu.dcache.ReadReq_miss_latency::cpu.data 6484100500 # number of ReadReq miss cycles 624system.cpu.dcache.ReadReq_miss_latency::total 6484100500 # number of ReadReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100782000 # number of WriteReq miss cycles 626system.cpu.dcache.WriteReq_miss_latency::total 19100782000 # number of WriteReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294212000 # number of LoadLockedReq miss cycles 628system.cpu.dcache.LoadLockedReq_miss_latency::total 294212000 # number of LoadLockedReq miss cycles 629system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles 630system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles 631system.cpu.dcache.demand_miss_latency::cpu.data 25584882500 # number of demand (read+write) miss cycles 632system.cpu.dcache.demand_miss_latency::total 25584882500 # number of demand (read+write) miss cycles 633system.cpu.dcache.overall_miss_latency::cpu.data 25584882500 # number of overall miss cycles 634system.cpu.dcache.overall_miss_latency::total 25584882500 # number of overall miss cycles 635system.cpu.dcache.ReadReq_accesses::cpu.data 23512886 # number of ReadReq accesses(hits+misses) 636system.cpu.dcache.ReadReq_accesses::total 23512886 # number of ReadReq accesses(hits+misses) 637system.cpu.dcache.WriteReq_accesses::cpu.data 19123074 # number of WriteReq accesses(hits+misses) 638system.cpu.dcache.WriteReq_accesses::total 19123074 # number of WriteReq accesses(hits+misses) 639system.cpu.dcache.SoftPFReq_accesses::cpu.data 511165 # number of SoftPFReq accesses(hits+misses) 640system.cpu.dcache.SoftPFReq_accesses::total 511165 # number of SoftPFReq accesses(hits+misses) 641system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465996 # number of LoadLockedReq accesses(hits+misses) 642system.cpu.dcache.LoadLockedReq_accesses::total 465996 # number of LoadLockedReq accesses(hits+misses) 643system.cpu.dcache.StoreCondReq_accesses::cpu.data 460215 # number of StoreCondReq accesses(hits+misses) 644system.cpu.dcache.StoreCondReq_accesses::total 460215 # number of StoreCondReq accesses(hits+misses) 645system.cpu.dcache.demand_accesses::cpu.data 42635960 # number of demand (read+write) accesses 646system.cpu.dcache.demand_accesses::total 42635960 # number of demand (read+write) accesses 647system.cpu.dcache.overall_accesses::cpu.data 43147125 # number of overall (read+write) accesses 648system.cpu.dcache.overall_accesses::total 43147125 # number of overall (read+write) accesses 649system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017010 # miss rate for ReadReq accesses 650system.cpu.dcache.ReadReq_miss_rate::total 0.017010 # miss rate for ReadReq accesses | 625system.cpu.dcache.demand_misses::cpu.data 698813 # number of demand (read+write) misses 626system.cpu.dcache.demand_misses::total 698813 # number of demand (read+write) misses 627system.cpu.dcache.overall_misses::cpu.data 817273 # number of overall misses 628system.cpu.dcache.overall_misses::total 817273 # number of overall misses 629system.cpu.dcache.ReadReq_miss_latency::cpu.data 5967732500 # number of ReadReq miss cycles 630system.cpu.dcache.ReadReq_miss_latency::total 5967732500 # number of ReadReq miss cycles 631system.cpu.dcache.WriteReq_miss_latency::cpu.data 12596392000 # number of WriteReq miss cycles 632system.cpu.dcache.WriteReq_miss_latency::total 12596392000 # number of WriteReq miss cycles 633system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280149500 # number of LoadLockedReq miss cycles 634system.cpu.dcache.LoadLockedReq_miss_latency::total 280149500 # number of LoadLockedReq miss cycles 635system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles 636system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles 637system.cpu.dcache.demand_miss_latency::cpu.data 18564124500 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 18564124500 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 18564124500 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 18564124500 # number of overall miss cycles 641system.cpu.dcache.ReadReq_accesses::cpu.data 23517618 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 23517618 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::cpu.data 19125003 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 19125003 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.SoftPFReq_accesses::cpu.data 511224 # number of SoftPFReq accesses(hits+misses) 646system.cpu.dcache.SoftPFReq_accesses::total 511224 # number of SoftPFReq accesses(hits+misses) 647system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466060 # number of LoadLockedReq accesses(hits+misses) 648system.cpu.dcache.LoadLockedReq_accesses::total 466060 # number of LoadLockedReq accesses(hits+misses) 649system.cpu.dcache.StoreCondReq_accesses::cpu.data 460279 # number of StoreCondReq accesses(hits+misses) 650system.cpu.dcache.StoreCondReq_accesses::total 460279 # number of StoreCondReq accesses(hits+misses) 651system.cpu.dcache.demand_accesses::cpu.data 42642621 # number of demand (read+write) accesses 652system.cpu.dcache.demand_accesses::total 42642621 # number of demand (read+write) accesses 653system.cpu.dcache.overall_accesses::cpu.data 43153845 # number of overall (read+write) accesses 654system.cpu.dcache.overall_accesses::total 43153845 # number of overall (read+write) accesses 655system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017011 # miss rate for ReadReq accesses 656system.cpu.dcache.ReadReq_miss_rate::total 0.017011 # miss rate for ReadReq accesses |
| 651system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015621 # miss rate for WriteReq accesses 652system.cpu.dcache.WriteReq_miss_rate::total 0.015621 # miss rate for WriteReq accesses | 657system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015621 # miss rate for WriteReq accesses 658system.cpu.dcache.WriteReq_miss_rate::total 0.015621 # miss rate for WriteReq accesses |
| 653system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231559 # miss rate for SoftPFReq accesses 654system.cpu.dcache.SoftPFReq_miss_rate::total 0.231559 # miss rate for SoftPFReq accesses 655system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048837 # miss rate for LoadLockedReq accesses 656system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048837 # miss rate for LoadLockedReq accesses | 659system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231718 # miss rate for SoftPFReq accesses 660system.cpu.dcache.SoftPFReq_miss_rate::total 0.231718 # miss rate for SoftPFReq accesses 661system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048588 # miss rate for LoadLockedReq accesses 662system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048588 # miss rate for LoadLockedReq accesses |
| 657system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 658system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses | 663system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 664system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses |
| 659system.cpu.dcache.demand_miss_rate::cpu.data 0.016387 # miss rate for demand accesses 660system.cpu.dcache.demand_miss_rate::total 0.016387 # miss rate for demand accesses 661system.cpu.dcache.overall_miss_rate::cpu.data 0.018936 # miss rate for overall accesses 662system.cpu.dcache.overall_miss_rate::total 0.018936 # miss rate for overall accesses 663system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16212.075108 # average ReadReq miss latency 664system.cpu.dcache.ReadReq_avg_miss_latency::total 16212.075108 # average ReadReq miss latency 665system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63940.594590 # average WriteReq miss latency 666system.cpu.dcache.WriteReq_avg_miss_latency::total 63940.594590 # average WriteReq miss latency 667system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12927.849547 # average LoadLockedReq miss latency 668system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12927.849547 # average LoadLockedReq miss latency 669system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 670system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 671system.cpu.dcache.demand_avg_miss_latency::cpu.data 36618.780074 # average overall miss latency 672system.cpu.dcache.demand_avg_miss_latency::total 36618.780074 # average overall miss latency 673system.cpu.dcache.overall_avg_miss_latency::cpu.data 31313.844246 # average overall miss latency 674system.cpu.dcache.overall_avg_miss_latency::total 31313.844246 # average overall miss latency 675system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked | 665system.cpu.dcache.demand_miss_rate::cpu.data 0.016388 # miss rate for demand accesses 666system.cpu.dcache.demand_miss_rate::total 0.016388 # miss rate for demand accesses 667system.cpu.dcache.overall_miss_rate::cpu.data 0.018939 # miss rate for overall accesses 668system.cpu.dcache.overall_miss_rate::total 0.018939 # miss rate for overall accesses 669system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399 # average ReadReq miss latency 670system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399 # average ReadReq miss latency 671system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965 # average WriteReq miss latency 672system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965 # average WriteReq miss latency 673system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332 # average LoadLockedReq miss latency 674system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332 # average LoadLockedReq miss latency 675system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 676system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency 677system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.224888 # average overall miss latency 678system.cpu.dcache.demand_avg_miss_latency::total 26565.224888 # average overall miss latency 679system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502 # average overall miss latency 680system.cpu.dcache.overall_avg_miss_latency::total 22714.716502 # average overall miss latency 681system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked |
| 676system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 682system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 677system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked | 683system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked |
| 678system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 684system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 679system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked | 685system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked |
| 680system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 686system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 681system.cpu.dcache.writebacks::writebacks 683888 # number of writebacks 682system.cpu.dcache.writebacks::total 683888 # number of writebacks 683system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits 684system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits 685system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14248 # number of LoadLockedReq MSHR hits 686system.cpu.dcache.LoadLockedReq_mshr_hits::total 14248 # number of LoadLockedReq MSHR hits 687system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits 688system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits 689system.cpu.dcache.overall_mshr_hits::cpu.data 929 # number of overall MSHR hits 690system.cpu.dcache.overall_mshr_hits::total 929 # number of overall MSHR hits 691system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399026 # number of ReadReq MSHR misses 692system.cpu.dcache.ReadReq_mshr_misses::total 399026 # number of ReadReq MSHR misses 693system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298727 # number of WriteReq MSHR misses 694system.cpu.dcache.WriteReq_mshr_misses::total 298727 # number of WriteReq MSHR misses 695system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116307 # number of SoftPFReq MSHR misses 696system.cpu.dcache.SoftPFReq_mshr_misses::total 116307 # number of SoftPFReq MSHR misses 697system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses 698system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses | 687system.cpu.dcache.writebacks::writebacks 683946 # number of writebacks 688system.cpu.dcache.writebacks::total 683946 # number of writebacks 689system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits 690system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits 691system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14146 # number of LoadLockedReq MSHR hits 692system.cpu.dcache.LoadLockedReq_mshr_hits::total 14146 # number of LoadLockedReq MSHR hits 693system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits 694system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits 695system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits 696system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits 697system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399381 # number of ReadReq MSHR misses 698system.cpu.dcache.ReadReq_mshr_misses::total 399381 # number of ReadReq MSHR misses 699system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298752 # number of WriteReq MSHR misses 700system.cpu.dcache.WriteReq_mshr_misses::total 298752 # number of WriteReq MSHR misses 701system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116429 # number of SoftPFReq MSHR misses 702system.cpu.dcache.SoftPFReq_mshr_misses::total 116429 # number of SoftPFReq MSHR misses 703system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8499 # number of LoadLockedReq MSHR misses 704system.cpu.dcache.LoadLockedReq_mshr_misses::total 8499 # number of LoadLockedReq MSHR misses |
| 699system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 700system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 705system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 706system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 701system.cpu.dcache.demand_mshr_misses::cpu.data 697753 # number of demand (read+write) MSHR misses 702system.cpu.dcache.demand_mshr_misses::total 697753 # number of demand (read+write) MSHR misses 703system.cpu.dcache.overall_mshr_misses::cpu.data 814060 # number of overall MSHR misses 704system.cpu.dcache.overall_mshr_misses::total 814060 # number of overall MSHR misses | 707system.cpu.dcache.demand_mshr_misses::cpu.data 698133 # number of demand (read+write) MSHR misses 708system.cpu.dcache.demand_mshr_misses::total 698133 # number of demand (read+write) MSHR misses 709system.cpu.dcache.overall_mshr_misses::cpu.data 814562 # number of overall MSHR misses 710system.cpu.dcache.overall_mshr_misses::total 814562 # number of overall MSHR misses |
| 705system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 706system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable 707system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 708system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 709system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 710system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses | 711system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 712system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable 713system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 714system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 715system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 716system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses |
| 711system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6054899500 # number of ReadReq MSHR miss cycles 712system.cpu.dcache.ReadReq_mshr_miss_latency::total 6054899500 # number of ReadReq MSHR miss cycles 713system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18802055000 # number of WriteReq MSHR miss cycles 714system.cpu.dcache.WriteReq_mshr_miss_latency::total 18802055000 # number of WriteReq MSHR miss cycles 715system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1615129000 # number of SoftPFReq MSHR miss cycles 716system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1615129000 # number of SoftPFReq MSHR miss cycles 717system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115315500 # number of LoadLockedReq MSHR miss cycles 718system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115315500 # number of LoadLockedReq MSHR miss cycles 719system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles 720system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles 721system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24856954500 # number of demand (read+write) MSHR miss cycles 722system.cpu.dcache.demand_mshr_miss_latency::total 24856954500 # number of demand (read+write) MSHR miss cycles 723system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472083500 # number of overall MSHR miss cycles 724system.cpu.dcache.overall_mshr_miss_latency::total 26472083500 # number of overall MSHR miss cycles 725system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278142000 # number of ReadReq MSHR uncacheable cycles 726system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278142000 # number of ReadReq MSHR uncacheable cycles 727system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278142000 # number of overall MSHR uncacheable cycles 728system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278142000 # number of overall MSHR uncacheable cycles 729system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016971 # mshr miss rate for ReadReq accesses 730system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016971 # mshr miss rate for ReadReq accesses | 717system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5555392000 # number of ReadReq MSHR miss cycles 718system.cpu.dcache.ReadReq_mshr_miss_latency::total 5555392000 # number of ReadReq MSHR miss cycles 719system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12297640000 # number of WriteReq MSHR miss cycles 720system.cpu.dcache.WriteReq_mshr_miss_latency::total 12297640000 # number of WriteReq MSHR miss cycles 721system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1530002500 # number of SoftPFReq MSHR miss cycles 722system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1530002500 # number of SoftPFReq MSHR miss cycles 723system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 108858500 # number of LoadLockedReq MSHR miss cycles 724system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108858500 # number of LoadLockedReq MSHR miss cycles 725system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles 726system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles 727system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17853032000 # number of demand (read+write) MSHR miss cycles 728system.cpu.dcache.demand_mshr_miss_latency::total 17853032000 # number of demand (read+write) MSHR miss cycles 729system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19383034500 # number of overall MSHR miss cycles 730system.cpu.dcache.overall_mshr_miss_latency::total 19383034500 # number of overall MSHR miss cycles 731system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281205500 # number of ReadReq MSHR uncacheable cycles 732system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281205500 # number of ReadReq MSHR uncacheable cycles 733system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281205500 # number of overall MSHR uncacheable cycles 734system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281205500 # number of overall MSHR uncacheable cycles 735system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016982 # mshr miss rate for ReadReq accesses 736system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016982 # mshr miss rate for ReadReq accesses |
| 731system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses 732system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses | 737system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses 738system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses |
| 733system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227533 # mshr miss rate for SoftPFReq accesses 734system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227533 # mshr miss rate for SoftPFReq accesses 735system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses 736system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses | 739system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227746 # mshr miss rate for SoftPFReq accesses 740system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227746 # mshr miss rate for SoftPFReq accesses 741system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018236 # mshr miss rate for LoadLockedReq accesses 742system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018236 # mshr miss rate for LoadLockedReq accesses |
| 737system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 738system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses | 743system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 744system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses |
| 739system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016365 # mshr miss rate for demand accesses 740system.cpu.dcache.demand_mshr_miss_rate::total 0.016365 # mshr miss rate for demand accesses 741system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018867 # mshr miss rate for overall accesses 742system.cpu.dcache.overall_mshr_miss_rate::total 0.018867 # mshr miss rate for overall accesses 743system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15174.197922 # average ReadReq mshr miss latency 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15174.197922 # average ReadReq mshr miss latency 745system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62940.594590 # average WriteReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62940.594590 # average WriteReq mshr miss latency 747system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13886.773797 # average SoftPFReq mshr miss latency 748system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13886.773797 # average SoftPFReq mshr miss latency 749system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13550.587544 # average LoadLockedReq mshr miss latency 750system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13550.587544 # average LoadLockedReq mshr miss latency 751system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 752system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 753system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35624.288968 # average overall mshr miss latency 754system.cpu.dcache.demand_avg_mshr_miss_latency::total 35624.288968 # average overall mshr miss latency 755system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32518.590153 # average overall mshr miss latency 756system.cpu.dcache.overall_avg_mshr_miss_latency::total 32518.590153 # average overall mshr miss latency 757system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.161410 # average ReadReq mshr uncacheable latency 758system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.161410 # average ReadReq mshr uncacheable latency 759system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.843207 # average overall mshr uncacheable latency 760system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.843207 # average overall mshr uncacheable latency 761system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 762system.cpu.icache.tags.replacements 1695563 # number of replacements 763system.cpu.icache.tags.tagsinuse 510.436859 # Cycle average of tags in use 764system.cpu.icache.tags.total_refs 113861174 # Total number of references to valid blocks. 765system.cpu.icache.tags.sampled_refs 1696075 # Sample count of references to valid blocks. 766system.cpu.icache.tags.avg_refs 67.132157 # Average number of references to valid blocks. 767system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. 768system.cpu.icache.tags.occ_blocks::cpu.inst 510.436859 # Average occupied blocks per requestor 769system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy 770system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy | 745system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016372 # mshr miss rate for demand accesses 746system.cpu.dcache.demand_mshr_miss_rate::total 0.016372 # mshr miss rate for demand accesses 747system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018876 # mshr miss rate for overall accesses 748system.cpu.dcache.overall_mshr_miss_rate::total 0.018876 # mshr miss rate for overall accesses 749system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13910.005734 # average ReadReq mshr miss latency 750system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734 # average ReadReq mshr miss latency 751system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965 # average WriteReq mshr miss latency 752system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965 # average WriteReq mshr miss latency 753system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395 # average SoftPFReq mshr miss latency 754system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395 # average SoftPFReq mshr miss latency 755system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222 # average LoadLockedReq mshr miss latency 756system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222 # average LoadLockedReq mshr miss latency 757system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 758system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency 759system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25572.537038 # average overall mshr miss latency 760system.cpu.dcache.demand_avg_mshr_miss_latency::total 25572.537038 # average overall mshr miss latency 761system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23795.652756 # average overall mshr miss latency 762system.cpu.dcache.overall_avg_mshr_miss_latency::total 23795.652756 # average overall mshr miss latency 763system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201721.546021 # average ReadReq mshr uncacheable latency 764system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.546021 # average ReadReq mshr uncacheable latency 765system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310 # average overall mshr uncacheable latency 766system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310 # average overall mshr uncacheable latency 767system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 768system.cpu.icache.tags.replacements 1698000 # number of replacements 769system.cpu.icache.tags.tagsinuse 510.728664 # Cycle average of tags in use 770system.cpu.icache.tags.total_refs 113875998 # Total number of references to valid blocks. 771system.cpu.icache.tags.sampled_refs 1698512 # Sample count of references to valid blocks. 772system.cpu.icache.tags.avg_refs 67.044565 # Average number of references to valid blocks. 773system.cpu.icache.tags.warmup_cycle 25832791500 # Cycle when the warmup percentage was hit. 774system.cpu.icache.tags.occ_blocks::cpu.inst 510.728664 # Average occupied blocks per requestor 775system.cpu.icache.tags.occ_percent::cpu.inst 0.997517 # Average percentage of cache occupancy 776system.cpu.icache.tags.occ_percent::total 0.997517 # Average percentage of cache occupancy |
| 771system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 772system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 773system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id | 777system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 778system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 779system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id |
| 774system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id 775system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id | 780system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 781system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id |
| 776system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 782system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 777system.cpu.icache.tags.tag_accesses 117253336 # Number of tag accesses 778system.cpu.icache.tags.data_accesses 117253336 # Number of data accesses 779system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 780system.cpu.icache.ReadReq_hits::cpu.inst 113861174 # number of ReadReq hits 781system.cpu.icache.ReadReq_hits::total 113861174 # number of ReadReq hits 782system.cpu.icache.demand_hits::cpu.inst 113861174 # number of demand (read+write) hits 783system.cpu.icache.demand_hits::total 113861174 # number of demand (read+write) hits 784system.cpu.icache.overall_hits::cpu.inst 113861174 # number of overall hits 785system.cpu.icache.overall_hits::total 113861174 # number of overall hits 786system.cpu.icache.ReadReq_misses::cpu.inst 1696081 # number of ReadReq misses 787system.cpu.icache.ReadReq_misses::total 1696081 # number of ReadReq misses 788system.cpu.icache.demand_misses::cpu.inst 1696081 # number of demand (read+write) misses 789system.cpu.icache.demand_misses::total 1696081 # number of demand (read+write) misses 790system.cpu.icache.overall_misses::cpu.inst 1696081 # number of overall misses 791system.cpu.icache.overall_misses::total 1696081 # number of overall misses 792system.cpu.icache.ReadReq_miss_latency::cpu.inst 24265706000 # number of ReadReq miss cycles 793system.cpu.icache.ReadReq_miss_latency::total 24265706000 # number of ReadReq miss cycles 794system.cpu.icache.demand_miss_latency::cpu.inst 24265706000 # number of demand (read+write) miss cycles 795system.cpu.icache.demand_miss_latency::total 24265706000 # number of demand (read+write) miss cycles 796system.cpu.icache.overall_miss_latency::cpu.inst 24265706000 # number of overall miss cycles 797system.cpu.icache.overall_miss_latency::total 24265706000 # number of overall miss cycles 798system.cpu.icache.ReadReq_accesses::cpu.inst 115557255 # number of ReadReq accesses(hits+misses) 799system.cpu.icache.ReadReq_accesses::total 115557255 # number of ReadReq accesses(hits+misses) 800system.cpu.icache.demand_accesses::cpu.inst 115557255 # number of demand (read+write) accesses 801system.cpu.icache.demand_accesses::total 115557255 # number of demand (read+write) accesses 802system.cpu.icache.overall_accesses::cpu.inst 115557255 # number of overall (read+write) accesses 803system.cpu.icache.overall_accesses::total 115557255 # number of overall (read+write) accesses 804system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014677 # miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses 806system.cpu.icache.demand_miss_rate::cpu.inst 0.014677 # miss rate for demand accesses 807system.cpu.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses 808system.cpu.icache.overall_miss_rate::cpu.inst 0.014677 # miss rate for overall accesses 809system.cpu.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses 810system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14306.926379 # average ReadReq miss latency 811system.cpu.icache.ReadReq_avg_miss_latency::total 14306.926379 # average ReadReq miss latency 812system.cpu.icache.demand_avg_miss_latency::cpu.inst 14306.926379 # average overall miss latency 813system.cpu.icache.demand_avg_miss_latency::total 14306.926379 # average overall miss latency 814system.cpu.icache.overall_avg_miss_latency::cpu.inst 14306.926379 # average overall miss latency 815system.cpu.icache.overall_avg_miss_latency::total 14306.926379 # average overall miss latency | 783system.cpu.icache.tags.tag_accesses 117273034 # Number of tag accesses 784system.cpu.icache.tags.data_accesses 117273034 # Number of data accesses 785system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 786system.cpu.icache.ReadReq_hits::cpu.inst 113875998 # number of ReadReq hits 787system.cpu.icache.ReadReq_hits::total 113875998 # number of ReadReq hits 788system.cpu.icache.demand_hits::cpu.inst 113875998 # number of demand (read+write) hits 789system.cpu.icache.demand_hits::total 113875998 # number of demand (read+write) hits 790system.cpu.icache.overall_hits::cpu.inst 113875998 # number of overall hits 791system.cpu.icache.overall_hits::total 113875998 # number of overall hits 792system.cpu.icache.ReadReq_misses::cpu.inst 1698518 # number of ReadReq misses 793system.cpu.icache.ReadReq_misses::total 1698518 # number of ReadReq misses 794system.cpu.icache.demand_misses::cpu.inst 1698518 # number of demand (read+write) misses 795system.cpu.icache.demand_misses::total 1698518 # number of demand (read+write) misses 796system.cpu.icache.overall_misses::cpu.inst 1698518 # number of overall misses 797system.cpu.icache.overall_misses::total 1698518 # number of overall misses 798system.cpu.icache.ReadReq_miss_latency::cpu.inst 23414403500 # number of ReadReq miss cycles 799system.cpu.icache.ReadReq_miss_latency::total 23414403500 # number of ReadReq miss cycles 800system.cpu.icache.demand_miss_latency::cpu.inst 23414403500 # number of demand (read+write) miss cycles 801system.cpu.icache.demand_miss_latency::total 23414403500 # number of demand (read+write) miss cycles 802system.cpu.icache.overall_miss_latency::cpu.inst 23414403500 # number of overall miss cycles 803system.cpu.icache.overall_miss_latency::total 23414403500 # number of overall miss cycles 804system.cpu.icache.ReadReq_accesses::cpu.inst 115574516 # number of ReadReq accesses(hits+misses) 805system.cpu.icache.ReadReq_accesses::total 115574516 # number of ReadReq accesses(hits+misses) 806system.cpu.icache.demand_accesses::cpu.inst 115574516 # number of demand (read+write) accesses 807system.cpu.icache.demand_accesses::total 115574516 # number of demand (read+write) accesses 808system.cpu.icache.overall_accesses::cpu.inst 115574516 # number of overall (read+write) accesses 809system.cpu.icache.overall_accesses::total 115574516 # number of overall (read+write) accesses 810system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014696 # miss rate for ReadReq accesses 811system.cpu.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses 812system.cpu.icache.demand_miss_rate::cpu.inst 0.014696 # miss rate for demand accesses 813system.cpu.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses 814system.cpu.icache.overall_miss_rate::cpu.inst 0.014696 # miss rate for overall accesses 815system.cpu.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses 816system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977 # average ReadReq miss latency 817system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977 # average ReadReq miss latency 818system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency 819system.cpu.icache.demand_avg_miss_latency::total 13785.195977 # average overall miss latency 820system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency 821system.cpu.icache.overall_avg_miss_latency::total 13785.195977 # average overall miss latency |
| 816system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 817system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 818system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 819system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 820system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 821system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 822system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 823system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 824system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 825system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 826system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 827system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 822system.cpu.icache.writebacks::writebacks 1695563 # number of writebacks 823system.cpu.icache.writebacks::total 1695563 # number of writebacks 824system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696081 # number of ReadReq MSHR misses 825system.cpu.icache.ReadReq_mshr_misses::total 1696081 # number of ReadReq MSHR misses 826system.cpu.icache.demand_mshr_misses::cpu.inst 1696081 # number of demand (read+write) MSHR misses 827system.cpu.icache.demand_mshr_misses::total 1696081 # number of demand (read+write) MSHR misses 828system.cpu.icache.overall_mshr_misses::cpu.inst 1696081 # number of overall MSHR misses 829system.cpu.icache.overall_mshr_misses::total 1696081 # number of overall MSHR misses | 828system.cpu.icache.writebacks::writebacks 1698000 # number of writebacks 829system.cpu.icache.writebacks::total 1698000 # number of writebacks 830system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1698518 # number of ReadReq MSHR misses 831system.cpu.icache.ReadReq_mshr_misses::total 1698518 # number of ReadReq MSHR misses 832system.cpu.icache.demand_mshr_misses::cpu.inst 1698518 # number of demand (read+write) MSHR misses 833system.cpu.icache.demand_mshr_misses::total 1698518 # number of demand (read+write) MSHR misses 834system.cpu.icache.overall_mshr_misses::cpu.inst 1698518 # number of overall MSHR misses 835system.cpu.icache.overall_mshr_misses::total 1698518 # number of overall MSHR misses |
| 830system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 831system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 832system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 833system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses | 836system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 837system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 838system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 839system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses |
| 834system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22569625000 # number of ReadReq MSHR miss cycles 835system.cpu.icache.ReadReq_mshr_miss_latency::total 22569625000 # number of ReadReq MSHR miss cycles 836system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22569625000 # number of demand (read+write) MSHR miss cycles 837system.cpu.icache.demand_mshr_miss_latency::total 22569625000 # number of demand (read+write) MSHR miss cycles 838system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22569625000 # number of overall MSHR miss cycles 839system.cpu.icache.overall_mshr_miss_latency::total 22569625000 # number of overall MSHR miss cycles 840system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles 841system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles 842system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles 843system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles 844system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014677 # mshr miss rate for ReadReq accesses 845system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses 846system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014677 # mshr miss rate for demand accesses 847system.cpu.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses 848system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014677 # mshr miss rate for overall accesses 849system.cpu.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses 850system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13306.926379 # average ReadReq mshr miss latency 851system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13306.926379 # average ReadReq mshr miss latency 852system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13306.926379 # average overall mshr miss latency 853system.cpu.icache.demand_avg_mshr_miss_latency::total 13306.926379 # average overall mshr miss latency 854system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13306.926379 # average overall mshr miss latency 855system.cpu.icache.overall_avg_mshr_miss_latency::total 13306.926379 # average overall mshr miss latency 856system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 857system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 858system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 859system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency 860system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 861system.cpu.l2cache.tags.replacements 87565 # number of replacements 862system.cpu.l2cache.tags.tagsinuse 64865.266824 # Cycle average of tags in use 863system.cpu.l2cache.tags.total_refs 4544306 # Total number of references to valid blocks. 864system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. 865system.cpu.l2cache.tags.avg_refs 29.740223 # Average number of references to valid blocks. 866system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 867system.cpu.l2cache.tags.occ_blocks::writebacks 50196.788245 # Average occupied blocks per requestor 868system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799337 # Average occupied blocks per requestor 869system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012648 # Average occupied blocks per requestor 870system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.702812 # Average occupied blocks per requestor 871system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.963782 # Average occupied blocks per requestor 872system.cpu.l2cache.tags.occ_percent::writebacks 0.765942 # Average percentage of cache occupancy 873system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 874system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 875system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148036 # Average percentage of cache occupancy 876system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy 877system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy 878system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 879system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id 880system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 881system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 882system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 883system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id 884system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id 885system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56201 # Occupied blocks per task id 886system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 887system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id 888system.cpu.l2cache.tags.tag_accesses 40510666 # Number of tag accesses 889system.cpu.l2cache.tags.data_accesses 40510666 # Number of data accesses 890system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 891system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits 892system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits 893system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits 894system.cpu.l2cache.WritebackDirty_hits::writebacks 683888 # number of WritebackDirty hits 895system.cpu.l2cache.WritebackDirty_hits::total 683888 # number of WritebackDirty hits 896system.cpu.l2cache.WritebackClean_hits::writebacks 1664800 # number of WritebackClean hits 897system.cpu.l2cache.WritebackClean_hits::total 1664800 # number of WritebackClean hits 898system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 899system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 900system.cpu.l2cache.ReadExReq_hits::cpu.data 167046 # number of ReadExReq hits 901system.cpu.l2cache.ReadExReq_hits::total 167046 # number of ReadExReq hits 902system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678073 # number of ReadCleanReq hits 903system.cpu.l2cache.ReadCleanReq_hits::total 1678073 # number of ReadCleanReq hits 904system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511671 # number of ReadSharedReq hits 905system.cpu.l2cache.ReadSharedReq_hits::total 511671 # number of ReadSharedReq hits 906system.cpu.l2cache.demand_hits::cpu.dtb.walker 7807 # number of demand (read+write) hits 907system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits 908system.cpu.l2cache.demand_hits::cpu.inst 1678073 # number of demand (read+write) hits 909system.cpu.l2cache.demand_hits::cpu.data 678717 # number of demand (read+write) hits 910system.cpu.l2cache.demand_hits::total 2368636 # number of demand (read+write) hits 911system.cpu.l2cache.overall_hits::cpu.dtb.walker 7807 # number of overall hits 912system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits 913system.cpu.l2cache.overall_hits::cpu.inst 1678073 # number of overall hits 914system.cpu.l2cache.overall_hits::cpu.data 678717 # number of overall hits 915system.cpu.l2cache.overall_hits::total 2368636 # number of overall hits 916system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses | 840system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21715885500 # number of ReadReq MSHR miss cycles 841system.cpu.icache.ReadReq_mshr_miss_latency::total 21715885500 # number of ReadReq MSHR miss cycles 842system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21715885500 # number of demand (read+write) MSHR miss cycles 843system.cpu.icache.demand_mshr_miss_latency::total 21715885500 # number of demand (read+write) MSHR miss cycles 844system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21715885500 # number of overall MSHR miss cycles 845system.cpu.icache.overall_mshr_miss_latency::total 21715885500 # number of overall MSHR miss cycles 846system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 687287000 # number of ReadReq MSHR uncacheable cycles 847system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles 848system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 687287000 # number of overall MSHR uncacheable cycles 849system.cpu.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles 850system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for ReadReq accesses 851system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses 852system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for demand accesses 853system.cpu.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses 854system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for overall accesses 855system.cpu.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses 856system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977 # average ReadReq mshr miss latency 857system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977 # average ReadReq mshr miss latency 858system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency 859system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency 860system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency 861system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency 862system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average ReadReq mshr uncacheable latency 863system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency 864system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average overall mshr uncacheable latency 865system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency 866system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 867system.cpu.l2cache.tags.replacements 89464 # number of replacements 868system.cpu.l2cache.tags.tagsinuse 65017.694965 # Cycle average of tags in use 869system.cpu.l2cache.tags.total_refs 4847707 # Total number of references to valid blocks. 870system.cpu.l2cache.tags.sampled_refs 154877 # Sample count of references to valid blocks. 871system.cpu.l2cache.tags.avg_refs 31.300367 # Average number of references to valid blocks. 872system.cpu.l2cache.tags.warmup_cycle 144041988000 # Cycle when the warmup percentage was hit. 873system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.877834 # Average occupied blocks per requestor 874system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.040783 # Average occupied blocks per requestor 875system.cpu.l2cache.tags.occ_blocks::cpu.inst 9524.120186 # Average occupied blocks per requestor 876system.cpu.l2cache.tags.occ_blocks::cpu.data 55489.656162 # Average occupied blocks per requestor 877system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 878system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy 879system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145327 # Average percentage of cache occupancy 880system.cpu.l2cache.tags.occ_percent::cpu.data 0.846705 # Average percentage of cache occupancy 881system.cpu.l2cache.tags.occ_percent::total 0.992091 # Average percentage of cache occupancy 882system.cpu.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 883system.cpu.l2cache.tags.occ_task_id_blocks::1024 65407 # Occupied blocks per task id 884system.cpu.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 885system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 886system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 887system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4600 # Occupied blocks per task id 888system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60798 # Occupied blocks per task id 889system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 890system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998032 # Percentage of cache occupancy per task id 891system.cpu.l2cache.tags.tag_accesses 40230644 # Number of tag accesses 892system.cpu.l2cache.tags.data_accesses 40230644 # Number of data accesses 893system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 894system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5114 # number of ReadReq hits 895system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2743 # number of ReadReq hits 896system.cpu.l2cache.ReadReq_hits::total 7857 # number of ReadReq hits 897system.cpu.l2cache.WritebackDirty_hits::writebacks 683946 # number of WritebackDirty hits 898system.cpu.l2cache.WritebackDirty_hits::total 683946 # number of WritebackDirty hits 899system.cpu.l2cache.WritebackClean_hits::writebacks 1666952 # number of WritebackClean hits 900system.cpu.l2cache.WritebackClean_hits::total 1666952 # number of WritebackClean hits 901system.cpu.l2cache.UpgradeReq_hits::cpu.data 2730 # number of UpgradeReq hits 902system.cpu.l2cache.UpgradeReq_hits::total 2730 # number of UpgradeReq hits 903system.cpu.l2cache.ReadExReq_hits::cpu.data 166687 # number of ReadExReq hits 904system.cpu.l2cache.ReadExReq_hits::total 166687 # number of ReadExReq hits 905system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1680478 # number of ReadCleanReq hits 906system.cpu.l2cache.ReadCleanReq_hits::total 1680478 # number of ReadCleanReq hits 907system.cpu.l2cache.ReadSharedReq_hits::cpu.data 512210 # number of ReadSharedReq hits 908system.cpu.l2cache.ReadSharedReq_hits::total 512210 # number of ReadSharedReq hits 909system.cpu.l2cache.demand_hits::cpu.dtb.walker 5114 # number of demand (read+write) hits 910system.cpu.l2cache.demand_hits::cpu.itb.walker 2743 # number of demand (read+write) hits 911system.cpu.l2cache.demand_hits::cpu.inst 1680478 # number of demand (read+write) hits 912system.cpu.l2cache.demand_hits::cpu.data 678897 # number of demand (read+write) hits 913system.cpu.l2cache.demand_hits::total 2367232 # number of demand (read+write) hits 914system.cpu.l2cache.overall_hits::cpu.dtb.walker 5114 # number of overall hits 915system.cpu.l2cache.overall_hits::cpu.itb.walker 2743 # number of overall hits 916system.cpu.l2cache.overall_hits::cpu.inst 1680478 # number of overall hits 917system.cpu.l2cache.overall_hits::cpu.data 678897 # number of overall hits 918system.cpu.l2cache.overall_hits::total 2367232 # number of overall hits 919system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 8 # number of ReadReq misses |
| 917system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 920system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 918system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses 919system.cpu.l2cache.UpgradeReq_misses::cpu.data 2742 # number of UpgradeReq misses 920system.cpu.l2cache.UpgradeReq_misses::total 2742 # number of UpgradeReq misses | 921system.cpu.l2cache.ReadReq_misses::total 10 # number of ReadReq misses 922system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses 923system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses |
| 921system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 922system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 924system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 925system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 923system.cpu.l2cache.ReadExReq_misses::cpu.data 128916 # number of ReadExReq misses 924system.cpu.l2cache.ReadExReq_misses::total 128916 # number of ReadExReq misses 925system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17976 # number of ReadCleanReq misses 926system.cpu.l2cache.ReadCleanReq_misses::total 17976 # number of ReadCleanReq misses 927system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses 928system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses 929system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses | 926system.cpu.l2cache.ReadExReq_misses::cpu.data 129315 # number of ReadExReq misses 927system.cpu.l2cache.ReadExReq_misses::total 129315 # number of ReadExReq misses 928system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18016 # number of ReadCleanReq misses 929system.cpu.l2cache.ReadCleanReq_misses::total 18016 # number of ReadCleanReq misses 930system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12099 # number of ReadSharedReq misses 931system.cpu.l2cache.ReadSharedReq_misses::total 12099 # number of ReadSharedReq misses 932system.cpu.l2cache.demand_misses::cpu.dtb.walker 8 # number of demand (read+write) misses |
| 930system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 933system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 931system.cpu.l2cache.demand_misses::cpu.inst 17976 # number of demand (read+write) misses 932system.cpu.l2cache.demand_misses::cpu.data 141088 # number of demand (read+write) misses 933system.cpu.l2cache.demand_misses::total 159073 # number of demand (read+write) misses 934system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses | 934system.cpu.l2cache.demand_misses::cpu.inst 18016 # number of demand (read+write) misses 935system.cpu.l2cache.demand_misses::cpu.data 141414 # number of demand (read+write) misses 936system.cpu.l2cache.demand_misses::total 159440 # number of demand (read+write) misses 937system.cpu.l2cache.overall_misses::cpu.dtb.walker 8 # number of overall misses |
| 935system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 938system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 936system.cpu.l2cache.overall_misses::cpu.inst 17976 # number of overall misses 937system.cpu.l2cache.overall_misses::cpu.data 141088 # number of overall misses 938system.cpu.l2cache.overall_misses::total 159073 # number of overall misses 939system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles 940system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles 941system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles 942system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles 943system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles 944system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles 945system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles 946system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382163500 # number of ReadExReq miss cycles 947system.cpu.l2cache.ReadExReq_miss_latency::total 16382163500 # number of ReadExReq miss cycles 948system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2346906500 # number of ReadCleanReq miss cycles 949system.cpu.l2cache.ReadCleanReq_miss_latency::total 2346906500 # number of ReadCleanReq miss cycles 950system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1609809500 # number of ReadSharedReq miss cycles 951system.cpu.l2cache.ReadSharedReq_miss_latency::total 1609809500 # number of ReadSharedReq miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles 954system.cpu.l2cache.demand_miss_latency::cpu.inst 2346906500 # number of demand (read+write) miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.data 17991973000 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::total 20340103000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::cpu.inst 2346906500 # number of overall miss cycles 960system.cpu.l2cache.overall_miss_latency::cpu.data 17991973000 # number of overall miss cycles 961system.cpu.l2cache.overall_miss_latency::total 20340103000 # number of overall miss cycles 962system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) 963system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) 964system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) 965system.cpu.l2cache.WritebackDirty_accesses::writebacks 683888 # number of WritebackDirty accesses(hits+misses) 966system.cpu.l2cache.WritebackDirty_accesses::total 683888 # number of WritebackDirty accesses(hits+misses) 967system.cpu.l2cache.WritebackClean_accesses::writebacks 1664800 # number of WritebackClean accesses(hits+misses) 968system.cpu.l2cache.WritebackClean_accesses::total 1664800 # number of WritebackClean accesses(hits+misses) 969system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses) 970system.cpu.l2cache.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) | 939system.cpu.l2cache.overall_misses::cpu.inst 18016 # number of overall misses 940system.cpu.l2cache.overall_misses::cpu.data 141414 # number of overall misses 941system.cpu.l2cache.overall_misses::total 159440 # number of overall misses 942system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 829500 # number of ReadReq miss cycles 943system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 168000 # number of ReadReq miss cycles 944system.cpu.l2cache.ReadReq_miss_latency::total 997500 # number of ReadReq miss cycles 945system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581000 # number of UpgradeReq miss cycles 946system.cpu.l2cache.UpgradeReq_miss_latency::total 581000 # number of UpgradeReq miss cycles 947system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles 948system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles 949system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10066469000 # number of ReadExReq miss cycles 950system.cpu.l2cache.ReadExReq_miss_latency::total 10066469000 # number of ReadExReq miss cycles 951system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1464060500 # number of ReadCleanReq miss cycles 952system.cpu.l2cache.ReadCleanReq_miss_latency::total 1464060500 # number of ReadCleanReq miss cycles 953system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1012302000 # number of ReadSharedReq miss cycles 954system.cpu.l2cache.ReadSharedReq_miss_latency::total 1012302000 # number of ReadSharedReq miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 829500 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 168000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.demand_miss_latency::cpu.inst 1464060500 # number of demand (read+write) miss cycles 958system.cpu.l2cache.demand_miss_latency::cpu.data 11078771000 # number of demand (read+write) miss cycles 959system.cpu.l2cache.demand_miss_latency::total 12543829000 # number of demand (read+write) miss cycles 960system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 829500 # number of overall miss cycles 961system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 168000 # number of overall miss cycles 962system.cpu.l2cache.overall_miss_latency::cpu.inst 1464060500 # number of overall miss cycles 963system.cpu.l2cache.overall_miss_latency::cpu.data 11078771000 # number of overall miss cycles 964system.cpu.l2cache.overall_miss_latency::total 12543829000 # number of overall miss cycles 965system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5122 # number of ReadReq accesses(hits+misses) 966system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2745 # number of ReadReq accesses(hits+misses) 967system.cpu.l2cache.ReadReq_accesses::total 7867 # number of ReadReq accesses(hits+misses) 968system.cpu.l2cache.WritebackDirty_accesses::writebacks 683946 # number of WritebackDirty accesses(hits+misses) 969system.cpu.l2cache.WritebackDirty_accesses::total 683946 # number of WritebackDirty accesses(hits+misses) 970system.cpu.l2cache.WritebackClean_accesses::writebacks 1666952 # number of WritebackClean accesses(hits+misses) 971system.cpu.l2cache.WritebackClean_accesses::total 1666952 # number of WritebackClean accesses(hits+misses) 972system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2750 # number of UpgradeReq accesses(hits+misses) 973system.cpu.l2cache.UpgradeReq_accesses::total 2750 # number of UpgradeReq accesses(hits+misses) |
| 971system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 974system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 975system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 973system.cpu.l2cache.ReadExReq_accesses::cpu.data 295962 # number of ReadExReq accesses(hits+misses) 974system.cpu.l2cache.ReadExReq_accesses::total 295962 # number of ReadExReq accesses(hits+misses) 975system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696049 # number of ReadCleanReq accesses(hits+misses) 976system.cpu.l2cache.ReadCleanReq_accesses::total 1696049 # number of ReadCleanReq accesses(hits+misses) 977system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523843 # number of ReadSharedReq accesses(hits+misses) 978system.cpu.l2cache.ReadSharedReq_accesses::total 523843 # number of ReadSharedReq accesses(hits+misses) 979system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7814 # number of demand (read+write) accesses 980system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses 981system.cpu.l2cache.demand_accesses::cpu.inst 1696049 # number of demand (read+write) accesses 982system.cpu.l2cache.demand_accesses::cpu.data 819805 # number of demand (read+write) accesses 983system.cpu.l2cache.demand_accesses::total 2527709 # number of demand (read+write) accesses 984system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7814 # number of overall (read+write) accesses 985system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses 986system.cpu.l2cache.overall_accesses::cpu.inst 1696049 # number of overall (read+write) accesses 987system.cpu.l2cache.overall_accesses::cpu.data 819805 # number of overall (read+write) accesses 988system.cpu.l2cache.overall_accesses::total 2527709 # number of overall (read+write) accesses 989system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses 990system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses 991system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses 992system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991682 # miss rate for UpgradeReq accesses 993system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses | 976system.cpu.l2cache.ReadExReq_accesses::cpu.data 296002 # number of ReadExReq accesses(hits+misses) 977system.cpu.l2cache.ReadExReq_accesses::total 296002 # number of ReadExReq accesses(hits+misses) 978system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1698494 # number of ReadCleanReq accesses(hits+misses) 979system.cpu.l2cache.ReadCleanReq_accesses::total 1698494 # number of ReadCleanReq accesses(hits+misses) 980system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 524309 # number of ReadSharedReq accesses(hits+misses) 981system.cpu.l2cache.ReadSharedReq_accesses::total 524309 # number of ReadSharedReq accesses(hits+misses) 982system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5122 # number of demand (read+write) accesses 983system.cpu.l2cache.demand_accesses::cpu.itb.walker 2745 # number of demand (read+write) accesses 984system.cpu.l2cache.demand_accesses::cpu.inst 1698494 # number of demand (read+write) accesses 985system.cpu.l2cache.demand_accesses::cpu.data 820311 # number of demand (read+write) accesses 986system.cpu.l2cache.demand_accesses::total 2526672 # number of demand (read+write) accesses 987system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5122 # number of overall (read+write) accesses 988system.cpu.l2cache.overall_accesses::cpu.itb.walker 2745 # number of overall (read+write) accesses 989system.cpu.l2cache.overall_accesses::cpu.inst 1698494 # number of overall (read+write) accesses 990system.cpu.l2cache.overall_accesses::cpu.data 820311 # number of overall (read+write) accesses 991system.cpu.l2cache.overall_accesses::total 2526672 # number of overall (read+write) accesses 992system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001562 # miss rate for ReadReq accesses 993system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000729 # miss rate for ReadReq accesses 994system.cpu.l2cache.ReadReq_miss_rate::total 0.001271 # miss rate for ReadReq accesses 995system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.007273 # miss rate for UpgradeReq accesses 996system.cpu.l2cache.UpgradeReq_miss_rate::total 0.007273 # miss rate for UpgradeReq accesses |
| 994system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 995system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 997system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 998system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 996system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435583 # miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadExReq_miss_rate::total 0.435583 # miss rate for ReadExReq accesses 998system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010599 # miss rate for ReadCleanReq accesses 999system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses 1000system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023236 # miss rate for ReadSharedReq accesses 1001system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023236 # miss rate for ReadSharedReq accesses 1002system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses 1003system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses 1004system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010599 # miss rate for demand accesses 1005system.cpu.l2cache.demand_miss_rate::cpu.data 0.172099 # miss rate for demand accesses 1006system.cpu.l2cache.demand_miss_rate::total 0.062932 # miss rate for demand accesses 1007system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses 1008system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses 1009system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010599 # miss rate for overall accesses 1010system.cpu.l2cache.overall_miss_rate::cpu.data 0.172099 # miss rate for overall accesses 1011system.cpu.l2cache.overall_miss_rate::total 0.062932 # miss rate for overall accesses 1012system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286 # average ReadReq miss latency 1013system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency 1014system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency 1015system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency 1016system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency 1017system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1018system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1019system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127076.262838 # average ReadExReq miss latency 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127076.262838 # average ReadExReq miss latency 1021system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130557.771473 # average ReadCleanReq miss latency 1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130557.771473 # average ReadCleanReq miss latency 1023system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132255.134735 # average ReadSharedReq miss latency 1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132255.134735 # average ReadSharedReq miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130557.771473 # average overall miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127523.056532 # average overall miss latency 1029system.cpu.l2cache.demand_avg_miss_latency::total 127866.470111 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency 1032system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130557.771473 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127523.056532 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::total 127866.470111 # average overall miss latency | 999system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436872 # miss rate for ReadExReq accesses 1000system.cpu.l2cache.ReadExReq_miss_rate::total 0.436872 # miss rate for ReadExReq accesses 1001system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadCleanReq accesses 1002system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010607 # miss rate for ReadCleanReq accesses 1003system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses 1004system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses 1005system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001562 # miss rate for demand accesses 1006system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000729 # miss rate for demand accesses 1007system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses 1008system.cpu.l2cache.demand_miss_rate::cpu.data 0.172391 # miss rate for demand accesses 1009system.cpu.l2cache.demand_miss_rate::total 0.063103 # miss rate for demand accesses 1010system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001562 # miss rate for overall accesses 1011system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000729 # miss rate for overall accesses 1012system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses 1013system.cpu.l2cache.overall_miss_rate::cpu.data 0.172391 # miss rate for overall accesses 1014system.cpu.l2cache.overall_miss_rate::total 0.063103 # miss rate for overall accesses 1015system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103687.500000 # average ReadReq miss latency 1016system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84000 # average ReadReq miss latency 1017system.cpu.l2cache.ReadReq_avg_miss_latency::total 99750 # average ReadReq miss latency 1018system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29050 # average UpgradeReq miss latency 1019system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29050 # average UpgradeReq miss latency 1020system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 1021system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency 1022system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77844.557863 # average ReadExReq miss latency 1023system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77844.557863 # average ReadExReq miss latency 1024system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81264.459369 # average ReadCleanReq miss latency 1025system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81264.459369 # average ReadCleanReq miss latency 1026system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83668.237044 # average ReadSharedReq miss latency 1027system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83668.237044 # average ReadSharedReq miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency 1029system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency 1030system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency 1031system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency 1032system.cpu.l2cache.demand_avg_miss_latency::total 78674.291269 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency 1037system.cpu.l2cache.overall_avg_miss_latency::total 78674.291269 # average overall miss latency |
| 1035system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1036system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1037system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1040system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1038system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1041system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1043system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1041system.cpu.l2cache.writebacks::writebacks 81184 # number of writebacks 1042system.cpu.l2cache.writebacks::total 81184 # number of writebacks 1043system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses | 1044system.cpu.l2cache.writebacks::writebacks 82853 # number of writebacks 1045system.cpu.l2cache.writebacks::total 82853 # number of writebacks 1046system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 8 # number of ReadReq MSHR misses |
| 1044system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 1047system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 1045system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses 1046system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses 1047system.cpu.l2cache.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses | 1048system.cpu.l2cache.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses 1049system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses 1050system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses |
| 1048system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1049system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1051system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1052system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1050system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128916 # number of ReadExReq MSHR misses 1051system.cpu.l2cache.ReadExReq_mshr_misses::total 128916 # number of ReadExReq MSHR misses 1052system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17976 # number of ReadCleanReq MSHR misses 1053system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17976 # number of ReadCleanReq MSHR misses 1054system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses 1055system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses 1056system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses | 1053system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129315 # number of ReadExReq MSHR misses 1054system.cpu.l2cache.ReadExReq_mshr_misses::total 129315 # number of ReadExReq MSHR misses 1055system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 18016 # number of ReadCleanReq MSHR misses 1056system.cpu.l2cache.ReadCleanReq_mshr_misses::total 18016 # number of ReadCleanReq MSHR misses 1057system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12099 # number of ReadSharedReq MSHR misses 1058system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12099 # number of ReadSharedReq MSHR misses 1059system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 8 # number of demand (read+write) MSHR misses |
| 1057system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 1060system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 1058system.cpu.l2cache.demand_mshr_misses::cpu.inst 17976 # number of demand (read+write) MSHR misses 1059system.cpu.l2cache.demand_mshr_misses::cpu.data 141088 # number of demand (read+write) MSHR misses 1060system.cpu.l2cache.demand_mshr_misses::total 159073 # number of demand (read+write) MSHR misses 1061system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses | 1061system.cpu.l2cache.demand_mshr_misses::cpu.inst 18016 # number of demand (read+write) MSHR misses 1062system.cpu.l2cache.demand_mshr_misses::cpu.data 141414 # number of demand (read+write) MSHR misses 1063system.cpu.l2cache.demand_mshr_misses::total 159440 # number of demand (read+write) MSHR misses 1064system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 8 # number of overall MSHR misses |
| 1062system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 1065system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 1063system.cpu.l2cache.overall_mshr_misses::cpu.inst 17976 # number of overall MSHR misses 1064system.cpu.l2cache.overall_mshr_misses::cpu.data 141088 # number of overall MSHR misses 1065system.cpu.l2cache.overall_mshr_misses::total 159073 # number of overall MSHR misses | 1066system.cpu.l2cache.overall_mshr_misses::cpu.inst 18016 # number of overall MSHR misses 1067system.cpu.l2cache.overall_mshr_misses::cpu.data 141414 # number of overall MSHR misses 1068system.cpu.l2cache.overall_mshr_misses::total 159440 # number of overall MSHR misses |
| 1066system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 1067system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 1068system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable 1069system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 1070system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 1071system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 1072system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 1073system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses | 1069system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 1070system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 1071system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable 1072system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 1073system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 1074system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 1075system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 1076system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses |
| 1074system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 887500 # number of ReadReq MSHR miss cycles 1075system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles 1076system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1133500 # number of ReadReq MSHR miss cycles 1077system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186569500 # number of UpgradeReq MSHR miss cycles 1078system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186569500 # number of UpgradeReq MSHR miss cycles 1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles 1080system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles 1081system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093003500 # number of ReadExReq MSHR miss cycles 1082system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093003500 # number of ReadExReq MSHR miss cycles 1083system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2167146500 # number of ReadCleanReq MSHR miss cycles 1084system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2167146500 # number of ReadCleanReq MSHR miss cycles 1085system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1488089500 # number of ReadSharedReq MSHR miss cycles 1086system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1488089500 # number of ReadSharedReq MSHR miss cycles 1087system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles 1088system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles 1089system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2167146500 # number of demand (read+write) MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16581093000 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.demand_mshr_miss_latency::total 18749373000 # number of demand (read+write) MSHR miss cycles 1092system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles 1093system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles 1094system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2167146500 # number of overall MSHR miss cycles 1095system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16581093000 # number of overall MSHR miss cycles 1096system.cpu.l2cache.overall_mshr_miss_latency::total 18749373000 # number of overall MSHR miss cycles 1097system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles 1098system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888796500 # number of ReadReq MSHR uncacheable cycles 1099system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918562500 # number of ReadReq MSHR uncacheable cycles 1100system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles 1101system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888796500 # number of overall MSHR uncacheable cycles 1102system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918562500 # number of overall MSHR uncacheable cycles 1103system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses 1104system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses 1105system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses 1106system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses 1107system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses | 1077system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 749500 # number of ReadReq MSHR miss cycles 1078system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 148000 # number of ReadReq MSHR miss cycles 1079system.cpu.l2cache.ReadReq_mshr_miss_latency::total 897500 # number of ReadReq MSHR miss cycles 1080system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 381000 # number of UpgradeReq MSHR miss cycles 1081system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 381000 # number of UpgradeReq MSHR miss cycles 1082system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles 1083system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles 1084system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8773319000 # number of ReadExReq MSHR miss cycles 1085system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8773319000 # number of ReadExReq MSHR miss cycles 1086system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1283900500 # number of ReadCleanReq MSHR miss cycles 1087system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1283900500 # number of ReadCleanReq MSHR miss cycles 1088system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 891312000 # number of ReadSharedReq MSHR miss cycles 1089system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 891312000 # number of ReadSharedReq MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 749500 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 148000 # number of demand (read+write) MSHR miss cycles 1092system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1283900500 # number of demand (read+write) MSHR miss cycles 1093system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9664631000 # number of demand (read+write) MSHR miss cycles 1094system.cpu.l2cache.demand_mshr_miss_latency::total 10949429000 # number of demand (read+write) MSHR miss cycles 1095system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 749500 # number of overall MSHR miss cycles 1096system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 148000 # number of overall MSHR miss cycles 1097system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1283900500 # number of overall MSHR miss cycles 1098system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9664631000 # number of overall MSHR miss cycles 1099system.cpu.l2cache.overall_mshr_miss_latency::total 10949429000 # number of overall MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 574512000 # number of ReadReq MSHR uncacheable cycles 1101system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5891860500 # number of ReadReq MSHR uncacheable cycles 1102system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6466372500 # number of ReadReq MSHR uncacheable cycles 1103system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 574512000 # number of overall MSHR uncacheable cycles 1104system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5891860500 # number of overall MSHR uncacheable cycles 1105system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6466372500 # number of overall MSHR uncacheable cycles 1106system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for ReadReq accesses 1107system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for ReadReq accesses 1108system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001271 # mshr miss rate for ReadReq accesses 1109system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.007273 # mshr miss rate for UpgradeReq accesses 1110system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.007273 # mshr miss rate for UpgradeReq accesses |
| 1108system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1109system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1111system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1112system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1110system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435583 # mshr miss rate for ReadExReq accesses 1111system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435583 # mshr miss rate for ReadExReq accesses 1112system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses 1113system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses 1114system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023236 # mshr miss rate for ReadSharedReq accesses 1115system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023236 # mshr miss rate for ReadSharedReq accesses 1116system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses 1117system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses 1118system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172099 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172099 # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses 1126system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency 1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency 1128system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency 1129system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68041.393144 # average UpgradeReq mshr miss latency 1130system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68041.393144 # average UpgradeReq mshr miss latency 1131system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1132system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1133system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117076.262838 # average ReadExReq mshr miss latency 1134system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117076.262838 # average ReadExReq mshr miss latency 1135system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120557.771473 # average ReadCleanReq mshr miss latency 1136system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120557.771473 # average ReadCleanReq mshr miss latency 1137system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122255.134735 # average ReadSharedReq mshr miss latency 1138system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122255.134735 # average ReadSharedReq mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120557.771473 # average overall mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117523.056532 # average overall mshr miss latency 1143system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117866.470111 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120557.771473 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117523.056532 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117866.470111 # average overall mshr miss latency 1149system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency 1150system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.291541 # average ReadReq mshr uncacheable latency 1151system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172274.962649 # average ReadReq mshr uncacheable latency 1152system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency 1153system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.090282 # average overall mshr uncacheable latency 1154system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.511004 # average overall mshr uncacheable latency 1155system.cpu.toL2Bus.snoop_filter.tot_requests 5052639 # Total number of requests made to the snoop filter. 1156system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536775 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1157system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38121 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1158system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. 1159system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1113system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436872 # mshr miss rate for ReadExReq accesses 1114system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436872 # mshr miss rate for ReadExReq accesses 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadCleanReq accesses 1116system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010607 # mshr miss rate for ReadCleanReq accesses 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses 1118system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses 1122system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for demand accesses 1123system.cpu.l2cache.demand_mshr_miss_rate::total 0.063103 # mshr miss rate for demand accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for overall accesses 1126system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for overall accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::total 0.063103 # mshr miss rate for overall accesses 1129system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average ReadReq mshr miss latency 1130system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74000 # average ReadReq mshr miss latency 1131system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 89750 # average ReadReq mshr miss latency 1132system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19050 # average UpgradeReq mshr miss latency 1133system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19050 # average UpgradeReq mshr miss latency 1134system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1135system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 1136system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863 # average ReadExReq mshr miss latency 1137system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863 # average ReadExReq mshr miss latency 1138system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369 # average ReadCleanReq mshr miss latency 1139system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369 # average ReadCleanReq mshr miss latency 1140system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044 # average ReadSharedReq mshr miss latency 1141system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044 # average ReadSharedReq mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency 1143system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency 1144system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency 1145system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency 1152system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average ReadReq mshr uncacheable latency 1153system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209 # average ReadReq mshr uncacheable latency 1154system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494 # average ReadReq mshr uncacheable latency 1155system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average overall mshr uncacheable latency 1156system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899 # average overall mshr uncacheable latency 1157system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343 # average overall mshr uncacheable latency 1158system.cpu.toL2Bus.snoop_filter.tot_requests 5058492 # Total number of requests made to the snoop filter. 1159system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539687 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1160system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38280 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1161system.cpu.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. 1162system.cpu.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1160system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1163system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1161system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1162system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::ReadResp 2287350 # Transaction distribution | 1164system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1165system.cpu.toL2Bus.trans_dist::ReadReq 67163 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadResp 2290209 # Transaction distribution |
| 1164system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution | 1167system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution |
| 1166system.cpu.toL2Bus.trans_dist::WritebackDirty 801268 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::WritebackClean 1695563 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::CleanEvict 141990 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution | 1169system.cpu.toL2Bus.trans_dist::WritebackDirty 766799 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::WritebackClean 1698000 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::CleanEvict 142435 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::UpgradeReq 2750 # Transaction distribution |
| 1170system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1173system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1171system.cpu.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::ReadExReq 295962 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::ReadExResp 295962 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696081 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::ReadSharedReq 524071 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1177system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5105737 # Packet count per connected master and slave (bytes) 1178system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582080 # Packet count per connected master and slave (bytes) 1179system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) 1180system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25651 # Packet count per connected master and slave (bytes) 1181system.cpu.toL2Bus.pkt_count::total 7726725 # Packet count per connected master and slave (bytes) 1182system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217099256 # Cumulative packet size per connected master and slave (bytes) 1183system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96433117 # Cumulative packet size per connected master and slave (bytes) 1184system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31256 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_size::total 313579793 # Cumulative packet size per connected master and slave (bytes) 1187system.cpu.toL2Bus.snoops 175884 # Total snoops (count) 1188system.cpu.toL2Bus.snoopTraffic 7588792 # Total snoop traffic (bytes) 1189system.cpu.toL2Bus.snoop_fanout::samples 2773896 # Request fanout histogram 1190system.cpu.toL2Bus.snoop_fanout::mean 0.020865 # Request fanout histogram 1191system.cpu.toL2Bus.snoop_fanout::stdev 0.142933 # Request fanout histogram | 1174system.cpu.toL2Bus.trans_dist::UpgradeResp 2752 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::ReadExReq 296002 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::ReadExResp 296002 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::ReadCleanReq 1698518 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::ReadSharedReq 524530 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::InvalidateReq 4455 # Transaction distribution 1180system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5113056 # Packet count per connected master and slave (bytes) 1181system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2583569 # Packet count per connected master and slave (bytes) 1182system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11960 # Packet count per connected master and slave (bytes) 1183system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22910 # Packet count per connected master and slave (bytes) 1184system.cpu.toL2Bus.pkt_count::total 7731495 # Packet count per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217411704 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96469597 # Cumulative packet size per connected master and slave (bytes) 1187system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10980 # Cumulative packet size per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20488 # Cumulative packet size per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_size::total 313912769 # Cumulative packet size per connected master and slave (bytes) 1190system.cpu.toL2Bus.snoops 113519 # Total snoops (count) 1191system.cpu.toL2Bus.snoopTraffic 5394688 # Total snoop traffic (bytes) 1192system.cpu.toL2Bus.snoop_fanout::samples 2710473 # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::mean 0.021286 # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::stdev 0.144336 # Request fanout histogram |
| 1192system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1195system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1193system.cpu.toL2Bus.snoop_fanout::0 2716018 97.91% 97.91% # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::1 57878 2.09% 100.00% # Request fanout histogram | 1196system.cpu.toL2Bus.snoop_fanout::0 2652778 97.87% 97.87% # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::1 57695 2.13% 100.00% # Request fanout histogram |
| 1195system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1196system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1198system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1198system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1199system.cpu.toL2Bus.snoop_fanout::total 2773896 # Request fanout histogram 1200system.cpu.toL2Bus.reqLayer0.occupancy 4957389000 # Layer occupancy (ticks) | 1202system.cpu.toL2Bus.snoop_fanout::total 2710473 # Request fanout histogram 1203system.cpu.toL2Bus.reqLayer0.occupancy 4962792000 # Layer occupancy (ticks) |
| 1201system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1204system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1202system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) | 1205system.cpu.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) |
| 1203system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1206system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1204system.cpu.toL2Bus.respLayer0.occupancy 2553143500 # Layer occupancy (ticks) | 1207system.cpu.toL2Bus.respLayer0.occupancy 2556799000 # Layer occupancy (ticks) |
| 1205system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1208system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1206system.cpu.toL2Bus.respLayer1.occupancy 1276023999 # Layer occupancy (ticks) | 1209system.cpu.toL2Bus.respLayer1.occupancy 1276777495 # Layer occupancy (ticks) |
| 1207system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1210system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1208system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) | 1211system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) |
| 1209system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1212system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1210system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) | 1213system.cpu.toL2Bus.respLayer3.occupancy 17788000 # Layer occupancy (ticks) |
| 1211system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1214system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1212system.iobus.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1213system.iobus.trans_dist::ReadReq 30177 # Transaction distribution 1214system.iobus.trans_dist::ReadResp 30177 # Transaction distribution | 1215system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1216system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1217system.iobus.trans_dist::ReadResp 30183 # Transaction distribution |
| 1215system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1216system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1217system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1219system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1220system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1229system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1230system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1231system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1232system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) | 1218system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1219system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1220system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1223system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1224system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1225system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1232system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) |
| 1237system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) | 1240system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1241system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) |
| 1240system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1241system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1242system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1243system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1244system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1245system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1246system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1247system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1252system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1253system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1254system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1255system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) | 1243system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1244system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1245system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1246system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1247system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1248system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1249system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1250system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1255system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) |
| 1260system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.reqLayer0.occupancy 46336000 # Layer occupancy (ticks) | 1263system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) |
| 1264system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1265system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) 1266system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1267system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1268system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) 1269system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1267system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) | 1270system.iobus.reqLayer2.occupancy 338500 # Layer occupancy (ticks) |
| 1268system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1269system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) 1270system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1271system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 1272system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1273system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) 1274system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1271system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1272system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) 1273system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1274system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 1275system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1276system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) 1277system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1275system.iobus.reqLayer8.occupancy 643000 # Layer occupancy (ticks) | 1278system.iobus.reqLayer8.occupancy 642000 # Layer occupancy (ticks) |
| 1276system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1277system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1278system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1279system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 1280system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1281system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 1282system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1283system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1289system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 1290system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1291system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1292system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1293system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1294system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1295system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 1296system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1279system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1280system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1281system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1282system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 1283system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1284system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 1285system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1286system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1292system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 1293system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1294system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1295system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1296system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1297system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1298system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 1299system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1297system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) | 1300system.iobus.reqLayer23.occupancy 6273000 # Layer occupancy (ticks) |
| 1298system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) 1300system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1301system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1302system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) 1303system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1301system.iobus.reqLayer25.occupancy 187079512 # Layer occupancy (ticks) | 1304system.iobus.reqLayer25.occupancy 187671849 # Layer occupancy (ticks) |
| 1302system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1303system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1304system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1305system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1306system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1307system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1305system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) | 1308system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) |
| 1306system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1309system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1307system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1308system.iocache.tags.replacements 36418 # number of replacements 1309system.iocache.tags.tagsinuse 1.084047 # Cycle average of tags in use | 1310system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1311system.iocache.tags.replacements 36424 # number of replacements 1312system.iocache.tags.tagsinuse 1.078594 # Cycle average of tags in use |
| 1310system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1313system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1311system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. | 1314system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. |
| 1312system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1315system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1313system.iocache.tags.warmup_cycle 313815669000 # Cycle when the warmup percentage was hit. 1314system.iocache.tags.occ_blocks::realview.ide 1.084047 # Average occupied blocks per requestor 1315system.iocache.tags.occ_percent::realview.ide 0.067753 # Average percentage of cache occupancy 1316system.iocache.tags.occ_percent::total 0.067753 # Average percentage of cache occupancy | 1316system.iocache.tags.warmup_cycle 309373303000 # Cycle when the warmup percentage was hit. 1317system.iocache.tags.occ_blocks::realview.ide 1.078594 # Average occupied blocks per requestor 1318system.iocache.tags.occ_percent::realview.ide 0.067412 # Average percentage of cache occupancy 1319system.iocache.tags.occ_percent::total 0.067412 # Average percentage of cache occupancy |
| 1317system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1318system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1319system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1320system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1321system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1322system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1320system.iocache.tags.tag_accesses 328068 # Number of tag accesses 1321system.iocache.tags.data_accesses 328068 # Number of data accesses 1322system.iocache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1323system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses 1324system.iocache.ReadReq_misses::total 228 # number of ReadReq misses | 1323system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1324system.iocache.tags.data_accesses 328122 # Number of data accesses 1325system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1326system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1327system.iocache.ReadReq_misses::total 234 # number of ReadReq misses |
| 1325system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1326system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses | 1328system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1329system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
| 1327system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses 1328system.iocache.demand_misses::total 36452 # number of demand (read+write) misses 1329system.iocache.overall_misses::realview.ide 36452 # number of overall misses 1330system.iocache.overall_misses::total 36452 # number of overall misses 1331system.iocache.ReadReq_miss_latency::realview.ide 30010377 # number of ReadReq miss cycles 1332system.iocache.ReadReq_miss_latency::total 30010377 # number of ReadReq miss cycles 1333system.iocache.WriteLineReq_miss_latency::realview.ide 4549130135 # number of WriteLineReq miss cycles 1334system.iocache.WriteLineReq_miss_latency::total 4549130135 # number of WriteLineReq miss cycles 1335system.iocache.demand_miss_latency::realview.ide 4579140512 # number of demand (read+write) miss cycles 1336system.iocache.demand_miss_latency::total 4579140512 # number of demand (read+write) miss cycles 1337system.iocache.overall_miss_latency::realview.ide 4579140512 # number of overall miss cycles 1338system.iocache.overall_miss_latency::total 4579140512 # number of overall miss cycles 1339system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) 1340system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) | 1330system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1331system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1332system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1333system.iocache.overall_misses::total 36458 # number of overall misses 1334system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles 1335system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles 1336system.iocache.WriteLineReq_miss_latency::realview.ide 4278807472 # number of WriteLineReq miss cycles 1337system.iocache.WriteLineReq_miss_latency::total 4278807472 # number of WriteLineReq miss cycles 1338system.iocache.demand_miss_latency::realview.ide 4307704849 # number of demand (read+write) miss cycles 1339system.iocache.demand_miss_latency::total 4307704849 # number of demand (read+write) miss cycles 1340system.iocache.overall_miss_latency::realview.ide 4307704849 # number of overall miss cycles 1341system.iocache.overall_miss_latency::total 4307704849 # number of overall miss cycles 1342system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1343system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) |
| 1341system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1342system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) | 1344system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1345system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
| 1343system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses 1344system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses 1345system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses 1346system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses | 1346system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1347system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1348system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1349system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses |
| 1347system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1348system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1349system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1350system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1351system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1352system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1353system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1354system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1350system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1351system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1352system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1353system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1354system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1355system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1356system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1357system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1355system.iocache.ReadReq_avg_miss_latency::realview.ide 131624.460526 # average ReadReq miss latency 1356system.iocache.ReadReq_avg_miss_latency::total 131624.460526 # average ReadReq miss latency 1357system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.318656 # average WriteLineReq miss latency 1358system.iocache.WriteLineReq_avg_miss_latency::total 125583.318656 # average WriteLineReq miss latency 1359system.iocache.demand_avg_miss_latency::realview.ide 125621.104795 # average overall miss latency 1360system.iocache.demand_avg_miss_latency::total 125621.104795 # average overall miss latency 1361system.iocache.overall_avg_miss_latency::realview.ide 125621.104795 # average overall miss latency 1362system.iocache.overall_avg_miss_latency::total 125621.104795 # average overall miss latency | 1358system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency 1359system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency 1360system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311 # average WriteLineReq miss latency 1361system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311 # average WriteLineReq miss latency 1362system.iocache.demand_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency 1363system.iocache.demand_avg_miss_latency::total 118155.270421 # average overall miss latency 1364system.iocache.overall_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency 1365system.iocache.overall_avg_miss_latency::total 118155.270421 # average overall miss latency |
| 1363system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1364system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1365system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1366system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1367system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1368system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1369system.iocache.writebacks::writebacks 36190 # number of writebacks 1370system.iocache.writebacks::total 36190 # number of writebacks | 1366system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1367system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1368system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1369system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1370system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1371system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1372system.iocache.writebacks::writebacks 36190 # number of writebacks 1373system.iocache.writebacks::total 36190 # number of writebacks |
| 1371system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses 1372system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses | 1374system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1375system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses |
| 1373system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1374system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses | 1376system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1377system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses |
| 1375system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses 1376system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses 1377system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses 1378system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses 1379system.iocache.ReadReq_mshr_miss_latency::realview.ide 18610377 # number of ReadReq MSHR miss cycles 1380system.iocache.ReadReq_mshr_miss_latency::total 18610377 # number of ReadReq MSHR miss cycles 1381system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736516617 # number of WriteLineReq MSHR miss cycles 1382system.iocache.WriteLineReq_mshr_miss_latency::total 2736516617 # number of WriteLineReq MSHR miss cycles 1383system.iocache.demand_mshr_miss_latency::realview.ide 2755126994 # number of demand (read+write) MSHR miss cycles 1384system.iocache.demand_mshr_miss_latency::total 2755126994 # number of demand (read+write) MSHR miss cycles 1385system.iocache.overall_mshr_miss_latency::realview.ide 2755126994 # number of overall MSHR miss cycles 1386system.iocache.overall_mshr_miss_latency::total 2755126994 # number of overall MSHR miss cycles | 1378system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1379system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1380system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1381system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses 1382system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles 1383system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles 1384system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465502723 # number of WriteLineReq MSHR miss cycles 1385system.iocache.WriteLineReq_mshr_miss_latency::total 2465502723 # number of WriteLineReq MSHR miss cycles 1386system.iocache.demand_mshr_miss_latency::realview.ide 2482700100 # number of demand (read+write) MSHR miss cycles 1387system.iocache.demand_mshr_miss_latency::total 2482700100 # number of demand (read+write) MSHR miss cycles 1388system.iocache.overall_mshr_miss_latency::realview.ide 2482700100 # number of overall MSHR miss cycles 1389system.iocache.overall_mshr_miss_latency::total 2482700100 # number of overall MSHR miss cycles |
| 1387system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1388system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1389system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1390system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1391system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1392system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1393system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1394system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1390system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1391system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1392system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1393system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1394system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1395system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1396system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1397system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1395system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81624.460526 # average ReadReq mshr miss latency 1396system.iocache.ReadReq_avg_mshr_miss_latency::total 81624.460526 # average ReadReq mshr miss latency 1397system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.297068 # average WriteLineReq mshr miss latency 1398system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.297068 # average WriteLineReq mshr miss latency 1399system.iocache.demand_avg_mshr_miss_latency::realview.ide 75582.327280 # average overall mshr miss latency 1400system.iocache.demand_avg_mshr_miss_latency::total 75582.327280 # average overall mshr miss latency 1401system.iocache.overall_avg_mshr_miss_latency::realview.ide 75582.327280 # average overall mshr miss latency 1402system.iocache.overall_avg_mshr_miss_latency::total 75582.327280 # average overall mshr miss latency 1403system.membus.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 1398system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency 1399system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency 1400system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595 # average WriteLineReq mshr miss latency 1401system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595 # average WriteLineReq mshr miss latency 1402system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency 1403system.iocache.demand_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency 1404system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency 1405system.iocache.overall_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency 1406system.membus.snoop_filter.tot_requests 321817 # Total number of requests made to the snoop filter. 1407system.membus.snoop_filter.hit_single_requests 130498 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1408system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1409system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1410system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1411system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1412system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 1404system.membus.trans_dist::ReadReq 40160 # Transaction distribution | 1413system.membus.trans_dist::ReadReq 40160 # Transaction distribution |
| 1405system.membus.trans_dist::ReadResp 70545 # Transaction distribution | 1414system.membus.trans_dist::ReadResp 70519 # Transaction distribution |
| 1406system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1407system.membus.trans_dist::WriteResp 27589 # Transaction distribution | 1415system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1416system.membus.trans_dist::WriteResp 27589 # Transaction distribution |
| 1408system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution 1409system.membus.trans_dist::CleanEvict 6609 # Transaction distribution 1410system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution | 1417system.membus.trans_dist::WritebackDirty 119043 # Transaction distribution 1418system.membus.trans_dist::CleanEvict 6845 # Transaction distribution 1419system.membus.trans_dist::UpgradeReq 128 # Transaction distribution |
| 1411system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1412system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1420system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1421system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1413system.membus.trans_dist::ReadExReq 127161 # Transaction distribution 1414system.membus.trans_dist::ReadExResp 127161 # Transaction distribution 1415system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution | 1422system.membus.trans_dist::ReadExReq 129207 # Transaction distribution 1423system.membus.trans_dist::ReadExResp 129207 # Transaction distribution 1424system.membus.trans_dist::ReadSharedReq 30359 # Transaction distribution |
| 1416system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1417system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1418system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1419system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) | 1425system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1426system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1427system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1428system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) |
| 1420system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 434329 # Packet count per connected master and slave (bytes) 1421system.membus.pkt_count_system.cpu.l2cache.mem_side::total 541921 # Packet count per connected master and slave (bytes) 1422system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) 1423system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) 1424system.membus.pkt_count::total 614806 # Packet count per connected master and slave (bytes) | 1429system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 435887 # Packet count per connected master and slave (bytes) 1430system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543479 # Packet count per connected master and slave (bytes) 1431system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1432system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) 1433system.membus.pkt_count::total 616376 # Packet count per connected master and slave (bytes) |
| 1425system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1426system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1427system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) | 1434system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1435system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1436system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) |
| 1428system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes) 1429system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes) | 1437system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15537980 # Cumulative packet size per connected master and slave (bytes) 1438system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15701333 # Cumulative packet size per connected master and slave (bytes) |
| 1430system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1431system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) | 1439system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1440system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) |
| 1432system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes) 1433system.membus.snoops 492 # Total snoops (count) 1434system.membus.snoopTraffic 31360 # Total snoop traffic (bytes) 1435system.membus.snoop_fanout::samples 390007 # Request fanout histogram 1436system.membus.snoop_fanout::mean 1 # Request fanout histogram 1437system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1441system.membus.pkt_size::total 18018453 # Cumulative packet size per connected master and slave (bytes) 1442system.membus.snoops 498 # Total snoops (count) 1443system.membus.snoopTraffic 31744 # Total snoop traffic (bytes) 1444system.membus.snoop_fanout::samples 263669 # Request fanout histogram 1445system.membus.snoop_fanout::mean 0.018793 # Request fanout histogram 1446system.membus.snoop_fanout::stdev 0.135792 # Request fanout histogram |
| 1438system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1447system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1439system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1440system.membus.snoop_fanout::1 390007 100.00% 100.00% # Request fanout histogram | 1448system.membus.snoop_fanout::0 258714 98.12% 98.12% # Request fanout histogram 1449system.membus.snoop_fanout::1 4955 1.88% 100.00% # Request fanout histogram |
| 1441system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1442system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1450system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1451system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1443system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1452system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1444system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1453system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1445system.membus.snoop_fanout::total 390007 # Request fanout histogram 1446system.membus.reqLayer0.occupancy 90458000 # Layer occupancy (ticks) | 1454system.membus.snoop_fanout::total 263669 # Request fanout histogram 1455system.membus.reqLayer0.occupancy 90449000 # Layer occupancy (ticks) |
| 1447system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1448system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1449system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1456system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1457system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1458system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1450system.membus.reqLayer2.occupancy 1730000 # Layer occupancy (ticks) | 1459system.membus.reqLayer2.occupancy 1734500 # Layer occupancy (ticks) |
| 1451system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1460system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1452system.membus.reqLayer5.occupancy 823140613 # Layer occupancy (ticks) | 1461system.membus.reqLayer5.occupancy 828323280 # Layer occupancy (ticks) |
| 1453system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1462system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1454system.membus.respLayer2.occupancy 943221250 # Layer occupancy (ticks) | 1463system.membus.respLayer2.occupancy 954014500 # Layer occupancy (ticks) |
| 1455system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1464system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1456system.membus.respLayer3.occupancy 1186373 # Layer occupancy (ticks) | 1465system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) |
| 1457system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1466system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1458system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1459system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1460system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1461system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1462system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1463system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1464system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 1467system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1468system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1469system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1470system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1471system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1472system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1473system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 1465system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1466system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1467system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1468system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1469system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1470system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1474system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1475system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1476system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1477system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1478system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1479system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1471system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1472system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 1480system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1481system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 1473system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1474system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1475system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1476system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1477system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1478system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1479system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1480system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1496system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1497system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1498system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1499system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1500system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1501system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1502system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1503system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1482system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1483system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1484system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1485system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1486system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1487system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1488system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1489system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1505system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1506system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1507system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1508system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1509system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1510system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1511system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1512system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1504system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1505system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1506system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1507system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1508system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1509system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1510system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 1513system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1514system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1515system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1516system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1517system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1518system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1519system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 1511system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1512system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1513system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1514system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1520system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1521system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1522system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1523system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1515system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1516system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1517system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1518system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1519system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1520system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1521system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1522system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1523system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1524system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1525system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states 1526system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states | 1524system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1525system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1526system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1527system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1528system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1529system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1530system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1531system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1532system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1533system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1534system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states 1535system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states |
| 1527 1528---------- End Simulation Statistics ---------- | 1536 1537---------- End Simulation Statistics ---------- |