Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

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1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 987334 # Simulator instruction rate (inst/s) 8host_op_rate 1190416 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25545157236 # Simulator tick rate (ticks/s) 10host_mem_usage 619552 # Number of bytes of host memory used 11host_seconds 113.90 # Real time elapsed on the host	7host_inst_rate 567099 # Simulator instruction rate (inst/s) 8host_op_rate 683745 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14672489619 # Simulator tick rate (ticks/s) 10host_mem_usage 579808 # Number of bytes of host memory used 11host_seconds 198.30 # Real time elapsed on the host
12sim_insts 112457035 # Number of instructions simulated 13sim_ops 135588119 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory --- 379 unchanged lines hidden (view full) --- 399system.cpu.dtb.read_hits 24520656 # DTB read hits 400system.cpu.dtb.read_misses 8124 # DTB read misses 401system.cpu.dtb.write_hits 19606817 # DTB write hits 402system.cpu.dtb.write_misses 1422 # DTB write misses 403system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 404system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 405system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 406system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	12sim_insts 112457035 # Number of instructions simulated 13sim_ops 135588119 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory --- 379 unchanged lines hidden (view full) --- 399system.cpu.dtb.read_hits 24520656 # DTB read hits 400system.cpu.dtb.read_misses 8124 # DTB read misses 401system.cpu.dtb.write_hits 19606817 # DTB write hits 402system.cpu.dtb.write_misses 1422 # DTB write misses 403system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 404system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 405system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 406system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
407system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB	407system.cpu.dtb.flush_entries 4208 # Number of entries that have been flushed from TLB
408system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 409system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch 410system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 412system.cpu.dtb.read_accesses 24528780 # DTB read accesses 413system.cpu.dtb.write_accesses 19608239 # DTB write accesses 414system.cpu.dtb.inst_accesses 0 # ITB inst accesses 415system.cpu.dtb.hits 44127473 # DTB hits --- 63 unchanged lines hidden (view full) --- 479system.cpu.itb.read_hits 0 # DTB read hits 480system.cpu.itb.read_misses 0 # DTB read misses 481system.cpu.itb.write_hits 0 # DTB write hits 482system.cpu.itb.write_misses 0 # DTB write misses 483system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 484system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 485system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 486system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	408system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 409system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch 410system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 412system.cpu.dtb.read_accesses 24528780 # DTB read accesses 413system.cpu.dtb.write_accesses 19608239 # DTB write accesses 414system.cpu.dtb.inst_accesses 0 # ITB inst accesses 415system.cpu.dtb.hits 44127473 # DTB hits --- 63 unchanged lines hidden (view full) --- 479system.cpu.itb.read_hits 0 # DTB read hits 480system.cpu.itb.read_misses 0 # DTB read misses 481system.cpu.itb.write_hits 0 # DTB write hits 482system.cpu.itb.write_misses 0 # DTB write misses 483system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 484system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 485system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 486system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
487system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB	487system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
488system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 489system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 490system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 491system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 492system.cpu.itb.read_accesses 0 # DTB read accesses 493system.cpu.itb.write_accesses 0 # DTB write accesses 494system.cpu.itb.inst_accesses 115559021 # ITB inst accesses 495system.cpu.itb.hits 115554258 # DTB hits --- 1030 unchanged lines hidden ---	488system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 489system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 490system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 491system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 492system.cpu.itb.read_accesses 0 # DTB read accesses 493system.cpu.itb.write_accesses 0 # DTB write accesses 494system.cpu.itb.inst_accesses 115559021 # ITB inst accesses 495system.cpu.itb.hits 115554258 # DTB hits --- 1030 unchanged lines hidden ---