| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1061137 # Simulator instruction rate (inst/s) 8host_op_rate 1279400 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27454664075 # Simulator tick rate (ticks/s) 10host_mem_usage 618904 # Number of bytes of host memory used 11host_seconds 105.98 # Real time elapsed on the host | 7host_inst_rate 987334 # Simulator instruction rate (inst/s) 8host_op_rate 1190416 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25545157236 # Simulator tick rate (ticks/s) 10host_mem_usage 619552 # Number of bytes of host memory used 11host_seconds 113.90 # Real time elapsed on the host |
| 12sim_insts 112457035 # Number of instructions simulated 13sim_ops 135588119 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 112457035 # Number of instructions simulated 13sim_ops 135588119 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory --- 282 unchanged lines hidden (view full) --- 306system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ) 308system.physmem_1.averagePower 669.477277 # Core power per rank (mW) 309system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states 310system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 312system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory --- 282 unchanged lines hidden (view full) --- 307system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ) 308system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ) 309system.physmem_1.averagePower 669.477277 # Core power per rank (mW) 310system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states 311system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 315system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 314system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 315system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 316system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 317system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 318system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 319system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 320system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 325system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) | 316system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) |
| 328system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 329system.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 330system.bridge.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 326system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 327system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 328system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 329system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 330system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 331system.cf0.dma_write_txs 631 # Number of DMA write transactions. 332system.cpu_clk_domain.clock 500 # Clock period in ticks | 331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 333system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 334system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 335system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 336system.cf0.dma_write_txs 631 # Number of DMA write transactions. 337system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 338system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 333system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 334system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 354system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 355system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 356system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 357system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 358system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 359system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 360system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 361system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 339system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 340system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 360system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 363system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 364system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 365system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 366system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 367system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 368system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 362system.cpu.dtb.walker.walks 9546 # Table walker walks requested 363system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors 364system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate 365system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate 366system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency 367system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency 368system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency 369system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency --- 33 unchanged lines hidden (view full) --- 403system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 405system.cpu.dtb.read_accesses 24528780 # DTB read accesses 406system.cpu.dtb.write_accesses 19608239 # DTB write accesses 407system.cpu.dtb.inst_accesses 0 # ITB inst accesses 408system.cpu.dtb.hits 44127473 # DTB hits 409system.cpu.dtb.misses 9546 # DTB misses 410system.cpu.dtb.accesses 44137019 # DTB accesses | 369system.cpu.dtb.walker.walks 9546 # Table walker walks requested 370system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors 371system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate 372system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate 373system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency 374system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency 375system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency --- 33 unchanged lines hidden (view full) --- 410system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 412system.cpu.dtb.read_accesses 24528780 # DTB read accesses 413system.cpu.dtb.write_accesses 19608239 # DTB write accesses 414system.cpu.dtb.inst_accesses 0 # ITB inst accesses 415system.cpu.dtb.hits 44127473 # DTB hits 416system.cpu.dtb.misses 9546 # DTB misses 417system.cpu.dtb.accesses 44137019 # DTB accesses |
| 418system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 411system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 412system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 413system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 415system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 416system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 417system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 418system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 432system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 433system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 434system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 435system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 436system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 437system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 438system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 439system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 419system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 420system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 423system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 424system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 440system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 441system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 442system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 443system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 444system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 445system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 446system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 447system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 448system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 440system.cpu.itb.walker.walks 4763 # Table walker walks requested 441system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors 442system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate 443system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate 444system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency 445system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency 446system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency 447system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency --- 33 unchanged lines hidden (view full) --- 481system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 482system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 483system.cpu.itb.read_accesses 0 # DTB read accesses 484system.cpu.itb.write_accesses 0 # DTB write accesses 485system.cpu.itb.inst_accesses 115559021 # ITB inst accesses 486system.cpu.itb.hits 115554258 # DTB hits 487system.cpu.itb.misses 4763 # DTB misses 488system.cpu.itb.accesses 115559021 # DTB accesses | 449system.cpu.itb.walker.walks 4763 # Table walker walks requested 450system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors 451system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate 452system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate 453system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency 454system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency 455system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency 456system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency --- 33 unchanged lines hidden (view full) --- 490system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 491system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 492system.cpu.itb.read_accesses 0 # DTB read accesses 493system.cpu.itb.write_accesses 0 # DTB write accesses 494system.cpu.itb.inst_accesses 115559021 # ITB inst accesses 495system.cpu.itb.hits 115554258 # DTB hits 496system.cpu.itb.misses 4763 # DTB misses 497system.cpu.itb.accesses 115559021 # DTB accesses |
| 498system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 499system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state 500system.cpu.pwrStateClkGateDist::mean 886754793.248599 # Distribution of time spent in the clock gated state 501system.cpu.pwrStateClkGateDist::stdev 17463725759.115368 # Distribution of time spent in the clock gated state 502system.cpu.pwrStateClkGateDist::underflows 2967 97.82% 97.82% # Distribution of time spent in the clock gated state 503system.cpu.pwrStateClkGateDist::1000-5e+10 60 1.98% 99.80% # Distribution of time spent in the clock gated state 504system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 505system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 506system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 507system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 508system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 509system.cpu.pwrStateClkGateDist::max_value 499963874372 # Distribution of time spent in the clock gated state 510system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state 511system.cpu.pwrStateResidencyTicks::ON 220059549577 # Cumulative time (in ticks) in various power states 512system.cpu.pwrStateResidencyTicks::CLK_GATED 2689527287923 # Cumulative time (in ticks) in various power states |
|
| 489system.cpu.numCycles 5819173675 # number of cpu cycles simulated 490system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 491system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 492system.cpu.kern.inst.arm 0 # number of arm instructions executed 493system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 494system.cpu.committedInsts 112457035 # Number of instructions committed 495system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed 496system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 543system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 544system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 545system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 546system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction 547system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction 548system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 549system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 550system.cpu.op_class::total 138708215 # Class of executed instruction | 513system.cpu.numCycles 5819173675 # number of cpu cycles simulated 514system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 515system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 516system.cpu.kern.inst.arm 0 # number of arm instructions executed 517system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 518system.cpu.committedInsts 112457035 # Number of instructions committed 519system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed 520system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 567system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 568system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 569system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 570system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction 571system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction 572system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 573system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 574system.cpu.op_class::total 138708215 # Class of executed instruction |
| 575system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 551system.cpu.dcache.tags.replacements 819223 # number of replacements 552system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use 553system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks. 554system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. 555system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks. 556system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. 557system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 563system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id 564system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 566system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses 567system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses | 576system.cpu.dcache.tags.replacements 819223 # number of replacements 577system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use 578system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks. 579system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. 580system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks. 581system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. 582system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor 583system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy 584system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy 585system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses |
| 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 568system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits 569system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits 570system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits 571system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits 572system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits 573system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits 574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits 575system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits --- 150 unchanged lines hidden (view full) --- 726system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency 727system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency 728system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency 729system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency 730system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency 731system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency 732system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency 733system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency | 594system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits 598system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits 599system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits 600system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits 601system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits --- 150 unchanged lines hidden (view full) --- 752system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency 753system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency 754system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency 755system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency 756system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency 757system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency 758system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency 759system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency |
| 760system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 734system.cpu.icache.tags.replacements 1695721 # number of replacements 735system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use 736system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. 737system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks. 738system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks. 739system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. 740system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor 741system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy 742system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy 743system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 744system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 745system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 746system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id 747system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 748system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 749system.cpu.icache.tags.tag_accesses 117250497 # Number of tag accesses 750system.cpu.icache.tags.data_accesses 117250497 # Number of data accesses | 761system.cpu.icache.tags.replacements 1695721 # number of replacements 762system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use 763system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. 764system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks. 765system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks. 766system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. 767system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor 768system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy 769system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy 770system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 771system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 772system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 773system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id 774system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 775system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 776system.cpu.icache.tags.tag_accesses 117250497 # Number of tag accesses 777system.cpu.icache.tags.data_accesses 117250497 # Number of data accesses |
| 778system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 751system.cpu.icache.ReadReq_hits::cpu.inst 113858019 # number of ReadReq hits 752system.cpu.icache.ReadReq_hits::total 113858019 # number of ReadReq hits 753system.cpu.icache.demand_hits::cpu.inst 113858019 # number of demand (read+write) hits 754system.cpu.icache.demand_hits::total 113858019 # number of demand (read+write) hits 755system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits 756system.cpu.icache.overall_hits::total 113858019 # number of overall hits 757system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses 758system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 823system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 824system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency 827system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 828system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 829system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 830system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency | 779system.cpu.icache.ReadReq_hits::cpu.inst 113858019 # number of ReadReq hits 780system.cpu.icache.ReadReq_hits::total 113858019 # number of ReadReq hits 781system.cpu.icache.demand_hits::cpu.inst 113858019 # number of demand (read+write) hits 782system.cpu.icache.demand_hits::total 113858019 # number of demand (read+write) hits 783system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits 784system.cpu.icache.overall_hits::total 113858019 # number of overall hits 785system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses 786system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 851system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 852system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency 853system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 854system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency 855system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 856system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 857system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 858system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency |
| 859system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 831system.cpu.l2cache.tags.replacements 87565 # number of replacements 832system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use 833system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. 834system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. 835system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks. 836system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 837system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor 838system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 852system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 853system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id 854system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6851 # Occupied blocks per task id 855system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id 856system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 857system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id 858system.cpu.l2cache.tags.tag_accesses 40512344 # Number of tag accesses 859system.cpu.l2cache.tags.data_accesses 40512344 # Number of data accesses | 860system.cpu.l2cache.tags.replacements 87565 # number of replacements 861system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use 862system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. 863system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. 864system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks. 865system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 866system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor 867system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 881system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 882system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id 883system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6851 # Occupied blocks per task id 884system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id 885system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 886system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id 887system.cpu.l2cache.tags.tag_accesses 40512344 # Number of tag accesses 888system.cpu.l2cache.tags.data_accesses 40512344 # Number of data accesses |
| 889system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 860system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits 861system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits 862system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits 863system.cpu.l2cache.WritebackDirty_hits::writebacks 683846 # number of WritebackDirty hits 864system.cpu.l2cache.WritebackDirty_hits::total 683846 # number of WritebackDirty hits 865system.cpu.l2cache.WritebackClean_hits::writebacks 1664945 # number of WritebackClean hits 866system.cpu.l2cache.WritebackClean_hits::total 1664945 # number of WritebackClean hits 867system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits --- 254 unchanged lines hidden (view full) --- 1122system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency 1123system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency 1124system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. 1125system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1126system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1127system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. 1128system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1129system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 890system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits 891system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits 892system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits 893system.cpu.l2cache.WritebackDirty_hits::writebacks 683846 # number of WritebackDirty hits 894system.cpu.l2cache.WritebackDirty_hits::total 683846 # number of WritebackDirty hits 895system.cpu.l2cache.WritebackClean_hits::writebacks 1664945 # number of WritebackClean hits 896system.cpu.l2cache.WritebackClean_hits::total 1664945 # number of WritebackClean hits 897system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits --- 254 unchanged lines hidden (view full) --- 1152system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency 1153system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency 1154system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. 1155system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1156system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1157system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. 1158system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1159system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1160system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1130system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution 1132system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1133system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution 1134system.cpu.toL2Bus.trans_dist::WritebackDirty 801231 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::WritebackClean 1695721 # Transaction distribution 1136system.cpu.toL2Bus.trans_dist::CleanEvict 141985 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution --- 33 unchanged lines hidden (view full) --- 1171system.cpu.toL2Bus.respLayer0.occupancy 2553380500 # Layer occupancy (ticks) 1172system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1173system.cpu.toL2Bus.respLayer1.occupancy 1275954500 # Layer occupancy (ticks) 1174system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1175system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) 1176system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1177system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) 1178system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1161system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::WritebackDirty 801231 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::WritebackClean 1695721 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::CleanEvict 141985 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution --- 33 unchanged lines hidden (view full) --- 1202system.cpu.toL2Bus.respLayer0.occupancy 2553380500 # Layer occupancy (ticks) 1203system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1204system.cpu.toL2Bus.respLayer1.occupancy 1275954500 # Layer occupancy (ticks) 1205system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1206system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) 1207system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1208system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) 1209system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1210system.iobus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1179system.iobus.trans_dist::ReadReq 30177 # Transaction distribution 1180system.iobus.trans_dist::ReadResp 30177 # Transaction distribution 1181system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1182system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1183system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 1265system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) 1266system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1267system.iobus.reqLayer25.occupancy 187058527 # Layer occupancy (ticks) 1268system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1269system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1270system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1271system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) 1272system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1211system.iobus.trans_dist::ReadReq 30177 # Transaction distribution 1212system.iobus.trans_dist::ReadResp 30177 # Transaction distribution 1213system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1214system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1215system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 1297system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) 1298system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer25.occupancy 187058527 # Layer occupancy (ticks) 1300system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1301system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1302system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1303system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) 1304system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1305system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1273system.iocache.tags.replacements 36418 # number of replacements 1274system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use 1275system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1276system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. 1277system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1278system.iocache.tags.warmup_cycle 313812610000 # Cycle when the warmup percentage was hit. 1279system.iocache.tags.occ_blocks::realview.ide 1.084082 # Average occupied blocks per requestor 1280system.iocache.tags.occ_percent::realview.ide 0.067755 # Average percentage of cache occupancy 1281system.iocache.tags.occ_percent::total 0.067755 # Average percentage of cache occupancy 1282system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1283system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1284system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1285system.iocache.tags.tag_accesses 328068 # Number of tag accesses 1286system.iocache.tags.data_accesses 328068 # Number of data accesses | 1306system.iocache.tags.replacements 36418 # number of replacements 1307system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use 1308system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1309system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. 1310system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1311system.iocache.tags.warmup_cycle 313812610000 # Cycle when the warmup percentage was hit. 1312system.iocache.tags.occ_blocks::realview.ide 1.084082 # Average occupied blocks per requestor 1313system.iocache.tags.occ_percent::realview.ide 0.067755 # Average percentage of cache occupancy 1314system.iocache.tags.occ_percent::total 0.067755 # Average percentage of cache occupancy 1315system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1316system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1317system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1318system.iocache.tags.tag_accesses 328068 # Number of tag accesses 1319system.iocache.tags.data_accesses 328068 # Number of data accesses |
| 1320system.iocache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1287system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses 1288system.iocache.ReadReq_misses::total 228 # number of ReadReq misses 1289system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1290system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1291system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses 1292system.iocache.demand_misses::total 36452 # number of demand (read+write) misses 1293system.iocache.overall_misses::realview.ide 36452 # number of overall misses 1294system.iocache.overall_misses::total 36452 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1359system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency 1360system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency 1361system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency 1362system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency 1363system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1364system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency 1365system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1366system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency | 1321system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses 1322system.iocache.ReadReq_misses::total 228 # number of ReadReq misses 1323system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1324system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1325system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses 1326system.iocache.demand_misses::total 36452 # number of demand (read+write) misses 1327system.iocache.overall_misses::realview.ide 36452 # number of overall misses 1328system.iocache.overall_misses::total 36452 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1393system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency 1394system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency 1395system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency 1396system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency 1397system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1398system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency 1399system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1400system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency |
| 1401system.membus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1367system.membus.trans_dist::ReadReq 40160 # Transaction distribution 1368system.membus.trans_dist::ReadResp 70548 # Transaction distribution 1369system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1370system.membus.trans_dist::WriteResp 27589 # Transaction distribution 1371system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution 1372system.membus.trans_dist::CleanEvict 6608 # Transaction distribution 1373system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution 1374system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1412system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks) 1413system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1414system.membus.reqLayer5.occupancy 823136860 # Layer occupancy (ticks) 1415system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1416system.membus.respLayer2.occupancy 943248500 # Layer occupancy (ticks) 1417system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1418system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks) 1419system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1402system.membus.trans_dist::ReadReq 40160 # Transaction distribution 1403system.membus.trans_dist::ReadResp 70548 # Transaction distribution 1404system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1405system.membus.trans_dist::WriteResp 27589 # Transaction distribution 1406system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution 1407system.membus.trans_dist::CleanEvict 6608 # Transaction distribution 1408system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution 1409system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1447system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks) 1448system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1449system.membus.reqLayer5.occupancy 823136860 # Layer occupancy (ticks) 1450system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1451system.membus.respLayer2.occupancy 943248500 # Layer occupancy (ticks) 1452system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1453system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks) 1454system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1455system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1456system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1457system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1458system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1459system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1460system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1461system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1420system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1421system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1422system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1423system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1424system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1425system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1462system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1463system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1464system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1465system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1466system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1467system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1468system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1469system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1426system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1427system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1428system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1429system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1430system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1431system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1432system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1433system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1449system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1450system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1451system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1452system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1453system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1454system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1455system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1456system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1470system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1471system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1472system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1473system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1474system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1475system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1476system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1477system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1493system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1494system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1495system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1496system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1497system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1498system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1499system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1500system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1501system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1502system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1503system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1504system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1505system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1506system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1507system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1457system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1458system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1459system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1460system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1508system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1509system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1510system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1511system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1512system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1513system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1514system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1515system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1516system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1517system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1518system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1519system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1520system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1521system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1522system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states 1523system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states |
|
| 1461 1462---------- End Simulation Statistics ---------- | 1524 1525---------- End Simulation Statistics ---------- |