| stats.txt (11502:e273e86a873d) | stats.txt (11507:be6065c1d8d2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 581636 # Simulator instruction rate (inst/s) 8host_op_rate 701272 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15048595995 # Simulator tick rate (ticks/s) 10host_mem_usage 573724 # Number of bytes of host memory used 11host_seconds 193.35 # Real time elapsed on the host 12sim_insts 112457033 # Number of instructions simulated 13sim_ops 135588117 # Number of ops (including micro ops) simulated | 7host_inst_rate 495886 # Simulator instruction rate (inst/s) 8host_op_rate 597884 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12830006266 # Simulator tick rate (ticks/s) 10host_mem_usage 573732 # Number of bytes of host memory used 11host_seconds 226.78 # Real time elapsed on the host 12sim_insts 112457035 # Number of instructions simulated 13sim_ops 135588119 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory --- 234 unchanged lines hidden (view full) --- 256system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::140-143 1 0.02% 99.75% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::144-147 7 0.12% 99.88% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory --- 234 unchanged lines hidden (view full) --- 256system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::140-143 1 0.02% 99.75% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::144-147 7 0.12% 99.88% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads |
| 264system.physmem.totQLat 1624802000 # Total ticks spent queuing 265system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM | 264system.physmem.totQLat 1624800000 # Total ticks spent queuing 265system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM |
| 266system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers | 266system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers |
| 267system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst | 267system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst |
| 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 269system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst | 269system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst |
| 270system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.05 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes --- 19 unchanged lines hidden (view full) --- 297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 298system.physmem_0.memoryStateTime::ACT 40208512500 # Time in different power states 299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 300system.physmem_1.actEnergy 213260040 # Energy for activate commands per rank (pJ) 301system.physmem_1.preEnergy 116362125 # Energy for precharge commands per rank (pJ) 302system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) 303system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) 304system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) | 270system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.05 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes --- 19 unchanged lines hidden (view full) --- 297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 298system.physmem_0.memoryStateTime::ACT 40208512500 # Time in different power states 299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 300system.physmem_1.actEnergy 213260040 # Energy for activate commands per rank (pJ) 301system.physmem_1.preEnergy 116362125 # Energy for precharge commands per rank (pJ) 302system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) 303system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) 304system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) |
| 305system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ) 306system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ) | 305system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ) 306system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ) |
| 308system.physmem_1.averagePower 669.477277 # Core power per rank (mW) | 308system.physmem_1.averagePower 669.477277 # Core power per rank (mW) |
| 309system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states | 309system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states |
| 310system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 310system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 312system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states | 312system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states |
| 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 314system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 315system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 316system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 317system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 318system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 319system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 320system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) --- 63 unchanged lines hidden (view full) --- 384system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst 386system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst 387system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst 389system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst 390system.cpu.dtb.inst_hits 0 # ITB inst hits 391system.cpu.dtb.inst_misses 0 # ITB inst misses | 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 314system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 315system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 316system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 317system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 318system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 319system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 320system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) --- 63 unchanged lines hidden (view full) --- 384system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst 386system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst 387system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst 389system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst 390system.cpu.dtb.inst_hits 0 # ITB inst hits 391system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 392system.cpu.dtb.read_hits 24520655 # DTB read hits | 392system.cpu.dtb.read_hits 24520656 # DTB read hits |
| 393system.cpu.dtb.read_misses 8124 # DTB read misses | 393system.cpu.dtb.read_misses 8124 # DTB read misses |
| 394system.cpu.dtb.write_hits 19606816 # DTB write hits | 394system.cpu.dtb.write_hits 19606817 # DTB write hits |
| 395system.cpu.dtb.write_misses 1422 # DTB write misses 396system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 397system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 398system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 399system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 400system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB 401system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 402system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch 403system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions | 395system.cpu.dtb.write_misses 1422 # DTB write misses 396system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 397system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 398system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 399system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 400system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB 401system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 402system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch 403system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions |
| 405system.cpu.dtb.read_accesses 24528779 # DTB read accesses 406system.cpu.dtb.write_accesses 19608238 # DTB write accesses | 405system.cpu.dtb.read_accesses 24528780 # DTB read accesses 406system.cpu.dtb.write_accesses 19608239 # DTB write accesses |
| 407system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 407system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 408system.cpu.dtb.hits 44127471 # DTB hits | 408system.cpu.dtb.hits 44127473 # DTB hits |
| 409system.cpu.dtb.misses 9546 # DTB misses | 409system.cpu.dtb.misses 9546 # DTB misses |
| 410system.cpu.dtb.accesses 44137017 # DTB accesses | 410system.cpu.dtb.accesses 44137019 # DTB accesses |
| 411system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 412system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 413system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 415system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 416system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 417system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 418system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 67 unchanged lines hidden (view full) --- 486system.cpu.itb.hits 115554258 # DTB hits 487system.cpu.itb.misses 4763 # DTB misses 488system.cpu.itb.accesses 115559021 # DTB accesses 489system.cpu.numCycles 5819173675 # number of cpu cycles simulated 490system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 491system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 492system.cpu.kern.inst.arm 0 # number of arm instructions executed 493system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed | 411system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 412system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 413system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 415system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 416system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 417system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 418system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 67 unchanged lines hidden (view full) --- 486system.cpu.itb.hits 115554258 # DTB hits 487system.cpu.itb.misses 4763 # DTB misses 488system.cpu.itb.accesses 115559021 # DTB accesses 489system.cpu.numCycles 5819173675 # number of cpu cycles simulated 490system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 491system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 492system.cpu.kern.inst.arm 0 # number of arm instructions executed 493system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed |
| 494system.cpu.committedInsts 112457033 # Number of instructions committed 495system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed | 494system.cpu.committedInsts 112457035 # Number of instructions committed 495system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed |
| 496system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses 497system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 498system.cpu.num_func_calls 9892146 # number of times a function call or return occured 499system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls 500system.cpu.num_int_insts 119893391 # number of integer instructions 501system.cpu.num_fp_insts 11161 # number of float instructions | 496system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses 497system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 498system.cpu.num_func_calls 9892146 # number of times a function call or return occured 499system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls 500system.cpu.num_int_insts 119893391 # number of integer instructions 501system.cpu.num_fp_insts 11161 # number of float instructions |
| 502system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read 503system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written | 502system.cpu.num_int_register_reads 218063466 # number of times the integer registers were read 503system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written |
| 504system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 505system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written | 504system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 505system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written |
| 506system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read | 506system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read |
| 507system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written 508system.cpu.num_mem_refs 45407924 # number of memory refs 509system.cpu.num_load_insts 24843119 # Number of load instructions 510system.cpu.num_store_insts 20564805 # Number of store instructions 511system.cpu.num_idle_cycles 5379054575.844151 # Number of idle cycles 512system.cpu.num_busy_cycles 440119099.155849 # Number of busy cycles 513system.cpu.not_idle_fraction 0.075633 # Percentage of non-idle cycles 514system.cpu.idle_fraction 0.924367 # Percentage of idle cycles --- 30 unchanged lines hidden (view full) --- 545system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 546system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction 547system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction 548system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 549system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 550system.cpu.op_class::total 138708215 # Class of executed instruction 551system.cpu.dcache.tags.replacements 819223 # number of replacements 552system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use | 507system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written 508system.cpu.num_mem_refs 45407924 # number of memory refs 509system.cpu.num_load_insts 24843119 # Number of load instructions 510system.cpu.num_store_insts 20564805 # Number of store instructions 511system.cpu.num_idle_cycles 5379054575.844151 # Number of idle cycles 512system.cpu.num_busy_cycles 440119099.155849 # Number of busy cycles 513system.cpu.not_idle_fraction 0.075633 # Percentage of non-idle cycles 514system.cpu.idle_fraction 0.924367 # Percentage of idle cycles --- 30 unchanged lines hidden (view full) --- 545system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 546system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction 547system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction 548system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 549system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 550system.cpu.op_class::total 138708215 # Class of executed instruction 551system.cpu.dcache.tags.replacements 819223 # number of replacements 552system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use |
| 553system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks. | 553system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks. |
| 554system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. | 554system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. |
| 555system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks. | 555system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks. |
| 556system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. 557system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 563system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id 564system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 556system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. 557system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 563system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id 564system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 566system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses 567system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses 568system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits 569system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits 570system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits 571system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits | 566system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses 567system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses 568system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits 569system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits 570system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits 571system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits |
| 572system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits 573system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits 574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits 575system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits 576system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits 577system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits | 572system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits 573system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits 574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits 575system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits 576system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits 577system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits |
| 578system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits 579system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits 580system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits 581system.cpu.dcache.overall_hits::total 42329995 # number of overall hits | 578system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits 579system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits 580system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits 581system.cpu.dcache.overall_hits::total 42329997 # number of overall hits |
| 582system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses 583system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses 584system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses 585system.cpu.dcache.WriteReq_misses::total 298709 # number of WriteReq misses 586system.cpu.dcache.SoftPFReq_misses::cpu.data 118381 # number of SoftPFReq misses 587system.cpu.dcache.SoftPFReq_misses::total 118381 # number of SoftPFReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 22756 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses --- 10 unchanged lines hidden (view full) --- 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293896000 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 293896000 # number of LoadLockedReq miss cycles 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles | 582system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses 583system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses 584system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses 585system.cpu.dcache.WriteReq_misses::total 298709 # number of WriteReq misses 586system.cpu.dcache.SoftPFReq_misses::cpu.data 118381 # number of SoftPFReq misses 587system.cpu.dcache.SoftPFReq_misses::total 118381 # number of SoftPFReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 22756 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses --- 10 unchanged lines hidden (view full) --- 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293896000 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 293896000 # number of LoadLockedReq miss cycles 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles |
| 608system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses) | 608system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses) |
| 612system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) 613system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) 614system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) 615system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) 616system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) 617system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) | 612system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) 613system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) 614system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) 615system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) 616system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) 617system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) |
| 618system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses 619system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses 620system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses 621system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses | 618system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses 619system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses 620system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses 621system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses |
| 622system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses 623system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses 624system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses 625system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses 626system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231590 # miss rate for SoftPFReq accesses 627system.cpu.dcache.SoftPFReq_miss_rate::total 0.231590 # miss rate for SoftPFReq accesses 628system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048832 # miss rate for LoadLockedReq accesses 629system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048832 # miss rate for LoadLockedReq accesses --- 125 unchanged lines hidden (view full) --- 755system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits 756system.cpu.icache.overall_hits::total 113858019 # number of overall hits 757system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses 758system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses 759system.cpu.icache.demand_misses::cpu.inst 1696239 # number of demand (read+write) misses 760system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses 761system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses 762system.cpu.icache.overall_misses::total 1696239 # number of overall misses | 622system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses 623system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses 624system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses 625system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses 626system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231590 # miss rate for SoftPFReq accesses 627system.cpu.dcache.SoftPFReq_miss_rate::total 0.231590 # miss rate for SoftPFReq accesses 628system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048832 # miss rate for LoadLockedReq accesses 629system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048832 # miss rate for LoadLockedReq accesses --- 125 unchanged lines hidden (view full) --- 755system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits 756system.cpu.icache.overall_hits::total 113858019 # number of overall hits 757system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses 758system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses 759system.cpu.icache.demand_misses::cpu.inst 1696239 # number of demand (read+write) misses 760system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses 761system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses 762system.cpu.icache.overall_misses::total 1696239 # number of overall misses |
| 763system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles 764system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles 765system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles 766system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles 767system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles 768system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles | 763system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles 764system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles 765system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles 766system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles 767system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles 768system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles |
| 769system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses) 770system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses) 771system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses 772system.cpu.icache.demand_accesses::total 115554258 # number of demand (read+write) accesses 773system.cpu.icache.overall_accesses::cpu.inst 115554258 # number of overall (read+write) accesses 774system.cpu.icache.overall_accesses::total 115554258 # number of overall (read+write) accesses 775system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014679 # miss rate for ReadReq accesses 776system.cpu.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses 777system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 # miss rate for demand accesses 778system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses 779system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses 780system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses | 769system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses) 770system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses) 771system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses 772system.cpu.icache.demand_accesses::total 115554258 # number of demand (read+write) accesses 773system.cpu.icache.overall_accesses::cpu.inst 115554258 # number of overall (read+write) accesses 774system.cpu.icache.overall_accesses::total 115554258 # number of overall (read+write) accesses 775system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014679 # miss rate for ReadReq accesses 776system.cpu.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses 777system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 # miss rate for demand accesses 778system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses 779system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses 780system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses |
| 781system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency 782system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency 783system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency 784system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency 785system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency 786system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency | 781system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency 782system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency 783system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency 784system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency 785system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency 786system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency |
| 787system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 793system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks 794system.cpu.icache.writebacks::total 1695721 # number of writebacks 795system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses 796system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses 797system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses 798system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses 799system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses 800system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses 801system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 802system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 803system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 804system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses | 787system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 793system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks 794system.cpu.icache.writebacks::total 1695721 # number of writebacks 795system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses 796system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses 797system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses 798system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses 799system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses 800system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses 801system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 802system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 803system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 804system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses |
| 805system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles 806system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles 807system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles 808system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles 809system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles 810system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles | 805system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles 806system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles 807system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles 808system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles 809system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles 810system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles |
| 811system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles 812system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles 813system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles 814system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles 815system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for ReadReq accesses 816system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses 817system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for demand accesses 818system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses 819system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses 820system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses | 811system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles 812system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles 813system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles 814system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles 815system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for ReadReq accesses 816system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses 817system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for demand accesses 818system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses 819system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses 820system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses |
| 821system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency 822system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency 823system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency 824system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency | 821system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency 822system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency 823system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 824system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency |
| 827system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 828system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 829system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 830system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency 831system.cpu.l2cache.tags.replacements 87565 # number of replacements 832system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use 833system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. 834system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. --- 74 unchanged lines hidden (view full) --- 909system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles 910system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles 911system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles 912system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles 913system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles 914system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles 915system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles 916system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles | 827system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 828system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 829system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 830system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency 831system.cpu.l2cache.tags.replacements 87565 # number of replacements 832system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use 833system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. 834system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. --- 74 unchanged lines hidden (view full) --- 909system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles 910system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles 911system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles 912system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles 913system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles 914system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles 915system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles 916system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles |
| 917system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles 918system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles | 917system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles 918system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles |
| 919system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles 920system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles 921system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles 922system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles | 919system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles 920system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles 921system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles 922system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles |
| 923system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles | 923system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles |
| 924system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles | 924system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles |
| 925system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles | 925system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles |
| 926system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles 927system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles | 926system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles 927system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles |
| 928system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles | 928system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles |
| 929system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles | 929system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles |
| 930system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles | 930system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles |
| 931system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) 932system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) 933system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) 934system.cpu.l2cache.WritebackDirty_accesses::writebacks 683846 # number of WritebackDirty accesses(hits+misses) 935system.cpu.l2cache.WritebackDirty_accesses::total 683846 # number of WritebackDirty accesses(hits+misses) 936system.cpu.l2cache.WritebackClean_accesses::writebacks 1664945 # number of WritebackClean accesses(hits+misses) 937system.cpu.l2cache.WritebackClean_accesses::total 1664945 # number of WritebackClean accesses(hits+misses) 938system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses) --- 43 unchanged lines hidden (view full) --- 982system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency 983system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency 984system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency 985system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency 986system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 987system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 988system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency 989system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency | 931system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) 932system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) 933system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) 934system.cpu.l2cache.WritebackDirty_accesses::writebacks 683846 # number of WritebackDirty accesses(hits+misses) 935system.cpu.l2cache.WritebackDirty_accesses::total 683846 # number of WritebackDirty accesses(hits+misses) 936system.cpu.l2cache.WritebackClean_accesses::writebacks 1664945 # number of WritebackClean accesses(hits+misses) 937system.cpu.l2cache.WritebackClean_accesses::total 1664945 # number of WritebackClean accesses(hits+misses) 938system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses) --- 43 unchanged lines hidden (view full) --- 982system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency 983system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency 984system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency 985system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency 986system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 987system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 988system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency 989system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency |
| 990system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency 991system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency | 990system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency 991system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency |
| 992system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency 993system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency 994system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 995system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency | 992system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency 993system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency 994system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 995system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency |
| 996system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency | 996system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency |
| 997system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency | 997system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency |
| 998system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency | 998system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency |
| 999system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 1000system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency | 999system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency 1000system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency |
| 1001system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency | 1001system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency |
| 1002system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency | 1002system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency |
| 1003system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency | 1003system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency |
| 1004system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1005system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1006system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1007system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1008system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1009system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1010system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks 1011system.cpu.l2cache.writebacks::total 81185 # number of writebacks --- 32 unchanged lines hidden (view full) --- 1044system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles 1045system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1133500 # number of ReadReq MSHR miss cycles 1046system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186544500 # number of UpgradeReq MSHR miss cycles 1047system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186544500 # number of UpgradeReq MSHR miss cycles 1048system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles 1049system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles 1050system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles 1051system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles | 1004system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1005system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1006system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1007system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1008system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1009system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1010system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks 1011system.cpu.l2cache.writebacks::total 81185 # number of writebacks --- 32 unchanged lines hidden (view full) --- 1044system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles 1045system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1133500 # number of ReadReq MSHR miss cycles 1046system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186544500 # number of UpgradeReq MSHR miss cycles 1047system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186544500 # number of UpgradeReq MSHR miss cycles 1048system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles 1049system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles 1050system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles 1051system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles |
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| 1054system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles 1055system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles 1056system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles 1057system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles | 1054system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles 1055system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles 1056system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles 1057system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles |
| 1058system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles | 1058system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles |
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| 1060system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles | 1060system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles |
| 1061system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles 1062system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles | 1061system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles 1062system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles |
| 1063system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles | 1063system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles |
| 1064system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles | 1064system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles |
| 1065system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles | 1065system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles |
| 1066system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles 1067system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles 1068system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles 1069system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles 1070system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles 1071system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles 1072system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses --- 22 unchanged lines hidden (view full) --- 1096system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency 1097system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency 1098system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711 # average UpgradeReq mshr miss latency 1099system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711 # average UpgradeReq mshr miss latency 1100system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1101system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1102system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency 1103system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency | 1066system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles 1067system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles 1068system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles 1069system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles 1070system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles 1071system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles 1072system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses --- 22 unchanged lines hidden (view full) --- 1096system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency 1097system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency 1098system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711 # average UpgradeReq mshr miss latency 1099system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711 # average UpgradeReq mshr miss latency 1100system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1101system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1102system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency 1103system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency |
| 1104system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency 1105system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency | 1104system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency 1105system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency |
| 1106system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency 1107system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency 1108system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1109system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency | 1106system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency 1107system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency 1108system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1109system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency |
| 1110system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency | 1110system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency |
| 1111system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency | 1111system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency |
| 1112system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency | 1112system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency |
| 1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1114system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency | 1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1114system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency |
| 1115system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency | 1115system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency |
| 1116system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency | 1116system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency |
| 1117system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency | 1117system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency |
| 1118system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency 1119system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency 1120system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency 1121system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency 1122system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency 1123system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency 1124system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. 1125system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. --- 337 unchanged lines hidden --- | 1118system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency 1119system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency 1120system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency 1121system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency 1122system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency 1123system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency 1124system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. 1125system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. --- 337 unchanged lines hidden --- |