| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.909587 # Number of seconds simulated 4sim_ticks 2909586837500 # Number of ticks simulated 5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 929184 # Simulator instruction rate (inst/s) 8host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24040663881 # Simulator tick rate (ticks/s) 10host_mem_usage 581600 # Number of bytes of host memory used 11host_seconds 121.03 # Real time elapsed on the host | 7host_inst_rate 812558 # Simulator instruction rate (inst/s) 8host_op_rate 979692 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 21023218607 # Simulator tick rate (ticks/s) 10host_mem_usage 578440 # Number of bytes of host memory used 11host_seconds 138.40 # Real time elapsed on the host |
| 12sim_insts 112457033 # Number of instructions simulated 13sim_ops 135588117 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory --- 626 unchanged lines hidden (view full) --- 646system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::total 31321.035322 # average overall miss latency 648system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked 649system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 112457033 # Number of instructions simulated 13sim_ops 135588117 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory --- 626 unchanged lines hidden (view full) --- 646system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::total 31321.035322 # average overall miss latency 648system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked 649system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 654system.cpu.dcache.fast_writes 0 # number of fast writes performed 655system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 656system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks 657system.cpu.dcache.writebacks::total 683846 # number of writebacks 658system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits 659system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits 660system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14246 # number of LoadLockedReq MSHR hits 661system.cpu.dcache.LoadLockedReq_mshr_hits::total 14246 # number of LoadLockedReq MSHR hits 662system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits 663system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits --- 30 unchanged lines hidden (view full) --- 694system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles 695system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24860984500 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 24860984500 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles 701system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles | 654system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks 655system.cpu.dcache.writebacks::total 683846 # number of writebacks 656system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits 657system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits 658system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14246 # number of LoadLockedReq MSHR hits 659system.cpu.dcache.LoadLockedReq_mshr_hits::total 14246 # number of LoadLockedReq MSHR hits 660system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits 661system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits --- 30 unchanged lines hidden (view full) --- 692system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles 693system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24860984500 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::total 24860984500 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 # number of overall MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles 698system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles 699system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles |
| 702system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles 703system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles 704system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles 705system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles | 700system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278149500 # number of overall MSHR uncacheable cycles 701system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278149500 # number of overall MSHR uncacheable cycles |
| 706system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses 707system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses 708system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses 709system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses 710system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227562 # mshr miss rate for SoftPFReq accesses 711system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227562 # mshr miss rate for SoftPFReq accesses 712system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses 713system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses --- 14 unchanged lines hidden (view full) --- 728system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 729system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 730system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency 731system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency 732system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency 733system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency 734system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency 735system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency | 702system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses 703system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses 704system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses 705system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses 706system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227562 # mshr miss rate for SoftPFReq accesses 707system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227562 # mshr miss rate for SoftPFReq accesses 708system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses 709system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses --- 14 unchanged lines hidden (view full) --- 724system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 725system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 726system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency 727system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency 728system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency 729system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency 730system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency 731system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency |
| 736system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency 737system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency 738system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency 739system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency 740system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 732system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency 733system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency |
| 741system.cpu.icache.tags.replacements 1695721 # number of replacements 742system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use 743system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. 744system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks. 745system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks. 746system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. 747system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor 748system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 792system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency 793system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency 794system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 795system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 796system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 797system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 798system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 799system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 734system.cpu.icache.tags.replacements 1695721 # number of replacements 735system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use 736system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. 737system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks. 738system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks. 739system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. 740system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor 741system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 785system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency 786system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency 787system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 800system.cpu.icache.fast_writes 0 # number of fast writes performed 801system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 802system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks 803system.cpu.icache.writebacks::total 1695721 # number of writebacks 804system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses 805system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses 806system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses 807system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses 808system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses 809system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 832system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency 833system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency 834system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency 835system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency 836system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 837system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 838system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 839system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency | 793system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks 794system.cpu.icache.writebacks::total 1695721 # number of writebacks 795system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses 796system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses 797system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses 798system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses 799system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses 800system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 823system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency 824system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency 827system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency 828system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency 829system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency 830system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency |
| 840system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 841system.cpu.l2cache.tags.replacements 87565 # number of replacements 842system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use 843system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. 844system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. 845system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks. 846system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 847system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor 848system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor --- 163 unchanged lines hidden (view full) --- 1012system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency 1013system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency 1014system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1015system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1016system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1017system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1018system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1019system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 831system.cpu.l2cache.tags.replacements 87565 # number of replacements 832system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use 833system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. 834system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. 835system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks. 836system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 837system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor 838system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor --- 163 unchanged lines hidden (view full) --- 1002system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency 1003system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency 1004system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1005system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1006system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1007system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1008system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1009system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1020system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1021system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1022system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks 1023system.cpu.l2cache.writebacks::total 81185 # number of writebacks 1024system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses 1025system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1026system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses 1027system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses 1028system.cpu.l2cache.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses 1029system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses --- 43 unchanged lines hidden (view full) --- 1073system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles 1074system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles 1075system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles 1076system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles 1077system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles 1078system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles 1079system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles 1080system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles | 1010system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks 1011system.cpu.l2cache.writebacks::total 81185 # number of writebacks 1012system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses 1013system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1014system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses 1015system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses 1016system.cpu.l2cache.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses 1017system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses --- 43 unchanged lines hidden (view full) --- 1061system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles 1062system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles 1063system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles 1064system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles 1065system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles 1066system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles 1067system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles 1068system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles |
| 1081system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles 1082system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles | |
| 1083system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles | 1069system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles |
| 1084system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles 1085system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles | 1070system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles 1071system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles |
| 1086system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses 1087system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses 1088system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses 1089system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses 1090system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses 1091system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1092system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1093system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435599 # mshr miss rate for ReadExReq accesses --- 33 unchanged lines hidden (view full) --- 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency 1129system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency 1130system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency 1131system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency 1132system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency 1133system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency 1134system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency | 1072system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses 1075system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses 1076system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses 1077system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1079system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435599 # mshr miss rate for ReadExReq accesses --- 33 unchanged lines hidden (view full) --- 1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency 1114system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency 1115system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency 1116system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency 1117system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency 1118system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency 1119system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency 1120system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency |
| 1135system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency 1136system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency | |
| 1137system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency | 1121system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency |
| 1138system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency 1139system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency 1140system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1122system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency 1123system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency |
| 1141system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. 1142system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1143system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1144system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. 1145system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1146system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1147system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution --- 151 unchanged lines hidden (view full) --- 1300system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1301system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1302system.iocache.tags.tag_accesses 328068 # Number of tag accesses 1303system.iocache.tags.data_accesses 328068 # Number of data accesses 1304system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses 1305system.iocache.ReadReq_misses::total 228 # number of ReadReq misses 1306system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1307system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses | 1124system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. 1125system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1126system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1127system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. 1128system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1129system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1130system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution --- 151 unchanged lines hidden (view full) --- 1283system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1284system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1285system.iocache.tags.tag_accesses 328068 # Number of tag accesses 1286system.iocache.tags.data_accesses 328068 # Number of data accesses 1287system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses 1288system.iocache.ReadReq_misses::total 228 # number of ReadReq misses 1289system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1290system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
| 1308system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses 1309system.iocache.demand_misses::total 228 # number of demand (read+write) misses 1310system.iocache.overall_misses::realview.ide 228 # number of overall misses 1311system.iocache.overall_misses::total 228 # number of overall misses | 1291system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses 1292system.iocache.demand_misses::total 36452 # number of demand (read+write) misses 1293system.iocache.overall_misses::realview.ide 36452 # number of overall misses 1294system.iocache.overall_misses::total 36452 # number of overall misses |
| 1312system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles 1313system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles 1314system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles 1315system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles | 1295system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles 1296system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles 1297system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles 1298system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles |
| 1316system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles 1317system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles 1318system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles 1319system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles | 1299system.iocache.demand_miss_latency::realview.ide 4577313527 # number of demand (read+write) miss cycles 1300system.iocache.demand_miss_latency::total 4577313527 # number of demand (read+write) miss cycles 1301system.iocache.overall_miss_latency::realview.ide 4577313527 # number of overall miss cycles 1302system.iocache.overall_miss_latency::total 4577313527 # number of overall miss cycles |
| 1320system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) 1321system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) 1322system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1323system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) | 1303system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) 1304system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) 1305system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1306system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
| 1324system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses 1325system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses 1326system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses 1327system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses | 1307system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses 1308system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses 1309system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses 1310system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses |
| 1328system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1329system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1330system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1331system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1332system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1333system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1334system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1335system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1336system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency 1337system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency 1338system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency 1339system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency | 1311system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1312system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1313system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1314system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1315system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1316system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1317system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1318system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1319system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency 1320system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency 1321system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency 1322system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency |
| 1340system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency 1341system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency 1342system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency 1343system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency | 1323system.iocache.demand_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency 1324system.iocache.demand_avg_miss_latency::total 125570.984500 # average overall miss latency 1325system.iocache.overall_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency 1326system.iocache.overall_avg_miss_latency::total 125570.984500 # average overall miss latency |
| 1344system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1345system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1346system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1347system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1348system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1349system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1327system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1328system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1329system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1330system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1331system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1332system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1350system.iocache.fast_writes 0 # number of fast writes performed 1351system.iocache.cache_copies 0 # number of cache copies performed | |
| 1352system.iocache.writebacks::writebacks 36190 # number of writebacks 1353system.iocache.writebacks::total 36190 # number of writebacks 1354system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses 1355system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 1356system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1357system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses | 1333system.iocache.writebacks::writebacks 36190 # number of writebacks 1334system.iocache.writebacks::total 36190 # number of writebacks 1335system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses 1336system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 1337system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1338system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses |
| 1358system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses 1359system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 1360system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses 1361system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses | 1339system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses 1340system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses 1341system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses 1342system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses |
| 1362system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles 1363system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles 1364system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles 1365system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles | 1343system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles 1344system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles 1345system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles 1346system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles |
| 1366system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles 1367system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles 1368system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles 1369system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles | 1347system.iocache.demand_mshr_miss_latency::realview.ide 2753302003 # number of demand (read+write) MSHR miss cycles 1348system.iocache.demand_mshr_miss_latency::total 2753302003 # number of demand (read+write) MSHR miss cycles 1349system.iocache.overall_mshr_miss_latency::realview.ide 2753302003 # number of overall MSHR miss cycles 1350system.iocache.overall_mshr_miss_latency::total 2753302003 # number of overall MSHR miss cycles |
| 1370system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1371system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1372system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1373system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1374system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1375system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1376system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1377system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1378system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency 1379system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency 1380system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency 1381system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency | 1351system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1352system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1353system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1354system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1355system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1356system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1357system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1358system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1359system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency 1360system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency 1361system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency 1362system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency |
| 1382system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency 1383system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency 1384system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency 1385system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency 1386system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1363system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1364system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency 1365system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency 1366system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency |
| 1387system.membus.trans_dist::ReadReq 40160 # Transaction distribution 1388system.membus.trans_dist::ReadResp 70548 # Transaction distribution 1389system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1390system.membus.trans_dist::WriteResp 27589 # Transaction distribution 1391system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution 1392system.membus.trans_dist::CleanEvict 6608 # Transaction distribution 1393system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution 1394system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 88 unchanged lines hidden --- | 1367system.membus.trans_dist::ReadReq 40160 # Transaction distribution 1368system.membus.trans_dist::ReadResp 70548 # Transaction distribution 1369system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1370system.membus.trans_dist::WriteResp 27589 # Transaction distribution 1371system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution 1372system.membus.trans_dist::CleanEvict 6608 # Transaction distribution 1373system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution 1374system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 88 unchanged lines hidden --- |