Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.909596 # Number of seconds simulated
4sim_ticks 2909596171500 # Number of ticks simulated
5final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.909587 # Number of seconds simulated
4sim_ticks 2909586837500 # Number of ticks simulated
5final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 322522 # Simulator instruction rate (inst/s)
8host_op_rate 388861 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 8344730622 # Simulator tick rate (ticks/s)
10host_mem_usage 560756 # Number of bytes of host memory used
11host_seconds 348.67 # Real time elapsed on the host
12sim_insts 112455206 # Number of instructions simulated
13sim_ops 135585876 # Number of ops (including micro ops) simulated

7host_inst_rate 929184 # Simulator instruction rate (inst/s)
8host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 24040663881 # Simulator tick rate (ticks/s)
10host_mem_usage 581600 # Number of bytes of host memory used
11host_seconds 121.03 # Real time elapsed on the host
12sim_insts 112457033 # Number of instructions simulated
13sim_ops 135588117 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 8901796 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory

20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory

21system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory

21system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory

25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory

26system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory

26system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory

27system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory

29system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 139610 # Number of read requests responded to by this memory

29system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 139611 # Number of read requests responded to by this memory

31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory

32system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory

32system.physmem.num_reads::total 166628 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory

34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory

35system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory

35system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory

36system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)

38system.physmem.bw_read::cpu.inst 407756 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 3059461 # Total read bandwidth from this memory (bytes/s)

38system.physmem.bw_read::cpu.inst 407801 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 3059493 # Total read bandwidth from this memory (bytes/s)

40system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)

41system.physmem.bw_read::total 3467744 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 407756 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 407756 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 2581758 # Write bandwidth from this memory (bytes/s)

41system.physmem.bw_read::total 3467822 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 407801 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 407801 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 2581810 # Write bandwidth from this memory (bytes/s)

45system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s)

46system.physmem.bw_write::total 2587780 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 2581758 # Total bandwidth to/from this memory (bytes/s)

46system.physmem.bw_write::total 2587833 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 2581810 # Total bandwidth to/from this memory (bytes/s)

48system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)

50system.physmem.bw_total::cpu.inst 407756 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 3065484 # Total bandwidth to/from this memory (bytes/s)

50system.physmem.bw_total::cpu.inst 407801 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 3065516 # Total bandwidth to/from this memory (bytes/s)

52system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)

53system.physmem.bw_total::total 6055525 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 166625 # Number of read requests accepted
55system.physmem.writeReqs 121754 # Number of write requests accepted
56system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue
60system.physmem.bytesWritten 7541952 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue

53system.physmem.bw_total::total 6055654 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 166628 # Number of read requests accepted
55system.physmem.writeReqs 121756 # Number of write requests accepted
56system.physmem.readBursts 166628 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 10657408 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
60system.physmem.bytesWritten 7542016 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 10089928 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue

64system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one

65system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write

65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write

66system.physmem.perBankRdBursts::0 10077 # Per bank write bursts
67system.physmem.perBankRdBursts::1 9979 # Per bank write bursts
68system.physmem.perBankRdBursts::2 10695 # Per bank write bursts

69system.physmem.perBankRdBursts::3 10661 # Per bank write bursts

69system.physmem.perBankRdBursts::3 10660 # Per bank write bursts

70system.physmem.perBankRdBursts::4 18797 # Per bank write bursts

71system.physmem.perBankRdBursts::5 9659 # Per bank write bursts
72system.physmem.perBankRdBursts::6 9663 # Per bank write bursts
73system.physmem.perBankRdBursts::7 10485 # Per bank write bursts

71system.physmem.perBankRdBursts::5 9664 # Per bank write bursts
72system.physmem.perBankRdBursts::6 9666 # Per bank write bursts
73system.physmem.perBankRdBursts::7 10487 # Per bank write bursts

74system.physmem.perBankRdBursts::8 9276 # Per bank write bursts
75system.physmem.perBankRdBursts::9 9973 # Per bank write bursts
76system.physmem.perBankRdBursts::10 9232 # Per bank write bursts
77system.physmem.perBankRdBursts::11 8679 # Per bank write bursts

78system.physmem.perBankRdBursts::12 9817 # Per bank write bursts

78system.physmem.perBankRdBursts::12 9822 # Per bank write bursts

79system.physmem.perBankRdBursts::13 10379 # Per bank write bursts

80system.physmem.perBankRdBursts::14 9722 # Per bank write bursts

80system.physmem.perBankRdBursts::14 9723 # Per bank write bursts

81system.physmem.perBankRdBursts::15 9413 # Per bank write bursts
82system.physmem.perBankWrBursts::0 7393 # Per bank write bursts
83system.physmem.perBankWrBursts::1 7263 # Per bank write bursts
84system.physmem.perBankWrBursts::2 8282 # Per bank write bursts
85system.physmem.perBankWrBursts::3 8171 # Per bank write bursts
86system.physmem.perBankWrBursts::4 7489 # Per bank write bursts
87system.physmem.perBankWrBursts::5 7265 # Per bank write bursts
88system.physmem.perBankWrBursts::6 7108 # Per bank write bursts

89system.physmem.perBankWrBursts::7 7659 # Per bank write bursts

89system.physmem.perBankWrBursts::7 7661 # Per bank write bursts

90system.physmem.perBankWrBursts::8 7080 # Per bank write bursts
91system.physmem.perBankWrBursts::9 7523 # Per bank write bursts
92system.physmem.perBankWrBursts::10 6695 # Per bank write bursts
93system.physmem.perBankWrBursts::11 6470 # Per bank write bursts

94system.physmem.perBankWrBursts::12 7534 # Per bank write bursts

94system.physmem.perBankWrBursts::12 7533 # Per bank write bursts

95system.physmem.perBankWrBursts::13 7859 # Per bank write bursts
96system.physmem.perBankWrBursts::14 7264 # Per bank write bursts
97system.physmem.perBankWrBursts::15 6788 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry

99system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
100system.physmem.totGap 2909595814500 # Total gap between requests

99system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
100system.physmem.totGap 2909586480500 # Total gap between requests

101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 9558 # Read request sizes (log2)
104system.physmem.readPktSize::3 14 # Read request sizes (log2)
105system.physmem.readPktSize::4 0 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)

107system.physmem.readPktSize::6 157053 # Read request sizes (log2)

107system.physmem.readPktSize::6 157056 # Read request sizes (log2)

108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 4381 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)

114system.physmem.writePktSize::6 117373 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 165628 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see

114system.physmem.writePktSize::6 117375 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 165639 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see

118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see

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154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see

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199system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 91 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 54 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 58778 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 309.611351 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 182.749688 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 329.493771 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 21450 36.49% 36.49% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 14701 25.01% 61.50% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 6086 10.35% 71.86% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3214 5.47% 77.33% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2550 4.34% 81.66% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1476 2.51% 84.18% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1054 1.79% 85.97% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1089 1.85% 87.82% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 7158 12.18% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 58778 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5758 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 28.915596 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 590.311059 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-2047 5757 99.98% 99.98% # Reads before turning the bus around for writes

162system.physmem.wrQLenPdf::15 1976 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 3160 # What write queue length does an incoming req see
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196system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see
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199system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see
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201system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see
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209system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 58742 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 309.818528 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 182.858167 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 329.750191 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 21399 36.43% 36.43% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 14737 25.09% 61.52% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 6061 10.32% 71.83% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3228 5.50% 77.33% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2535 4.32% 81.65% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1458 2.48% 84.13% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1057 1.80% 85.93% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1079 1.84% 87.76% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 7188 12.24% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 58742 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5615 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 29.654497 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 597.763680 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-2047 5614 99.98% 99.98% # Reads before turning the bus around for writes

229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes

230system.physmem.rdPerTurnAround::total 5758 # Reads before turning the bus around for writes
231system.physmem.wrPerTurnAround::samples 5758 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::mean 20.465960 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::gmean 18.711564 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::stdev 13.116644 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::16-19 4961 86.16% 86.16% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::20-23 87 1.51% 87.67% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-27 33 0.57% 88.24% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28-31 172 2.99% 91.23% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-35 23 0.40% 91.63% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::36-39 160 2.78% 94.41% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::40-43 50 0.87% 95.28% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::44-47 6 0.10% 95.38% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::48-51 7 0.12% 95.50% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::52-55 22 0.38% 95.88% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::56-59 2 0.03% 95.92% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::60-63 6 0.10% 96.02% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::64-67 163 2.83% 98.85% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::68-71 3 0.05% 98.91% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::72-75 10 0.17% 99.08% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::76-79 20 0.35% 99.43% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::88-91 1 0.02% 99.48% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::100-103 1 0.02% 99.50% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::108-111 2 0.03% 99.53% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::128-131 16 0.28% 99.86% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::total 5758 # Writes before turning the bus around for reads
267system.physmem.totQLat 1616458000 # Total ticks spent queuing
268system.physmem.totMemAccLat 4738464250 # Total ticks spent from burst creation until serviced by the DRAM
269system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers
270system.physmem.avgQLat 9708.05 # Average queueing delay per DRAM burst

230system.physmem.rdPerTurnAround::total 5615 # Reads before turning the bus around for writes
231system.physmem.wrPerTurnAround::samples 5615 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::mean 20.987355 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::gmean 18.791633 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::stdev 15.100649 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::16-19 4949 88.14% 88.14% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::20-23 78 1.39% 89.53% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-27 32 0.57% 90.10% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28-31 46 0.82% 90.92% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-35 24 0.43% 91.34% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::36-39 20 0.36% 91.70% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::40-43 46 0.82% 92.52% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::44-47 4 0.07% 92.59% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::48-51 153 2.72% 95.32% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::52-55 11 0.20% 95.51% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::56-59 7 0.12% 95.64% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::60-63 13 0.23% 95.87% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::64-67 63 1.12% 96.99% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::68-71 5 0.09% 97.08% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::72-75 5 0.09% 97.17% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::76-79 26 0.46% 97.63% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::80-83 103 1.83% 99.47% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::112-115 2 0.04% 99.57% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::140-143 1 0.02% 99.75% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::144-147 7 0.12% 99.88% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads
264system.physmem.totQLat 1624802000 # Total ticks spent queuing
265system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM
266system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers
267system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst

271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

272system.physmem.avgMemAccLat 28458.05 # Average memory access latency per DRAM burst

269system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst

273system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
274system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
275system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
276system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s
277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
278system.physmem.busUtil 0.05 # Data bus utilization in percentage
279system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
280system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
281system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
282system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing

270system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
271system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
272system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
273system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s
274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
275system.physmem.busUtil 0.05 # Data bus utilization in percentage
276system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
277system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
278system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
279system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing

283system.physmem.readRowHits 136072 # Number of row buffer hits during reads
284system.physmem.writeRowHits 89499 # Number of row buffer hits during writes
285system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads
286system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes
287system.physmem.avgGap 10089485.76 # Average gap between requests
288system.physmem.pageHitRate 79.32 # Row buffer hit rate, read and write combined
289system.physmem_0.actEnergy 230958000 # Energy for activate commands per rank (pJ)
290system.physmem_0.preEnergy 126018750 # Energy for precharge commands per rank (pJ)
291system.physmem_0.readEnergy 702124800 # Energy for read commands per rank (pJ)
292system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ)
293system.physmem_0.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ)
294system.physmem_0.actBackEnergy 90366604425 # Energy for active background per rank (pJ)
295system.physmem_0.preBackEnergy 1666484751750 # Energy for precharge background per rank (pJ)
296system.physmem_0.totalEnergy 1948343566605 # Total energy per rank (pJ)
297system.physmem_0.averagePower 669.628332 # Core power per rank (mW)
298system.physmem_0.memoryStateTime::IDLE 2772164122000 # Time in different power states
299system.physmem_0.memoryStateTime::REF 97157580000 # Time in different power states

280system.physmem.readRowHits 136095 # Number of row buffer hits during reads
281system.physmem.writeRowHits 89528 # Number of row buffer hits during writes
282system.physmem.readRowHitRate 81.73 # Row buffer hit rate for reads
283system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes
284system.physmem.avgGap 10089278.46 # Average gap between requests
285system.physmem.pageHitRate 79.34 # Row buffer hit rate, read and write combined
286system.physmem_0.actEnergy 230829480 # Energy for activate commands per rank (pJ)
287system.physmem_0.preEnergy 125948625 # Energy for precharge commands per rank (pJ)
288system.physmem_0.readEnergy 702195000 # Energy for read commands per rank (pJ)
289system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ)
290system.physmem_0.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ)
291system.physmem_0.actBackEnergy 90325761075 # Energy for active background per rank (pJ)
292system.physmem_0.preBackEnergy 1666515907500 # Energy for precharge background per rank (pJ)
293system.physmem_0.totalEnergy 1948333254960 # Total energy per rank (pJ)
294system.physmem_0.averagePower 669.626580 # Core power per rank (mW)
295system.physmem_0.memoryStateTime::IDLE 2772215900000 # Time in different power states
296system.physmem_0.memoryStateTime::REF 97157320000 # Time in different power states

300system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

301system.physmem_0.memoryStateTime::ACT 40267816750 # Time in different power states

298system.physmem_0.memoryStateTime::ACT 40208512500 # Time in different power states

302system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states

299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states

303system.physmem_1.actEnergy 213403680 # Energy for activate commands per rank (pJ)
304system.physmem_1.preEnergy 116440500 # Energy for precharge commands per rank (pJ)
305system.physmem_1.readEnergy 596622000 # Energy for read commands per rank (pJ)
306system.physmem_1.writeEnergy 370740240 # Energy for write commands per rank (pJ)
307system.physmem_1.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ)
308system.physmem_1.actBackEnergy 88072375230 # Energy for active background per rank (pJ)
309system.physmem_1.preBackEnergy 1668497233500 # Energy for precharge background per rank (pJ)
310system.physmem_1.totalEnergy 1947907041630 # Total energy per rank (pJ)
311system.physmem_1.averagePower 669.478302 # Core power per rank (mW)
312system.physmem_1.memoryStateTime::IDLE 2775541834250 # Time in different power states
313system.physmem_1.memoryStateTime::REF 97157580000 # Time in different power states

300system.physmem_1.actEnergy 213260040 # Energy for activate commands per rank (pJ)
301system.physmem_1.preEnergy 116362125 # Energy for precharge commands per rank (pJ)
302system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ)
303system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ)
304system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ)
305system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ)
306system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ)
307system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ)
308system.physmem_1.averagePower 669.477277 # Core power per rank (mW)
309system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states
310system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states

314system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

315system.physmem_1.memoryStateTime::ACT 36896609250 # Time in different power states

312system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states

316system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
317system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
318system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
319system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
320system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
321system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
322system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
323system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)

--- 41 unchanged lines hidden (view full) ---

365system.cpu.dtb.walker.walks 9546 # Table walker walks requested
366system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors
367system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate
368system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate
369system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency
370system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency
371system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency
372system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency

313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
314system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
315system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
316system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
317system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
318system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
319system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
320system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)

--- 41 unchanged lines hidden (view full) ---

362system.cpu.dtb.walker.walks 9546 # Table walker walks requested
363system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors
364system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate
365system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate
366system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency
367system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency
368system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency
369system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency

373system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982 # Table walker service (enqueue to completion) latency
374system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330 # Table walker service (enqueue to completion) latency
375system.cpu.dtb.walker.walkCompletionTime::stdev 8540.848722 # Table walker service (enqueue to completion) latency

370system.cpu.dtb.walker.walkCompletionTime::mean 13159.035492 # Table walker service (enqueue to completion) latency
371system.cpu.dtb.walker.walkCompletionTime::gmean 10920.963738 # Table walker service (enqueue to completion) latency
372system.cpu.dtb.walker.walkCompletionTime::stdev 8541.710442 # Table walker service (enqueue to completion) latency

376system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency
377system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
378system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
379system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency
380system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution
381system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution
382system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution
383system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated
384system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated
385system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated
386system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst
387system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
388system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst
389system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst
390system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
391system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst
392system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst
393system.cpu.dtb.inst_hits 0 # ITB inst hits
394system.cpu.dtb.inst_misses 0 # ITB inst misses

373system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency
374system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
375system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
376system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency
377system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution
378system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution
379system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution
380system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated
381system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated
382system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated
383system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst
384system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
385system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst
386system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst
387system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
388system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst
389system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst
390system.cpu.dtb.inst_hits 0 # ITB inst hits
391system.cpu.dtb.inst_misses 0 # ITB inst misses

395system.cpu.dtb.read_hits 24520178 # DTB read hits

392system.cpu.dtb.read_hits 24520655 # DTB read hits

396system.cpu.dtb.read_misses 8124 # DTB read misses

393system.cpu.dtb.read_misses 8124 # DTB read misses

397system.cpu.dtb.write_hits 19606457 # DTB write hits

394system.cpu.dtb.write_hits 19606816 # DTB write hits

398system.cpu.dtb.write_misses 1422 # DTB write misses
399system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
400system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
401system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
402system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
403system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
404system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
405system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch
406system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
407system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions

395system.cpu.dtb.write_misses 1422 # DTB write misses
396system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
397system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
398system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
399system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
400system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
401system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
402system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch
403system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
404system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions

408system.cpu.dtb.read_accesses 24528302 # DTB read accesses
409system.cpu.dtb.write_accesses 19607879 # DTB write accesses

405system.cpu.dtb.read_accesses 24528779 # DTB read accesses
406system.cpu.dtb.write_accesses 19608238 # DTB write accesses

410system.cpu.dtb.inst_accesses 0 # ITB inst accesses

407system.cpu.dtb.inst_accesses 0 # ITB inst accesses

411system.cpu.dtb.hits 44126635 # DTB hits

408system.cpu.dtb.hits 44127471 # DTB hits

412system.cpu.dtb.misses 9546 # DTB misses

409system.cpu.dtb.misses 9546 # DTB misses

413system.cpu.dtb.accesses 44136181 # DTB accesses

410system.cpu.dtb.accesses 44137017 # DTB accesses

414system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
415system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
416system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
417system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
418system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
419system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
420system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
421system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 41 unchanged lines hidden (view full) ---

463system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
464system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
465system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
466system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
467system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
468system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
469system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
470system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst

411system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
412system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
413system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
414system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
415system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
416system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
417system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
418system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 41 unchanged lines hidden (view full) ---

460system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
461system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
462system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
463system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
464system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
465system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
466system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
467system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst

471system.cpu.itb.inst_hits 115552414 # ITB inst hits

468system.cpu.itb.inst_hits 115554258 # ITB inst hits

472system.cpu.itb.inst_misses 4763 # ITB inst misses
473system.cpu.itb.read_hits 0 # DTB read hits
474system.cpu.itb.read_misses 0 # DTB read misses
475system.cpu.itb.write_hits 0 # DTB write hits
476system.cpu.itb.write_misses 0 # DTB write misses
477system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
478system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
479system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
480system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
481system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
482system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
483system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
484system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
485system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
486system.cpu.itb.read_accesses 0 # DTB read accesses
487system.cpu.itb.write_accesses 0 # DTB write accesses

469system.cpu.itb.inst_misses 4763 # ITB inst misses
470system.cpu.itb.read_hits 0 # DTB read hits
471system.cpu.itb.read_misses 0 # DTB read misses
472system.cpu.itb.write_hits 0 # DTB write hits
473system.cpu.itb.write_misses 0 # DTB write misses
474system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
475system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
476system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
477system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
478system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
479system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
480system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
481system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
482system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
483system.cpu.itb.read_accesses 0 # DTB read accesses
484system.cpu.itb.write_accesses 0 # DTB write accesses

488system.cpu.itb.inst_accesses 115557177 # ITB inst accesses
489system.cpu.itb.hits 115552414 # DTB hits

485system.cpu.itb.inst_accesses 115559021 # ITB inst accesses
486system.cpu.itb.hits 115554258 # DTB hits

490system.cpu.itb.misses 4763 # DTB misses

487system.cpu.itb.misses 4763 # DTB misses

491system.cpu.itb.accesses 115557177 # DTB accesses
492system.cpu.numCycles 5819192343 # number of cpu cycles simulated

488system.cpu.itb.accesses 115559021 # DTB accesses
489system.cpu.numCycles 5819173675 # number of cpu cycles simulated

493system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
494system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
495system.cpu.kern.inst.arm 0 # number of arm instructions executed
496system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed

490system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
491system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
492system.cpu.kern.inst.arm 0 # number of arm instructions executed
493system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed

497system.cpu.committedInsts 112455206 # Number of instructions committed
498system.cpu.committedOps 135585876 # Number of ops (including micro ops) committed
499system.cpu.num_int_alu_accesses 119891340 # Number of integer alu accesses

494system.cpu.committedInsts 112457033 # Number of instructions committed
495system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed
496system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses

500system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses

497system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses

501system.cpu.num_func_calls 9892021 # number of times a function call or return occured
502system.cpu.num_conditional_control_insts 15230391 # number of instructions that are conditional controls
503system.cpu.num_int_insts 119891340 # number of integer instructions

498system.cpu.num_func_calls 9892146 # number of times a function call or return occured
499system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls
500system.cpu.num_int_insts 119893391 # number of integer instructions

504system.cpu.num_fp_insts 11161 # number of float instructions

501system.cpu.num_fp_insts 11161 # number of float instructions

505system.cpu.num_int_register_reads 218059811 # number of times the integer registers were read
506system.cpu.num_int_register_writes 82644916 # number of times the integer registers were written

502system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read
503system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written

507system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
508system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written

504system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
505system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written

509system.cpu.num_cc_register_reads 489735153 # number of times the CC registers were read
510system.cpu.num_cc_register_writes 51893214 # number of times the CC registers were written
511system.cpu.num_mem_refs 45407055 # number of memory refs
512system.cpu.num_load_insts 24842618 # Number of load instructions
513system.cpu.num_store_insts 20564437 # Number of store instructions
514system.cpu.num_idle_cycles 5379072985.844151 # Number of idle cycles
515system.cpu.num_busy_cycles 440119357.155849 # Number of busy cycles
516system.cpu.not_idle_fraction 0.075632 # Percentage of non-idle cycles
517system.cpu.idle_fraction 0.924368 # Percentage of idle cycles
518system.cpu.Branches 25916470 # Number of branches fetched

506system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read
507system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written
508system.cpu.num_mem_refs 45407924 # number of memory refs
509system.cpu.num_load_insts 24843119 # Number of load instructions
510system.cpu.num_store_insts 20564805 # Number of store instructions
511system.cpu.num_idle_cycles 5379054575.844151 # Number of idle cycles
512system.cpu.num_busy_cycles 440119099.155849 # Number of busy cycles
513system.cpu.not_idle_fraction 0.075633 # Percentage of non-idle cycles
514system.cpu.idle_fraction 0.924367 # Percentage of idle cycles
515system.cpu.Branches 25916787 # Number of branches fetched

519system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction

516system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction

520system.cpu.op_class::IntAlu 93173703 67.17% 67.18% # Class of executed instruction
521system.cpu.op_class::IntMult 114388 0.08% 67.26% # Class of executed instruction

517system.cpu.op_class::IntAlu 93175095 67.17% 67.18% # Class of executed instruction
518system.cpu.op_class::IntMult 114406 0.08% 67.26% # Class of executed instruction

522system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
523system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
524system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
525system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
526system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
527system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
528system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
529system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction

--- 11 unchanged lines hidden (view full) ---

541system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
542system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
543system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
544system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
545system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction
546system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
547system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
548system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction

519system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
520system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
521system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
522system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
523system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
524system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
525system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
526system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction

--- 11 unchanged lines hidden (view full) ---

538system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
539system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
540system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
541system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
542system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction
543system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
544system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
545system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction

549system.cpu.op_class::MemRead 24842618 17.91% 85.17% # Class of executed instruction
550system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction

546system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction
547system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction

551system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
552system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

548system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
549system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

553system.cpu.op_class::total 138705936 # Class of executed instruction
554system.cpu.dcache.tags.replacements 819217 # number of replacements
555system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use
556system.cpu.dcache.tags.total_refs 43235406 # Total number of references to valid blocks.
557system.cpu.dcache.tags.sampled_refs 819729 # Sample count of references to valid blocks.
558system.cpu.dcache.tags.avg_refs 52.743536 # Average number of references to valid blocks.

550system.cpu.op_class::total 138708215 # Class of executed instruction
551system.cpu.dcache.tags.replacements 819223 # number of replacements
552system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use
553system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks.
554system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks.
555system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks.

559system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit.

556system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit.

560system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor

557system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor

561system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy
562system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy
563system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
564system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
565system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
566system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
567system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
568system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

558system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy
559system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy
560system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
561system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
562system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
563system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
564system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

569system.cpu.dcache.tags.tag_accesses 177109321 # Number of tag accesses
570system.cpu.dcache.tags.data_accesses 177109321 # Number of data accesses
571system.cpu.dcache.ReadReq_hits::cpu.data 23112521 # number of ReadReq hits
572system.cpu.dcache.ReadReq_hits::total 23112521 # number of ReadReq hits
573system.cpu.dcache.WriteReq_hits::cpu.data 18823879 # number of WriteReq hits
574system.cpu.dcache.WriteReq_hits::total 18823879 # number of WriteReq hits
575system.cpu.dcache.SoftPFReq_hits::cpu.data 392783 # number of SoftPFReq hits
576system.cpu.dcache.SoftPFReq_hits::total 392783 # number of SoftPFReq hits
577system.cpu.dcache.LoadLockedReq_hits::cpu.data 443242 # number of LoadLockedReq hits
578system.cpu.dcache.LoadLockedReq_hits::total 443242 # number of LoadLockedReq hits
579system.cpu.dcache.StoreCondReq_hits::cpu.data 460216 # number of StoreCondReq hits
580system.cpu.dcache.StoreCondReq_hits::total 460216 # number of StoreCondReq hits
581system.cpu.dcache.demand_hits::cpu.data 41936400 # number of demand (read+write) hits
582system.cpu.dcache.demand_hits::total 41936400 # number of demand (read+write) hits
583system.cpu.dcache.overall_hits::cpu.data 42329183 # number of overall hits
584system.cpu.dcache.overall_hits::total 42329183 # number of overall hits
585system.cpu.dcache.ReadReq_misses::cpu.data 399911 # number of ReadReq misses
586system.cpu.dcache.ReadReq_misses::total 399911 # number of ReadReq misses
587system.cpu.dcache.WriteReq_misses::cpu.data 298704 # number of WriteReq misses
588system.cpu.dcache.WriteReq_misses::total 298704 # number of WriteReq misses
589system.cpu.dcache.SoftPFReq_misses::cpu.data 118377 # number of SoftPFReq misses
590system.cpu.dcache.SoftPFReq_misses::total 118377 # number of SoftPFReq misses
591system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses
592system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses

566system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses
567system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses
568system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits
569system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits
570system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits
571system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits
572system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits
573system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits
574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits
575system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits
576system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits
577system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits
578system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits
579system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits
580system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits
581system.cpu.dcache.overall_hits::total 42329995 # number of overall hits
582system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses
583system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses
584system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses
585system.cpu.dcache.WriteReq_misses::total 298709 # number of WriteReq misses
586system.cpu.dcache.SoftPFReq_misses::cpu.data 118381 # number of SoftPFReq misses
587system.cpu.dcache.SoftPFReq_misses::total 118381 # number of SoftPFReq misses
588system.cpu.dcache.LoadLockedReq_misses::cpu.data 22756 # number of LoadLockedReq misses
589system.cpu.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses

593system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
594system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses

590system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
591system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses

595system.cpu.dcache.demand_misses::cpu.data 698615 # number of demand (read+write) misses
596system.cpu.dcache.demand_misses::total 698615 # number of demand (read+write) misses
597system.cpu.dcache.overall_misses::cpu.data 816992 # number of overall misses
598system.cpu.dcache.overall_misses::total 816992 # number of overall misses
599system.cpu.dcache.ReadReq_miss_latency::cpu.data 6486417000 # number of ReadReq miss cycles
600system.cpu.dcache.ReadReq_miss_latency::total 6486417000 # number of ReadReq miss cycles
601system.cpu.dcache.WriteReq_miss_latency::cpu.data 19109109000 # number of WriteReq miss cycles
602system.cpu.dcache.WriteReq_miss_latency::total 19109109000 # number of WriteReq miss cycles
603system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294489000 # number of LoadLockedReq miss cycles
604system.cpu.dcache.LoadLockedReq_miss_latency::total 294489000 # number of LoadLockedReq miss cycles

592system.cpu.dcache.demand_misses::cpu.data 698621 # number of demand (read+write) misses
593system.cpu.dcache.demand_misses::total 698621 # number of demand (read+write) misses
594system.cpu.dcache.overall_misses::cpu.data 817002 # number of overall misses
595system.cpu.dcache.overall_misses::total 817002 # number of overall misses
596system.cpu.dcache.ReadReq_miss_latency::cpu.data 6488404500 # number of ReadReq miss cycles
597system.cpu.dcache.ReadReq_miss_latency::total 6488404500 # number of ReadReq miss cycles
598system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100944000 # number of WriteReq miss cycles
599system.cpu.dcache.WriteReq_miss_latency::total 19100944000 # number of WriteReq miss cycles
600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293896000 # number of LoadLockedReq miss cycles
601system.cpu.dcache.LoadLockedReq_miss_latency::total 293896000 # number of LoadLockedReq miss cycles

605system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
606system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles

602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
603system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles

607system.cpu.dcache.demand_miss_latency::cpu.data 25595526000 # number of demand (read+write) miss cycles
608system.cpu.dcache.demand_miss_latency::total 25595526000 # number of demand (read+write) miss cycles
609system.cpu.dcache.overall_miss_latency::cpu.data 25595526000 # number of overall miss cycles
610system.cpu.dcache.overall_miss_latency::total 25595526000 # number of overall miss cycles
611system.cpu.dcache.ReadReq_accesses::cpu.data 23512432 # number of ReadReq accesses(hits+misses)
612system.cpu.dcache.ReadReq_accesses::total 23512432 # number of ReadReq accesses(hits+misses)
613system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses)
614system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses)
615system.cpu.dcache.SoftPFReq_accesses::cpu.data 511160 # number of SoftPFReq accesses(hits+misses)
616system.cpu.dcache.SoftPFReq_accesses::total 511160 # number of SoftPFReq accesses(hits+misses)
617system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465999 # number of LoadLockedReq accesses(hits+misses)
618system.cpu.dcache.LoadLockedReq_accesses::total 465999 # number of LoadLockedReq accesses(hits+misses)
619system.cpu.dcache.StoreCondReq_accesses::cpu.data 460218 # number of StoreCondReq accesses(hits+misses)
620system.cpu.dcache.StoreCondReq_accesses::total 460218 # number of StoreCondReq accesses(hits+misses)
621system.cpu.dcache.demand_accesses::cpu.data 42635015 # number of demand (read+write) accesses
622system.cpu.dcache.demand_accesses::total 42635015 # number of demand (read+write) accesses
623system.cpu.dcache.overall_accesses::cpu.data 43146175 # number of overall (read+write) accesses
624system.cpu.dcache.overall_accesses::total 43146175 # number of overall (read+write) accesses

604system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 # number of demand (read+write) miss cycles
605system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles
606system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles
607system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles
608system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses)
609system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses)
610system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses)
611system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses)
612system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses)
613system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses)
614system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses)
615system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses)
616system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses)
617system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses)
618system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses
619system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses
620system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses
621system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses

625system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses
626system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses
627system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses
628system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses

622system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses
623system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses
624system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses
625system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses

629system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231585 # miss rate for SoftPFReq accesses
630system.cpu.dcache.SoftPFReq_miss_rate::total 0.231585 # miss rate for SoftPFReq accesses
631system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048835 # miss rate for LoadLockedReq accesses
632system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048835 # miss rate for LoadLockedReq accesses

626system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231590 # miss rate for SoftPFReq accesses
627system.cpu.dcache.SoftPFReq_miss_rate::total 0.231590 # miss rate for SoftPFReq accesses
628system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048832 # miss rate for LoadLockedReq accesses
629system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048832 # miss rate for LoadLockedReq accesses

633system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
634system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
635system.cpu.dcache.demand_miss_rate::cpu.data 0.016386 # miss rate for demand accesses
636system.cpu.dcache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
637system.cpu.dcache.overall_miss_rate::cpu.data 0.018935 # miss rate for overall accesses
638system.cpu.dcache.overall_miss_rate::total 0.018935 # miss rate for overall accesses

630system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
631system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
632system.cpu.dcache.demand_miss_rate::cpu.data 0.016386 # miss rate for demand accesses
633system.cpu.dcache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
634system.cpu.dcache.overall_miss_rate::cpu.data 0.018935 # miss rate for overall accesses
635system.cpu.dcache.overall_miss_rate::total 0.018935 # miss rate for overall accesses

639system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372 # average ReadReq miss latency
640system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372 # average ReadReq miss latency
641system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067 # average WriteReq miss latency
642system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067 # average WriteReq miss latency
643system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709 # average LoadLockedReq miss latency
644system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709 # average LoadLockedReq miss latency

636system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16224.580658 # average ReadReq miss latency
637system.cpu.dcache.ReadReq_avg_miss_latency::total 16224.580658 # average ReadReq miss latency
638system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63944.989940 # average WriteReq miss latency
639system.cpu.dcache.WriteReq_avg_miss_latency::total 63944.989940 # average WriteReq miss latency
640system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12915.099314 # average LoadLockedReq miss latency
641system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12915.099314 # average LoadLockedReq miss latency

645system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
646system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency

642system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
643system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency

647system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107 # average overall miss latency
648system.cpu.dcache.demand_avg_miss_latency::total 36637.527107 # average overall miss latency
649system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966 # average overall miss latency
650system.cpu.dcache.overall_avg_miss_latency::total 31328.979966 # average overall miss latency
651system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked

644system.cpu.dcache.demand_avg_miss_latency::cpu.data 36628.370032 # average overall miss latency
645system.cpu.dcache.demand_avg_miss_latency::total 36628.370032 # average overall miss latency
646system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322 # average overall miss latency
647system.cpu.dcache.overall_avg_miss_latency::total 31321.035322 # average overall miss latency
648system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked

652system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

649system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

653system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked

650system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked

654system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

651system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

655system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked

652system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked

656system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
657system.cpu.dcache.fast_writes 0 # number of fast writes performed
658system.cpu.dcache.cache_copies 0 # number of cache copies performed

653system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
654system.cpu.dcache.fast_writes 0 # number of fast writes performed
655system.cpu.dcache.cache_copies 0 # number of cache copies performed

659system.cpu.dcache.writebacks::writebacks 683842 # number of writebacks
660system.cpu.dcache.writebacks::total 683842 # number of writebacks
661system.cpu.dcache.ReadReq_mshr_hits::cpu.data 930 # number of ReadReq MSHR hits
662system.cpu.dcache.ReadReq_mshr_hits::total 930 # number of ReadReq MSHR hits
663system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14247 # number of LoadLockedReq MSHR hits
664system.cpu.dcache.LoadLockedReq_mshr_hits::total 14247 # number of LoadLockedReq MSHR hits
665system.cpu.dcache.demand_mshr_hits::cpu.data 930 # number of demand (read+write) MSHR hits
666system.cpu.dcache.demand_mshr_hits::total 930 # number of demand (read+write) MSHR hits
667system.cpu.dcache.overall_mshr_hits::cpu.data 930 # number of overall MSHR hits
668system.cpu.dcache.overall_mshr_hits::total 930 # number of overall MSHR hits
669system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398981 # number of ReadReq MSHR misses
670system.cpu.dcache.ReadReq_mshr_misses::total 398981 # number of ReadReq MSHR misses
671system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298704 # number of WriteReq MSHR misses
672system.cpu.dcache.WriteReq_mshr_misses::total 298704 # number of WriteReq MSHR misses
673system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116321 # number of SoftPFReq MSHR misses
674system.cpu.dcache.SoftPFReq_mshr_misses::total 116321 # number of SoftPFReq MSHR misses

656system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks
657system.cpu.dcache.writebacks::total 683846 # number of writebacks
658system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits
659system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits
660system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14246 # number of LoadLockedReq MSHR hits
661system.cpu.dcache.LoadLockedReq_mshr_hits::total 14246 # number of LoadLockedReq MSHR hits
662system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits
663system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits
664system.cpu.dcache.overall_mshr_hits::cpu.data 929 # number of overall MSHR hits
665system.cpu.dcache.overall_mshr_hits::total 929 # number of overall MSHR hits
666system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398983 # number of ReadReq MSHR misses
667system.cpu.dcache.ReadReq_mshr_misses::total 398983 # number of ReadReq MSHR misses
668system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298709 # number of WriteReq MSHR misses
669system.cpu.dcache.WriteReq_mshr_misses::total 298709 # number of WriteReq MSHR misses
670system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116322 # number of SoftPFReq MSHR misses
671system.cpu.dcache.SoftPFReq_mshr_misses::total 116322 # number of SoftPFReq MSHR misses

675system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses
676system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses
677system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
678system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses

672system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses
673system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses
674system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
675system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses

679system.cpu.dcache.demand_mshr_misses::cpu.data 697685 # number of demand (read+write) MSHR misses
680system.cpu.dcache.demand_mshr_misses::total 697685 # number of demand (read+write) MSHR misses
681system.cpu.dcache.overall_mshr_misses::cpu.data 814006 # number of overall MSHR misses
682system.cpu.dcache.overall_mshr_misses::total 814006 # number of overall MSHR misses

676system.cpu.dcache.demand_mshr_misses::cpu.data 697692 # number of demand (read+write) MSHR misses
677system.cpu.dcache.demand_mshr_misses::total 697692 # number of demand (read+write) MSHR misses
678system.cpu.dcache.overall_mshr_misses::cpu.data 814014 # number of overall MSHR misses
679system.cpu.dcache.overall_mshr_misses::total 814014 # number of overall MSHR misses

683system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
684system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
685system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
686system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
687system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
688system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses

680system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
681system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
682system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
683system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
684system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
685system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses

689system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058107000 # number of ReadReq MSHR miss cycles
690system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058107000 # number of ReadReq MSHR miss cycles
691system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18810405000 # number of WriteReq MSHR miss cycles
692system.cpu.dcache.WriteReq_mshr_miss_latency::total 18810405000 # number of WriteReq MSHR miss cycles
693system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1614233500 # number of SoftPFReq MSHR miss cycles
694system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1614233500 # number of SoftPFReq MSHR miss cycles

686system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058749500 # number of ReadReq MSHR miss cycles
687system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058749500 # number of ReadReq MSHR miss cycles
688system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18802235000 # number of WriteReq MSHR miss cycles
689system.cpu.dcache.WriteReq_mshr_miss_latency::total 18802235000 # number of WriteReq MSHR miss cycles
690system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1616519000 # number of SoftPFReq MSHR miss cycles
691system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1616519000 # number of SoftPFReq MSHR miss cycles

695system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115353500 # number of LoadLockedReq MSHR miss cycles
696system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115353500 # number of LoadLockedReq MSHR miss cycles
697system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles
698system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles

692system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115353500 # number of LoadLockedReq MSHR miss cycles
693system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115353500 # number of LoadLockedReq MSHR miss cycles
694system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles
695system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles

699system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24868512000 # number of demand (read+write) MSHR miss cycles
700system.cpu.dcache.demand_mshr_miss_latency::total 24868512000 # number of demand (read+write) MSHR miss cycles
701system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26482745500 # number of overall MSHR miss cycles
702system.cpu.dcache.overall_mshr_miss_latency::total 26482745500 # number of overall MSHR miss cycles
703system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278172000 # number of ReadReq MSHR uncacheable cycles
704system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278172000 # number of ReadReq MSHR uncacheable cycles
705system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089977500 # number of WriteReq MSHR uncacheable cycles
706system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089977500 # number of WriteReq MSHR uncacheable cycles
707system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368149500 # number of overall MSHR uncacheable cycles
708system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368149500 # number of overall MSHR uncacheable cycles

696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24860984500 # number of demand (read+write) MSHR miss cycles
697system.cpu.dcache.demand_mshr_miss_latency::total 24860984500 # number of demand (read+write) MSHR miss cycles
698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 # number of overall MSHR miss cycles
699system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles
700system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles
701system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles
702system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles
703system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles
704system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles
705system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles

709system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses
710system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses
711system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
712system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses

706system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses
707system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses
708system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
709system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses

713system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227563 # mshr miss rate for SoftPFReq accesses
714system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227563 # mshr miss rate for SoftPFReq accesses

710system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227562 # mshr miss rate for SoftPFReq accesses
711system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227562 # mshr miss rate for SoftPFReq accesses

715system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses
716system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses
717system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
718system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
719system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016364 # mshr miss rate for demand accesses
720system.cpu.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses
721system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018866 # mshr miss rate for overall accesses
722system.cpu.dcache.overall_mshr_miss_rate::total 0.018866 # mshr miss rate for overall accesses

712system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses
713system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses
714system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
715system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
716system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016364 # mshr miss rate for demand accesses
717system.cpu.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses
718system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018866 # mshr miss rate for overall accesses
719system.cpu.dcache.overall_mshr_miss_rate::total 0.018866 # mshr miss rate for overall accesses

723system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609 # average ReadReq mshr miss latency
724system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609 # average ReadReq mshr miss latency
725system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067 # average WriteReq mshr miss latency
726system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067 # average WriteReq mshr miss latency
727system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908 # average SoftPFReq mshr miss latency
728system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908 # average SoftPFReq mshr miss latency

720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15185.482840 # average ReadReq mshr miss latency
721system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15185.482840 # average ReadReq mshr miss latency
722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62944.989940 # average WriteReq mshr miss latency
723system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62944.989940 # average WriteReq mshr miss latency
724system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13896.932652 # average SoftPFReq mshr miss latency
725system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13896.932652 # average SoftPFReq mshr miss latency

729system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879 # average LoadLockedReq mshr miss latency
730system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879 # average LoadLockedReq mshr miss latency
731system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
732system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency

726system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879 # average LoadLockedReq mshr miss latency
727system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879 # average LoadLockedReq mshr miss latency
728system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
729system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency

733system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594 # average overall mshr miss latency
734system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594 # average overall mshr miss latency
735system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574 # average overall mshr miss latency
736system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574 # average overall mshr miss latency
737system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864 # average ReadReq mshr uncacheable latency
738system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864 # average ReadReq mshr uncacheable latency
739system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458 # average WriteReq mshr uncacheable latency
740system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458 # average WriteReq mshr uncacheable latency
741system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044 # average overall mshr uncacheable latency
742system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044 # average overall mshr uncacheable latency

730system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency
731system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency
732system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency
733system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency
734system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency
735system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency
736system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency
737system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency
738system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency
739system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency

743system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

740system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

744system.cpu.icache.tags.replacements 1695565 # number of replacements
745system.cpu.icache.tags.tagsinuse 510.436866 # Cycle average of tags in use
746system.cpu.icache.tags.total_refs 113856331 # Total number of references to valid blocks.
747system.cpu.icache.tags.sampled_refs 1696077 # Sample count of references to valid blocks.
748system.cpu.icache.tags.avg_refs 67.129223 # Average number of references to valid blocks.

741system.cpu.icache.tags.replacements 1695721 # number of replacements
742system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use
743system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks.
744system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks.
745system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks.

749system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit.

746system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit.

750system.cpu.icache.tags.occ_blocks::cpu.inst 510.436866 # Average occupied blocks per requestor

747system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor

751system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy
752system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy
753system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
754system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
755system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
756system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
757system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
758system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

748system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy
749system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy
750system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
751system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
752system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
753system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
754system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
755system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

759system.cpu.icache.tags.tag_accesses 117248497 # Number of tag accesses
760system.cpu.icache.tags.data_accesses 117248497 # Number of data accesses
761system.cpu.icache.ReadReq_hits::cpu.inst 113856331 # number of ReadReq hits
762system.cpu.icache.ReadReq_hits::total 113856331 # number of ReadReq hits
763system.cpu.icache.demand_hits::cpu.inst 113856331 # number of demand (read+write) hits
764system.cpu.icache.demand_hits::total 113856331 # number of demand (read+write) hits
765system.cpu.icache.overall_hits::cpu.inst 113856331 # number of overall hits
766system.cpu.icache.overall_hits::total 113856331 # number of overall hits
767system.cpu.icache.ReadReq_misses::cpu.inst 1696083 # number of ReadReq misses
768system.cpu.icache.ReadReq_misses::total 1696083 # number of ReadReq misses
769system.cpu.icache.demand_misses::cpu.inst 1696083 # number of demand (read+write) misses
770system.cpu.icache.demand_misses::total 1696083 # number of demand (read+write) misses
771system.cpu.icache.overall_misses::cpu.inst 1696083 # number of overall misses
772system.cpu.icache.overall_misses::total 1696083 # number of overall misses
773system.cpu.icache.ReadReq_miss_latency::cpu.inst 24267960000 # number of ReadReq miss cycles
774system.cpu.icache.ReadReq_miss_latency::total 24267960000 # number of ReadReq miss cycles
775system.cpu.icache.demand_miss_latency::cpu.inst 24267960000 # number of demand (read+write) miss cycles
776system.cpu.icache.demand_miss_latency::total 24267960000 # number of demand (read+write) miss cycles
777system.cpu.icache.overall_miss_latency::cpu.inst 24267960000 # number of overall miss cycles
778system.cpu.icache.overall_miss_latency::total 24267960000 # number of overall miss cycles
779system.cpu.icache.ReadReq_accesses::cpu.inst 115552414 # number of ReadReq accesses(hits+misses)
780system.cpu.icache.ReadReq_accesses::total 115552414 # number of ReadReq accesses(hits+misses)
781system.cpu.icache.demand_accesses::cpu.inst 115552414 # number of demand (read+write) accesses
782system.cpu.icache.demand_accesses::total 115552414 # number of demand (read+write) accesses
783system.cpu.icache.overall_accesses::cpu.inst 115552414 # number of overall (read+write) accesses
784system.cpu.icache.overall_accesses::total 115552414 # number of overall (read+write) accesses
785system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses
786system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses
787system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses
788system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses
789system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses
790system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses
791system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453 # average ReadReq miss latency
792system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453 # average ReadReq miss latency
793system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency
794system.cpu.icache.demand_avg_miss_latency::total 14308.238453 # average overall miss latency
795system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency
796system.cpu.icache.overall_avg_miss_latency::total 14308.238453 # average overall miss latency

756system.cpu.icache.tags.tag_accesses 117250497 # Number of tag accesses
757system.cpu.icache.tags.data_accesses 117250497 # Number of data accesses
758system.cpu.icache.ReadReq_hits::cpu.inst 113858019 # number of ReadReq hits
759system.cpu.icache.ReadReq_hits::total 113858019 # number of ReadReq hits
760system.cpu.icache.demand_hits::cpu.inst 113858019 # number of demand (read+write) hits
761system.cpu.icache.demand_hits::total 113858019 # number of demand (read+write) hits
762system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits
763system.cpu.icache.overall_hits::total 113858019 # number of overall hits
764system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses
765system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses
766system.cpu.icache.demand_misses::cpu.inst 1696239 # number of demand (read+write) misses
767system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses
768system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses
769system.cpu.icache.overall_misses::total 1696239 # number of overall misses
770system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles
771system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles
772system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles
773system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles
774system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles
775system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles
776system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses)
777system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses)
778system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses
779system.cpu.icache.demand_accesses::total 115554258 # number of demand (read+write) accesses
780system.cpu.icache.overall_accesses::cpu.inst 115554258 # number of overall (read+write) accesses
781system.cpu.icache.overall_accesses::total 115554258 # number of overall (read+write) accesses
782system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014679 # miss rate for ReadReq accesses
783system.cpu.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses
784system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 # miss rate for demand accesses
785system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses
786system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses
787system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses
788system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency
789system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency
790system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
791system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency
792system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
793system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency

797system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
798system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
799system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
800system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
801system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
802system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
803system.cpu.icache.fast_writes 0 # number of fast writes performed
804system.cpu.icache.cache_copies 0 # number of cache copies performed

794system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
795system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
796system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
797system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
798system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
799system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
800system.cpu.icache.fast_writes 0 # number of fast writes performed
801system.cpu.icache.cache_copies 0 # number of cache copies performed

805system.cpu.icache.writebacks::writebacks 1695565 # number of writebacks
806system.cpu.icache.writebacks::total 1695565 # number of writebacks
807system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696083 # number of ReadReq MSHR misses
808system.cpu.icache.ReadReq_mshr_misses::total 1696083 # number of ReadReq MSHR misses
809system.cpu.icache.demand_mshr_misses::cpu.inst 1696083 # number of demand (read+write) MSHR misses
810system.cpu.icache.demand_mshr_misses::total 1696083 # number of demand (read+write) MSHR misses
811system.cpu.icache.overall_mshr_misses::cpu.inst 1696083 # number of overall MSHR misses
812system.cpu.icache.overall_mshr_misses::total 1696083 # number of overall MSHR misses

802system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks
803system.cpu.icache.writebacks::total 1695721 # number of writebacks
804system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses
805system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses
806system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses
807system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses
808system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses
809system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses

813system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
814system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
815system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
816system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses

810system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
811system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
812system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
813system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses

817system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22571877000 # number of ReadReq MSHR miss cycles
818system.cpu.icache.ReadReq_mshr_miss_latency::total 22571877000 # number of ReadReq MSHR miss cycles
819system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22571877000 # number of demand (read+write) MSHR miss cycles
820system.cpu.icache.demand_mshr_miss_latency::total 22571877000 # number of demand (read+write) MSHR miss cycles
821system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22571877000 # number of overall MSHR miss cycles
822system.cpu.icache.overall_mshr_miss_latency::total 22571877000 # number of overall MSHR miss cycles

814system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles
815system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles
816system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles
817system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles
818system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles
819system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles

823system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles
824system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles
825system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles
826system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles

820system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles
821system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles
822system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles
823system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles

827system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses
828system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses
829system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses
830system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses
831system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses
832system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses
833system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13308.238453 # average ReadReq mshr miss latency
834system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13308.238453 # average ReadReq mshr miss latency
835system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency
836system.cpu.icache.demand_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency
837system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency
838system.cpu.icache.overall_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency

824system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for ReadReq accesses
825system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses
826system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for demand accesses
827system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses
828system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses
829system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses
830system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency
831system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency
832system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
833system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
834system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
835system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency

839system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency
840system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
841system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
842system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
843system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

836system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency
837system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
838system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
839system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
840system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

844system.cpu.l2cache.tags.replacements 87562 # number of replacements
845system.cpu.l2cache.tags.tagsinuse 64865.195753 # Cycle average of tags in use
846system.cpu.l2cache.tags.total_refs 4544223 # Total number of references to valid blocks.
847system.cpu.l2cache.tags.sampled_refs 152797 # Sample count of references to valid blocks.
848system.cpu.l2cache.tags.avg_refs 29.740263 # Average number of references to valid blocks.

841system.cpu.l2cache.tags.replacements 87565 # number of replacements
842system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use
843system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks.
844system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks.
845system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks.

849system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

846system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

850system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494 # Average occupied blocks per requestor

847system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor

851system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor

848system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor

852system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012652 # Average occupied blocks per requestor
853system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.731977 # Average occupied blocks per requestor
854system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.980293 # Average occupied blocks per requestor
855system.cpu.l2cache.tags.occ_percent::writebacks 0.765940 # Average percentage of cache occupancy

849system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012649 # Average occupied blocks per requestor
850system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.721355 # Average occupied blocks per requestor
851system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.976923 # Average occupied blocks per requestor
852system.cpu.l2cache.tags.occ_percent::writebacks 0.765941 # Average percentage of cache occupancy

856system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
857system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
858system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy
859system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy

853system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
854system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
855system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy
856system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy

860system.cpu.l2cache.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy

857system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy

861system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
862system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id
863system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
864system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id
865system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
866system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id

858system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
859system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id
860system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
861system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id
862system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
863system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id

867system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id
868system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56201 # Occupied blocks per task id

864system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6851 # Occupied blocks per task id
865system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id

869system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
870system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id

866system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
867system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id

871system.cpu.l2cache.tags.tag_accesses 40509810 # Number of tag accesses
872system.cpu.l2cache.tags.data_accesses 40509810 # Number of data accesses
873system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7810 # number of ReadReq hits

868system.cpu.l2cache.tags.tag_accesses 40512344 # Number of tag accesses
869system.cpu.l2cache.tags.data_accesses 40512344 # Number of data accesses
870system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits

874system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits

871system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits

875system.cpu.l2cache.ReadReq_hits::total 11849 # number of ReadReq hits
876system.cpu.l2cache.WritebackDirty_hits::writebacks 683842 # number of WritebackDirty hits
877system.cpu.l2cache.WritebackDirty_hits::total 683842 # number of WritebackDirty hits
878system.cpu.l2cache.WritebackClean_hits::writebacks 1664795 # number of WritebackClean hits
879system.cpu.l2cache.WritebackClean_hits::total 1664795 # number of WritebackClean hits

872system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits
873system.cpu.l2cache.WritebackDirty_hits::writebacks 683846 # number of WritebackDirty hits
874system.cpu.l2cache.WritebackDirty_hits::total 683846 # number of WritebackDirty hits
875system.cpu.l2cache.WritebackClean_hits::writebacks 1664945 # number of WritebackClean hits
876system.cpu.l2cache.WritebackClean_hits::total 1664945 # number of WritebackClean hits

880system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
881system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits

877system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
878system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits

882system.cpu.l2cache.ReadExReq_hits::cpu.data 167026 # number of ReadExReq hits
883system.cpu.l2cache.ReadExReq_hits::total 167026 # number of ReadExReq hits
884system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678074 # number of ReadCleanReq hits
885system.cpu.l2cache.ReadCleanReq_hits::total 1678074 # number of ReadCleanReq hits
886system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511640 # number of ReadSharedReq hits
887system.cpu.l2cache.ReadSharedReq_hits::total 511640 # number of ReadSharedReq hits
888system.cpu.l2cache.demand_hits::cpu.dtb.walker 7810 # number of demand (read+write) hits

879system.cpu.l2cache.ReadExReq_hits::cpu.data 167031 # number of ReadExReq hits
880system.cpu.l2cache.ReadExReq_hits::total 167031 # number of ReadExReq hits
881system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678228 # number of ReadCleanReq hits
882system.cpu.l2cache.ReadCleanReq_hits::total 1678228 # number of ReadCleanReq hits
883system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511642 # number of ReadSharedReq hits
884system.cpu.l2cache.ReadSharedReq_hits::total 511642 # number of ReadSharedReq hits
885system.cpu.l2cache.demand_hits::cpu.dtb.walker 7807 # number of demand (read+write) hits

889system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits

886system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits

890system.cpu.l2cache.demand_hits::cpu.inst 1678074 # number of demand (read+write) hits
891system.cpu.l2cache.demand_hits::cpu.data 678666 # number of demand (read+write) hits
892system.cpu.l2cache.demand_hits::total 2368589 # number of demand (read+write) hits
893system.cpu.l2cache.overall_hits::cpu.dtb.walker 7810 # number of overall hits

887system.cpu.l2cache.demand_hits::cpu.inst 1678228 # number of demand (read+write) hits
888system.cpu.l2cache.demand_hits::cpu.data 678673 # number of demand (read+write) hits
889system.cpu.l2cache.demand_hits::total 2368747 # number of demand (read+write) hits
890system.cpu.l2cache.overall_hits::cpu.dtb.walker 7807 # number of overall hits

894system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits

891system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits

895system.cpu.l2cache.overall_hits::cpu.inst 1678074 # number of overall hits
896system.cpu.l2cache.overall_hits::cpu.data 678666 # number of overall hits
897system.cpu.l2cache.overall_hits::total 2368589 # number of overall hits

892system.cpu.l2cache.overall_hits::cpu.inst 1678228 # number of overall hits
893system.cpu.l2cache.overall_hits::cpu.data 678673 # number of overall hits
894system.cpu.l2cache.overall_hits::total 2368747 # number of overall hits

898system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
899system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
900system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses

895system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
896system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
897system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses

901system.cpu.l2cache.UpgradeReq_misses::cpu.data 2740 # number of UpgradeReq misses
902system.cpu.l2cache.UpgradeReq_misses::total 2740 # number of UpgradeReq misses

898system.cpu.l2cache.UpgradeReq_misses::cpu.data 2742 # number of UpgradeReq misses
899system.cpu.l2cache.UpgradeReq_misses::total 2742 # number of UpgradeReq misses

903system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
904system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses

900system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
901system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses

905system.cpu.l2cache.ReadExReq_misses::cpu.data 128915 # number of ReadExReq misses
906system.cpu.l2cache.ReadExReq_misses::total 128915 # number of ReadExReq misses
907system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17976 # number of ReadCleanReq misses
908system.cpu.l2cache.ReadCleanReq_misses::total 17976 # number of ReadCleanReq misses
909system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses
910system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses

902system.cpu.l2cache.ReadExReq_misses::cpu.data 128913 # number of ReadExReq misses
903system.cpu.l2cache.ReadExReq_misses::total 128913 # number of ReadExReq misses
904system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses
905system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses
906system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12173 # number of ReadSharedReq misses
907system.cpu.l2cache.ReadSharedReq_misses::total 12173 # number of ReadSharedReq misses

911system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
912system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses

908system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
909system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses

913system.cpu.l2cache.demand_misses::cpu.inst 17976 # number of demand (read+write) misses
914system.cpu.l2cache.demand_misses::cpu.data 141087 # number of demand (read+write) misses
915system.cpu.l2cache.demand_misses::total 159072 # number of demand (read+write) misses

910system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses
911system.cpu.l2cache.demand_misses::cpu.data 141086 # number of demand (read+write) misses
912system.cpu.l2cache.demand_misses::total 159073 # number of demand (read+write) misses

916system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
917system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses

913system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
914system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses

918system.cpu.l2cache.overall_misses::cpu.inst 17976 # number of overall misses
919system.cpu.l2cache.overall_misses::cpu.data 141087 # number of overall misses
920system.cpu.l2cache.overall_misses::total 159072 # number of overall misses

915system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses
916system.cpu.l2cache.overall_misses::cpu.data 141086 # number of overall misses
917system.cpu.l2cache.overall_misses::total 159073 # number of overall misses

921system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles
922system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles
923system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles

918system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles
919system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles
920system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles

924system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1857500 # number of UpgradeReq miss cycles
925system.cpu.l2cache.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles

921system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles
922system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles

926system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
927system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles

923system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
924system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles

928system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16383348000 # number of ReadExReq miss cycles
929system.cpu.l2cache.ReadExReq_miss_latency::total 16383348000 # number of ReadExReq miss cycles
930system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2349142000 # number of ReadCleanReq miss cycles
931system.cpu.l2cache.ReadCleanReq_miss_latency::total 2349142000 # number of ReadCleanReq miss cycles
932system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1612524000 # number of ReadSharedReq miss cycles
933system.cpu.l2cache.ReadSharedReq_miss_latency::total 1612524000 # number of ReadSharedReq miss cycles

925system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles
926system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles
927system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles
928system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles
929system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles
930system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles

934system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles
935system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles

931system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles
932system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles

936system.cpu.l2cache.demand_miss_latency::cpu.inst 2349142000 # number of demand (read+write) miss cycles
937system.cpu.l2cache.demand_miss_latency::cpu.data 17995872000 # number of demand (read+write) miss cycles
938system.cpu.l2cache.demand_miss_latency::total 20346237500 # number of demand (read+write) miss cycles

933system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles
934system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles
935system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles

939system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles
940system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles

936system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles
937system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles

941system.cpu.l2cache.overall_miss_latency::cpu.inst 2349142000 # number of overall miss cycles
942system.cpu.l2cache.overall_miss_latency::cpu.data 17995872000 # number of overall miss cycles
943system.cpu.l2cache.overall_miss_latency::total 20346237500 # number of overall miss cycles
944system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7817 # number of ReadReq accesses(hits+misses)

938system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles
939system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles
940system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles
941system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses)

945system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses)

942system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses)

946system.cpu.l2cache.ReadReq_accesses::total 11858 # number of ReadReq accesses(hits+misses)
947system.cpu.l2cache.WritebackDirty_accesses::writebacks 683842 # number of WritebackDirty accesses(hits+misses)
948system.cpu.l2cache.WritebackDirty_accesses::total 683842 # number of WritebackDirty accesses(hits+misses)
949system.cpu.l2cache.WritebackClean_accesses::writebacks 1664795 # number of WritebackClean accesses(hits+misses)
950system.cpu.l2cache.WritebackClean_accesses::total 1664795 # number of WritebackClean accesses(hits+misses)
951system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2763 # number of UpgradeReq accesses(hits+misses)
952system.cpu.l2cache.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses)

943system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses)
944system.cpu.l2cache.WritebackDirty_accesses::writebacks 683846 # number of WritebackDirty accesses(hits+misses)
945system.cpu.l2cache.WritebackDirty_accesses::total 683846 # number of WritebackDirty accesses(hits+misses)
946system.cpu.l2cache.WritebackClean_accesses::writebacks 1664945 # number of WritebackClean accesses(hits+misses)
947system.cpu.l2cache.WritebackClean_accesses::total 1664945 # number of WritebackClean accesses(hits+misses)
948system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses)
949system.cpu.l2cache.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses)

953system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
954system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)

950system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
951system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)

955system.cpu.l2cache.ReadExReq_accesses::cpu.data 295941 # number of ReadExReq accesses(hits+misses)
956system.cpu.l2cache.ReadExReq_accesses::total 295941 # number of ReadExReq accesses(hits+misses)
957system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696050 # number of ReadCleanReq accesses(hits+misses)
958system.cpu.l2cache.ReadCleanReq_accesses::total 1696050 # number of ReadCleanReq accesses(hits+misses)
959system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523812 # number of ReadSharedReq accesses(hits+misses)
960system.cpu.l2cache.ReadSharedReq_accesses::total 523812 # number of ReadSharedReq accesses(hits+misses)
961system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7817 # number of demand (read+write) accesses

952system.cpu.l2cache.ReadExReq_accesses::cpu.data 295944 # number of ReadExReq accesses(hits+misses)
953system.cpu.l2cache.ReadExReq_accesses::total 295944 # number of ReadExReq accesses(hits+misses)
954system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696206 # number of ReadCleanReq accesses(hits+misses)
955system.cpu.l2cache.ReadCleanReq_accesses::total 1696206 # number of ReadCleanReq accesses(hits+misses)
956system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523815 # number of ReadSharedReq accesses(hits+misses)
957system.cpu.l2cache.ReadSharedReq_accesses::total 523815 # number of ReadSharedReq accesses(hits+misses)
958system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7814 # number of demand (read+write) accesses

962system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses

959system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses

963system.cpu.l2cache.demand_accesses::cpu.inst 1696050 # number of demand (read+write) accesses
964system.cpu.l2cache.demand_accesses::cpu.data 819753 # number of demand (read+write) accesses
965system.cpu.l2cache.demand_accesses::total 2527661 # number of demand (read+write) accesses
966system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7817 # number of overall (read+write) accesses

960system.cpu.l2cache.demand_accesses::cpu.inst 1696206 # number of demand (read+write) accesses
961system.cpu.l2cache.demand_accesses::cpu.data 819759 # number of demand (read+write) accesses
962system.cpu.l2cache.demand_accesses::total 2527820 # number of demand (read+write) accesses
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975system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses

971system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991682 # miss rate for UpgradeReq accesses
972system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses

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978system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses

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995system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency
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991system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286 # average ReadReq miss latency
992system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency
993system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency

997system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 677.919708 # average UpgradeReq miss latency
998system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 677.919708 # average UpgradeReq miss latency

994system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency
995system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency

999system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
1000system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency

996system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
997system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency

1001system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127086.436799 # average ReadExReq miss latency
1002system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127086.436799 # average ReadExReq miss latency
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1004system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731 # average ReadCleanReq miss latency
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1006system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566 # average ReadSharedReq miss latency

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1001system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency
1002system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency
1003system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency

1007system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
1008system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency

1004system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
1005system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency

1009system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency
1010system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency
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1006system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
1007system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency
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1012system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
1013system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency

1009system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency
1010system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency

1014system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency
1015system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency
1016system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237 # average overall miss latency

1011system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
1012system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency
1013system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency

1017system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1018system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1019system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1020system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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1022system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1023system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1024system.cpu.l2cache.cache_copies 0 # number of cache copies performed

1014system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1015system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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1017system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1018system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1019system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1020system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1021system.cpu.l2cache.cache_copies 0 # number of cache copies performed

1025system.cpu.l2cache.writebacks::writebacks 81183 # number of writebacks
1026system.cpu.l2cache.writebacks::total 81183 # number of writebacks

1022system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks
1023system.cpu.l2cache.writebacks::total 81185 # number of writebacks

1027system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
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1026system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses

1030system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2740 # number of UpgradeReq MSHR misses
1031system.cpu.l2cache.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses

1027system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses
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1032system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
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1029system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1030system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses

1034system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128915 # number of ReadExReq MSHR misses
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1051system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
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1056system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
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1059system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles
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1059system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186544500 # number of UpgradeReq MSHR miss cycles

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1065system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15094198000 # number of ReadExReq MSHR miss cycles
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1078system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2169382000 # number of overall MSHR miss cycles
1079system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16585002000 # number of overall MSHR miss cycles
1080system.cpu.l2cache.overall_mshr_miss_latency::total 18755517500 # number of overall MSHR miss cycles

1075system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles
1076system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles
1077system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles

1081system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles

1078system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles

1082system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888826500 # number of ReadReq MSHR uncacheable cycles
1083system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918592500 # number of ReadReq MSHR uncacheable cycles
1084system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574000 # number of WriteReq MSHR uncacheable cycles
1085system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574000 # number of WriteReq MSHR uncacheable cycles

1079system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles
1080system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles
1081system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles
1082system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles

1086system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles

1083system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles

1087system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661400500 # number of overall MSHR uncacheable cycles
1088system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691166500 # number of overall MSHR uncacheable cycles
1089system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses

1084system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles
1085system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles
1086system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses

1090system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
1091system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses

1087system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
1088system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses

1092system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 # mshr miss rate for UpgradeReq accesses
1093system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses

1089system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses
1090system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses

1094system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1095system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses

1091system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1092system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses

1096system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435610 # mshr miss rate for ReadExReq accesses
1097system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435610 # mshr miss rate for ReadExReq accesses

1093system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435599 # mshr miss rate for ReadExReq accesses
1094system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435599 # mshr miss rate for ReadExReq accesses

1098system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses
1099system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses

1095system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses
1096system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses

1100system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023237 # mshr miss rate for ReadSharedReq accesses
1101system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023237 # mshr miss rate for ReadSharedReq accesses
1102system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses

1097system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023239 # mshr miss rate for ReadSharedReq accesses
1098system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses
1099system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses

1103system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses
1104system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses

1100system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses
1101system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses

1105system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for demand accesses
1106system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses
1107system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses

1102system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for demand accesses
1103system.cpu.l2cache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses
1104system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses

1108system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses
1109system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses

1105system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses
1106system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses

1110system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for overall accesses
1111system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses

1107system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for overall accesses
1108system.cpu.l2cache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses

1112system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency
1113system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency
1114system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency

1109system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency
1110system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency
1111system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency

1115system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080 # average UpgradeReq mshr miss latency
1116system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080 # average UpgradeReq mshr miss latency

1112system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711 # average UpgradeReq mshr miss latency
1113system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711 # average UpgradeReq mshr miss latency

1117system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
1118system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency

1114system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
1115system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency

1119system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799 # average ReadExReq mshr miss latency
1120system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799 # average ReadExReq mshr miss latency
1121system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731 # average ReadCleanReq mshr miss latency
1122system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731 # average ReadCleanReq mshr miss latency
1123system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566 # average ReadSharedReq mshr miss latency
1124system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566 # average ReadSharedReq mshr miss latency

1116system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency
1117system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency
1118system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency
1119system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency
1120system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency
1121system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency

1125system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
1126system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency

1122system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
1123system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency

1127system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency
1128system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency
1129system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency

1124system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
1125system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency
1126system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency

1130system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
1131system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency

1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency
1128system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency

1132system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency
1133system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency
1134system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency

1129system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
1130system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency
1131system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency

1135system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency

1132system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency

1136system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994 # average ReadReq mshr uncacheable latency
1137system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661 # average ReadReq mshr uncacheable latency
1138system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435 # average WriteReq mshr uncacheable latency
1139system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435 # average WriteReq mshr uncacheable latency

1133system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency
1134system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency
1135system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency
1136system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency

1140system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency

1137system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency

1141system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460 # average overall mshr uncacheable latency
1142system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271 # average overall mshr uncacheable latency

1138system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency
1139system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency

1143system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1140system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1144system.cpu.toL2Bus.snoop_filter.tot_requests 5052537 # Total number of requests made to the snoop filter.
1145system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536723 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1146system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

1141system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter.
1142system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1143system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

1147system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter.
1148system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1149system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1150system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution

1144system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter.
1145system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1146system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1147system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution

1151system.cpu.toL2Bus.trans_dist::ReadResp 2287321 # Transaction distribution

1148system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution

1152system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
1153system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution

1149system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
1150system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution

1154system.cpu.toL2Bus.trans_dist::WritebackDirty 801217 # Transaction distribution
1155system.cpu.toL2Bus.trans_dist::WritebackClean 1664795 # Transaction distribution
1156system.cpu.toL2Bus.trans_dist::CleanEvict 134627 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution

1151system.cpu.toL2Bus.trans_dist::WritebackDirty 801231 # Transaction distribution
1152system.cpu.toL2Bus.trans_dist::WritebackClean 1695721 # Transaction distribution
1153system.cpu.toL2Bus.trans_dist::CleanEvict 141985 # Transaction distribution
1154system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution

1158system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution

1155system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution

1159system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution
1160system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution
1161system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution
1162system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696083 # Transaction distribution
1163system.cpu.toL2Bus.trans_dist::ReadSharedReq 524040 # Transaction distribution

1156system.cpu.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::ReadExReq 295944 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::ReadExResp 295944 # Transaction distribution
1159system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696239 # Transaction distribution
1160system.cpu.toL2Bus.trans_dist::ReadSharedReq 524043 # Transaction distribution

1164system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution

1161system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution

1165system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074972 # Packet count per connected master and slave (bytes)
1166system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574565 # Packet count per connected master and slave (bytes)

1162system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5106210 # Packet count per connected master and slave (bytes)
1163system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581942 # Packet count per connected master and slave (bytes)

1167system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes)

1164system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes)

1168system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25654 # Packet count per connected master and slave (bytes)
1169system.cpu.toL2Bus.pkt_count::total 7688448 # Packet count per connected master and slave (bytes)
1170system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215130168 # Cumulative packet size per connected master and slave (bytes)
1171system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96426845 # Cumulative packet size per connected master and slave (bytes)

1165system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25651 # Packet count per connected master and slave (bytes)
1166system.cpu.toL2Bus.pkt_count::total 7727060 # Packet count per connected master and slave (bytes)
1167system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217119416 # Cumulative packet size per connected master and slave (bytes)
1168system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96427485 # Cumulative packet size per connected master and slave (bytes)

1172system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes)

1169system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes)

1173system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31268 # Cumulative packet size per connected master and slave (bytes)
1174system.cpu.toL2Bus.pkt_size::total 311604445 # Cumulative packet size per connected master and slave (bytes)
1175system.cpu.toL2Bus.snoops 175875 # Total snoops (count)
1176system.cpu.toL2Bus.snoop_fanout::samples 2773837 # Request fanout histogram
1177system.cpu.toL2Bus.snoop_fanout::mean 0.020867 # Request fanout histogram
1178system.cpu.toL2Bus.snoop_fanout::stdev 0.142939 # Request fanout histogram

1170system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31256 # Cumulative packet size per connected master and slave (bytes)
1171system.cpu.toL2Bus.pkt_size::total 313594321 # Cumulative packet size per connected master and slave (bytes)
1172system.cpu.toL2Bus.snoops 175889 # Total snoops (count)
1173system.cpu.toL2Bus.snoop_fanout::samples 2774012 # Request fanout histogram
1174system.cpu.toL2Bus.snoop_fanout::mean 0.020868 # Request fanout histogram
1175system.cpu.toL2Bus.snoop_fanout::stdev 0.142944 # Request fanout histogram

1179system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1176system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1180system.cpu.toL2Bus.snoop_fanout::0 2715955 97.91% 97.91% # Request fanout histogram
1181system.cpu.toL2Bus.snoop_fanout::1 57882 2.09% 100.00% # Request fanout histogram

1177system.cpu.toL2Bus.snoop_fanout::0 2716123 97.91% 97.91% # Request fanout histogram
1178system.cpu.toL2Bus.snoop_fanout::1 57889 2.09% 100.00% # Request fanout histogram

1182system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1183system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1184system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1185system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

1179system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1180system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1181system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1182system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

1186system.cpu.toL2Bus.snoop_fanout::total 2773837 # Request fanout histogram
1187system.cpu.toL2Bus.reqLayer0.occupancy 4957294000 # Layer occupancy (ticks)

1183system.cpu.toL2Bus.snoop_fanout::total 2774012 # Request fanout histogram
1184system.cpu.toL2Bus.reqLayer0.occupancy 4957617000 # Layer occupancy (ticks)

1188system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)

1185system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)

1189system.cpu.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks)

1186system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks)

1190system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

1187system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

1191system.cpu.toL2Bus.respLayer0.occupancy 2553146500 # Layer occupancy (ticks)

1188system.cpu.toL2Bus.respLayer0.occupancy 2553380500 # Layer occupancy (ticks)

1192system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1189system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1193system.cpu.toL2Bus.respLayer1.occupancy 1275944500 # Layer occupancy (ticks)

1190system.cpu.toL2Bus.respLayer1.occupancy 1275954500 # Layer occupancy (ticks)

1194system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1195system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
1196system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1197system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks)
1198system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1199system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
1200system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
1201system.iobus.trans_dist::WriteReq 59014 # Transaction distribution

--- 39 unchanged lines hidden (view full) ---

1241system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1242system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1243system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1244system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1245system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1246system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes)
1247system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes)
1248system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes)

1191system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1192system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
1193system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1194system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks)
1195system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1196system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
1197system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
1198system.iobus.trans_dist::WriteReq 59014 # Transaction distribution

--- 39 unchanged lines hidden (view full) ---

1238system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1239system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1240system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1241system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1242system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1243system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes)
1244system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes)
1245system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes)

1249system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks)

1246system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks)

1250system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1251system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
1252system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1253system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
1254system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1255system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
1256system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1257system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)

--- 17 unchanged lines hidden (view full) ---

1275system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks)
1276system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1277system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
1278system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1279system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
1280system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1281system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
1282system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)

1247system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1248system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
1249system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1250system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
1251system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1252system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
1253system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1254system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)

--- 17 unchanged lines hidden (view full) ---

1272system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks)
1273system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1274system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
1275system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1276system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
1277system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1278system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
1279system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)

1283system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks)

1280system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks)

1284system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1285system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks)
1286system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)

1281system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1282system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks)
1283system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)

1287system.iobus.reqLayer25.occupancy 186221548 # Layer occupancy (ticks)

1284system.iobus.reqLayer25.occupancy 187058527 # Layer occupancy (ticks)

1288system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1289system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1290system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1291system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
1292system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1293system.iocache.tags.replacements 36418 # number of replacements

1285system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1286system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1287system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1288system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
1289system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1290system.iocache.tags.replacements 36418 # number of replacements

1294system.iocache.tags.tagsinuse 1.084130 # Cycle average of tags in use

1291system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use

1295system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1296system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks.
1297system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.

1292system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1293system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks.
1294system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.

1298system.iocache.tags.warmup_cycle 313812613000 # Cycle when the warmup percentage was hit.
1299system.iocache.tags.occ_blocks::realview.ide 1.084130 # Average occupied blocks per requestor
1300system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy
1301system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy

1295system.iocache.tags.warmup_cycle 313812610000 # Cycle when the warmup percentage was hit.
1296system.iocache.tags.occ_blocks::realview.ide 1.084082 # Average occupied blocks per requestor
1297system.iocache.tags.occ_percent::realview.ide 0.067755 # Average percentage of cache occupancy
1298system.iocache.tags.occ_percent::total 0.067755 # Average percentage of cache occupancy

1302system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1303system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1304system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1305system.iocache.tags.tag_accesses 328068 # Number of tag accesses
1306system.iocache.tags.data_accesses 328068 # Number of data accesses
1307system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
1308system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
1309system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1310system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1311system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
1312system.iocache.demand_misses::total 228 # number of demand (read+write) misses
1313system.iocache.overall_misses::realview.ide 228 # number of overall misses
1314system.iocache.overall_misses::total 228 # number of overall misses

1299system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1300system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1301system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1302system.iocache.tags.tag_accesses 328068 # Number of tag accesses
1303system.iocache.tags.data_accesses 328068 # Number of data accesses
1304system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
1305system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
1306system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1307system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1308system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
1309system.iocache.demand_misses::total 228 # number of demand (read+write) misses
1310system.iocache.overall_misses::realview.ide 228 # number of overall misses
1311system.iocache.overall_misses::total 228 # number of overall misses

1315system.iocache.ReadReq_miss_latency::realview.ide 28228376 # number of ReadReq miss cycles
1316system.iocache.ReadReq_miss_latency::total 28228376 # number of ReadReq miss cycles
1317system.iocache.WriteLineReq_miss_latency::realview.ide 4717653172 # number of WriteLineReq miss cycles
1318system.iocache.WriteLineReq_miss_latency::total 4717653172 # number of WriteLineReq miss cycles
1319system.iocache.demand_miss_latency::realview.ide 28228376 # number of demand (read+write) miss cycles
1320system.iocache.demand_miss_latency::total 28228376 # number of demand (read+write) miss cycles
1321system.iocache.overall_miss_latency::realview.ide 28228376 # number of overall miss cycles
1322system.iocache.overall_miss_latency::total 28228376 # number of overall miss cycles

1312system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles
1313system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles
1314system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles
1315system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles
1316system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles
1317system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles
1318system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles
1319system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles

1323system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
1324system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
1325system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1326system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1327system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
1328system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
1329system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
1330system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
1331system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1332system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1333system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1334system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1335system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1336system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1337system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1338system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses

1320system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
1321system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
1322system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1323system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1324system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
1325system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
1326system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
1327system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
1328system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1329system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1330system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1331system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1332system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1333system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1334system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1335system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses

1339system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667 # average ReadReq miss latency
1340system.iocache.ReadReq_avg_miss_latency::total 123808.666667 # average ReadReq miss latency
1341system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807 # average WriteLineReq miss latency
1342system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807 # average WriteLineReq miss latency
1343system.iocache.demand_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency
1344system.iocache.demand_avg_miss_latency::total 123808.666667 # average overall miss latency
1345system.iocache.overall_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency
1346system.iocache.overall_avg_miss_latency::total 123808.666667 # average overall miss latency
1347system.iocache.blocked_cycles::no_mshrs 910 # number of cycles access was blocked

1336system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency
1337system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency
1338system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency
1339system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency
1340system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
1341system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency
1342system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
1343system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency
1344system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

1348system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1345system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1349system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked

1346system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked

1350system.iocache.blocked::no_targets 0 # number of cycles access was blocked

1347system.iocache.blocked::no_targets 0 # number of cycles access was blocked

1351system.iocache.avg_blocked_cycles::no_mshrs 11.234568 # average number of cycles each access was blocked

1348system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

1352system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1353system.iocache.fast_writes 0 # number of fast writes performed
1354system.iocache.cache_copies 0 # number of cache copies performed
1355system.iocache.writebacks::writebacks 36190 # number of writebacks
1356system.iocache.writebacks::total 36190 # number of writebacks
1357system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
1358system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
1359system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1360system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1361system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
1362system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
1363system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
1364system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses

1349system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1350system.iocache.fast_writes 0 # number of fast writes performed
1351system.iocache.cache_copies 0 # number of cache copies performed
1352system.iocache.writebacks::writebacks 36190 # number of writebacks
1353system.iocache.writebacks::total 36190 # number of writebacks
1354system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
1355system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
1356system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1357system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1358system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
1359system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
1360system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
1361system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses

1365system.iocache.ReadReq_mshr_miss_latency::realview.ide 16828376 # number of ReadReq MSHR miss cycles
1366system.iocache.ReadReq_mshr_miss_latency::total 16828376 # number of ReadReq MSHR miss cycles
1367system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906453172 # number of WriteLineReq MSHR miss cycles
1368system.iocache.WriteLineReq_mshr_miss_latency::total 2906453172 # number of WriteLineReq MSHR miss cycles
1369system.iocache.demand_mshr_miss_latency::realview.ide 16828376 # number of demand (read+write) MSHR miss cycles
1370system.iocache.demand_mshr_miss_latency::total 16828376 # number of demand (read+write) MSHR miss cycles
1371system.iocache.overall_mshr_miss_latency::realview.ide 16828376 # number of overall MSHR miss cycles
1372system.iocache.overall_mshr_miss_latency::total 16828376 # number of overall MSHR miss cycles

1362system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles
1363system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles
1364system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles
1365system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles
1366system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles
1367system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles
1368system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles
1369system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles

1373system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1374system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1375system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1376system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1377system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1378system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1379system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1380system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses

1370system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1371system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1372system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1373system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1374system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1375system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1376system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1377system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses

1381system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667 # average ReadReq mshr miss latency
1382system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667 # average ReadReq mshr miss latency
1383system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807 # average WriteLineReq mshr miss latency
1384system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807 # average WriteLineReq mshr miss latency
1385system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency
1386system.iocache.demand_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency
1387system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency
1388system.iocache.overall_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency

1378system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency
1379system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency
1380system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency
1381system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency
1382system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
1383system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
1384system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
1385system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency

1389system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1390system.membus.trans_dist::ReadReq 40160 # Transaction distribution

1386system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1387system.membus.trans_dist::ReadReq 40160 # Transaction distribution

1391system.membus.trans_dist::ReadResp 70545 # Transaction distribution

1388system.membus.trans_dist::ReadResp 70548 # Transaction distribution

1392system.membus.trans_dist::WriteReq 27589 # Transaction distribution
1393system.membus.trans_dist::WriteResp 27589 # Transaction distribution

1389system.membus.trans_dist::WriteReq 27589 # Transaction distribution
1390system.membus.trans_dist::WriteResp 27589 # Transaction distribution

1394system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution
1395system.membus.trans_dist::CleanEvict 6392 # Transaction distribution

1391system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution
1392system.membus.trans_dist::CleanEvict 6608 # Transaction distribution

1396system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution
1397system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution

1393system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution
1394system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution

1398system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution

1395system.membus.trans_dist::UpgradeResp 2 # Transaction distribution

1399system.membus.trans_dist::ReadExReq 127158 # Transaction distribution
1400system.membus.trans_dist::ReadExResp 127158 # Transaction distribution

1396system.membus.trans_dist::ReadExReq 127158 # Transaction distribution
1397system.membus.trans_dist::ReadExResp 127158 # Transaction distribution

1401system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution

1398system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution

1402system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution

1399system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution

1403system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution

1404system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1405system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
1406system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)

1400system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1401system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
1402system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)

1407system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438817 # Packet count per connected master and slave (bytes)
1408system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546409 # Packet count per connected master and slave (bytes)
1409system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes)
1410system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes)
1411system.membus.pkt_count::total 655303 # Packet count per connected master and slave (bytes)

1403system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 434329 # Packet count per connected master and slave (bytes)
1404system.membus.pkt_count_system.cpu.l2cache.mem_side::total 541921 # Packet count per connected master and slave (bytes)
1405system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes)
1406system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes)
1407system.membus.pkt_count::total 614806 # Packet count per connected master and slave (bytes)

1412system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1413system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
1414system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)

1408system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1409system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
1410system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)

1415system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes)
1416system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes)

1411system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302332 # Cumulative packet size per connected master and slave (bytes)
1412system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465685 # Cumulative packet size per connected master and slave (bytes)

1417system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1418system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)

1413system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1414system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)

1419system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes)

1415system.membus.pkt_size::total 17782805 # Cumulative packet size per connected master and slave (bytes)

1420system.membus.snoops 492 # Total snoops (count)

1416system.membus.snoops 492 # Total snoops (count)

1421system.membus.snoop_fanout::samples 389997 # Request fanout histogram

1417system.membus.snoop_fanout::samples 390011 # Request fanout histogram

1422system.membus.snoop_fanout::mean 1 # Request fanout histogram
1423system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1424system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1425system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1418system.membus.snoop_fanout::mean 1 # Request fanout histogram
1419system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1420system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1421system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1426system.membus.snoop_fanout::1 389997 100.00% 100.00% # Request fanout histogram

1422system.membus.snoop_fanout::1 390011 100.00% 100.00% # Request fanout histogram

1427system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1428system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1429system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1430system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1423system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1424system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1425system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1426system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1431system.membus.snoop_fanout::total 389997 # Request fanout histogram
1432system.membus.reqLayer0.occupancy 90470000 # Layer occupancy (ticks)

1427system.membus.snoop_fanout::total 390011 # Request fanout histogram
1428system.membus.reqLayer0.occupancy 90460500 # Layer occupancy (ticks)

1433system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1434system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1435system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)

1429system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1430system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1431system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)

1436system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks)

1432system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks)

1437system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)

1433system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)

1438system.membus.reqLayer5.occupancy 823068661 # Layer occupancy (ticks)

1434system.membus.reqLayer5.occupancy 823136860 # Layer occupancy (ticks)

1439system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)

1435system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)

1440system.membus.respLayer2.occupancy 952238748 # Layer occupancy (ticks)

1436system.membus.respLayer2.occupancy 943248500 # Layer occupancy (ticks)

1441system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1437system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1442system.membus.respLayer3.occupancy 64113741 # Layer occupancy (ticks)

1438system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks)