| stats.txt (10726:8a20e2a1562d) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.903548 # Number of seconds simulated 4sim_ticks 2903547931500 # Number of ticks simulated 5final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.903548 # Number of seconds simulated 4sim_ticks 2903547931500 # Number of ticks simulated 5final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 732027 # Simulator instruction rate (inst/s) 8host_op_rate 882601 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18897780106 # Simulator tick rate (ticks/s) 10host_mem_usage 614620 # Number of bytes of host memory used 11host_seconds 153.65 # Real time elapsed on the host | 7host_inst_rate 571103 # Simulator instruction rate (inst/s) 8host_op_rate 688575 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14743405801 # Simulator tick rate (ticks/s) 10host_mem_usage 560940 # Number of bytes of host memory used 11host_seconds 196.94 # Real time elapsed on the host |
| 12sim_insts 112472279 # Number of instructions simulated 13sim_ops 135607130 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory --- 662 unchanged lines hidden (view full) --- 682system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses 683system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses 684system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 685system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses | 12sim_insts 112472279 # Number of instructions simulated 13sim_ops 135607130 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory --- 662 unchanged lines hidden (view full) --- 682system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses 683system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses 684system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 685system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses |
| 690system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 691system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable 692system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 693system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 694system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 695system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses |
|
| 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles 695system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles 696system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles 697system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles --- 32 unchanged lines hidden (view full) --- 730system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency 731system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency 732system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 733system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 734system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency 735system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency 736system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency 737system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency | 696system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles 697system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles 698system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles 699system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles 700system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles 701system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles 702system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles 703system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles --- 32 unchanged lines hidden (view full) --- 736system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency 737system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency 738system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 739system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 740system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency 741system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency 742system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency 743system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency |
| 738system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 739system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 740system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 741system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 742system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 743system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 744system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187331.540240 # average ReadReq mshr uncacheable latency 745system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187331.540240 # average ReadReq mshr uncacheable latency 746system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163580.847439 # average WriteReq mshr uncacheable latency 747system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163580.847439 # average WriteReq mshr uncacheable latency 748system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176173.846783 # average overall mshr uncacheable latency 749system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176173.846783 # average overall mshr uncacheable latency |
| 744system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.icache.tags.replacements 1698619 # number of replacements 746system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use 747system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks. 748system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks. 749system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks. 750system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit. 751system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor --- 52 unchanged lines hidden (view full) --- 804system.cpu.icache.fast_writes 0 # number of fast writes performed 805system.cpu.icache.cache_copies 0 # number of cache copies performed 806system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses 807system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses 808system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses 809system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses 810system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses 811system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses | 750system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 751system.cpu.icache.tags.replacements 1698619 # number of replacements 752system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use 753system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks. 754system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks. 755system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks. 756system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit. 757system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor --- 52 unchanged lines hidden (view full) --- 810system.cpu.icache.fast_writes 0 # number of fast writes performed 811system.cpu.icache.cache_copies 0 # number of cache copies performed 812system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses 813system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses 814system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses 815system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses 816system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses 817system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses |
| 818system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 819system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 820system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 821system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses |
|
| 812system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles 813system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles 814system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles 815system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles 816system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles 817system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles 818system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles 819system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 826system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses 827system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses 828system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency 829system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency 830system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency 831system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency 832system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency 833system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency | 822system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles 823system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles 824system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles 825system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles 826system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles 827system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles 828system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles 829system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 836system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses 837system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses 838system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency 839system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency 840system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency 841system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency 842system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency 843system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency |
| 834system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 835system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 836system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 837system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 844system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average ReadReq mshr uncacheable latency 845system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency 846system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average overall mshr uncacheable latency 847system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency |
| 838system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 839system.cpu.l2cache.tags.replacements 89783 # number of replacements 840system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use 841system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks. 842system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks. 843system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks. 844system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 845system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor --- 173 unchanged lines hidden (view full) --- 1019system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses 1020system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses 1021system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses 1022system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses 1023system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1024system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses 1025system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses 1026system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses | 848system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 849system.cpu.l2cache.tags.replacements 89783 # number of replacements 850system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use 851system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks. 852system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks. 853system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks. 854system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 855system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor --- 173 unchanged lines hidden (view full) --- 1029system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses 1030system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses 1031system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses 1032system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses 1033system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1034system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses 1035system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses 1036system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses |
| 1037system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable 1038system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable 1039system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable 1040system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable 1041system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable 1042system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses 1043system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses 1044system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses |
|
| 1027system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles 1028system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles 1029system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles 1030system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles 1031system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles 1032system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles 1033system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles 1034system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles --- 55 unchanged lines hidden (view full) --- 1090system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency 1091system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency 1092system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency 1093system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency 1094system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency 1095system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency 1096system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency 1097system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency | 1045system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles 1046system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles 1047system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles 1048system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles 1049system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles 1050system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles 1051system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles 1052system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles --- 55 unchanged lines hidden (view full) --- 1108system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency 1109system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency 1110system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency 1111system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency 1112system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency 1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency 1114system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency 1115system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency |
| 1098system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1099system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1100system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1101system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1102system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1103system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1104system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1105system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1116system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average ReadReq mshr uncacheable latency 1117system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173318.092042 # average ReadReq mshr uncacheable latency 1118system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147983.478586 # average ReadReq mshr uncacheable latency 1119system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150576.987205 # average WriteReq mshr uncacheable latency 1120system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150576.987205 # average WriteReq mshr uncacheable latency 1121system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average overall mshr uncacheable latency 1122system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162634.686771 # average overall mshr uncacheable latency 1123system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149039.616821 # average overall mshr uncacheable latency |
| 1106system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1107system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution 1108system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution 1109system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1110system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution 1111system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution 1112system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution 1113system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution --- 7 unchanged lines hidden (view full) --- 1121system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes) 1122system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes) 1123system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes) 1124system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes) 1125system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes) 1126system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) 1127system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) 1128system.cpu.toL2Bus.snoops 53413 # Total snoops (count) | 1124system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1125system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution 1129system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution 1130system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution --- 7 unchanged lines hidden (view full) --- 1139system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes) 1140system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes) 1141system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes) 1143system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes) 1144system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) 1145system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) 1146system.cpu.toL2Bus.snoops 53413 # Total snoops (count) |
| 1129system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram 1130system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram 1131system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram | 1147system.cpu.toL2Bus.snoop_fanout::samples 3338113 # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::mean 1.019032 # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::stdev 0.136637 # Request fanout histogram |
| 1132system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1133system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1150system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1134system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1135system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1136system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram | 1152system.cpu.toL2Bus.snoop_fanout::1 3274582 98.10% 98.10% # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::2 63531 1.90% 100.00% # Request fanout histogram |
| 1138system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1154system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1139system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1140system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram | 1155system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1156system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::total 3338113 # Request fanout histogram |
| 1142system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) 1143system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1144system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1145system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1146system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks) 1147system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1148system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks) 1149system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 225 unchanged lines hidden (view full) --- 1375system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1376system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) 1377system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes) 1378system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes) 1379system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1380system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 1381system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) 1382system.membus.snoops 498 # Total snoops (count) | 1158system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) 1159system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1160system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1161system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1162system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks) 1163system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1164system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks) 1165system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 225 unchanged lines hidden (view full) --- 1391system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1392system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) 1393system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes) 1394system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes) 1395system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1396system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 1397system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) 1398system.membus.snoops 498 # Total snoops (count) |
| 1383system.membus.snoop_fanout::samples 319985 # Request fanout histogram | 1399system.membus.snoop_fanout::samples 387734 # Request fanout histogram |
| 1384system.membus.snoop_fanout::mean 1 # Request fanout histogram 1385system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1386system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1387system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1400system.membus.snoop_fanout::mean 1 # Request fanout histogram 1401system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1402system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1403system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1388system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram | 1404system.membus.snoop_fanout::1 387734 100.00% 100.00% # Request fanout histogram |
| 1389system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1390system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1391system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1392system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1405system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1406system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1407system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1408system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1393system.membus.snoop_fanout::total 319985 # Request fanout histogram | 1409system.membus.snoop_fanout::total 387734 # Request fanout histogram |
| 1394system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) 1395system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1396system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1397system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1398system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) 1399system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1400system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks) 1401system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 37 unchanged lines hidden --- | 1410system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) 1411system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1412system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1413system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1414system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) 1415system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1416system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks) 1417system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 37 unchanged lines hidden --- |