| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.902862 # Number of seconds simulated 4sim_ticks 2902861767000 # Number of ticks simulated 5final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.903548 # Number of seconds simulated 4sim_ticks 2903547931500 # Number of ticks simulated 5final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 747193 # Simulator instruction rate (inst/s) 8host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19275657141 # Simulator tick rate (ticks/s) 10host_mem_usage 615228 # Number of bytes of host memory used 11host_seconds 150.60 # Real time elapsed on the host 12sim_insts 112525269 # Number of instructions simulated 13sim_ops 135672104 # Number of ops (including micro ops) simulated | 7host_inst_rate 732027 # Simulator instruction rate (inst/s) 8host_op_rate 882601 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18897780106 # Simulator tick rate (ticks/s) 10host_mem_usage 614620 # Number of bytes of host memory used 11host_seconds 153.65 # Real time elapsed on the host 12sim_insts 112472279 # Number of instructions simulated 13sim_ops 135607130 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory | 26system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory |
| 27system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory | 32system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory | 35system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) | 40system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) | 48system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) | 50system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s) |
| 52system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) | 52system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 168015 # Number of read requests accepted 55system.physmem.writeReqs 158980 # Number of write requests accepted 56system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 9689 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9230 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10198 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10267 # Per bank write bursts 70system.physmem.perBankRdBursts::4 18984 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10226 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10551 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10350 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9702 # Per bank write bursts 75system.physmem.perBankRdBursts::9 9930 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9908 # Per bank write bursts 77system.physmem.perBankRdBursts::11 8848 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9929 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10408 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9925 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9750 # Per bank write bursts 82system.physmem.perBankWrBursts::0 9389 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8975 # Per bank write bursts 84system.physmem.perBankWrBursts::2 10251 # Per bank write bursts 85system.physmem.perBankWrBursts::3 9953 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9418 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9499 # Per bank write bursts 88system.physmem.perBankWrBursts::6 9770 # Per bank write bursts 89system.physmem.perBankWrBursts::7 9764 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9682 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9836 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9791 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9091 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9681 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9852 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9372 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9026 # Per bank write bursts | 53system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 168876 # Number of read requests accepted 55system.physmem.writeReqs 160010 # Number of write requests accepted 56system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10030 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9665 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10302 # Per bank write bursts 69system.physmem.perBankRdBursts::3 9920 # Per bank write bursts 70system.physmem.perBankRdBursts::4 18863 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10093 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10296 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10601 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9928 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10198 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9956 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9036 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9857 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10481 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9974 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9528 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8313 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8253 # Per bank write bursts 84system.physmem.perBankWrBursts::2 9067 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8494 # Per bank write bursts 86system.physmem.perBankWrBursts::4 8419 # Per bank write bursts 87system.physmem.perBankWrBursts::5 8394 # Per bank write bursts 88system.physmem.perBankWrBursts::6 8676 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8975 # Per bank write bursts 90system.physmem.perBankWrBursts::8 8824 # Per bank write bursts 91system.physmem.perBankWrBursts::9 8984 # Per bank write bursts 92system.physmem.perBankWrBursts::10 8586 # Per bank write bursts 93system.physmem.perBankWrBursts::11 8136 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8548 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8715 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8203 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7843 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2902861390500 # Total gap between requests | 99system.physmem.numWrRetry 46 # Number of times write queue was full causing retry 100system.physmem.totGap 2903547607000 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 9558 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 9558 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 158443 # Read request sizes (log2) | 107system.physmem.readPktSize::6 159304 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 154599 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 155629 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see |
| 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes | 162system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 1890 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5390 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 5752 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 5631 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 5694 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 5724 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6143 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7234 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 5981 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6694 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 7843 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6228 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6318 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 8094 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6968 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6571 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6360 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1258 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 1176 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 1202 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 2331 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 1806 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 1887 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 2576 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 1933 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 1944 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 1580 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 1707 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 1648 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 1319 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 1310 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 998 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 760 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 309 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 274 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 170 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 128 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 130 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 60277 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 324.004977 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 188.393020 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 342.651376 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 21725 36.04% 36.04% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14933 24.77% 60.82% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5631 9.34% 70.16% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2561 4.25% 79.85% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1497 2.48% 82.33% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1055 1.75% 84.08% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5494 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 577.316613 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 5492 99.96% 99.96% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 231system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads 285system.physmem.totQLat 1487834250 # Total ticks spent queuing 286system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM 287system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers 288system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst | 231system.physmem.rdPerTurnAround::total 5494 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5494 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 24.832545 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.556239 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 46.623010 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-31 5170 94.10% 94.10% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::32-47 87 1.58% 95.69% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::48-63 17 0.31% 96.00% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::64-79 12 0.22% 96.21% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::80-95 19 0.35% 96.56% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::96-111 28 0.51% 97.07% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::112-127 22 0.40% 97.47% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::128-143 14 0.25% 97.72% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::144-159 9 0.16% 97.89% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::160-175 4 0.07% 97.96% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-191 29 0.53% 98.49% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::192-207 12 0.22% 98.71% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::208-223 6 0.11% 98.82% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::224-239 2 0.04% 98.85% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::240-255 2 0.04% 98.89% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::256-271 1 0.02% 98.91% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::272-287 2 0.04% 98.94% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::288-303 7 0.13% 99.07% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::304-319 8 0.15% 99.22% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::320-335 4 0.07% 99.29% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::336-351 4 0.07% 99.36% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::352-367 10 0.18% 99.54% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::368-383 2 0.04% 99.58% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::384-399 3 0.05% 99.64% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::400-415 1 0.02% 99.65% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads 270system.physmem.totQLat 1499821694 # Total ticks spent queuing 271system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst |
| 289system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 290system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst 291system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s 292system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s 293system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 294system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s | 275system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s |
| 295system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 296system.physmem.busUtil 0.06 # Data bus utilization in percentage | 281system.physmem.busUtil 0.05 # Data bus utilization in percentage |
| 297system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads | 282system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads |
| 298system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 299system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 284system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 300system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing 301system.physmem.readRowHits 138089 # Number of row buffer hits during reads 302system.physmem.writeRowHits 122193 # Number of row buffer hits during writes 303system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads 304system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes 305system.physmem.avgGap 8877387.70 # Average gap between requests 306system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined 307system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) 308system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) 309system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) 310system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) 311system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) 312system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) 313system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) 314system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) 315system.physmem_0.averagePower 669.522458 # Core power per rank (mW) 316system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states 317system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states | 285system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing 286system.physmem.readRowHits 138826 # Number of row buffer hits during reads 287system.physmem.writeRowHits 106054 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes 290system.physmem.avgGap 8828431.76 # Average gap between requests 291system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ) 300system.physmem_0.averagePower 669.525264 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states 302system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states |
| 318system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 319system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states | 304system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states |
| 320system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 321system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) 322system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) 323system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) 324system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) 325system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) 326system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) 327system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) 328system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) 329system.physmem_1.averagePower 669.435479 # Core power per rank (mW) 330system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states 331system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states | 306system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ) 314system.physmem_1.averagePower 669.425095 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states 316system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states |
| 332system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 333system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states | 318system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states |
| 334system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 335system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 336system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 337system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 338system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 339system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 340system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 341system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) --- 33 unchanged lines hidden (view full) --- 375system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 378system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 379system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 380system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 381system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 382system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 320system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 321system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 322system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 323system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 324system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 325system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 326system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) --- 33 unchanged lines hidden (view full) --- 360system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 363system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 364system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 365system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 366system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 367system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 383system.cpu.dtb.walker.walks 9552 # Table walker walks requested 384system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors 385system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate 386system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate 387system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution 401system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution 402system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution 403system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated 404system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated 405system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated 406system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst | 368system.cpu.dtb.walker.walks 9545 # Table walker walks requested 369system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors 370system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate 371system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate 372system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency 373system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency 374system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency 375system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency 376system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency 377system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency 378system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency 379system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency 380system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution 386system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution 387system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution 388system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated 389system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated 390system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated 391system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst |
| 407system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 392system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 408system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst 409system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst | 393system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst 394system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst |
| 410system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 395system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 411system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst 412system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst | 396system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst 397system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst |
| 413system.cpu.dtb.inst_hits 0 # ITB inst hits 414system.cpu.dtb.inst_misses 0 # ITB inst misses | 398system.cpu.dtb.inst_hits 0 # ITB inst hits 399system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 415system.cpu.dtb.read_hits 24537663 # DTB read hits 416system.cpu.dtb.read_misses 8142 # DTB read misses 417system.cpu.dtb.write_hits 19618927 # DTB write hits 418system.cpu.dtb.write_misses 1410 # DTB write misses | 400system.cpu.dtb.read_hits 24524755 # DTB read hits 401system.cpu.dtb.read_misses 8132 # DTB read misses 402system.cpu.dtb.write_hits 19610055 # DTB write hits 403system.cpu.dtb.write_misses 1413 # DTB write misses |
| 419system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 420system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 421system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 422system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 404system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 405system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 406system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 407system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 423system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB | 408system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB |
| 424system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 409system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 425system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch | 410system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch |
| 426system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 427system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions | 411system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions |
| 428system.cpu.dtb.read_accesses 24545805 # DTB read accesses 429system.cpu.dtb.write_accesses 19620337 # DTB write accesses | 413system.cpu.dtb.read_accesses 24532887 # DTB read accesses 414system.cpu.dtb.write_accesses 19611468 # DTB write accesses |
| 430system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 415system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 431system.cpu.dtb.hits 44156590 # DTB hits 432system.cpu.dtb.misses 9552 # DTB misses 433system.cpu.dtb.accesses 44166142 # DTB accesses | 416system.cpu.dtb.hits 44134810 # DTB hits 417system.cpu.dtb.misses 9545 # DTB misses 418system.cpu.dtb.accesses 44144355 # DTB accesses |
| 434system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 435system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 436system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 437system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 438system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 21 unchanged lines hidden (view full) --- 463system.cpu.itb.walker.walks 4762 # Table walker walks requested 464system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 465system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate 466system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate 467system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 468system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 469system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 470system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency | 419system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 420system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 423system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 424system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 21 unchanged lines hidden (view full) --- 448system.cpu.itb.walker.walks 4762 # Table walker walks requested 449system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 450system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate 451system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate 452system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 453system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 454system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 455system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency |
| 471system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency 472system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency 473system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency 474system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency | 456system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency 457system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency 458system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency 459system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency 460system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency 461system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency |
| 479system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency | 464system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency |
| 480system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution 481system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution 482system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution | 465system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution 466system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution 467system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution |
| 483system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 484system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 485system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 486system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 487system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 488system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 489system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 490system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 491system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 492system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst | 468system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 469system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 470system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 471system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 472system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 475system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst |
| 493system.cpu.itb.inst_hits 115624412 # ITB inst hits | 478system.cpu.itb.inst_hits 115569545 # ITB inst hits |
| 494system.cpu.itb.inst_misses 4762 # ITB inst misses 495system.cpu.itb.read_hits 0 # DTB read hits 496system.cpu.itb.read_misses 0 # DTB read misses 497system.cpu.itb.write_hits 0 # DTB write hits 498system.cpu.itb.write_misses 0 # DTB write misses 499system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 500system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 501system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 502system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 503system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 504system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 505system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 506system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu.itb.read_accesses 0 # DTB read accesses 509system.cpu.itb.write_accesses 0 # DTB write accesses | 479system.cpu.itb.inst_misses 4762 # ITB inst misses 480system.cpu.itb.read_hits 0 # DTB read hits 481system.cpu.itb.read_misses 0 # DTB read misses 482system.cpu.itb.write_hits 0 # DTB write hits 483system.cpu.itb.write_misses 0 # DTB write misses 484system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 485system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 488system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 489system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 490system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 491system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 493system.cpu.itb.read_accesses 0 # DTB read accesses 494system.cpu.itb.write_accesses 0 # DTB write accesses |
| 510system.cpu.itb.inst_accesses 115629174 # ITB inst accesses 511system.cpu.itb.hits 115624412 # DTB hits | 495system.cpu.itb.inst_accesses 115574307 # ITB inst accesses 496system.cpu.itb.hits 115569545 # DTB hits |
| 512system.cpu.itb.misses 4762 # DTB misses | 497system.cpu.itb.misses 4762 # DTB misses |
| 513system.cpu.itb.accesses 115629174 # DTB accesses 514system.cpu.numCycles 5805723534 # number of cpu cycles simulated | 498system.cpu.itb.accesses 115574307 # DTB accesses 499system.cpu.numCycles 5807095863 # number of cpu cycles simulated |
| 515system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 516system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 500system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 501system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 517system.cpu.committedInsts 112525269 # Number of instructions committed 518system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed 519system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses 520system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses 521system.cpu.num_func_calls 9899985 # number of times a function call or return occured 522system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls 523system.cpu.num_int_insts 119969678 # number of integer instructions 524system.cpu.num_fp_insts 11290 # number of float instructions 525system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read 526system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written 527system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read | 502system.cpu.committedInsts 112472279 # Number of instructions committed 503system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed 504system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses 505system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 506system.cpu.num_func_calls 9892504 # number of times a function call or return occured 507system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls 508system.cpu.num_int_insts 119910547 # number of integer instructions 509system.cpu.num_fp_insts 11161 # number of float instructions 510system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read 511system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written 512system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read |
| 528system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written | 513system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written |
| 529system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read 530system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written 531system.cpu.num_mem_refs 45438019 # number of memory refs 532system.cpu.num_load_insts 24860597 # Number of load instructions 533system.cpu.num_store_insts 20577422 # Number of store instructions 534system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles 535system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles 536system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles 537system.cpu.idle_fraction 0.927847 # Percentage of idle cycles 538system.cpu.Branches 25932360 # Number of branches fetched | 514system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read 515system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written 516system.cpu.num_mem_refs 45415290 # number of memory refs 517system.cpu.num_load_insts 24846976 # Number of load instructions 518system.cpu.num_store_insts 20568314 # Number of store instructions 519system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles 520system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles 521system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles 522system.cpu.idle_fraction 0.927424 # Percentage of idle cycles 523system.cpu.Branches 25918910 # Number of branches fetched |
| 539system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction | 524system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction |
| 540system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction 541system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction | 525system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction 526system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction |
| 542system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 543system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 544system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 545system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 546system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 547system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 548system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 549system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 557system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 558system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 559system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 560system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 561system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 562system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 563system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 564system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction | 527system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 528system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 529system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 530system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 531system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 532system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 533system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 534system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 542system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 543system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 544system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 545system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 546system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 547system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 548system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 549system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction |
| 565system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction | 550system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction |
| 566system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 567system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 568system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction | 551system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 552system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 553system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction |
| 569system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction 570system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction | 554system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction 555system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction |
| 571system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 572system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 556system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 557system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 573system.cpu.op_class::total 138794587 # Class of executed instruction | 558system.cpu.op_class::total 138727463 # Class of executed instruction |
| 574system.cpu.kern.inst.arm 0 # number of arm instructions executed | 559system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 575system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 576system.cpu.dcache.tags.replacements 823321 # number of replacements 577system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use 578system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. 579system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. 580system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. 581system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. 582system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor 583system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy 584system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy | 560system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed 561system.cpu.dcache.tags.replacements 820494 # number of replacements 562system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use 563system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks. 564system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks. 565system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks. 566system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit. 567system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor 568system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy 569system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy |
| 585system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 570system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 586system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id | 571system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 572system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id 573system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 574system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id |
| 590system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 575system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 591system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses 593system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits 594system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits 595system.cpu.dcache.WriteReq_hits::cpu.data 18835651 # number of WriteReq hits 596system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits 597system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits 598system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits 599system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits 600system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits 601system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits 602system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits 603system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits 604system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits 605system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits 606system.cpu.dcache.overall_hits::total 42354457 # number of overall hits 607system.cpu.dcache.ReadReq_misses::cpu.data 402703 # number of ReadReq misses 608system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses 609system.cpu.dcache.WriteReq_misses::cpu.data 299019 # number of WriteReq misses 610system.cpu.dcache.WriteReq_misses::total 299019 # number of WriteReq misses 611system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses 612system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses 613system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses 614system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses | 576system.cpu.dcache.tags.tag_accesses 177143306 # Number of tag accesses 577system.cpu.dcache.tags.data_accesses 177143306 # Number of data accesses 578system.cpu.dcache.ReadReq_hits::cpu.data 23115915 # number of ReadReq hits 579system.cpu.dcache.ReadReq_hits::total 23115915 # number of ReadReq hits 580system.cpu.dcache.WriteReq_hits::cpu.data 18827300 # number of WriteReq hits 581system.cpu.dcache.WriteReq_hits::total 18827300 # number of WriteReq hits 582system.cpu.dcache.SoftPFReq_hits::cpu.data 392830 # number of SoftPFReq hits 583system.cpu.dcache.SoftPFReq_hits::total 392830 # number of SoftPFReq hits 584system.cpu.dcache.LoadLockedReq_hits::cpu.data 443506 # number of LoadLockedReq hits 585system.cpu.dcache.LoadLockedReq_hits::total 443506 # number of LoadLockedReq hits 586system.cpu.dcache.StoreCondReq_hits::cpu.data 460403 # number of StoreCondReq hits 587system.cpu.dcache.StoreCondReq_hits::total 460403 # number of StoreCondReq hits 588system.cpu.dcache.demand_hits::cpu.data 41943215 # number of demand (read+write) hits 589system.cpu.dcache.demand_hits::total 41943215 # number of demand (read+write) hits 590system.cpu.dcache.overall_hits::cpu.data 42336045 # number of overall hits 591system.cpu.dcache.overall_hits::total 42336045 # number of overall hits 592system.cpu.dcache.ReadReq_misses::cpu.data 400875 # number of ReadReq misses 593system.cpu.dcache.ReadReq_misses::total 400875 # number of ReadReq misses 594system.cpu.dcache.WriteReq_misses::cpu.data 298693 # number of WriteReq misses 595system.cpu.dcache.WriteReq_misses::total 298693 # number of WriteReq misses 596system.cpu.dcache.SoftPFReq_misses::cpu.data 118357 # number of SoftPFReq misses 597system.cpu.dcache.SoftPFReq_misses::total 118357 # number of SoftPFReq misses 598system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses 599system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses |
| 615system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 616system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 600system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 601system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 617system.cpu.dcache.demand_misses::cpu.data 701722 # number of demand (read+write) misses 618system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses 619system.cpu.dcache.overall_misses::cpu.data 820894 # number of overall misses 620system.cpu.dcache.overall_misses::total 820894 # number of overall misses 621system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916458250 # number of ReadReq miss cycles 622system.cpu.dcache.ReadReq_miss_latency::total 5916458250 # number of ReadReq miss cycles 623system.cpu.dcache.WriteReq_miss_latency::cpu.data 11650381750 # number of WriteReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles 625system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280295250 # number of LoadLockedReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::total 280295250 # number of LoadLockedReq miss cycles 627system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles 628system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles 629system.cpu.dcache.demand_miss_latency::cpu.data 17566840000 # number of demand (read+write) miss cycles 630system.cpu.dcache.demand_miss_latency::total 17566840000 # number of demand (read+write) miss cycles 631system.cpu.dcache.overall_miss_latency::cpu.data 17566840000 # number of overall miss cycles 632system.cpu.dcache.overall_miss_latency::total 17566840000 # number of overall miss cycles 633system.cpu.dcache.ReadReq_accesses::cpu.data 23529387 # number of ReadReq accesses(hits+misses) 634system.cpu.dcache.ReadReq_accesses::total 23529387 # number of ReadReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::cpu.data 19134670 # number of WriteReq accesses(hits+misses) 636system.cpu.dcache.WriteReq_accesses::total 19134670 # number of WriteReq accesses(hits+misses) 637system.cpu.dcache.SoftPFReq_accesses::cpu.data 511294 # number of SoftPFReq accesses(hits+misses) 638system.cpu.dcache.SoftPFReq_accesses::total 511294 # number of SoftPFReq accesses(hits+misses) 639system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466379 # number of LoadLockedReq accesses(hits+misses) 640system.cpu.dcache.LoadLockedReq_accesses::total 466379 # number of LoadLockedReq accesses(hits+misses) 641system.cpu.dcache.StoreCondReq_accesses::cpu.data 460572 # number of StoreCondReq accesses(hits+misses) 642system.cpu.dcache.StoreCondReq_accesses::total 460572 # number of StoreCondReq accesses(hits+misses) 643system.cpu.dcache.demand_accesses::cpu.data 42664057 # number of demand (read+write) accesses 644system.cpu.dcache.demand_accesses::total 42664057 # number of demand (read+write) accesses 645system.cpu.dcache.overall_accesses::cpu.data 43175351 # number of overall (read+write) accesses 646system.cpu.dcache.overall_accesses::total 43175351 # number of overall (read+write) accesses 647system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017115 # miss rate for ReadReq accesses 648system.cpu.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses 649system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015627 # miss rate for WriteReq accesses 650system.cpu.dcache.WriteReq_miss_rate::total 0.015627 # miss rate for WriteReq accesses 651system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233079 # miss rate for SoftPFReq accesses 652system.cpu.dcache.SoftPFReq_miss_rate::total 0.233079 # miss rate for SoftPFReq accesses 653system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048765 # miss rate for LoadLockedReq accesses 654system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048765 # miss rate for LoadLockedReq accesses | 602system.cpu.dcache.demand_misses::cpu.data 699568 # number of demand (read+write) misses 603system.cpu.dcache.demand_misses::total 699568 # number of demand (read+write) misses 604system.cpu.dcache.overall_misses::cpu.data 817925 # number of overall misses 605system.cpu.dcache.overall_misses::total 817925 # number of overall misses 606system.cpu.dcache.ReadReq_miss_latency::cpu.data 5965444702 # number of ReadReq miss cycles 607system.cpu.dcache.ReadReq_miss_latency::total 5965444702 # number of ReadReq miss cycles 608system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639649008 # number of WriteReq miss cycles 609system.cpu.dcache.WriteReq_miss_latency::total 12639649008 # number of WriteReq miss cycles 610system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280760500 # number of LoadLockedReq miss cycles 611system.cpu.dcache.LoadLockedReq_miss_latency::total 280760500 # number of LoadLockedReq miss cycles 612system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles 613system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles 614system.cpu.dcache.demand_miss_latency::cpu.data 18605093710 # number of demand (read+write) miss cycles 615system.cpu.dcache.demand_miss_latency::total 18605093710 # number of demand (read+write) miss cycles 616system.cpu.dcache.overall_miss_latency::cpu.data 18605093710 # number of overall miss cycles 617system.cpu.dcache.overall_miss_latency::total 18605093710 # number of overall miss cycles 618system.cpu.dcache.ReadReq_accesses::cpu.data 23516790 # number of ReadReq accesses(hits+misses) 619system.cpu.dcache.ReadReq_accesses::total 23516790 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.WriteReq_accesses::cpu.data 19125993 # number of WriteReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::total 19125993 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.SoftPFReq_accesses::cpu.data 511187 # number of SoftPFReq accesses(hits+misses) 623system.cpu.dcache.SoftPFReq_accesses::total 511187 # number of SoftPFReq accesses(hits+misses) 624system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466191 # number of LoadLockedReq accesses(hits+misses) 625system.cpu.dcache.LoadLockedReq_accesses::total 466191 # number of LoadLockedReq accesses(hits+misses) 626system.cpu.dcache.StoreCondReq_accesses::cpu.data 460405 # number of StoreCondReq accesses(hits+misses) 627system.cpu.dcache.StoreCondReq_accesses::total 460405 # number of StoreCondReq accesses(hits+misses) 628system.cpu.dcache.demand_accesses::cpu.data 42642783 # number of demand (read+write) accesses 629system.cpu.dcache.demand_accesses::total 42642783 # number of demand (read+write) accesses 630system.cpu.dcache.overall_accesses::cpu.data 43153970 # number of overall (read+write) accesses 631system.cpu.dcache.overall_accesses::total 43153970 # number of overall (read+write) accesses 632system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017046 # miss rate for ReadReq accesses 633system.cpu.dcache.ReadReq_miss_rate::total 0.017046 # miss rate for ReadReq accesses 634system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses 635system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses 636system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231534 # miss rate for SoftPFReq accesses 637system.cpu.dcache.SoftPFReq_miss_rate::total 0.231534 # miss rate for SoftPFReq accesses 638system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048660 # miss rate for LoadLockedReq accesses 639system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048660 # miss rate for LoadLockedReq accesses |
| 655system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 656system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses | 640system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 641system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses |
| 657system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses 658system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses 659system.cpu.dcache.overall_miss_rate::cpu.data 0.019013 # miss rate for overall accesses 660system.cpu.dcache.overall_miss_rate::total 0.019013 # miss rate for overall accesses 661system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345 # average ReadReq miss latency 662system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345 # average ReadReq miss latency 663system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611 # average WriteReq miss latency 664system.cpu.dcache.WriteReq_avg_miss_latency::total 38962.011611 # average WriteReq miss latency 665system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12324.462472 # average LoadLockedReq miss latency 666system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12324.462472 # average LoadLockedReq miss latency 667system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency 668system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency 669system.cpu.dcache.demand_avg_miss_latency::cpu.data 25033.902315 # average overall miss latency 670system.cpu.dcache.demand_avg_miss_latency::total 25033.902315 # average overall miss latency 671system.cpu.dcache.overall_avg_miss_latency::cpu.data 21399.644778 # average overall miss latency 672system.cpu.dcache.overall_avg_miss_latency::total 21399.644778 # average overall miss latency 673system.cpu.dcache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked | 642system.cpu.dcache.demand_miss_rate::cpu.data 0.016405 # miss rate for demand accesses 643system.cpu.dcache.demand_miss_rate::total 0.016405 # miss rate for demand accesses 644system.cpu.dcache.overall_miss_rate::cpu.data 0.018954 # miss rate for overall accesses 645system.cpu.dcache.overall_miss_rate::total 0.018954 # miss rate for overall accesses 646system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14881.059437 # average ReadReq miss latency 647system.cpu.dcache.ReadReq_avg_miss_latency::total 14881.059437 # average ReadReq miss latency 648system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42316.522342 # average WriteReq miss latency 649system.cpu.dcache.WriteReq_avg_miss_latency::total 42316.522342 # average WriteReq miss latency 650system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12376.482257 # average LoadLockedReq miss latency 651system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12376.482257 # average LoadLockedReq miss latency 652system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 653system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 654system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287 # average overall miss latency 655system.cpu.dcache.demand_avg_miss_latency::total 26595.118287 # average overall miss latency 656system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::total 22746.698915 # average overall miss latency 658system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked |
| 674system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 659system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 675system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked | 660system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked |
| 676system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 661system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 677system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # average number of cycles each access was blocked | 662system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked |
| 678system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 679system.cpu.dcache.fast_writes 0 # number of fast writes performed 680system.cpu.dcache.cache_copies 0 # number of cache copies performed | 663system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 664system.cpu.dcache.fast_writes 0 # number of fast writes performed 665system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 681system.cpu.dcache.writebacks::writebacks 686487 # number of writebacks 682system.cpu.dcache.writebacks::total 686487 # number of writebacks 683system.cpu.dcache.ReadReq_mshr_hits::cpu.data 629 # number of ReadReq MSHR hits 684system.cpu.dcache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits 685system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14254 # number of LoadLockedReq MSHR hits 686system.cpu.dcache.LoadLockedReq_mshr_hits::total 14254 # number of LoadLockedReq MSHR hits 687system.cpu.dcache.demand_mshr_hits::cpu.data 629 # number of demand (read+write) MSHR hits 688system.cpu.dcache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits 689system.cpu.dcache.overall_mshr_hits::cpu.data 629 # number of overall MSHR hits 690system.cpu.dcache.overall_mshr_hits::total 629 # number of overall MSHR hits 691system.cpu.dcache.ReadReq_mshr_misses::cpu.data 402074 # number of ReadReq MSHR misses 692system.cpu.dcache.ReadReq_mshr_misses::total 402074 # number of ReadReq MSHR misses 693system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299019 # number of WriteReq MSHR misses 694system.cpu.dcache.WriteReq_mshr_misses::total 299019 # number of WriteReq MSHR misses 695system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses 696system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses 697system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8489 # number of LoadLockedReq MSHR misses 698system.cpu.dcache.LoadLockedReq_mshr_misses::total 8489 # number of LoadLockedReq MSHR misses | 666system.cpu.dcache.writebacks::writebacks 683915 # number of writebacks 667system.cpu.dcache.writebacks::total 683915 # number of writebacks 668system.cpu.dcache.ReadReq_mshr_hits::cpu.data 674 # number of ReadReq MSHR hits 669system.cpu.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits 670system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14143 # number of LoadLockedReq MSHR hits 671system.cpu.dcache.LoadLockedReq_mshr_hits::total 14143 # number of LoadLockedReq MSHR hits 672system.cpu.dcache.demand_mshr_hits::cpu.data 674 # number of demand (read+write) MSHR hits 673system.cpu.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits 674system.cpu.dcache.overall_mshr_hits::cpu.data 674 # number of overall MSHR hits 675system.cpu.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits 676system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400201 # number of ReadReq MSHR misses 677system.cpu.dcache.ReadReq_mshr_misses::total 400201 # number of ReadReq MSHR misses 678system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298693 # number of WriteReq MSHR misses 679system.cpu.dcache.WriteReq_mshr_misses::total 298693 # number of WriteReq MSHR misses 680system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116343 # number of SoftPFReq MSHR misses 681system.cpu.dcache.SoftPFReq_mshr_misses::total 116343 # number of SoftPFReq MSHR misses 682system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses 683system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses |
| 699system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 700system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 684system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 685system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 701system.cpu.dcache.demand_mshr_misses::cpu.data 701093 # number of demand (read+write) MSHR misses 702system.cpu.dcache.demand_mshr_misses::total 701093 # number of demand (read+write) MSHR misses 703system.cpu.dcache.overall_mshr_misses::cpu.data 818114 # number of overall MSHR misses 704system.cpu.dcache.overall_mshr_misses::total 818114 # number of overall MSHR misses 705system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5098164750 # number of ReadReq MSHR miss cycles 706system.cpu.dcache.ReadReq_mshr_miss_latency::total 5098164750 # number of ReadReq MSHR miss cycles 707system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994871250 # number of WriteReq MSHR miss cycles 708system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994871250 # number of WriteReq MSHR miss cycles 709system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411142000 # number of SoftPFReq MSHR miss cycles 710system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411142000 # number of SoftPFReq MSHR miss cycles 711system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 100012000 # number of LoadLockedReq MSHR miss cycles 712system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 100012000 # number of LoadLockedReq MSHR miss cycles 713system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles 714system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles 715system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16093036000 # number of demand (read+write) MSHR miss cycles 716system.cpu.dcache.demand_mshr_miss_latency::total 16093036000 # number of demand (read+write) MSHR miss cycles 717system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17504178000 # number of overall MSHR miss cycles 718system.cpu.dcache.overall_mshr_miss_latency::total 17504178000 # number of overall MSHR miss cycles 719system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791398250 # number of ReadReq MSHR uncacheable cycles 720system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791398250 # number of ReadReq MSHR uncacheable cycles 721system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429682000 # number of WriteReq MSHR uncacheable cycles 722system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429682000 # number of WriteReq MSHR uncacheable cycles 723system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080250 # number of overall MSHR uncacheable cycles 724system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles 725system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses 726system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses 727system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses 728system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses 729system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses 730system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses 731system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses 732system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # mshr miss rate for LoadLockedReq accesses | 686system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles 695system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles 696system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles 697system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles 698system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles 699system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles 700system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483461242 # number of demand (read+write) MSHR miss cycles 701system.cpu.dcache.demand_mshr_miss_latency::total 17483461242 # number of demand (read+write) MSHR miss cycles 702system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18953838790 # number of overall MSHR miss cycles 703system.cpu.dcache.overall_mshr_miss_latency::total 18953838790 # number of overall MSHR miss cycles 704system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833129500 # number of ReadReq MSHR uncacheable cycles 705system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833129500 # number of ReadReq MSHR uncacheable cycles 706system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4513032000 # number of WriteReq MSHR uncacheable cycles 707system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4513032000 # number of WriteReq MSHR uncacheable cycles 708system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346161500 # number of overall MSHR uncacheable cycles 709system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346161500 # number of overall MSHR uncacheable cycles 710system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017018 # mshr miss rate for ReadReq accesses 711system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017018 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses 713system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227594 # mshr miss rate for SoftPFReq accesses 715system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227594 # mshr miss rate for SoftPFReq accesses 716system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018323 # mshr miss rate for LoadLockedReq accesses 717system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018323 # mshr miss rate for LoadLockedReq accesses |
| 733system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 734system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses | 718system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 719system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses |
| 735system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses 736system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses 737system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses 738system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses 739system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency 740system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency 741system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency 742system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # average WriteReq mshr miss latency 743system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321 # average SoftPFReq mshr miss latency 744system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321 # average SoftPFReq mshr miss latency 745system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118 # average LoadLockedReq mshr miss latency 746system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118 # average LoadLockedReq mshr miss latency 747system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency 748system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency 749system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069 # average overall mshr miss latency 750system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069 # average overall mshr miss latency 751system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency 752system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency | 720system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016390 # mshr miss rate for demand accesses 721system.cpu.dcache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses 722system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018891 # mshr miss rate for overall accesses 723system.cpu.dcache.overall_mshr_miss_rate::total 0.018891 # mshr miss rate for overall accesses 724system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13367.614649 # average ReadReq mshr miss latency 725system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13367.614649 # average ReadReq mshr miss latency 726system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40622.741383 # average WriteReq mshr miss latency 727system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40622.741383 # average WriteReq mshr miss latency 728system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12638.298376 # average SoftPFReq mshr miss latency 729system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12638.298376 # average SoftPFReq mshr miss latency 730system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency 731system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency 732system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 733system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 734system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency 735system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency 736system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency 737system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency |
| 753system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 754system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 755system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 756system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 757system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 758system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 759system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 738system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 739system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 740system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 741system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 742system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 743system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 744system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 760system.cpu.icache.tags.replacements 1701491 # number of replacements 761system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use 762system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks. 763system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks. 764system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks. 765system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. 766system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # Average occupied blocks per requestor 767system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy 768system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy | 745system.cpu.icache.tags.replacements 1698619 # number of replacements 746system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use 747system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks. 748system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks. 749system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks. 750system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit. 751system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor 752system.cpu.icache.tags.occ_percent::cpu.inst 0.997528 # Average percentage of cache occupancy 753system.cpu.icache.tags.occ_percent::total 0.997528 # Average percentage of cache occupancy |
| 769system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 770system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 771system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 772system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 773system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 774system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 754system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 755system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 756system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 757system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 758system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 759system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 775system.cpu.icache.tags.tag_accesses 117326421 # Number of tag accesses 776system.cpu.icache.tags.data_accesses 117326421 # Number of data accesses 777system.cpu.icache.ReadReq_hits::cpu.inst 113922403 # number of ReadReq hits 778system.cpu.icache.ReadReq_hits::total 113922403 # number of ReadReq hits 779system.cpu.icache.demand_hits::cpu.inst 113922403 # number of demand (read+write) hits 780system.cpu.icache.demand_hits::total 113922403 # number of demand (read+write) hits 781system.cpu.icache.overall_hits::cpu.inst 113922403 # number of overall hits 782system.cpu.icache.overall_hits::total 113922403 # number of overall hits 783system.cpu.icache.ReadReq_misses::cpu.inst 1702009 # number of ReadReq misses 784system.cpu.icache.ReadReq_misses::total 1702009 # number of ReadReq misses 785system.cpu.icache.demand_misses::cpu.inst 1702009 # number of demand (read+write) misses 786system.cpu.icache.demand_misses::total 1702009 # number of demand (read+write) misses 787system.cpu.icache.overall_misses::cpu.inst 1702009 # number of overall misses 788system.cpu.icache.overall_misses::total 1702009 # number of overall misses 789system.cpu.icache.ReadReq_miss_latency::cpu.inst 23268250500 # number of ReadReq miss cycles 790system.cpu.icache.ReadReq_miss_latency::total 23268250500 # number of ReadReq miss cycles 791system.cpu.icache.demand_miss_latency::cpu.inst 23268250500 # number of demand (read+write) miss cycles 792system.cpu.icache.demand_miss_latency::total 23268250500 # number of demand (read+write) miss cycles 793system.cpu.icache.overall_miss_latency::cpu.inst 23268250500 # number of overall miss cycles 794system.cpu.icache.overall_miss_latency::total 23268250500 # number of overall miss cycles 795system.cpu.icache.ReadReq_accesses::cpu.inst 115624412 # number of ReadReq accesses(hits+misses) 796system.cpu.icache.ReadReq_accesses::total 115624412 # number of ReadReq accesses(hits+misses) 797system.cpu.icache.demand_accesses::cpu.inst 115624412 # number of demand (read+write) accesses 798system.cpu.icache.demand_accesses::total 115624412 # number of demand (read+write) accesses 799system.cpu.icache.overall_accesses::cpu.inst 115624412 # number of overall (read+write) accesses 800system.cpu.icache.overall_accesses::total 115624412 # number of overall (read+write) accesses 801system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014720 # miss rate for ReadReq accesses 802system.cpu.icache.ReadReq_miss_rate::total 0.014720 # miss rate for ReadReq accesses 803system.cpu.icache.demand_miss_rate::cpu.inst 0.014720 # miss rate for demand accesses 804system.cpu.icache.demand_miss_rate::total 0.014720 # miss rate for demand accesses 805system.cpu.icache.overall_miss_rate::cpu.inst 0.014720 # miss rate for overall accesses 806system.cpu.icache.overall_miss_rate::total 0.014720 # miss rate for overall accesses 807system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13671.050212 # average ReadReq miss latency 808system.cpu.icache.ReadReq_avg_miss_latency::total 13671.050212 # average ReadReq miss latency 809system.cpu.icache.demand_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency 810system.cpu.icache.demand_avg_miss_latency::total 13671.050212 # average overall miss latency 811system.cpu.icache.overall_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency 812system.cpu.icache.overall_avg_miss_latency::total 13671.050212 # average overall miss latency | 760system.cpu.icache.tags.tag_accesses 117268682 # Number of tag accesses 761system.cpu.icache.tags.data_accesses 117268682 # Number of data accesses 762system.cpu.icache.ReadReq_hits::cpu.inst 113870408 # number of ReadReq hits 763system.cpu.icache.ReadReq_hits::total 113870408 # number of ReadReq hits 764system.cpu.icache.demand_hits::cpu.inst 113870408 # number of demand (read+write) hits 765system.cpu.icache.demand_hits::total 113870408 # number of demand (read+write) hits 766system.cpu.icache.overall_hits::cpu.inst 113870408 # number of overall hits 767system.cpu.icache.overall_hits::total 113870408 # number of overall hits 768system.cpu.icache.ReadReq_misses::cpu.inst 1699137 # number of ReadReq misses 769system.cpu.icache.ReadReq_misses::total 1699137 # number of ReadReq misses 770system.cpu.icache.demand_misses::cpu.inst 1699137 # number of demand (read+write) misses 771system.cpu.icache.demand_misses::total 1699137 # number of demand (read+write) misses 772system.cpu.icache.overall_misses::cpu.inst 1699137 # number of overall misses 773system.cpu.icache.overall_misses::total 1699137 # number of overall misses 774system.cpu.icache.ReadReq_miss_latency::cpu.inst 23363194999 # number of ReadReq miss cycles 775system.cpu.icache.ReadReq_miss_latency::total 23363194999 # number of ReadReq miss cycles 776system.cpu.icache.demand_miss_latency::cpu.inst 23363194999 # number of demand (read+write) miss cycles 777system.cpu.icache.demand_miss_latency::total 23363194999 # number of demand (read+write) miss cycles 778system.cpu.icache.overall_miss_latency::cpu.inst 23363194999 # number of overall miss cycles 779system.cpu.icache.overall_miss_latency::total 23363194999 # number of overall miss cycles 780system.cpu.icache.ReadReq_accesses::cpu.inst 115569545 # number of ReadReq accesses(hits+misses) 781system.cpu.icache.ReadReq_accesses::total 115569545 # number of ReadReq accesses(hits+misses) 782system.cpu.icache.demand_accesses::cpu.inst 115569545 # number of demand (read+write) accesses 783system.cpu.icache.demand_accesses::total 115569545 # number of demand (read+write) accesses 784system.cpu.icache.overall_accesses::cpu.inst 115569545 # number of overall (read+write) accesses 785system.cpu.icache.overall_accesses::total 115569545 # number of overall (read+write) accesses 786system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses 787system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses 788system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses 789system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses 790system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses 791system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses 792system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13750.036047 # average ReadReq miss latency 793system.cpu.icache.ReadReq_avg_miss_latency::total 13750.036047 # average ReadReq miss latency 794system.cpu.icache.demand_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency 795system.cpu.icache.demand_avg_miss_latency::total 13750.036047 # average overall miss latency 796system.cpu.icache.overall_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency 797system.cpu.icache.overall_avg_miss_latency::total 13750.036047 # average overall miss latency |
| 813system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.icache.fast_writes 0 # number of fast writes performed 820system.cpu.icache.cache_copies 0 # number of cache copies performed | 798system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 799system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 800system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 801system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 802system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 803system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 804system.cpu.icache.fast_writes 0 # number of fast writes performed 805system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 821system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1702009 # number of ReadReq MSHR misses 822system.cpu.icache.ReadReq_mshr_misses::total 1702009 # number of ReadReq MSHR misses 823system.cpu.icache.demand_mshr_misses::cpu.inst 1702009 # number of demand (read+write) MSHR misses 824system.cpu.icache.demand_mshr_misses::total 1702009 # number of demand (read+write) MSHR misses 825system.cpu.icache.overall_mshr_misses::cpu.inst 1702009 # number of overall MSHR misses 826system.cpu.icache.overall_mshr_misses::total 1702009 # number of overall MSHR misses 827system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19857660500 # number of ReadReq MSHR miss cycles 828system.cpu.icache.ReadReq_mshr_miss_latency::total 19857660500 # number of ReadReq MSHR miss cycles 829system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19857660500 # number of demand (read+write) MSHR miss cycles 830system.cpu.icache.demand_mshr_miss_latency::total 19857660500 # number of demand (read+write) MSHR miss cycles 831system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19857660500 # number of overall MSHR miss cycles 832system.cpu.icache.overall_mshr_miss_latency::total 19857660500 # number of overall MSHR miss cycles 833system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles 834system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles 835system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles 836system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles 837system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for ReadReq accesses 838system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014720 # mshr miss rate for ReadReq accesses 839system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for demand accesses 840system.cpu.icache.demand_mshr_miss_rate::total 0.014720 # mshr miss rate for demand accesses 841system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for overall accesses 842system.cpu.icache.overall_mshr_miss_rate::total 0.014720 # mshr miss rate for overall accesses 843system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11667.188893 # average ReadReq mshr miss latency 844system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11667.188893 # average ReadReq mshr miss latency 845system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency 846system.cpu.icache.demand_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency 847system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency 848system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency | 806system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses 807system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses 808system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses 809system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses 810system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses 811system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses 812system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles 813system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles 814system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles 815system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles 816system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles 817system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles 818system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles 819system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles 820system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 677067750 # number of overall MSHR uncacheable cycles 821system.cpu.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles 822system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses 823system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses 824system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses 825system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses 826system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses 827system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses 828system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency 829system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency 830system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency 831system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency 832system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency 833system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency |
| 849system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 850system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 851system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 852system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 853system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 834system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 835system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 836system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 837system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 838system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 854system.cpu.l2cache.tags.replacements 88884 # number of replacements 855system.cpu.l2cache.tags.tagsinuse 64931.599128 # Cycle average of tags in use 856system.cpu.l2cache.tags.total_refs 2763158 # Total number of references to valid blocks. 857system.cpu.l2cache.tags.sampled_refs 154151 # Sample count of references to valid blocks. 858system.cpu.l2cache.tags.avg_refs 17.925009 # Average number of references to valid blocks. | 839system.cpu.l2cache.tags.replacements 89783 # number of replacements 840system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use 841system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks. 842system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks. 843system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks. |
| 859system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 844system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 860system.cpu.l2cache.tags.occ_blocks::writebacks 50668.289778 # Average occupied blocks per requestor 861system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809348 # Average occupied blocks per requestor 862system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012227 # Average occupied blocks per requestor 863system.cpu.l2cache.tags.occ_blocks::cpu.inst 9584.205539 # Average occupied blocks per requestor 864system.cpu.l2cache.tags.occ_blocks::cpu.data 4675.282236 # Average occupied blocks per requestor 865system.cpu.l2cache.tags.occ_percent::writebacks 0.773137 # Average percentage of cache occupancy | 845system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor 846system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807659 # Average occupied blocks per requestor 847system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012269 # Average occupied blocks per requestor 848system.cpu.l2cache.tags.occ_blocks::cpu.inst 9560.730853 # Average occupied blocks per requestor 849system.cpu.l2cache.tags.occ_blocks::cpu.data 4902.381289 # Average occupied blocks per requestor 850system.cpu.l2cache.tags.occ_percent::writebacks 0.769944 # Average percentage of cache occupancy |
| 866system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 867system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 851system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 852system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 868system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146243 # Average percentage of cache occupancy 869system.cpu.l2cache.tags.occ_percent::cpu.data 0.071339 # Average percentage of cache occupancy 870system.cpu.l2cache.tags.occ_percent::total 0.990778 # Average percentage of cache occupancy | 853system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145885 # Average percentage of cache occupancy 854system.cpu.l2cache.tags.occ_percent::cpu.data 0.074804 # Average percentage of cache occupancy 855system.cpu.l2cache.tags.occ_percent::total 0.990692 # Average percentage of cache occupancy |
| 871system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id | 856system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id |
| 872system.cpu.l2cache.tags.occ_task_id_blocks::1024 65262 # Occupied blocks per task id | 857system.cpu.l2cache.tags.occ_task_id_blocks::1024 65228 # Occupied blocks per task id |
| 873system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id | 858system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id |
| 874system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 875system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 876system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id 877system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6961 # Occupied blocks per task id 878system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56128 # Occupied blocks per task id | 859system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 860system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id 861system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id 862system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id 863system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id |
| 879system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id | 864system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id |
| 880system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995819 # Percentage of cache occupancy per task id 881system.cpu.l2cache.tags.tag_accesses 26260695 # Number of tag accesses 882system.cpu.l2cache.tags.data_accesses 26260695 # Number of data accesses 883system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6986 # number of ReadReq hits 884system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3658 # number of ReadReq hits 885system.cpu.l2cache.ReadReq_hits::cpu.inst 1683931 # number of ReadReq hits 886system.cpu.l2cache.ReadReq_hits::cpu.data 515395 # number of ReadReq hits 887system.cpu.l2cache.ReadReq_hits::total 2209970 # number of ReadReq hits 888system.cpu.l2cache.Writeback_hits::writebacks 686487 # number of Writeback hits 889system.cpu.l2cache.Writeback_hits::total 686487 # number of Writeback hits | 865system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id 866system.cpu.l2cache.tags.tag_accesses 26192754 # Number of tag accesses 867system.cpu.l2cache.tags.data_accesses 26192754 # Number of data accesses 868system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6798 # number of ReadReq hits 869system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits 870system.cpu.l2cache.ReadReq_hits::cpu.inst 1681053 # number of ReadReq hits 871system.cpu.l2cache.ReadReq_hits::cpu.data 512833 # number of ReadReq hits 872system.cpu.l2cache.ReadReq_hits::total 2204235 # number of ReadReq hits 873system.cpu.l2cache.Writeback_hits::writebacks 683915 # number of Writeback hits 874system.cpu.l2cache.Writeback_hits::total 683915 # number of Writeback hits |
| 890system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 891system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits | 875system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 876system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits |
| 892system.cpu.l2cache.ReadExReq_hits::cpu.data 166042 # number of ReadExReq hits 893system.cpu.l2cache.ReadExReq_hits::total 166042 # number of ReadExReq hits 894system.cpu.l2cache.demand_hits::cpu.dtb.walker 6986 # number of demand (read+write) hits 895system.cpu.l2cache.demand_hits::cpu.itb.walker 3658 # number of demand (read+write) hits 896system.cpu.l2cache.demand_hits::cpu.inst 1683931 # number of demand (read+write) hits 897system.cpu.l2cache.demand_hits::cpu.data 681437 # number of demand (read+write) hits 898system.cpu.l2cache.demand_hits::total 2376012 # number of demand (read+write) hits 899system.cpu.l2cache.overall_hits::cpu.dtb.walker 6986 # number of overall hits 900system.cpu.l2cache.overall_hits::cpu.itb.walker 3658 # number of overall hits 901system.cpu.l2cache.overall_hits::cpu.inst 1683931 # number of overall hits 902system.cpu.l2cache.overall_hits::cpu.data 681437 # number of overall hits 903system.cpu.l2cache.overall_hits::total 2376012 # number of overall hits | 877system.cpu.l2cache.ReadExReq_hits::cpu.data 164921 # number of ReadExReq hits 878system.cpu.l2cache.ReadExReq_hits::total 164921 # number of ReadExReq hits 879system.cpu.l2cache.demand_hits::cpu.dtb.walker 6798 # number of demand (read+write) hits 880system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits 881system.cpu.l2cache.demand_hits::cpu.inst 1681053 # number of demand (read+write) hits 882system.cpu.l2cache.demand_hits::cpu.data 677754 # number of demand (read+write) hits 883system.cpu.l2cache.demand_hits::total 2369156 # number of demand (read+write) hits 884system.cpu.l2cache.overall_hits::cpu.dtb.walker 6798 # number of overall hits 885system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits 886system.cpu.l2cache.overall_hits::cpu.inst 1681053 # number of overall hits 887system.cpu.l2cache.overall_hits::cpu.data 677754 # number of overall hits 888system.cpu.l2cache.overall_hits::total 2369156 # number of overall hits |
| 904system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 905system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 889system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 890system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 906system.cpu.l2cache.ReadReq_misses::cpu.inst 18053 # number of ReadReq misses 907system.cpu.l2cache.ReadReq_misses::cpu.data 12189 # number of ReadReq misses 908system.cpu.l2cache.ReadReq_misses::total 30251 # number of ReadReq misses 909system.cpu.l2cache.UpgradeReq_misses::cpu.data 2710 # number of UpgradeReq misses 910system.cpu.l2cache.UpgradeReq_misses::total 2710 # number of UpgradeReq misses | 891system.cpu.l2cache.ReadReq_misses::cpu.inst 18063 # number of ReadReq misses 892system.cpu.l2cache.ReadReq_misses::cpu.data 12253 # number of ReadReq misses 893system.cpu.l2cache.ReadReq_misses::total 30325 # number of ReadReq misses 894system.cpu.l2cache.UpgradeReq_misses::cpu.data 2714 # number of UpgradeReq misses 895system.cpu.l2cache.UpgradeReq_misses::total 2714 # number of UpgradeReq misses |
| 911system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 912system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 896system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 897system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 913system.cpu.l2cache.ReadExReq_misses::cpu.data 130244 # number of ReadExReq misses 914system.cpu.l2cache.ReadExReq_misses::total 130244 # number of ReadExReq misses | 898system.cpu.l2cache.ReadExReq_misses::cpu.data 131035 # number of ReadExReq misses 899system.cpu.l2cache.ReadExReq_misses::total 131035 # number of ReadExReq misses |
| 915system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 916system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 900system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 901system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 917system.cpu.l2cache.demand_misses::cpu.inst 18053 # number of demand (read+write) misses 918system.cpu.l2cache.demand_misses::cpu.data 142433 # number of demand (read+write) misses 919system.cpu.l2cache.demand_misses::total 160495 # number of demand (read+write) misses | 902system.cpu.l2cache.demand_misses::cpu.inst 18063 # number of demand (read+write) misses 903system.cpu.l2cache.demand_misses::cpu.data 143288 # number of demand (read+write) misses 904system.cpu.l2cache.demand_misses::total 161360 # number of demand (read+write) misses |
| 920system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 921system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 905system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 906system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 922system.cpu.l2cache.overall_misses::cpu.inst 18053 # number of overall misses 923system.cpu.l2cache.overall_misses::cpu.data 142433 # number of overall misses 924system.cpu.l2cache.overall_misses::total 160495 # number of overall misses 925system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 495250 # number of ReadReq miss cycles 926system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 927system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1316295500 # number of ReadReq miss cycles 928system.cpu.l2cache.ReadReq_miss_latency::cpu.data 927332750 # number of ReadReq miss cycles 929system.cpu.l2cache.ReadReq_miss_latency::total 2244273000 # number of ReadReq miss cycles 930system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 444481 # number of UpgradeReq miss cycles 931system.cpu.l2cache.UpgradeReq_miss_latency::total 444481 # number of UpgradeReq miss cycles 932system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144000 # number of SCUpgradeReq miss cycles 933system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144000 # number of SCUpgradeReq miss cycles 934system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8974834460 # number of ReadExReq miss cycles 935system.cpu.l2cache.ReadExReq_miss_latency::total 8974834460 # number of ReadExReq miss cycles 936system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 495250 # number of demand (read+write) miss cycles 937system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 938system.cpu.l2cache.demand_miss_latency::cpu.inst 1316295500 # number of demand (read+write) miss cycles 939system.cpu.l2cache.demand_miss_latency::cpu.data 9902167210 # number of demand (read+write) miss cycles 940system.cpu.l2cache.demand_miss_latency::total 11219107460 # number of demand (read+write) miss cycles 941system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 495250 # number of overall miss cycles 942system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 943system.cpu.l2cache.overall_miss_latency::cpu.inst 1316295500 # number of overall miss cycles 944system.cpu.l2cache.overall_miss_latency::cpu.data 9902167210 # number of overall miss cycles 945system.cpu.l2cache.overall_miss_latency::total 11219107460 # number of overall miss cycles 946system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6993 # number of ReadReq accesses(hits+misses) 947system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3660 # number of ReadReq accesses(hits+misses) 948system.cpu.l2cache.ReadReq_accesses::cpu.inst 1701984 # number of ReadReq accesses(hits+misses) 949system.cpu.l2cache.ReadReq_accesses::cpu.data 527584 # number of ReadReq accesses(hits+misses) 950system.cpu.l2cache.ReadReq_accesses::total 2240221 # number of ReadReq accesses(hits+misses) 951system.cpu.l2cache.Writeback_accesses::writebacks 686487 # number of Writeback accesses(hits+misses) 952system.cpu.l2cache.Writeback_accesses::total 686487 # number of Writeback accesses(hits+misses) 953system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2733 # number of UpgradeReq accesses(hits+misses) 954system.cpu.l2cache.UpgradeReq_accesses::total 2733 # number of UpgradeReq accesses(hits+misses) | 907system.cpu.l2cache.overall_misses::cpu.inst 18063 # number of overall misses 908system.cpu.l2cache.overall_misses::cpu.data 143288 # number of overall misses 909system.cpu.l2cache.overall_misses::total 161360 # number of overall misses 910system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 722250 # number of ReadReq miss cycles 911system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 165500 # number of ReadReq miss cycles 912system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1457697500 # number of ReadReq miss cycles 913system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1014855798 # number of ReadReq miss cycles 914system.cpu.l2cache.ReadReq_miss_latency::total 2473441048 # number of ReadReq miss cycles 915system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 528483 # number of UpgradeReq miss cycles 916system.cpu.l2cache.UpgradeReq_miss_latency::total 528483 # number of UpgradeReq miss cycles 917system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles 918system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles 919system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10018114706 # number of ReadExReq miss cycles 920system.cpu.l2cache.ReadExReq_miss_latency::total 10018114706 # number of ReadExReq miss cycles 921system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 722250 # number of demand (read+write) miss cycles 922system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 165500 # number of demand (read+write) miss cycles 923system.cpu.l2cache.demand_miss_latency::cpu.inst 1457697500 # number of demand (read+write) miss cycles 924system.cpu.l2cache.demand_miss_latency::cpu.data 11032970504 # number of demand (read+write) miss cycles 925system.cpu.l2cache.demand_miss_latency::total 12491555754 # number of demand (read+write) miss cycles 926system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 722250 # number of overall miss cycles 927system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 165500 # number of overall miss cycles 928system.cpu.l2cache.overall_miss_latency::cpu.inst 1457697500 # number of overall miss cycles 929system.cpu.l2cache.overall_miss_latency::cpu.data 11032970504 # number of overall miss cycles 930system.cpu.l2cache.overall_miss_latency::total 12491555754 # number of overall miss cycles 931system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6805 # number of ReadReq accesses(hits+misses) 932system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses) 933system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699116 # number of ReadReq accesses(hits+misses) 934system.cpu.l2cache.ReadReq_accesses::cpu.data 525086 # number of ReadReq accesses(hits+misses) 935system.cpu.l2cache.ReadReq_accesses::total 2234560 # number of ReadReq accesses(hits+misses) 936system.cpu.l2cache.Writeback_accesses::writebacks 683915 # number of Writeback accesses(hits+misses) 937system.cpu.l2cache.Writeback_accesses::total 683915 # number of Writeback accesses(hits+misses) 938system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2737 # number of UpgradeReq accesses(hits+misses) 939system.cpu.l2cache.UpgradeReq_accesses::total 2737 # number of UpgradeReq accesses(hits+misses) |
| 955system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 956system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 940system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 941system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 957system.cpu.l2cache.ReadExReq_accesses::cpu.data 296286 # number of ReadExReq accesses(hits+misses) 958system.cpu.l2cache.ReadExReq_accesses::total 296286 # number of ReadExReq accesses(hits+misses) 959system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6993 # number of demand (read+write) accesses 960system.cpu.l2cache.demand_accesses::cpu.itb.walker 3660 # number of demand (read+write) accesses 961system.cpu.l2cache.demand_accesses::cpu.inst 1701984 # number of demand (read+write) accesses 962system.cpu.l2cache.demand_accesses::cpu.data 823870 # number of demand (read+write) accesses 963system.cpu.l2cache.demand_accesses::total 2536507 # number of demand (read+write) accesses 964system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6993 # number of overall (read+write) accesses 965system.cpu.l2cache.overall_accesses::cpu.itb.walker 3660 # number of overall (read+write) accesses 966system.cpu.l2cache.overall_accesses::cpu.inst 1701984 # number of overall (read+write) accesses 967system.cpu.l2cache.overall_accesses::cpu.data 823870 # number of overall (read+write) accesses 968system.cpu.l2cache.overall_accesses::total 2536507 # number of overall (read+write) accesses 969system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001001 # miss rate for ReadReq accesses 970system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000546 # miss rate for ReadReq accesses 971system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadReq accesses 972system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023103 # miss rate for ReadReq accesses 973system.cpu.l2cache.ReadReq_miss_rate::total 0.013504 # miss rate for ReadReq accesses 974system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991584 # miss rate for UpgradeReq accesses 975system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991584 # miss rate for UpgradeReq accesses | 942system.cpu.l2cache.ReadExReq_accesses::cpu.data 295956 # number of ReadExReq accesses(hits+misses) 943system.cpu.l2cache.ReadExReq_accesses::total 295956 # number of ReadExReq accesses(hits+misses) 944system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6805 # number of demand (read+write) accesses 945system.cpu.l2cache.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses 946system.cpu.l2cache.demand_accesses::cpu.inst 1699116 # number of demand (read+write) accesses 947system.cpu.l2cache.demand_accesses::cpu.data 821042 # number of demand (read+write) accesses 948system.cpu.l2cache.demand_accesses::total 2530516 # number of demand (read+write) accesses 949system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6805 # number of overall (read+write) accesses 950system.cpu.l2cache.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses 951system.cpu.l2cache.overall_accesses::cpu.inst 1699116 # number of overall (read+write) accesses 952system.cpu.l2cache.overall_accesses::cpu.data 821042 # number of overall (read+write) accesses 953system.cpu.l2cache.overall_accesses::total 2530516 # number of overall (read+write) accesses 954system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001029 # miss rate for ReadReq accesses 955system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses 956system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010631 # miss rate for ReadReq accesses 957system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023335 # miss rate for ReadReq accesses 958system.cpu.l2cache.ReadReq_miss_rate::total 0.013571 # miss rate for ReadReq accesses 959system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991597 # miss rate for UpgradeReq accesses 960system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991597 # miss rate for UpgradeReq accesses |
| 976system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 977system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 961system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 962system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 978system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439589 # miss rate for ReadExReq accesses 979system.cpu.l2cache.ReadExReq_miss_rate::total 0.439589 # miss rate for ReadExReq accesses 980system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001001 # miss rate for demand accesses 981system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000546 # miss rate for demand accesses 982system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses 983system.cpu.l2cache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 984system.cpu.l2cache.demand_miss_rate::total 0.063274 # miss rate for demand accesses 985system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001001 # miss rate for overall accesses 986system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000546 # miss rate for overall accesses 987system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses 988system.cpu.l2cache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 989system.cpu.l2cache.overall_miss_rate::total 0.063274 # miss rate for overall accesses 990system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70750 # average ReadReq miss latency 991system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 992system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72912.839971 # average ReadReq miss latency 993system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76079.477398 # average ReadReq miss latency 994system.cpu.l2cache.ReadReq_avg_miss_latency::total 74188.390466 # average ReadReq miss latency 995system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 164.015129 # average UpgradeReq miss latency 996system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 164.015129 # average UpgradeReq miss latency 997system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72000 # average SCUpgradeReq miss latency 998system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72000 # average SCUpgradeReq miss latency 999system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68907.853414 # average ReadExReq miss latency 1000system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68907.853414 # average ReadExReq miss latency 1001system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency 1002system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 1003system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency 1004system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency 1005system.cpu.l2cache.demand_avg_miss_latency::total 69903.158728 # average overall miss latency 1006system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency 1007system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 1008system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency 1009system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency 1010system.cpu.l2cache.overall_avg_miss_latency::total 69903.158728 # average overall miss latency | 963system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442752 # miss rate for ReadExReq accesses 964system.cpu.l2cache.ReadExReq_miss_rate::total 0.442752 # miss rate for ReadExReq accesses 965system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001029 # miss rate for demand accesses 966system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses 967system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010631 # miss rate for demand accesses 968system.cpu.l2cache.demand_miss_rate::cpu.data 0.174520 # miss rate for demand accesses 969system.cpu.l2cache.demand_miss_rate::total 0.063766 # miss rate for demand accesses 970system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001029 # miss rate for overall accesses 971system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses 972system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010631 # miss rate for overall accesses 973system.cpu.l2cache.overall_miss_rate::cpu.data 0.174520 # miss rate for overall accesses 974system.cpu.l2cache.overall_miss_rate::total 0.063766 # miss rate for overall accesses 975system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103178.571429 # average ReadReq miss latency 976system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82750 # average ReadReq miss latency 977system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80700.741848 # average ReadReq miss latency 978system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82825.087570 # average ReadReq miss latency 979system.cpu.l2cache.ReadReq_avg_miss_latency::total 81564.420379 # average ReadReq miss latency 980system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 194.724761 # average UpgradeReq miss latency 981system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 194.724761 # average UpgradeReq miss latency 982system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 983system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 984system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76453.731492 # average ReadExReq miss latency 985system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76453.731492 # average ReadExReq miss latency 986system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency 987system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency 988system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency 989system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency 990system.cpu.l2cache.demand_avg_miss_latency::total 77414.202739 # average overall miss latency 991system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency 992system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency 993system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency 994system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency 995system.cpu.l2cache.overall_avg_miss_latency::total 77414.202739 # average overall miss latency |
| 1011system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1012system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1013system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1014system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1015system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1016system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1017system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1018system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 996system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 997system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 998system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 999system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1000system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1001system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1002system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1003system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1019system.cpu.l2cache.writebacks::writebacks 82185 # number of writebacks 1020system.cpu.l2cache.writebacks::total 82185 # number of writebacks | 1004system.cpu.l2cache.writebacks::writebacks 83215 # number of writebacks 1005system.cpu.l2cache.writebacks::total 83215 # number of writebacks |
| 1021system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses 1022system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 1006system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses 1007system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 1023system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18053 # number of ReadReq MSHR misses 1024system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12189 # number of ReadReq MSHR misses 1025system.cpu.l2cache.ReadReq_mshr_misses::total 30251 # number of ReadReq MSHR misses 1026system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2710 # number of UpgradeReq MSHR misses 1027system.cpu.l2cache.UpgradeReq_mshr_misses::total 2710 # number of UpgradeReq MSHR misses | 1008system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18063 # number of ReadReq MSHR misses 1009system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12253 # number of ReadReq MSHR misses 1010system.cpu.l2cache.ReadReq_mshr_misses::total 30325 # number of ReadReq MSHR misses 1011system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2714 # number of UpgradeReq MSHR misses 1012system.cpu.l2cache.UpgradeReq_mshr_misses::total 2714 # number of UpgradeReq MSHR misses |
| 1028system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1029system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1013system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1014system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1030system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130244 # number of ReadExReq MSHR misses 1031system.cpu.l2cache.ReadExReq_mshr_misses::total 130244 # number of ReadExReq MSHR misses | 1015system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131035 # number of ReadExReq MSHR misses 1016system.cpu.l2cache.ReadExReq_mshr_misses::total 131035 # number of ReadExReq MSHR misses |
| 1032system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses 1033system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 1017system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses 1018system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 1034system.cpu.l2cache.demand_mshr_misses::cpu.inst 18053 # number of demand (read+write) MSHR misses 1035system.cpu.l2cache.demand_mshr_misses::cpu.data 142433 # number of demand (read+write) MSHR misses 1036system.cpu.l2cache.demand_mshr_misses::total 160495 # number of demand (read+write) MSHR misses | 1019system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses 1020system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses 1021system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses |
| 1037system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses 1038system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 1022system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses 1023system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 1039system.cpu.l2cache.overall_mshr_misses::cpu.inst 18053 # number of overall MSHR misses 1040system.cpu.l2cache.overall_mshr_misses::cpu.data 142433 # number of overall MSHR misses 1041system.cpu.l2cache.overall_mshr_misses::total 160495 # number of overall MSHR misses 1042system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 408750 # number of ReadReq MSHR miss cycles 1043system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 1044system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1090271000 # number of ReadReq MSHR miss cycles 1045system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 775288750 # number of ReadReq MSHR miss cycles 1046system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1866093500 # number of ReadReq MSHR miss cycles 1047system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27282710 # number of UpgradeReq MSHR miss cycles 1048system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27282710 # number of UpgradeReq MSHR miss cycles 1049system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 1050system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 1051system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7345006540 # number of ReadExReq MSHR miss cycles 1052system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7345006540 # number of ReadExReq MSHR miss cycles 1053system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles 1054system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 1055system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1090271000 # number of demand (read+write) MSHR miss cycles 1056system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8120295290 # number of demand (read+write) MSHR miss cycles 1057system.cpu.l2cache.demand_mshr_miss_latency::total 9211100040 # number of demand (read+write) MSHR miss cycles 1058system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 408750 # number of overall MSHR miss cycles 1059system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 1060system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1090271000 # number of overall MSHR miss cycles 1061system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8120295290 # number of overall MSHR miss cycles 1062system.cpu.l2cache.overall_mshr_miss_latency::total 9211100040 # number of overall MSHR miss cycles 1063system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles 1064system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles 1065system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles 1066system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098165500 # number of WriteReq MSHR uncacheable cycles 1067system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 # number of WriteReq MSHR uncacheable cycles 1068system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles 1069system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles 1070system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles 1071system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses 1072system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses 1075system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses 1076system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses 1077system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses | 1024system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses 1025system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses 1026system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses 1027system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles 1028system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles 1029system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles 1030system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles 1031system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles 1032system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles 1033system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles 1034system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles 1035system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles 1036system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8377798294 # number of ReadExReq MSHR miss cycles 1037system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8377798294 # number of ReadExReq MSHR miss cycles 1038system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 635250 # number of demand (read+write) MSHR miss cycles 1039system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 140500 # number of demand (read+write) MSHR miss cycles 1040system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1231366500 # number of demand (read+write) MSHR miss cycles 1041system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9239411996 # number of demand (read+write) MSHR miss cycles 1042system.cpu.l2cache.demand_mshr_miss_latency::total 10471554246 # number of demand (read+write) MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 635250 # number of overall MSHR miss cycles 1044system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 140500 # number of overall MSHR miss cycles 1045system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1231366500 # number of overall MSHR miss cycles 1046system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9239411996 # number of overall MSHR miss cycles 1047system.cpu.l2cache.overall_mshr_miss_latency::total 10471554246 # number of overall MSHR miss cycles 1048system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 546237750 # number of ReadReq MSHR uncacheable cycles 1049system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5396778750 # number of ReadReq MSHR uncacheable cycles 1050system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5943016500 # number of ReadReq MSHR uncacheable cycles 1051system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4154268500 # number of WriteReq MSHR uncacheable cycles 1052system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4154268500 # number of WriteReq MSHR uncacheable cycles 1053system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 546237750 # number of overall MSHR uncacheable cycles 1054system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551047250 # number of overall MSHR uncacheable cycles 1055system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10097285000 # number of overall MSHR uncacheable cycles 1056system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for ReadReq accesses 1057system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses 1058system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for ReadReq accesses 1059system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023335 # mshr miss rate for ReadReq accesses 1060system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013571 # mshr miss rate for ReadReq accesses 1061system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991597 # mshr miss rate for UpgradeReq accesses 1062system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991597 # mshr miss rate for UpgradeReq accesses |
| 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1063system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1064system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1080system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses 1081system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses 1082system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses 1083system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses 1084system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses 1085system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses 1086system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses 1087system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses 1088system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses 1089system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses 1090system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses 1091system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses 1092system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency 1093system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 1094system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency 1095system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency 1096system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency 1097system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency 1098system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency 1099system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency 1100system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency 1101system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency 1102system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency 1103system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency 1104system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1105system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency 1106system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency 1107system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency 1108system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency 1109system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1110system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency 1111system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency 1112system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency | 1065system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442752 # mshr miss rate for ReadExReq accesses 1066system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442752 # mshr miss rate for ReadExReq accesses 1067system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for demand accesses 1068system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses 1069system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for demand accesses 1070system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for demand accesses 1071system.cpu.l2cache.demand_mshr_miss_rate::total 0.063766 # mshr miss rate for demand accesses 1072system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for overall accesses 1073system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses 1074system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for overall accesses 1075system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for overall accesses 1076system.cpu.l2cache.overall_mshr_miss_rate::total 0.063766 # mshr miss rate for overall accesses 1077system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average ReadReq mshr miss latency 1078system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70250 # average ReadReq mshr miss latency 1079system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715 # average ReadReq mshr miss latency 1080system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529 # average ReadReq mshr miss latency 1081system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596 # average ReadReq mshr miss latency 1082system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139 # average UpgradeReq mshr miss latency 1083system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139 # average UpgradeReq mshr miss latency 1084system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency 1085system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency 1086system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709 # average ReadExReq mshr miss latency 1087system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709 # average ReadExReq mshr miss latency 1088system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency 1089system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency 1090system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency 1091system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency 1092system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency 1093system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency 1094system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency 1095system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency 1096system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency 1097system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency |
| 1113system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1114system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1115system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1116system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1117system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1118system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1119system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1120system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1121system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1098system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1099system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1100system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1101system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1102system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1103system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1104system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1105system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1106system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1122system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution | 1107system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution 1108system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution 1109system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution 1110system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution 1111system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution 1112system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution 1113system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution |
| 1129system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1114system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1130system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution 1132system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution 1133system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) 1135system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) 1136system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) 1137system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) 1138system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) 1139system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) 1140system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) 1143system.cpu.toL2Bus.snoops 53107 # Total snoops (count) 1144system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram | 1115system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution 1116system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution 1118system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes) 1119system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes) 1120system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes) 1121system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes) 1122system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes) 1123system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes) 1124system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes) 1125system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes) 1126system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) 1127system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) 1128system.cpu.toL2Bus.snoops 53413 # Total snoops (count) 1129system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram 1130system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram 1131system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram |
| 1147system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1150system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1132system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1133system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1134system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1135system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1151system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1152system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram 1154system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram | 1136system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram |
| 1155system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1138system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1156system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram 1159system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) | 1139system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1140system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram 1142system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) |
| 1160system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1161system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1162system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1143system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1144system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1145system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1163system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) | 1146system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks) |
| 1164system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1147system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1165system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) | 1148system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks) |
| 1166system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1167system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1168system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1149system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1150system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1151system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1169system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) | 1152system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks) |
| 1170system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1153system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1171system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 1172system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 1173system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 1174system.iobus.trans_dist::WriteResp 22814 # Transaction distribution | 1154system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1155system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1156system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1157system.iobus.trans_dist::WriteResp 22790 # Transaction distribution |
| 1175system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 1158system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 1176system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) | 1159system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) |
| 1177system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1189system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1195system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 1160system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1172system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1197system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) | 1180system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) |
| 1198system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1199system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) | 1181system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) |
| 1200system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) | 1183system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) |
| 1202system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1214system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1221system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 1185system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1197system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1222system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) | 1205system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) |
| 1223system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1224system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) | 1206system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) |
| 1225system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 1226system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) | 1208system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) |
| 1227system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1228system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1229system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1230system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1231system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1232system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1233system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1234system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 1258system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1259system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1260system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1261system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1262system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1263system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1264system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1265system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1210system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1211system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1212system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1213system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1214system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1215system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1216system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1217system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 1241system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1242system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1244system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1246system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1247system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1248system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1266system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) | 1249system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks) |
| 1267system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1268system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1269system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1250system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1251system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1252system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1270system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) | 1253system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) |
| 1271system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1254system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1272system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) | 1255system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks) |
| 1273system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1274system.iocache.tags.replacements 36424 # number of replacements | 1256system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1257system.iocache.tags.replacements 36424 # number of replacements |
| 1275system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use | 1258system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use |
| 1276system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1277system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1278system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1259system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1260system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1261system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1279system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. 1280system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor 1281system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy 1282system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy | 1262system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit. 1263system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor 1264system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy 1265system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy |
| 1283system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1284system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1285system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1286system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1287system.iocache.tags.data_accesses 328122 # Number of data accesses 1288system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1289system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1290system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1291system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 1292system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1293system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1294system.iocache.overall_misses::realview.ide 234 # number of overall misses 1295system.iocache.overall_misses::total 234 # number of overall misses | 1266system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1267system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1268system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1269system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1270system.iocache.tags.data_accesses 328122 # Number of data accesses 1271system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1272system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1273system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1274system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 1275system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1276system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1277system.iocache.overall_misses::realview.ide 234 # number of overall misses 1278system.iocache.overall_misses::total 234 # number of overall misses |
| 1296system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles 1297system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles 1298system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles 1299system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles 1300system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles 1301system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles 1302system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles 1303system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles | 1279system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles 1280system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles 1281system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles 1282system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles 1283system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles 1284system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles 1285system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles 1286system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles |
| 1304system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1305system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1306system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1307system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1308system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1309system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1310system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1311system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1312system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1313system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1314system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1315system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1316system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1317system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1318system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1319system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1287system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1288system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1289system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1290system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1291system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1292system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1293system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1294system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1295system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1296system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1297system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1298system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1299system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1300system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1301system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1302system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1320system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency 1321system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency 1322system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency 1323system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency 1324system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency 1325system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency 1326system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency 1327system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency 1328system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked | 1303system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency 1304system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency 1305system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency 1306system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency 1307system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency 1308system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency 1309system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency 1310system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency 1311system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked |
| 1329system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1312system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1330system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked | 1313system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked |
| 1331system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1314system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1332system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked | 1315system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked |
| 1333system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1334system.iocache.fast_writes 0 # number of fast writes performed 1335system.iocache.cache_copies 0 # number of cache copies performed 1336system.iocache.writebacks::writebacks 36190 # number of writebacks 1337system.iocache.writebacks::total 36190 # number of writebacks 1338system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1339system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1340system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1341system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 1342system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1343system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1344system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1345system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses | 1316system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1317system.iocache.fast_writes 0 # number of fast writes performed 1318system.iocache.cache_copies 0 # number of cache copies performed 1319system.iocache.writebacks::writebacks 36190 # number of writebacks 1320system.iocache.writebacks::total 36190 # number of writebacks 1321system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1322system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1323system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1324system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 1325system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1326system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1327system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1328system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses |
| 1346system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles 1347system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles 1348system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles 1349system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles 1350system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles 1351system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles 1352system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles 1353system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles | 1329system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles 1330system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles 1331system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles 1332system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles 1333system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles 1334system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles 1335system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles 1336system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles |
| 1354system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1355system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1356system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1357system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1358system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1359system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1360system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1361system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1337system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1338system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1339system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1340system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1341system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1342system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1343system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1344system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1362system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency 1363system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency 1364system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency 1365system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency 1366system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency 1367system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency 1368system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency 1369system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency | 1345system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency 1346system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency 1347system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency 1348system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency 1349system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency 1350system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency 1351system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency 1352system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency |
| 1370system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1353system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1371system.membus.trans_dist::ReadReq 70661 # Transaction distribution 1372system.membus.trans_dist::ReadResp 70661 # Transaction distribution 1373system.membus.trans_dist::WriteReq 27618 # Transaction distribution 1374system.membus.trans_dist::WriteResp 27618 # Transaction distribution 1375system.membus.trans_dist::Writeback 118375 # Transaction distribution | 1354system.membus.trans_dist::ReadReq 70719 # Transaction distribution 1355system.membus.trans_dist::ReadResp 70719 # Transaction distribution 1356system.membus.trans_dist::WriteReq 27589 # Transaction distribution 1357system.membus.trans_dist::WriteResp 27589 # Transaction distribution 1358system.membus.trans_dist::Writeback 119405 # Transaction distribution |
| 1376system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1377system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 1359system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1360system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 1378system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution | 1361system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution |
| 1379system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1362system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1380system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution 1381system.membus.trans_dist::ReadExReq 128454 # Transaction distribution 1382system.membus.trans_dist::ReadExResp 128454 # Transaction distribution 1383system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) | 1363system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution 1364system.membus.trans_dist::ReadExReq 129241 # Transaction distribution 1365system.membus.trans_dist::ReadExResp 129241 # Transaction distribution 1366system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) |
| 1384system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) | 1367system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) |
| 1385system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 1386system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) 1387system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) | 1368system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) 1369system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes) 1370system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes) |
| 1388system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) 1389system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) | 1371system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) 1372system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) |
| 1390system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) 1391system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) | 1373system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes) 1374system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) |
| 1392system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) | 1375system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) |
| 1393system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 1394system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) 1395system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) | 1376system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) 1377system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes) 1378system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes) |
| 1396system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1397system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) | 1379system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1380system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) |
| 1398system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) | 1381system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) |
| 1399system.membus.snoops 498 # Total snoops (count) | 1382system.membus.snoops 498 # Total snoops (count) |
| 1400system.membus.snoop_fanout::samples 318040 # Request fanout histogram | 1383system.membus.snoop_fanout::samples 319985 # Request fanout histogram |
| 1401system.membus.snoop_fanout::mean 1 # Request fanout histogram 1402system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1403system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1404system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1384system.membus.snoop_fanout::mean 1 # Request fanout histogram 1385system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1386system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1387system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1405system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram | 1388system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram |
| 1406system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1407system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1408system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1409system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1389system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1390system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1391system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1392system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1410system.membus.snoop_fanout::total 318040 # Request fanout histogram 1411system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) | 1393system.membus.snoop_fanout::total 319985 # Request fanout histogram 1394system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) |
| 1412system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1395system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1413system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) | 1396system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) |
| 1414system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1397system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1415system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) | 1398system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) |
| 1416system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1399system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1417system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) 1418system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 1419system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) 1420system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1421system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) | 1400system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks) 1401system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1402system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks) 1403system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1404system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks) |
| 1422system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1423system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1424system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1425system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1426system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1427system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1428system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1429system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- | 1405system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1406system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1407system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1408system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1409system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1410system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1411system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1412system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- |