| stats.txt (10517:ba51f8572571) | stats.txt (10535:4ccec5baf82c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.902619 # Number of seconds simulated 4sim_ticks 2902619131000 # Number of ticks simulated 5final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.902619 # Number of seconds simulated 4sim_ticks 2902619131000 # Number of ticks simulated 5final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 756630 # Simulator instruction rate (inst/s) 8host_op_rate 912268 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19520630002 # Simulator tick rate (ticks/s) 10host_mem_usage 553652 # Number of bytes of host memory used 11host_seconds 148.70 # Real time elapsed on the host 12sim_insts 112506995 # Number of instructions simulated 13sim_ops 135649572 # Number of ops (including micro ops) simulated | 7host_inst_rate 783857 # Simulator instruction rate (inst/s) 8host_op_rate 945096 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20223090080 # Simulator tick rate (ticks/s) 10host_mem_usage 560080 # Number of bytes of host memory used 11host_seconds 143.53 # Real time elapsed on the host 12sim_insts 112507011 # Number of instructions simulated 13sim_ops 135649580 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | |
| 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
|
| 21system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory | |
| 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory |
|
| 27system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory | 27system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory |
| 28system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | |
| 29system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
|
| 33system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory | |
| 36system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory |
|
| 37system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory | 37system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory |
| 38system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) | |
| 39system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) |
|
| 43system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s) | 43system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s) |
| 47system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) | |
| 48system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) | 47system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) |
|
| 49system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s) 50system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s) 50system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) | |
| 52system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s) | 51system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s) |
| 55system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) |
|
| 56system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.readReqs 168277 # Number of read requests accepted 58system.physmem.writeReqs 122785 # Number of write requests accepted 59system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue 60system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue 61system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM 62system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue 63system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM --- 142 unchanged lines hidden (view full) --- 206system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see | 56system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.readReqs 168277 # Number of read requests accepted 58system.physmem.writeReqs 122785 # Number of write requests accepted 59system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue 60system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue 61system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM 62system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue 63system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM --- 142 unchanged lines hidden (view full) --- 206system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see |
| 214system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation 218system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation | 214system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::gmean 183.640199 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::stdev 334.584074 # Bytes accessed per row activation 218system.physmem.bytesPerActivate::0-127 21469 36.67% 36.67% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::128-255 14640 25.00% 61.67% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::256-383 5516 9.42% 71.09% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::384-511 3473 5.93% 77.02% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::512-639 2278 3.89% 80.91% # Bytes accessed per row activation |
| 223system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation | 223system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation |
| 224system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation | 224system.physmem.bytesPerActivate::768-895 999 1.71% 85.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.12% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1024-1151 7539 12.88% 100.00% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation |
| 228system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads --- 27 unchanged lines hidden (view full) --- 263system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads | 228system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads --- 27 unchanged lines hidden (view full) --- 263system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads |
| 271system.physmem.totQLat 1492072500 # Total ticks spent queuing 272system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM | 271system.physmem.totQLat 1491102500 # Total ticks spent queuing 272system.physmem.totMemAccLat 4642883750 # Total ticks spent from burst creation until serviced by the DRAM |
| 273system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers | 273system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers |
| 274system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst | 274system.physmem.avgQLat 8870.59 # Average queueing delay per DRAM burst |
| 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 276system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst | 276system.physmem.avgMemAccLat 27620.59 # Average memory access latency per DRAM burst |
| 277system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.05 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing | 277system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.05 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing |
| 287system.physmem.readRowHits 138435 # Number of row buffer hits during reads 288system.physmem.writeRowHits 90000 # Number of row buffer hits during writes | 287system.physmem.readRowHits 138436 # Number of row buffer hits during reads 288system.physmem.writeRowHits 90002 # Number of row buffer hits during writes |
| 289system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes 291system.physmem.avgGap 9972510.17 # Average gap between requests 292system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined | 289system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes 291system.physmem.avgGap 9972510.17 # Average gap between requests 292system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined |
| 293system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states | 293system.physmem.memoryStateTime::IDLE 2755210874500 # Time in different power states |
| 294system.physmem.memoryStateTime::REF 96924620000 # Time in different power states 295system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 294system.physmem.memoryStateTime::REF 96924620000 # Time in different power states 295system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 296system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states | 296system.physmem.memoryStateTime::ACT 50483546000 # Time in different power states |
| 297system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 297system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 298system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ) 299system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ) 300system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ) 301system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ) | 298system.physmem.actEnergy::0 226731960 # Energy for activate commands per rank (pJ) 299system.physmem.actEnergy::1 215936280 # Energy for activate commands per rank (pJ) 300system.physmem.preEnergy::0 123712875 # Energy for precharge commands per rank (pJ) 301system.physmem.preEnergy::1 117822375 # Energy for precharge commands per rank (pJ) |
| 302system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) 303system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) 304system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) 305system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) 306system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) 307system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) | 302system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) 303system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) 304system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) 305system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) 306system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) 307system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) |
| 308system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ) 309system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ) 310system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ) 311system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ) 312system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ) 313system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ) 314system.physmem.averagePower::0 669.480439 # Core power per rank (mW) 315system.physmem.averagePower::1 669.392466 # Core power per rank (mW) | 308system.physmem.actBackEnergy::0 86730297120 # Energy for active background per rank (pJ) 309system.physmem.actBackEnergy::1 85558991580 # Energy for active background per rank (pJ) 310system.physmem.preBackEnergy::0 1665488607000 # Energy for precharge background per rank (pJ) 311system.physmem.preBackEnergy::1 1666516068000 # Energy for precharge background per rank (pJ) 312system.physmem.totalEnergy::0 1943242491315 # Total energy per rank (pJ) 313system.physmem.totalEnergy::1 1942986381555 # Total energy per rank (pJ) 314system.physmem.averagePower::0 669.480387 # Core power per rank (mW) 315system.physmem.averagePower::1 669.392153 # Core power per rank (mW) |
| 316system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) | 316system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) |
| 328system.membus.trans_dist::ReadReq 70649 # Transaction distribution 329system.membus.trans_dist::ReadResp 70649 # Transaction distribution 330system.membus.trans_dist::WriteReq 27618 # Transaction distribution 331system.membus.trans_dist::WriteResp 27618 # Transaction distribution 332system.membus.trans_dist::Writeback 82180 # Transaction distribution 333system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 334system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 335system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution 336system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 337system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution 338system.membus.trans_dist::ReadExReq 128451 # Transaction distribution 339system.membus.trans_dist::ReadExResp 128451 # Transaction distribution 340system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) 345system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 346system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) 347system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) 348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) 352system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) 353system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 354system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 355system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) 356system.membus.snoops 219 # Total snoops (count) 357system.membus.snoop_fanout::samples 281834 # Request fanout histogram 358system.membus.snoop_fanout::mean 1 # Request fanout histogram 359system.membus.snoop_fanout::stdev 0 # Request fanout histogram 360system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 361system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 362system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram 363system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 365system.membus.snoop_fanout::min_value 1 # Request fanout histogram 366system.membus.snoop_fanout::max_value 1 # Request fanout histogram 367system.membus.snoop_fanout::total 281834 # Request fanout histogram 368system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) 369system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 370system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 371system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 372system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) 373system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 374system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) 375system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 376system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks) 377system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 378system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) 379system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 380system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 381system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 382system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 383system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 384system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 385system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 386system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 387system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 388system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 389system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 390system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 391system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 392system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 393system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 394system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 395system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 396system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 397system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 398system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 399system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 400system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 401system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 402system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 403system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 404system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 405system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 406system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 407system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 408system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 409system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 410system.realview.ethernet.droppedPackets 0 # number of packets dropped | |
| 411system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 412system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 413system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 414system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 415system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 416system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 328system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 329system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 330system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 331system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 332system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 333system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 417system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 418system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 419system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 420system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 421system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 422system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 423system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 424system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 425system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 426system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 427system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 428system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 429system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 430system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 431system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 432system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 433system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 434system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 435system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 436system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 437system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 438system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 439system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 440system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 441system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 442system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 443system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 444system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 445system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 446system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 447system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 448system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 449system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 450system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 451system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 452system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 453system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 454system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 455system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 456system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 457system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 458system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 459system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 460system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 461system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 462system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 463system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 464system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 465system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 466system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 467system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 468system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 469system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 470system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 471system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 472system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 473system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 474system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 475system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 476system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 477system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 478system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 479system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 480system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 481system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 482system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 483system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 484system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 485system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 486system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 487system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 488system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 489system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 490system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 491system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 492system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 493system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 494system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 495system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 496system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 497system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 498system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 499system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 500system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 501system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 502system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 503system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 504system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 505system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 506system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 507system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 508system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 509system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 510system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 511system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) 512system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 513system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 514system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 515system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 516system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 517system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) 518system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | |
| 519system.cpu_clk_domain.clock 500 # Clock period in ticks 520system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 521system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 522system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 523system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 524system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 525system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 526system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 535system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 536system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 537system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 538system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 539system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 540system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 541system.cpu.dtb.inst_hits 0 # ITB inst hits 542system.cpu.dtb.inst_misses 0 # ITB inst misses | 334system.cpu_clk_domain.clock 500 # Clock period in ticks 335system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 336system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 337system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 338system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 339system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 340system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 341system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 350system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 351system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 352system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 353system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 354system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 355system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 356system.cpu.dtb.inst_hits 0 # ITB inst hits 357system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 543system.cpu.dtb.read_hits 24532668 # DTB read hits | 358system.cpu.dtb.read_hits 24532671 # DTB read hits |
| 544system.cpu.dtb.read_misses 8148 # DTB read misses | 359system.cpu.dtb.read_misses 8148 # DTB read misses |
| 545system.cpu.dtb.write_hits 19614514 # DTB write hits | 360system.cpu.dtb.write_hits 19614515 # DTB write hits |
| 546system.cpu.dtb.write_misses 1410 # DTB write misses 547system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 548system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 549system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 550system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 551system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB 552system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 553system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch 554system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 555system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions | 361system.cpu.dtb.write_misses 1410 # DTB write misses 362system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 363system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 364system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 365system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 366system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB 367system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 368system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch 369system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions |
| 556system.cpu.dtb.read_accesses 24540816 # DTB read accesses 557system.cpu.dtb.write_accesses 19615924 # DTB write accesses | 371system.cpu.dtb.read_accesses 24540819 # DTB read accesses 372system.cpu.dtb.write_accesses 19615925 # DTB write accesses |
| 558system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 373system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 559system.cpu.dtb.hits 44147182 # DTB hits | 374system.cpu.dtb.hits 44147186 # DTB hits |
| 560system.cpu.dtb.misses 9558 # DTB misses | 375system.cpu.dtb.misses 9558 # DTB misses |
| 561system.cpu.dtb.accesses 44156740 # DTB accesses | 376system.cpu.dtb.accesses 44156744 # DTB accesses |
| 562system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 563system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 564system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 565system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 566system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 567system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 568system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 569system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 575system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 576system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 577system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 578system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 579system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 580system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 581system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 582system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 377system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 378system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 379system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 380system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 381system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 382system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 390system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 583system.cpu.itb.inst_hits 115605897 # ITB inst hits | 398system.cpu.itb.inst_hits 115605918 # ITB inst hits |
| 584system.cpu.itb.inst_misses 4762 # ITB inst misses 585system.cpu.itb.read_hits 0 # DTB read hits 586system.cpu.itb.read_misses 0 # DTB read misses 587system.cpu.itb.write_hits 0 # DTB write hits 588system.cpu.itb.write_misses 0 # DTB write misses 589system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 590system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 591system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 592system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 593system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 594system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 595system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 596system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 597system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 598system.cpu.itb.read_accesses 0 # DTB read accesses 599system.cpu.itb.write_accesses 0 # DTB write accesses | 399system.cpu.itb.inst_misses 4762 # ITB inst misses 400system.cpu.itb.read_hits 0 # DTB read hits 401system.cpu.itb.read_misses 0 # DTB read misses 402system.cpu.itb.write_hits 0 # DTB write hits 403system.cpu.itb.write_misses 0 # DTB write misses 404system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 405system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 406system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 407system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 409system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 410system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 411system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu.itb.read_accesses 0 # DTB read accesses 414system.cpu.itb.write_accesses 0 # DTB write accesses |
| 600system.cpu.itb.inst_accesses 115610659 # ITB inst accesses 601system.cpu.itb.hits 115605897 # DTB hits | 415system.cpu.itb.inst_accesses 115610680 # ITB inst accesses 416system.cpu.itb.hits 115605918 # DTB hits |
| 602system.cpu.itb.misses 4762 # DTB misses | 417system.cpu.itb.misses 4762 # DTB misses |
| 603system.cpu.itb.accesses 115610659 # DTB accesses | 418system.cpu.itb.accesses 115610680 # DTB accesses |
| 604system.cpu.numCycles 5805238262 # number of cpu cycles simulated 605system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 606system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 419system.cpu.numCycles 5805238262 # number of cpu cycles simulated 420system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 421system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 607system.cpu.committedInsts 112506995 # Number of instructions committed 608system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed 609system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses | 422system.cpu.committedInsts 112507011 # Number of instructions committed 423system.cpu.committedOps 135649580 # Number of ops (including micro ops) committed 424system.cpu.num_int_alu_accesses 119948946 # Number of integer alu accesses |
| 610system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 611system.cpu.num_func_calls 9898964 # number of times a function call or return occured | 425system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 426system.cpu.num_func_calls 9898964 # number of times a function call or return occured |
| 612system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls 613system.cpu.num_int_insts 119948923 # number of integer instructions | 427system.cpu.num_conditional_control_insts 15236406 # number of instructions that are conditional controls 428system.cpu.num_int_insts 119948946 # number of integer instructions |
| 614system.cpu.num_fp_insts 11161 # number of float instructions | 429system.cpu.num_fp_insts 11161 # number of float instructions |
| 615system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read 616system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written | 430system.cpu.num_int_register_reads 218165471 # number of times the integer registers were read 431system.cpu.num_int_register_writes 82686622 # number of times the integer registers were written |
| 617system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 618system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written | 432system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 433system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written |
| 619system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read 620system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written 621system.cpu.num_mem_refs 45428231 # number of memory refs 622system.cpu.num_load_insts 24855392 # Number of load instructions 623system.cpu.num_store_insts 20572839 # Number of store instructions 624system.cpu.num_idle_cycles 5386456122.024144 # Number of idle cycles 625system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles 626system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles 627system.cpu.idle_fraction 0.927861 # Percentage of idle cycles 628system.cpu.Branches 25929456 # Number of branches fetched | 434system.cpu.num_cc_register_reads 489970666 # number of times the CC registers were read 435system.cpu.num_cc_register_writes 51914345 # number of times the CC registers were written 436system.cpu.num_mem_refs 45428250 # number of memory refs 437system.cpu.num_load_insts 24855398 # Number of load instructions 438system.cpu.num_store_insts 20572852 # Number of store instructions 439system.cpu.num_idle_cycles 5386458042.024144 # Number of idle cycles 440system.cpu.num_busy_cycles 418780219.975856 # Number of busy cycles 441system.cpu.not_idle_fraction 0.072138 # Percentage of non-idle cycles 442system.cpu.idle_fraction 0.927862 # Percentage of idle cycles 443system.cpu.Branches 25929462 # Number of branches fetched |
| 629system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction | 444system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction |
| 630system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction 631system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction | 445system.cpu.op_class::IntAlu 93218062 67.17% 67.18% # Class of executed instruction 446system.cpu.op_class::IntMult 114523 0.08% 67.26% # Class of executed instruction |
| 632system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 633system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 634system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 635system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 636system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 637system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 638system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 639system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 651system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 652system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 653system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 654system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 655system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction 656system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 657system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 658system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction | 447system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 448system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 449system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 450system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 451system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 452system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 453system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 454system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 466system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 467system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 468system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 469system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 470system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction 471system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 472system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 473system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction |
| 659system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction 660system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction | 474system.cpu.op_class::MemRead 24855398 17.91% 85.18% # Class of executed instruction 475system.cpu.op_class::MemWrite 20572852 14.82% 100.00% # Class of executed instruction |
| 661system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 662system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 476system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 477system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 663system.cpu.op_class::total 138771625 # Class of executed instruction | 478system.cpu.op_class::total 138771647 # Class of executed instruction |
| 664system.cpu.kern.inst.arm 0 # number of arm instructions executed 665system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed | 479system.cpu.kern.inst.arm 0 # number of arm instructions executed 480system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed |
| 481system.cpu.dcache.tags.replacements 822746 # number of replacements 482system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use 483system.cpu.dcache.tags.total_refs 43252602 # Total number of references to valid blocks. 484system.cpu.dcache.tags.sampled_refs 823258 # Sample count of references to valid blocks. 485system.cpu.dcache.tags.avg_refs 52.538332 # Average number of references to valid blocks. 486system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. 487system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor 488system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy 489system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy 490system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 491system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 492system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 493system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 494system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 495system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 496system.cpu.dcache.tags.tag_accesses 177194888 # Number of tag accesses 497system.cpu.dcache.tags.data_accesses 177194888 # Number of data accesses 498system.cpu.dcache.ReadReq_hits::cpu.data 23122389 # number of ReadReq hits 499system.cpu.dcache.ReadReq_hits::total 23122389 # number of ReadReq hits 500system.cpu.dcache.WriteReq_hits::cpu.data 18831358 # number of WriteReq hits 501system.cpu.dcache.WriteReq_hits::total 18831358 # number of WriteReq hits 502system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits 503system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits 504system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits 505system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits 506system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits 507system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits 508system.cpu.dcache.demand_hits::cpu.data 41953747 # number of demand (read+write) hits 509system.cpu.dcache.demand_hits::total 41953747 # number of demand (read+write) hits 510system.cpu.dcache.overall_hits::cpu.data 42345868 # number of overall hits 511system.cpu.dcache.overall_hits::total 42345868 # number of overall hits 512system.cpu.dcache.ReadReq_misses::cpu.data 402166 # number of ReadReq misses 513system.cpu.dcache.ReadReq_misses::total 402166 # number of ReadReq misses 514system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses 515system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses 516system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses 517system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses 518system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses 519system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses 520system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 521system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 522system.cpu.dcache.demand_misses::cpu.data 701192 # number of demand (read+write) misses 523system.cpu.dcache.demand_misses::total 701192 # number of demand (read+write) misses 524system.cpu.dcache.overall_misses::cpu.data 820347 # number of overall misses 525system.cpu.dcache.overall_misses::total 820347 # number of overall misses 526system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900442000 # number of ReadReq miss cycles 527system.cpu.dcache.ReadReq_miss_latency::total 5900442000 # number of ReadReq miss cycles 528system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658351003 # number of WriteReq miss cycles 529system.cpu.dcache.WriteReq_miss_latency::total 11658351003 # number of WriteReq miss cycles 530system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles 531system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles 532system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles 533system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles 534system.cpu.dcache.demand_miss_latency::cpu.data 17558793003 # number of demand (read+write) miss cycles 535system.cpu.dcache.demand_miss_latency::total 17558793003 # number of demand (read+write) miss cycles 536system.cpu.dcache.overall_miss_latency::cpu.data 17558793003 # number of overall miss cycles 537system.cpu.dcache.overall_miss_latency::total 17558793003 # number of overall miss cycles 538system.cpu.dcache.ReadReq_accesses::cpu.data 23524555 # number of ReadReq accesses(hits+misses) 539system.cpu.dcache.ReadReq_accesses::total 23524555 # number of ReadReq accesses(hits+misses) 540system.cpu.dcache.WriteReq_accesses::cpu.data 19130384 # number of WriteReq accesses(hits+misses) 541system.cpu.dcache.WriteReq_accesses::total 19130384 # number of WriteReq accesses(hits+misses) 542system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) 543system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) 544system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) 545system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) 546system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses) 547system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses) 548system.cpu.dcache.demand_accesses::cpu.data 42654939 # number of demand (read+write) accesses 549system.cpu.dcache.demand_accesses::total 42654939 # number of demand (read+write) accesses 550system.cpu.dcache.overall_accesses::cpu.data 43166215 # number of overall (read+write) accesses 551system.cpu.dcache.overall_accesses::total 43166215 # number of overall (read+write) accesses 552system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses 553system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses 554system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses 555system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses 556system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses 557system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses 558system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses 559system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses 560system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 561system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 562system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses 563system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses 564system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses 565system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses 566system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14671.657972 # average ReadReq miss latency 567system.cpu.dcache.ReadReq_avg_miss_latency::total 14671.657972 # average ReadReq miss latency 568system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.750239 # average WriteReq miss latency 569system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.750239 # average WriteReq miss latency 570system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency 571system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency 572system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency 573system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency 574system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.348166 # average overall miss latency 575system.cpu.dcache.demand_avg_miss_latency::total 25041.348166 # average overall miss latency 576system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.104608 # average overall miss latency 577system.cpu.dcache.overall_avg_miss_latency::total 21404.104608 # average overall miss latency 578system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 579system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 581system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked 583system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 584system.cpu.dcache.fast_writes 0 # number of fast writes performed 585system.cpu.dcache.cache_copies 0 # number of cache copies performed 586system.cpu.dcache.writebacks::writebacks 686230 # number of writebacks 587system.cpu.dcache.writebacks::total 686230 # number of writebacks 588system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits 589system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits 590system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits 591system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits 592system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits 593system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits 594system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits 595system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits 596system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401539 # number of ReadReq MSHR misses 597system.cpu.dcache.ReadReq_mshr_misses::total 401539 # number of ReadReq MSHR misses 598system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses 599system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses 600system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses 601system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses 602system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses 603system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses 604system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 605system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 606system.cpu.dcache.demand_mshr_misses::cpu.data 700565 # number of demand (read+write) MSHR misses 607system.cpu.dcache.demand_mshr_misses::total 700565 # number of demand (read+write) MSHR misses 608system.cpu.dcache.overall_mshr_misses::cpu.data 817569 # number of overall MSHR misses 609system.cpu.dcache.overall_mshr_misses::total 817569 # number of overall MSHR misses 610system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083326500 # number of ReadReq MSHR miss cycles 611system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083326500 # number of ReadReq MSHR miss cycles 612system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002800997 # number of WriteReq MSHR miss cycles 613system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002800997 # number of WriteReq MSHR miss cycles 614system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles 615system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles 616system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles 617system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles 618system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles 619system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles 620system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086127497 # number of demand (read+write) MSHR miss cycles 621system.cpu.dcache.demand_mshr_miss_latency::total 16086127497 # number of demand (read+write) MSHR miss cycles 622system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497317497 # number of overall MSHR miss cycles 623system.cpu.dcache.overall_mshr_miss_latency::total 17497317497 # number of overall MSHR miss cycles 624system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles 625system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles 626system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles 627system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles 628system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles 629system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles 630system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses 631system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses 632system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses 633system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses 634system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses 635system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses 636system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses 637system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses 638system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 639system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 640system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses 641system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses 642system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses 643system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses 644system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12659.608407 # average ReadReq mshr miss latency 645system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12659.608407 # average ReadReq mshr miss latency 646system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.465936 # average WriteReq mshr miss latency 647system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.465936 # average WriteReq mshr miss latency 648system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency 649system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency 650system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency 651system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency 652system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency 653system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency 654system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22961.648808 # average overall mshr miss latency 655system.cpu.dcache.demand_avg_mshr_miss_latency::total 22961.648808 # average overall mshr miss latency 656system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21401.640103 # average overall mshr miss latency 657system.cpu.dcache.overall_avg_mshr_miss_latency::total 21401.640103 # average overall mshr miss latency 658system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 659system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 660system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 661system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 662system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 663system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 664system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 666system.cpu.icache.tags.replacements 1699818 # number of replacements 667system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use | 665system.cpu.icache.tags.replacements 1699818 # number of replacements 666system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use |
| 668system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks. | 667system.cpu.icache.tags.total_refs 113905582 # Total number of references to valid blocks. |
| 669system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. | 668system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. |
| 670system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks. | 669system.cpu.icache.tags.avg_refs 66.990280 # Average number of references to valid blocks. |
| 671system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. 672system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor 673system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy 675system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 678system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 679system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 680system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 670system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. 671system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor 672system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 678system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 679system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 681system.cpu.icache.tags.tag_accesses 117306233 # Number of tag accesses 682system.cpu.icache.tags.data_accesses 117306233 # Number of data accesses 683system.cpu.icache.ReadReq_hits::cpu.inst 113905561 # number of ReadReq hits 684system.cpu.icache.ReadReq_hits::total 113905561 # number of ReadReq hits 685system.cpu.icache.demand_hits::cpu.inst 113905561 # number of demand (read+write) hits 686system.cpu.icache.demand_hits::total 113905561 # number of demand (read+write) hits 687system.cpu.icache.overall_hits::cpu.inst 113905561 # number of overall hits 688system.cpu.icache.overall_hits::total 113905561 # number of overall hits | 680system.cpu.icache.tags.tag_accesses 117306254 # Number of tag accesses 681system.cpu.icache.tags.data_accesses 117306254 # Number of data accesses 682system.cpu.icache.ReadReq_hits::cpu.inst 113905582 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 113905582 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 113905582 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 113905582 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 113905582 # number of overall hits 687system.cpu.icache.overall_hits::total 113905582 # number of overall hits |
| 689system.cpu.icache.ReadReq_misses::cpu.inst 1700336 # number of ReadReq misses 690system.cpu.icache.ReadReq_misses::total 1700336 # number of ReadReq misses 691system.cpu.icache.demand_misses::cpu.inst 1700336 # number of demand (read+write) misses 692system.cpu.icache.demand_misses::total 1700336 # number of demand (read+write) misses 693system.cpu.icache.overall_misses::cpu.inst 1700336 # number of overall misses 694system.cpu.icache.overall_misses::total 1700336 # number of overall misses | 688system.cpu.icache.ReadReq_misses::cpu.inst 1700336 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 1700336 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 1700336 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 1700336 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 1700336 # number of overall misses 693system.cpu.icache.overall_misses::total 1700336 # number of overall misses |
| 695system.cpu.icache.ReadReq_miss_latency::cpu.inst 23243215000 # number of ReadReq miss cycles 696system.cpu.icache.ReadReq_miss_latency::total 23243215000 # number of ReadReq miss cycles 697system.cpu.icache.demand_miss_latency::cpu.inst 23243215000 # number of demand (read+write) miss cycles 698system.cpu.icache.demand_miss_latency::total 23243215000 # number of demand (read+write) miss cycles 699system.cpu.icache.overall_miss_latency::cpu.inst 23243215000 # number of overall miss cycles 700system.cpu.icache.overall_miss_latency::total 23243215000 # number of overall miss cycles 701system.cpu.icache.ReadReq_accesses::cpu.inst 115605897 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.ReadReq_accesses::total 115605897 # number of ReadReq accesses(hits+misses) 703system.cpu.icache.demand_accesses::cpu.inst 115605897 # number of demand (read+write) accesses 704system.cpu.icache.demand_accesses::total 115605897 # number of demand (read+write) accesses 705system.cpu.icache.overall_accesses::cpu.inst 115605897 # number of overall (read+write) accesses 706system.cpu.icache.overall_accesses::total 115605897 # number of overall (read+write) accesses | 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 23242723500 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 23242723500 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 23242723500 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 23242723500 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 23242723500 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 23242723500 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 115605918 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 115605918 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 115605918 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 115605918 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 115605918 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 115605918 # number of overall (read+write) accesses |
| 707system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014708 # miss rate for ReadReq accesses 708system.cpu.icache.ReadReq_miss_rate::total 0.014708 # miss rate for ReadReq accesses 709system.cpu.icache.demand_miss_rate::cpu.inst 0.014708 # miss rate for demand accesses 710system.cpu.icache.demand_miss_rate::total 0.014708 # miss rate for demand accesses 711system.cpu.icache.overall_miss_rate::cpu.inst 0.014708 # miss rate for overall accesses 712system.cpu.icache.overall_miss_rate::total 0.014708 # miss rate for overall accesses | 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014708 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.014708 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.014708 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.014708 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.014708 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.014708 # miss rate for overall accesses |
| 713system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.777620 # average ReadReq miss latency 714system.cpu.icache.ReadReq_avg_miss_latency::total 13669.777620 # average ReadReq miss latency 715system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency 716system.cpu.icache.demand_avg_miss_latency::total 13669.777620 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency 718system.cpu.icache.overall_avg_miss_latency::total 13669.777620 # average overall miss latency | 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.488560 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 13669.488560 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 13669.488560 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 13669.488560 # average overall miss latency |
| 719system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.icache.fast_writes 0 # number of fast writes performed 726system.cpu.icache.cache_copies 0 # number of cache copies performed 727system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses 728system.cpu.icache.ReadReq_mshr_misses::total 1700336 # number of ReadReq MSHR misses 729system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 # number of demand (read+write) MSHR misses 730system.cpu.icache.demand_mshr_misses::total 1700336 # number of demand (read+write) MSHR misses 731system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses 732system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses | 718system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed 726system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses 727system.cpu.icache.ReadReq_mshr_misses::total 1700336 # number of ReadReq MSHR misses 728system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 # number of demand (read+write) MSHR misses 729system.cpu.icache.demand_mshr_misses::total 1700336 # number of demand (read+write) MSHR misses 730system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses 731system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses |
| 733system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835992000 # number of ReadReq MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_latency::total 19835992000 # number of ReadReq MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles 738system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles | 732system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835501500 # number of ReadReq MSHR miss cycles 733system.cpu.icache.ReadReq_mshr_miss_latency::total 19835501500 # number of ReadReq MSHR miss cycles 734system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835501500 # number of demand (read+write) MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::total 19835501500 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835501500 # number of overall MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::total 19835501500 # number of overall MSHR miss cycles |
| 739system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles 740system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles 741system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles 742system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles 743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses 745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses 746system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses 747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses 748system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses | 738system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles 739system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles 740system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles 741system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses |
| 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency | 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.636380 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.636380 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency |
| 755system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 756system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 757system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 758system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 759system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 760system.cpu.l2cache.tags.replacements 88869 # number of replacements | 754system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 755system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 756system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 757system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 758system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 759system.cpu.l2cache.tags.replacements 88869 # number of replacements |
| 761system.cpu.l2cache.tags.tagsinuse 64932.369340 # Cycle average of tags in use 762system.cpu.l2cache.tags.total_refs 2760846 # Total number of references to valid blocks. | 760system.cpu.l2cache.tags.tagsinuse 64932.369335 # Cycle average of tags in use 761system.cpu.l2cache.tags.total_refs 2760844 # Total number of references to valid blocks. |
| 763system.cpu.l2cache.tags.sampled_refs 154135 # Sample count of references to valid blocks. | 762system.cpu.l2cache.tags.sampled_refs 154135 # Sample count of references to valid blocks. |
| 764system.cpu.l2cache.tags.avg_refs 17.911869 # Average number of references to valid blocks. | 763system.cpu.l2cache.tags.avg_refs 17.911856 # Average number of references to valid blocks. |
| 765system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 764system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 766system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822165 # Average occupied blocks per requestor | 765system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822123 # Average occupied blocks per requestor |
| 767system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809354 # Average occupied blocks per requestor 768system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012212 # Average occupied blocks per requestor | 766system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809354 # Average occupied blocks per requestor 767system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012212 # Average occupied blocks per requestor |
| 769system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724019 # Average occupied blocks per requestor 770system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001590 # Average occupied blocks per requestor | 768system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724050 # Average occupied blocks per requestor 769system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001596 # Average occupied blocks per requestor |
| 771system.cpu.l2cache.tags.occ_percent::writebacks 0.773221 # Average percentage of cache occupancy 772system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 773system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146190 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::cpu.data 0.071320 # Average percentage of cache occupancy 776system.cpu.l2cache.tags.occ_percent::total 0.990789 # Average percentage of cache occupancy 777system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 778system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id 779system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 780system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id 785system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 786system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995804 # Percentage of cache occupancy per task id | 770system.cpu.l2cache.tags.occ_percent::writebacks 0.773221 # Average percentage of cache occupancy 771system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 772system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 773system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146190 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_percent::cpu.data 0.071320 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::total 0.990789 # Average percentage of cache occupancy 776system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 777system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id 778system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 779system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 780system.cpu.l2cache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id 784system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 785system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995804 # Percentage of cache occupancy per task id |
| 787system.cpu.l2cache.tags.tag_accesses 26241966 # Number of tag accesses 788system.cpu.l2cache.tags.data_accesses 26241966 # Number of data accesses | 786system.cpu.l2cache.tags.tag_accesses 26241950 # Number of tag accesses 787system.cpu.l2cache.tags.data_accesses 26241950 # Number of data accesses |
| 789system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7097 # number of ReadReq hits 790system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3700 # number of ReadReq hits 791system.cpu.l2cache.ReadReq_hits::cpu.inst 1682273 # number of ReadReq hits | 788system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7097 # number of ReadReq hits 789system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3700 # number of ReadReq hits 790system.cpu.l2cache.ReadReq_hits::cpu.inst 1682273 # number of ReadReq hits |
| 792system.cpu.l2cache.ReadReq_hits::cpu.data 514822 # number of ReadReq hits 793system.cpu.l2cache.ReadReq_hits::total 2207892 # number of ReadReq hits 794system.cpu.l2cache.Writeback_hits::writebacks 686231 # number of Writeback hits 795system.cpu.l2cache.Writeback_hits::total 686231 # number of Writeback hits | 791system.cpu.l2cache.ReadReq_hits::cpu.data 514821 # number of ReadReq hits 792system.cpu.l2cache.ReadReq_hits::total 2207891 # number of ReadReq hits 793system.cpu.l2cache.Writeback_hits::writebacks 686230 # number of Writeback hits 794system.cpu.l2cache.Writeback_hits::total 686230 # number of Writeback hits |
| 796system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 797system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 798system.cpu.l2cache.ReadExReq_hits::cpu.data 166049 # number of ReadExReq hits 799system.cpu.l2cache.ReadExReq_hits::total 166049 # number of ReadExReq hits 800system.cpu.l2cache.demand_hits::cpu.dtb.walker 7097 # number of demand (read+write) hits 801system.cpu.l2cache.demand_hits::cpu.itb.walker 3700 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.inst 1682273 # number of demand (read+write) hits | 795system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 796system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 797system.cpu.l2cache.ReadExReq_hits::cpu.data 166049 # number of ReadExReq hits 798system.cpu.l2cache.ReadExReq_hits::total 166049 # number of ReadExReq hits 799system.cpu.l2cache.demand_hits::cpu.dtb.walker 7097 # number of demand (read+write) hits 800system.cpu.l2cache.demand_hits::cpu.itb.walker 3700 # number of demand (read+write) hits 801system.cpu.l2cache.demand_hits::cpu.inst 1682273 # number of demand (read+write) hits |
| 803system.cpu.l2cache.demand_hits::cpu.data 680871 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::total 2373941 # number of demand (read+write) hits | 802system.cpu.l2cache.demand_hits::cpu.data 680870 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 2373940 # number of demand (read+write) hits |
| 805system.cpu.l2cache.overall_hits::cpu.dtb.walker 7097 # number of overall hits 806system.cpu.l2cache.overall_hits::cpu.itb.walker 3700 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.inst 1682273 # number of overall hits | 804system.cpu.l2cache.overall_hits::cpu.dtb.walker 7097 # number of overall hits 805system.cpu.l2cache.overall_hits::cpu.itb.walker 3700 # number of overall hits 806system.cpu.l2cache.overall_hits::cpu.inst 1682273 # number of overall hits |
| 808system.cpu.l2cache.overall_hits::cpu.data 680871 # number of overall hits 809system.cpu.l2cache.overall_hits::total 2373941 # number of overall hits | 807system.cpu.l2cache.overall_hits::cpu.data 680870 # number of overall hits 808system.cpu.l2cache.overall_hits::total 2373940 # number of overall hits |
| 810system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::cpu.inst 18039 # number of ReadReq misses 813system.cpu.l2cache.ReadReq_misses::cpu.data 12191 # number of ReadReq misses 814system.cpu.l2cache.ReadReq_misses::total 30239 # number of ReadReq misses 815system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses 816system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses 817system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses --- 7 unchanged lines hidden (view full) --- 825system.cpu.l2cache.demand_misses::total 160474 # number of demand (read+write) misses 826system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 827system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 828system.cpu.l2cache.overall_misses::cpu.inst 18039 # number of overall misses 829system.cpu.l2cache.overall_misses::cpu.data 142426 # number of overall misses 830system.cpu.l2cache.overall_misses::total 160474 # number of overall misses 831system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 567750 # number of ReadReq miss cycles 832system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles | 809system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 810system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.inst 18039 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::cpu.data 12191 # number of ReadReq misses 813system.cpu.l2cache.ReadReq_misses::total 30239 # number of ReadReq misses 814system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses 815system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses 816system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses --- 7 unchanged lines hidden (view full) --- 824system.cpu.l2cache.demand_misses::total 160474 # number of demand (read+write) misses 825system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 826system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 827system.cpu.l2cache.overall_misses::cpu.inst 18039 # number of overall misses 828system.cpu.l2cache.overall_misses::cpu.data 142426 # number of overall misses 829system.cpu.l2cache.overall_misses::total 160474 # number of overall misses 830system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 567750 # number of ReadReq miss cycles 831system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles |
| 833system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312883000 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918689000 # number of ReadReq miss cycles 835system.cpu.l2cache.ReadReq_miss_latency::total 2232289250 # number of ReadReq miss cycles | 832system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312392500 # number of ReadReq miss cycles 833system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918323250 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::total 2231433000 # number of ReadReq miss cycles |
| 836system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 # number of UpgradeReq miss cycles 837system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles 838system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles 839system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles | 835system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 # number of UpgradeReq miss cycles 836system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles 837system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles 838system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles |
| 840system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles 841system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles | 839system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982643216 # number of ReadExReq miss cycles 840system.cpu.l2cache.ReadExReq_miss_latency::total 8982643216 # number of ReadExReq miss cycles |
| 842system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles | 841system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles 842system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles |
| 844system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles 846system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles | 843system.cpu.l2cache.demand_miss_latency::cpu.inst 1312392500 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.data 9900966466 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::total 11214076216 # number of demand (read+write) miss cycles |
| 847system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles | 846system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles 847system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles |
| 849system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles | 848system.cpu.l2cache.overall_miss_latency::cpu.inst 1312392500 # number of overall miss cycles 849system.cpu.l2cache.overall_miss_latency::cpu.data 9900966466 # number of overall miss cycles 850system.cpu.l2cache.overall_miss_latency::total 11214076216 # number of overall miss cycles |
| 852system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) 854system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) | 851system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) 852system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) |
| 855system.cpu.l2cache.ReadReq_accesses::cpu.data 527013 # number of ReadReq accesses(hits+misses) 856system.cpu.l2cache.ReadReq_accesses::total 2238131 # number of ReadReq accesses(hits+misses) 857system.cpu.l2cache.Writeback_accesses::writebacks 686231 # number of Writeback accesses(hits+misses) 858system.cpu.l2cache.Writeback_accesses::total 686231 # number of Writeback accesses(hits+misses) | 854system.cpu.l2cache.ReadReq_accesses::cpu.data 527012 # number of ReadReq accesses(hits+misses) 855system.cpu.l2cache.ReadReq_accesses::total 2238130 # number of ReadReq accesses(hits+misses) 856system.cpu.l2cache.Writeback_accesses::writebacks 686230 # number of Writeback accesses(hits+misses) 857system.cpu.l2cache.Writeback_accesses::total 686230 # number of Writeback accesses(hits+misses) |
| 859system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2742 # number of UpgradeReq accesses(hits+misses) 860system.cpu.l2cache.UpgradeReq_accesses::total 2742 # number of UpgradeReq accesses(hits+misses) 861system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 862system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 863system.cpu.l2cache.ReadExReq_accesses::cpu.data 296284 # number of ReadExReq accesses(hits+misses) 864system.cpu.l2cache.ReadExReq_accesses::total 296284 # number of ReadExReq accesses(hits+misses) 865system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7104 # number of demand (read+write) accesses 866system.cpu.l2cache.demand_accesses::cpu.itb.walker 3702 # number of demand (read+write) accesses 867system.cpu.l2cache.demand_accesses::cpu.inst 1700312 # number of demand (read+write) accesses | 858system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2742 # number of UpgradeReq accesses(hits+misses) 859system.cpu.l2cache.UpgradeReq_accesses::total 2742 # number of UpgradeReq accesses(hits+misses) 860system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 861system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 862system.cpu.l2cache.ReadExReq_accesses::cpu.data 296284 # number of ReadExReq accesses(hits+misses) 863system.cpu.l2cache.ReadExReq_accesses::total 296284 # number of ReadExReq accesses(hits+misses) 864system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7104 # number of demand (read+write) accesses 865system.cpu.l2cache.demand_accesses::cpu.itb.walker 3702 # number of demand (read+write) accesses 866system.cpu.l2cache.demand_accesses::cpu.inst 1700312 # number of demand (read+write) accesses |
| 868system.cpu.l2cache.demand_accesses::cpu.data 823297 # number of demand (read+write) accesses 869system.cpu.l2cache.demand_accesses::total 2534415 # number of demand (read+write) accesses | 867system.cpu.l2cache.demand_accesses::cpu.data 823296 # number of demand (read+write) accesses 868system.cpu.l2cache.demand_accesses::total 2534414 # number of demand (read+write) accesses |
| 870system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7104 # number of overall (read+write) accesses 871system.cpu.l2cache.overall_accesses::cpu.itb.walker 3702 # number of overall (read+write) accesses 872system.cpu.l2cache.overall_accesses::cpu.inst 1700312 # number of overall (read+write) accesses | 869system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7104 # number of overall (read+write) accesses 870system.cpu.l2cache.overall_accesses::cpu.itb.walker 3702 # number of overall (read+write) accesses 871system.cpu.l2cache.overall_accesses::cpu.inst 1700312 # number of overall (read+write) accesses |
| 873system.cpu.l2cache.overall_accesses::cpu.data 823297 # number of overall (read+write) accesses 874system.cpu.l2cache.overall_accesses::total 2534415 # number of overall (read+write) accesses | 872system.cpu.l2cache.overall_accesses::cpu.data 823296 # number of overall (read+write) accesses 873system.cpu.l2cache.overall_accesses::total 2534414 # number of overall (read+write) accesses |
| 875system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000985 # miss rate for ReadReq accesses 876system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000540 # miss rate for ReadReq accesses 877system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010609 # miss rate for ReadReq accesses 878system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023132 # miss rate for ReadReq accesses 879system.cpu.l2cache.ReadReq_miss_rate::total 0.013511 # miss rate for ReadReq accesses 880system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991612 # miss rate for UpgradeReq accesses 881system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991612 # miss rate for UpgradeReq accesses 882system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses --- 7 unchanged lines hidden (view full) --- 890system.cpu.l2cache.demand_miss_rate::total 0.063318 # miss rate for demand accesses 891system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000985 # miss rate for overall accesses 892system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000540 # miss rate for overall accesses 893system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010609 # miss rate for overall accesses 894system.cpu.l2cache.overall_miss_rate::cpu.data 0.172995 # miss rate for overall accesses 895system.cpu.l2cache.overall_miss_rate::total 0.063318 # miss rate for overall accesses 896system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857 # average ReadReq miss latency 897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency | 874system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000985 # miss rate for ReadReq accesses 875system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000540 # miss rate for ReadReq accesses 876system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010609 # miss rate for ReadReq accesses 877system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023132 # miss rate for ReadReq accesses 878system.cpu.l2cache.ReadReq_miss_rate::total 0.013511 # miss rate for ReadReq accesses 879system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991612 # miss rate for UpgradeReq accesses 880system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991612 # miss rate for UpgradeReq accesses 881system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses --- 7 unchanged lines hidden (view full) --- 889system.cpu.l2cache.demand_miss_rate::total 0.063318 # miss rate for demand accesses 890system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000985 # miss rate for overall accesses 891system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000540 # miss rate for overall accesses 892system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010609 # miss rate for overall accesses 893system.cpu.l2cache.overall_miss_rate::cpu.data 0.172995 # miss rate for overall accesses 894system.cpu.l2cache.overall_miss_rate::total 0.063318 # miss rate for overall accesses 895system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857 # average ReadReq miss latency 896system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency |
| 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143 # average ReadReq miss latency | 897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72753.062808 # average ReadReq miss latency 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75327.967353 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::total 73793.214061 # average ReadReq miss latency |
| 901system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency 903system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency 904system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency | 900system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency 901system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency 902system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency 903system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency |
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| 909system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency 910system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency 911system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency | 908system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency 909system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency 910system.cpu.l2cache.demand_avg_miss_latency::total 69880.954024 # average overall miss latency |
| 912system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 913system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency | 911system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 912system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency |
| 914system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency 916system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency | 913system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency 914system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::total 69880.954024 # average overall miss latency |
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| 950system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087047500 # number of ReadReq MSHR miss cycles 951system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766535000 # number of ReadReq MSHR miss cycles 952system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1854188250 # number of ReadReq MSHR miss cycles | 949system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1086559000 # number of ReadReq MSHR miss cycles 950system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766168250 # number of ReadReq MSHR miss cycles 951system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1853333000 # number of ReadReq MSHR miss cycles |
| 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles 955system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 956system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles | 952system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 955system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles |
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| 959system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles | 958system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles 959system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles |
| 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles 962system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles | 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1086559000 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119076034 # number of demand (read+write) MSHR miss cycles 962system.cpu.l2cache.demand_mshr_miss_latency::total 9206240784 # number of demand (read+write) MSHR miss cycles |
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| 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles 967system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles 968system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles | 965system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1086559000 # number of overall MSHR miss cycles 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119076034 # number of overall MSHR miss cycles 967system.cpu.l2cache.overall_mshr_miss_latency::total 9206240784 # number of overall MSHR miss cycles |
| 969system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles 970system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles 971system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles 972system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles 973system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles 974system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles 975system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles 976system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles --- 15 unchanged lines hidden (view full) --- 992system.cpu.l2cache.demand_mshr_miss_rate::total 0.063318 # mshr miss rate for demand accesses 993system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for overall accesses 994system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for overall accesses 995system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for overall accesses 996system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for overall accesses 997system.cpu.l2cache.overall_mshr_miss_rate::total 0.063318 # mshr miss rate for overall accesses 998system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average ReadReq mshr miss latency 999system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency | 968system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles 969system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles 970system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles 971system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles 972system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles 973system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles 974system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles 975system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles --- 15 unchanged lines hidden (view full) --- 991system.cpu.l2cache.demand_mshr_miss_rate::total 0.063318 # mshr miss rate for demand accesses 992system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for overall accesses 993system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for overall accesses 994system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for overall accesses 995system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for overall accesses 996system.cpu.l2cache.overall_mshr_miss_rate::total 0.063318 # mshr miss rate for overall accesses 997system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average ReadReq mshr miss latency 998system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency |
| 1000system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359 # average ReadReq mshr miss latency 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467 # average ReadReq mshr miss latency 1002system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712 # average ReadReq mshr miss latency | 999system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60233.882144 # average ReadReq mshr miss latency 1000system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62847.038799 # average ReadReq mshr miss latency 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61289.493700 # average ReadReq mshr miss latency |
| 1003system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency 1004system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency 1005system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1006system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 1002system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency 1003system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency 1004system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1005system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 1007system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency 1008system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency | 1006system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56458.769025 # average ReadExReq mshr miss latency 1007system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56458.769025 # average ReadExReq mshr miss latency |
| 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 1008system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency 1013system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency | 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency |
| 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 1013system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency 1017system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency 1018system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency | 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency 1017system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency |
| 1019system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1020system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1021system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1022system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1023system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1024system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1025system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1026system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1027system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1018system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1019system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1020system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1021system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1022system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1023system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1024system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1025system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1026system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1028system.cpu.dcache.tags.replacements 822747 # number of replacements 1029system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use 1030system.cpu.dcache.tags.total_refs 43252597 # Total number of references to valid blocks. 1031system.cpu.dcache.tags.sampled_refs 823259 # Sample count of references to valid blocks. 1032system.cpu.dcache.tags.avg_refs 52.538262 # Average number of references to valid blocks. 1033system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. 1034system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor 1035system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy 1036system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy 1037system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1038system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1039system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 1040system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 1041system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1042system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1043system.cpu.dcache.tags.tag_accesses 177194873 # Number of tag accesses 1044system.cpu.dcache.tags.data_accesses 177194873 # Number of data accesses 1045system.cpu.dcache.ReadReq_hits::cpu.data 23122385 # number of ReadReq hits 1046system.cpu.dcache.ReadReq_hits::total 23122385 # number of ReadReq hits 1047system.cpu.dcache.WriteReq_hits::cpu.data 18831357 # number of WriteReq hits 1048system.cpu.dcache.WriteReq_hits::total 18831357 # number of WriteReq hits 1049system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits 1050system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits 1051system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits 1052system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits 1053system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits 1054system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits 1055system.cpu.dcache.demand_hits::cpu.data 41953742 # number of demand (read+write) hits 1056system.cpu.dcache.demand_hits::total 41953742 # number of demand (read+write) hits 1057system.cpu.dcache.overall_hits::cpu.data 42345863 # number of overall hits 1058system.cpu.dcache.overall_hits::total 42345863 # number of overall hits 1059system.cpu.dcache.ReadReq_misses::cpu.data 402167 # number of ReadReq misses 1060system.cpu.dcache.ReadReq_misses::total 402167 # number of ReadReq misses 1061system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses 1062system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses 1063system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses 1064system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses 1065system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses 1066system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses 1067system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1068system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 1069system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses 1070system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses 1071system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses 1072system.cpu.dcache.overall_misses::total 820348 # number of overall misses 1073system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles 1074system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles 1075system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles 1076system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles 1077system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles 1078system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles 1079system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles 1080system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles 1081system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles 1082system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles 1083system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles 1084system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles 1085system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) 1086system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) 1087system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) 1088system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses) 1089system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) 1090system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) 1091system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) 1092system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) 1093system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses) 1094system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses) 1095system.cpu.dcache.demand_accesses::cpu.data 42654935 # number of demand (read+write) accesses 1096system.cpu.dcache.demand_accesses::total 42654935 # number of demand (read+write) accesses 1097system.cpu.dcache.overall_accesses::cpu.data 43166211 # number of overall (read+write) accesses 1098system.cpu.dcache.overall_accesses::total 43166211 # number of overall (read+write) accesses 1099system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses 1100system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses 1101system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses 1102system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses 1103system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses 1104system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses 1105system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses 1106system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses 1107system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 1108system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 1109system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses 1110system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses 1111system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses 1112system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses 1113system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency 1114system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency 1115system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency 1116system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency 1117system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency 1118system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency 1119system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency 1120system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency 1121system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency 1122system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency 1123system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency 1124system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency 1125system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 1126system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1127system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 1128system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1129system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked 1130system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1131system.cpu.dcache.fast_writes 0 # number of fast writes performed 1132system.cpu.dcache.cache_copies 0 # number of cache copies performed 1133system.cpu.dcache.writebacks::writebacks 686231 # number of writebacks 1134system.cpu.dcache.writebacks::total 686231 # number of writebacks 1135system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits 1136system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits 1137system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits 1138system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits 1139system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits 1140system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits 1141system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits 1142system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits 1143system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401540 # number of ReadReq MSHR misses 1144system.cpu.dcache.ReadReq_mshr_misses::total 401540 # number of ReadReq MSHR misses 1145system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses 1146system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses 1147system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses 1148system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses 1149system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses 1150system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses 1151system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1152system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 1153system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses 1154system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses 1155system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses 1156system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses 1157system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles 1158system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles 1159system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles 1160system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles 1161system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles 1162system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles 1163system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles 1164system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles 1165system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles 1166system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles 1167system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles 1168system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles 1169system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles 1170system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles 1171system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles 1172system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles 1173system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles 1174system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles 1175system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles 1176system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles 1177system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses 1178system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses 1179system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses 1180system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses 1181system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses 1182system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses 1183system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses 1184system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses 1185system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 1186system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 1187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses 1188system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses 1189system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses 1190system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses 1191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency 1192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency 1193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency 1194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency 1195system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency 1196system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency 1197system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency 1198system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency 1199system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency 1200system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency 1201system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency 1202system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency 1203system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency 1204system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency 1205system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1206system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1207system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1208system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1209system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1210system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1211system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1212system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution | 1027system.cpu.toL2Bus.trans_dist::ReadReq 2294825 # Transaction distribution 1028system.cpu.toL2Bus.trans_dist::ReadResp 2294810 # Transaction distribution |
| 1214system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution | 1029system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1030system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution |
| 1216system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution | 1031system.cpu.toL2Bus.trans_dist::Writeback 686230 # Transaction distribution |
| 1217system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution 1221system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution 1222system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution 1223system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) | 1032system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1033system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution 1034system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1035system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution 1036system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution 1037system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution 1038system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) |
| 1224system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) | 1039system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456073 # Packet count per connected master and slave (bytes) |
| 1225system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) 1226system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) | 1040system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) 1041system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) |
| 1227system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes) | 1042system.cpu.toL2Bus.pkt_count::total 5912638 # Packet count per connected master and slave (bytes) |
| 1228system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) | 1043system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) |
| 1229system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) | 1044system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96806921 # Cumulative packet size per connected master and slave (bytes) |
| 1230system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) | 1045system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) 1046system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) |
| 1232system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes) | 1047system.cpu.toL2Bus.pkt_size::total 205706201 # Cumulative packet size per connected master and slave (bytes) |
| 1233system.cpu.toL2Bus.snoops 52963 # Total snoops (count) | 1048system.cpu.toL2Bus.snoops 52963 # Total snoops (count) |
| 1234system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram | 1049system.cpu.toL2Bus.snoop_fanout::samples 3276132 # Request fanout histogram |
| 1235system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram 1236system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram 1237system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1238system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1239system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1240system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1241system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1242system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1050system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram 1052system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1054system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1056system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1057system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1243system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram | 1058system.cpu.toL2Bus.snoop_fanout::5 3239673 98.89% 98.89% # Request fanout histogram |
| 1244system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram 1245system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1246system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1247system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1059system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram 1060system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1061system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1062system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1248system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram 1249system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks) | 1063system.cpu.toL2Bus.snoop_fanout::total 3276132 # Request fanout histogram 1064system.cpu.toL2Bus.reqLayer0.occupancy 2353772500 # Layer occupancy (ticks) |
| 1250system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1251system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1252system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1065system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1066system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1067system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1253system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks) | 1068system.cpu.toL2Bus.respLayer0.occupancy 2564911000 # Layer occupancy (ticks) |
| 1254system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1069system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1255system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks) | 1070system.cpu.toL2Bus.respLayer1.occupancy 1311851755 # Layer occupancy (ticks) |
| 1256system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1257system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1258system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1259system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) 1260system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1071system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1072system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1073system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1074system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) 1075system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1076system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 1077system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 1078system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 1079system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 1080system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1085system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1086system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1087system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1088system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1093system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1094system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1096system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1098system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1100system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1104system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 1105system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 1131system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1132system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1133system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1134system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1135system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1136system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1137system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1138system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1139system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1140system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1141system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1142system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1143system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1144system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1145system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1146system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1147system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1148system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1149system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1150system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1151system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1152system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1153system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1154system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1155system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1156system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1157system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1158system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1159system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1160system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1161system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1162system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1163system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1164system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1165system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1166system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1167system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1168system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1169system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1170system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) 1171system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1172system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1173system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1174system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1175system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1176system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) 1177system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
|
| 1261system.iocache.tags.replacements 36424 # number of replacements 1262system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use 1263system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1264system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1265system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1266system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit. 1267system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor 1268system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy --- 69 unchanged lines hidden (view full) --- 1338system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency 1339system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1340system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1341system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1342system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency 1343system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1344system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency 1345system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1178system.iocache.tags.replacements 36424 # number of replacements 1179system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use 1180system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1181system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1182system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1183system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit. 1184system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor 1185system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy --- 69 unchanged lines hidden (view full) --- 1255system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency 1256system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1257system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1258system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1259system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency 1260system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1261system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency 1262system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1263system.membus.trans_dist::ReadReq 70649 # Transaction distribution 1264system.membus.trans_dist::ReadResp 70649 # Transaction distribution 1265system.membus.trans_dist::WriteReq 27618 # Transaction distribution 1266system.membus.trans_dist::WriteResp 27618 # Transaction distribution 1267system.membus.trans_dist::Writeback 82180 # Transaction distribution 1268system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1269system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1270system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution 1271system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1272system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution 1273system.membus.trans_dist::ReadExReq 128451 # Transaction distribution 1274system.membus.trans_dist::ReadExResp 128451 # Transaction distribution 1275system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1276system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1277system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 1278system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) 1279system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) 1280system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 1281system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) 1282system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) 1283system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1284system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1285system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 1286system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) 1287system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) 1288system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 1289system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 1290system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) 1291system.membus.snoops 219 # Total snoops (count) 1292system.membus.snoop_fanout::samples 281834 # Request fanout histogram 1293system.membus.snoop_fanout::mean 1 # Request fanout histogram 1294system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1295system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1296system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1297system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram 1298system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1299system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1300system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1301system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1302system.membus.snoop_fanout::total 281834 # Request fanout histogram 1303system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) 1304system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1305system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 1306system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1307system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) 1308system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1309system.membus.reqLayer5.occupancy 1264017500 # Layer occupancy (ticks) 1310system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1311system.membus.respLayer2.occupancy 1594856995 # Layer occupancy (ticks) 1312system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1313system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) 1314system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1315system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1316system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1317system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1318system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1319system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1320system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1321system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1322system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1323system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1324system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1325system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1326system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1327system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1328system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1329system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1330system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1331system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1332system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1333system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1334system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1335system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1336system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1337system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1338system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1339system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1340system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1341system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1342system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1343system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1344system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1345system.realview.ethernet.droppedPackets 0 # number of packets dropped |
|
| 1346 1347---------- End Simulation Statistics ---------- | 1346 1347---------- End Simulation Statistics ---------- |