| stats.txt (10513:ca4438b6e39a) | stats.txt (10517:ba51f8572571) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.902619 # Number of seconds simulated 4sim_ticks 2902619131000 # Number of ticks simulated 5final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.902619 # Number of seconds simulated 4sim_ticks 2902619131000 # Number of ticks simulated 5final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 744858 # Simulator instruction rate (inst/s) 8host_op_rate 898074 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19216925045 # Simulator tick rate (ticks/s) 10host_mem_usage 553548 # Number of bytes of host memory used 11host_seconds 151.05 # Real time elapsed on the host 12sim_insts 112506996 # Number of instructions simulated 13sim_ops 135649573 # Number of ops (including micro ops) simulated | 7host_inst_rate 756630 # Simulator instruction rate (inst/s) 8host_op_rate 912268 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19520630002 # Simulator tick rate (ticks/s) 10host_mem_usage 553652 # Number of bytes of host memory used 11host_seconds 148.70 # Real time elapsed on the host 12sim_insts 112506995 # Number of instructions simulated 13sim_ops 135649572 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory --- 73 unchanged lines hidden (view full) --- 95system.physmem.perBankWrBursts::10 7503 # Per bank write bursts 96system.physmem.perBankWrBursts::11 6751 # Per bank write bursts 97system.physmem.perBankWrBursts::12 7436 # Per bank write bursts 98system.physmem.perBankWrBursts::13 7741 # Per bank write bursts 99system.physmem.perBankWrBursts::14 7284 # Per bank write bursts 100system.physmem.perBankWrBursts::15 7101 # Per bank write bursts 101system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 102system.physmem.numWrRetry 1 # Number of times write queue was full causing retry | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory --- 73 unchanged lines hidden (view full) --- 95system.physmem.perBankWrBursts::10 7503 # Per bank write bursts 96system.physmem.perBankWrBursts::11 6751 # Per bank write bursts 97system.physmem.perBankWrBursts::12 7436 # Per bank write bursts 98system.physmem.perBankWrBursts::13 7741 # Per bank write bursts 99system.physmem.perBankWrBursts::14 7284 # Per bank write bursts 100system.physmem.perBankWrBursts::15 7101 # Per bank write bursts 101system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 102system.physmem.numWrRetry 1 # Number of times write queue was full causing retry |
| 103system.physmem.totGap 2902618699500 # Total gap between requests | 103system.physmem.totGap 2902618754500 # Total gap between requests |
| 104system.physmem.readPktSize::0 0 # Read request sizes (log2) 105system.physmem.readPktSize::1 0 # Read request sizes (log2) 106system.physmem.readPktSize::2 9558 # Read request sizes (log2) 107system.physmem.readPktSize::3 14 # Read request sizes (log2) 108system.physmem.readPktSize::4 0 # Read request sizes (log2) 109system.physmem.readPktSize::5 0 # Read request sizes (log2) 110system.physmem.readPktSize::6 158705 # Read request sizes (log2) 111system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 206system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see | 104system.physmem.readPktSize::0 0 # Read request sizes (log2) 105system.physmem.readPktSize::1 0 # Read request sizes (log2) 106system.physmem.readPktSize::2 9558 # Read request sizes (log2) 107system.physmem.readPktSize::3 14 # Read request sizes (log2) 108system.physmem.readPktSize::4 0 # Read request sizes (log2) 109system.physmem.readPktSize::5 0 # Read request sizes (log2) 110system.physmem.readPktSize::6 158705 # Read request sizes (log2) 111system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 206system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see |
| 214system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation 218system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation | 214system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation 218system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation |
| 221system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation | 221system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation |
| 222system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation | 222system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation |
| 223system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation | 223system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation |
| 224system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation | 224system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation |
| 228system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads --- 27 unchanged lines hidden (view full) --- 263system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads | 228system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads --- 27 unchanged lines hidden (view full) --- 263system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads |
| 271system.physmem.totQLat 1491787750 # Total ticks spent queuing 272system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM | 271system.physmem.totQLat 1492072500 # Total ticks spent queuing 272system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM |
| 273system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers | 273system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers |
| 274system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst | 274system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst |
| 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 276system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst | 276system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst |
| 277system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.05 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing | 277system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.05 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing |
| 287system.physmem.readRowHits 138438 # Number of row buffer hits during reads | 287system.physmem.readRowHits 138435 # Number of row buffer hits during reads |
| 288system.physmem.writeRowHits 90000 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes | 288system.physmem.writeRowHits 90000 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes |
| 291system.physmem.avgGap 9972509.98 # Average gap between requests | 291system.physmem.avgGap 9972510.17 # Average gap between requests |
| 292system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined | 292system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined |
| 293system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states | 293system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states |
| 294system.physmem.memoryStateTime::REF 96924620000 # Time in different power states 295system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 294system.physmem.memoryStateTime::REF 96924620000 # Time in different power states 295system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 296system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states | 296system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states |
| 297system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 297system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 298system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ) 299system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ) 300system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ) 301system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ) | 298system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ) 299system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ) 300system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ) 301system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ) |
| 302system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) 303system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) 304system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) 305system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) 306system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) 307system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) | 302system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) 303system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) 304system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) 305system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) 306system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) 307system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) |
| 308system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ) 309system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ) 310system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ) 311system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ) 312system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ) 313system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ) 314system.physmem.averagePower::0 669.480430 # Core power per rank (mW) 315system.physmem.averagePower::1 669.392372 # Core power per rank (mW) 316system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 328system.membus.trans_dist::ReadReq 70650 # Transaction distribution 329system.membus.trans_dist::ReadResp 70650 # Transaction distribution | 308system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ) 309system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ) 310system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ) 311system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ) 312system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ) 313system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ) 314system.physmem.averagePower::0 669.480439 # Core power per rank (mW) 315system.physmem.averagePower::1 669.392466 # Core power per rank (mW) 316system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 328system.membus.trans_dist::ReadReq 70649 # Transaction distribution 329system.membus.trans_dist::ReadResp 70649 # Transaction distribution |
| 330system.membus.trans_dist::WriteReq 27618 # Transaction distribution 331system.membus.trans_dist::WriteResp 27618 # Transaction distribution 332system.membus.trans_dist::Writeback 82180 # Transaction distribution 333system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 334system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 335system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution 336system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 337system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution 338system.membus.trans_dist::ReadExReq 128451 # Transaction distribution 339system.membus.trans_dist::ReadExResp 128451 # Transaction distribution 340system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) | 330system.membus.trans_dist::WriteReq 27618 # Transaction distribution 331system.membus.trans_dist::WriteResp 27618 # Transaction distribution 332system.membus.trans_dist::Writeback 82180 # Transaction distribution 333system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 334system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 335system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution 336system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 337system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution 338system.membus.trans_dist::ReadExReq 128451 # Transaction distribution 339system.membus.trans_dist::ReadExResp 128451 # Transaction distribution 340system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) |
| 341system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) | 341system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) |
| 342system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) | 342system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) |
| 344system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes) | 344system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) |
| 345system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 346system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) | 345system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 346system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) |
| 347system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes) | 347system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) |
| 348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) | 348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) |
| 349system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) | 349system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) |
| 350system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) | 350system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) |
| 352system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes) | 352system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) |
| 353system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 354system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) | 353system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 354system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) |
| 355system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes) | 355system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) |
| 356system.membus.snoops 219 # Total snoops (count) 357system.membus.snoop_fanout::samples 281834 # Request fanout histogram 358system.membus.snoop_fanout::mean 1 # Request fanout histogram 359system.membus.snoop_fanout::stdev 0 # Request fanout histogram 360system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 361system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 362system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram 363system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 365system.membus.snoop_fanout::min_value 1 # Request fanout histogram 366system.membus.snoop_fanout::max_value 1 # Request fanout histogram 367system.membus.snoop_fanout::total 281834 # Request fanout histogram 368system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) 369system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 356system.membus.snoops 219 # Total snoops (count) 357system.membus.snoop_fanout::samples 281834 # Request fanout histogram 358system.membus.snoop_fanout::mean 1 # Request fanout histogram 359system.membus.snoop_fanout::stdev 0 # Request fanout histogram 360system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 361system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 362system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram 363system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 365system.membus.snoop_fanout::min_value 1 # Request fanout histogram 366system.membus.snoop_fanout::max_value 1 # Request fanout histogram 367system.membus.snoop_fanout::total 281834 # Request fanout histogram 368system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) 369system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 370system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) | 370system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) |
| 371system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 372system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) 373system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 374system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) 375system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 371system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 372system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) 373system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 374system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) 375system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 376system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks) | 376system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks) |
| 377system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 378system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) 379system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 380system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 381system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 382system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 383system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 384system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 214 unchanged lines hidden (view full) --- 599system.cpu.itb.write_accesses 0 # DTB write accesses 600system.cpu.itb.inst_accesses 115610659 # ITB inst accesses 601system.cpu.itb.hits 115605897 # DTB hits 602system.cpu.itb.misses 4762 # DTB misses 603system.cpu.itb.accesses 115610659 # DTB accesses 604system.cpu.numCycles 5805238262 # number of cpu cycles simulated 605system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 606system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 377system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 378system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) 379system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 380system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 381system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 382system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 383system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 384system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 214 unchanged lines hidden (view full) --- 599system.cpu.itb.write_accesses 0 # DTB write accesses 600system.cpu.itb.inst_accesses 115610659 # ITB inst accesses 601system.cpu.itb.hits 115605897 # DTB hits 602system.cpu.itb.misses 4762 # DTB misses 603system.cpu.itb.accesses 115610659 # DTB accesses 604system.cpu.numCycles 5805238262 # number of cpu cycles simulated 605system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 606system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 607system.cpu.committedInsts 112506996 # Number of instructions committed 608system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed 609system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses | 607system.cpu.committedInsts 112506995 # Number of instructions committed 608system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed 609system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses |
| 610system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 611system.cpu.num_func_calls 9898964 # number of times a function call or return occured 612system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls | 610system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 611system.cpu.num_func_calls 9898964 # number of times a function call or return occured 612system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls |
| 613system.cpu.num_int_insts 119948924 # number of integer instructions | 613system.cpu.num_int_insts 119948923 # number of integer instructions |
| 614system.cpu.num_fp_insts 11161 # number of float instructions | 614system.cpu.num_fp_insts 11161 # number of float instructions |
| 615system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read 616system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written | 615system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read 616system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written |
| 617system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 618system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written | 617system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 618system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written |
| 619system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read 620system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written | 619system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read 620system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written |
| 621system.cpu.num_mem_refs 45428231 # number of memory refs 622system.cpu.num_load_insts 24855392 # Number of load instructions 623system.cpu.num_store_insts 20572839 # Number of store instructions 624system.cpu.num_idle_cycles 5386456122.024144 # Number of idle cycles 625system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles 626system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles 627system.cpu.idle_fraction 0.927861 # Percentage of idle cycles 628system.cpu.Branches 25929456 # Number of branches fetched 629system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction | 621system.cpu.num_mem_refs 45428231 # number of memory refs 622system.cpu.num_load_insts 24855392 # Number of load instructions 623system.cpu.num_store_insts 20572839 # Number of store instructions 624system.cpu.num_idle_cycles 5386456122.024144 # Number of idle cycles 625system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles 626system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles 627system.cpu.idle_fraction 0.927861 # Percentage of idle cycles 628system.cpu.Branches 25929456 # Number of branches fetched 629system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction |
| 630system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction | 630system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction |
| 631system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction 632system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 633system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 634system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 635system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 636system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 637system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 638system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction --- 16 unchanged lines hidden (view full) --- 655system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction 656system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 657system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 658system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 659system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction 660system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction 661system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 662system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 631system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction 632system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 633system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 634system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 635system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 636system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 637system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 638system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction --- 16 unchanged lines hidden (view full) --- 655system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction 656system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 657system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 658system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 659system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction 660system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction 661system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 662system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 663system.cpu.op_class::total 138771626 # Class of executed instruction | 663system.cpu.op_class::total 138771625 # Class of executed instruction |
| 664system.cpu.kern.inst.arm 0 # number of arm instructions executed 665system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed 666system.cpu.icache.tags.replacements 1699818 # number of replacements 667system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use 668system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. --- 59 unchanged lines hidden (view full) --- 731system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses 732system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses 733system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835992000 # number of ReadReq MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_latency::total 19835992000 # number of ReadReq MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles 738system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles | 664system.cpu.kern.inst.arm 0 # number of arm instructions executed 665system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed 666system.cpu.icache.tags.replacements 1699818 # number of replacements 667system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use 668system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. --- 59 unchanged lines hidden (view full) --- 731system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses 732system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses 733system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835992000 # number of ReadReq MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_latency::total 19835992000 # number of ReadReq MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles 738system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles |
| 739system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles 740system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles 741system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles 742system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles | 739system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles 740system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles 741system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles 742system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles |
| 743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses 745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses 746system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses 747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses 748system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency --- 81 unchanged lines hidden (view full) --- 832system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 833system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312883000 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918689000 # number of ReadReq miss cycles 835system.cpu.l2cache.ReadReq_miss_latency::total 2232289250 # number of ReadReq miss cycles 836system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 # number of UpgradeReq miss cycles 837system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles 838system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles 839system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles | 743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses 745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses 746system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses 747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses 748system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency --- 81 unchanged lines hidden (view full) --- 832system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 833system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312883000 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918689000 # number of ReadReq miss cycles 835system.cpu.l2cache.ReadReq_miss_latency::total 2232289250 # number of ReadReq miss cycles 836system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 # number of UpgradeReq miss cycles 837system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles 838system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles 839system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles |
| 840system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles 841system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles | 840system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles 841system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles |
| 842system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles | 842system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles |
| 845system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles 846system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles | 845system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles 846system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles |
| 847system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 849system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles | 847system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 849system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles |
| 850system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles | 850system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles |
| 852system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) 854system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) 855system.cpu.l2cache.ReadReq_accesses::cpu.data 527013 # number of ReadReq accesses(hits+misses) 856system.cpu.l2cache.ReadReq_accesses::total 2238131 # number of ReadReq accesses(hits+misses) 857system.cpu.l2cache.Writeback_accesses::writebacks 686231 # number of Writeback accesses(hits+misses) 858system.cpu.l2cache.Writeback_accesses::total 686231 # number of Writeback accesses(hits+misses) 859system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2742 # number of UpgradeReq accesses(hits+misses) --- 37 unchanged lines hidden (view full) --- 897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143 # average ReadReq miss latency 901system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency 903system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency 904system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency | 852system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) 854system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) 855system.cpu.l2cache.ReadReq_accesses::cpu.data 527013 # number of ReadReq accesses(hits+misses) 856system.cpu.l2cache.ReadReq_accesses::total 2238131 # number of ReadReq accesses(hits+misses) 857system.cpu.l2cache.Writeback_accesses::writebacks 686231 # number of Writeback accesses(hits+misses) 858system.cpu.l2cache.Writeback_accesses::total 686231 # number of Writeback accesses(hits+misses) 859system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2742 # number of UpgradeReq accesses(hits+misses) --- 37 unchanged lines hidden (view full) --- 897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143 # average ReadReq miss latency 901system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency 903system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency 904system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency |
| 905system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency 906system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency | 905system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency 906system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency |
| 907system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 908system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 909system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency | 907system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 908system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 909system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency |
| 910system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency 911system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency | 910system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency 911system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency |
| 912system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 913system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 914system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency | 912system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 913system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 914system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency |
| 915system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency 916system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency | 915system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency 916system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency |
| 917system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 918system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 919system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 920system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 921system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 922system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 923system.cpu.l2cache.fast_writes 0 # number of fast writes performed 924system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 24 unchanged lines hidden (view full) --- 949system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 950system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087047500 # number of ReadReq MSHR miss cycles 951system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766535000 # number of ReadReq MSHR miss cycles 952system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1854188250 # number of ReadReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles 955system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 956system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles | 917system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 918system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 919system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 920system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 921system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 922system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 923system.cpu.l2cache.fast_writes 0 # number of fast writes performed 924system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 24 unchanged lines hidden (view full) --- 949system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 950system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087047500 # number of ReadReq MSHR miss cycles 951system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766535000 # number of ReadReq MSHR miss cycles 952system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1854188250 # number of ReadReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles 955system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 956system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles |
| 957system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles 958system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles | 957system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles 958system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles |
| 959system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles | 959system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles |
| 962system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles | 962system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles |
| 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles 965system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles | 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles 965system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles |
| 967system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles 968system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles 969system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles 970system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles 971system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles | 967system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles 968system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles 969system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles 970system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles 971system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles |
| 972system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles 973system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles | 972system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles 973system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles |
| 974system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles 975system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles 976system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles | 974system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles 975system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles 976system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles |
| 977system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses 978system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023132 # mshr miss rate for ReadReq accesses 981system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013511 # mshr miss rate for ReadReq accesses 982system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991612 # mshr miss rate for UpgradeReq accesses 983system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991612 # mshr miss rate for UpgradeReq accesses 984system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses --- 14 unchanged lines hidden (view full) --- 999system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 1000system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359 # average ReadReq mshr miss latency 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467 # average ReadReq mshr miss latency 1002system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712 # average ReadReq mshr miss latency 1003system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency 1004system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency 1005system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1006system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 977system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses 978system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023132 # mshr miss rate for ReadReq accesses 981system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013511 # mshr miss rate for ReadReq accesses 982system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991612 # mshr miss rate for UpgradeReq accesses 983system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991612 # mshr miss rate for UpgradeReq accesses 984system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses --- 14 unchanged lines hidden (view full) --- 999system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 1000system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359 # average ReadReq mshr miss latency 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467 # average ReadReq mshr miss latency 1002system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712 # average ReadReq mshr miss latency 1003system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency 1004system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency 1005system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1006system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 1007system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency 1008system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency | 1007system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency 1008system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency |
| 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency | 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency |
| 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency 1013system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency | 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency 1013system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency |
| 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency | 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency |
| 1017system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency 1018system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency | 1017system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency 1018system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency |
| 1019system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1020system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1021system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1022system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1023system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1024system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1025system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1026system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 40 unchanged lines hidden (view full) --- 1067system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1068system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 1069system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses 1070system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses 1071system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses 1072system.cpu.dcache.overall_misses::total 820348 # number of overall misses 1073system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles 1074system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles | 1019system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1020system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1021system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1022system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1023system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1024system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1025system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1026system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency --- 40 unchanged lines hidden (view full) --- 1067system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1068system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 1069system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses 1070system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses 1071system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses 1072system.cpu.dcache.overall_misses::total 820348 # number of overall misses 1073system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles 1074system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles |
| 1075system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles 1076system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles | 1075system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles 1076system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles |
| 1077system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles 1078system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles 1079system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles 1080system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles | 1077system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles 1078system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles 1079system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles 1080system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles |
| 1081system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles 1082system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles 1083system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles 1084system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles | 1081system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles 1082system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles 1083system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles 1084system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles |
| 1085system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) 1086system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) 1087system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) 1088system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses) 1089system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) 1090system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) 1091system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) 1092system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 1107system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 1108system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 1109system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses 1110system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses 1111system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses 1112system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses 1113system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency 1114system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency | 1085system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) 1086system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) 1087system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) 1088system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses) 1089system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) 1090system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) 1091system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) 1092system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 1107system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 1108system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 1109system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses 1110system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses 1111system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses 1112system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses 1113system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency 1114system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency |
| 1115system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency 1116system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency | 1115system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency 1116system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency |
| 1117system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency 1118system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency 1119system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency 1120system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency | 1117system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency 1118system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency 1119system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency 1120system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency |
| 1121system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency 1122system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency 1123system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency 1124system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency | 1121system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency 1122system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency 1123system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency 1124system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency |
| 1125system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 1126system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1127system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 1128system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1129system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked 1130system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1131system.cpu.dcache.fast_writes 0 # number of fast writes performed 1132system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 1151system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1152system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 1153system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses 1154system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses 1155system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses 1156system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses 1157system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles 1158system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles | 1125system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 1126system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1127system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 1128system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1129system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked 1130system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1131system.cpu.dcache.fast_writes 0 # number of fast writes performed 1132system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 1151system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1152system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 1153system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses 1154system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses 1155system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses 1156system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses 1157system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles 1158system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles |
| 1159system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles 1160system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles | 1159system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles 1160system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles |
| 1161system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles 1162system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles 1163system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles 1164system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles 1165system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles 1166system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles | 1161system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles 1162system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles 1163system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles 1164system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles 1165system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles 1166system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles |
| 1167system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles 1168system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles 1169system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles 1170system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles 1171system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles 1172system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles | 1167system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles 1168system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles 1169system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles 1170system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles 1171system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles 1172system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles |
| 1173system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles 1174system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles | 1173system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles 1174system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles |
| 1175system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles 1176system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles | 1175system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles 1176system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles |
| 1177system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses 1178system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses 1179system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses 1180system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses 1181system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses 1182system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses 1183system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses 1184system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses 1185system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 1186system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 1187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses 1188system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses 1189system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses 1190system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses 1191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency 1192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency | 1177system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses 1178system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses 1179system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses 1180system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses 1181system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses 1182system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses 1183system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses 1184system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses 1185system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 1186system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 1187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses 1188system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses 1189system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses 1190system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses 1191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency 1192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency |
| 1193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency 1194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency | 1193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency 1194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency |
| 1195system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency 1196system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency 1197system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency 1198system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency 1199system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency 1200system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency | 1195system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency 1196system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency 1197system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency 1198system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency 1199system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency 1200system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency |
| 1201system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency 1202system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency 1203system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency 1204system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency | 1201system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency 1202system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency 1203system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency 1204system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency |
| 1205system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1206system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1207system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1208system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1209system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1210system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1211system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1205system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1206system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1207system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1208system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1209system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1210system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1211system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1212system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution | 1212system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution |
| 1214system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution 1221system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution 1222system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution | 1214system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution 1221system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution 1222system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution |
| 1223system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes) | 1223system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) |
| 1224system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) 1225system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) 1226system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) | 1224system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) 1225system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) 1226system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) |
| 1227system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes) 1228system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes) | 1227system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes) 1228system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) |
| 1229system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) 1230system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) | 1229system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) 1230system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) |
| 1232system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes) | 1232system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes) |
| 1233system.cpu.toL2Bus.snoops 52963 # Total snoops (count) 1234system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram 1236system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram 1237system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1238system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1239system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1240system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1241system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1242system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1243system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram 1244system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram 1245system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1246system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1247system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1248system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram | 1233system.cpu.toL2Bus.snoops 52963 # Total snoops (count) 1234system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram 1236system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram 1237system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1238system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1239system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1240system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1241system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1242system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1243system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram 1244system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram 1245system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1246system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1247system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1248system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram |
| 1249system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks) | 1249system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks) |
| 1250system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1251system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1252system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1250system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1251system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1252system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1253system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks) | 1253system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks) |
| 1254system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1254system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1255system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks) | 1255system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks) |
| 1256system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1257system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1258system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1259system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) 1260system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1261system.iocache.tags.replacements 36424 # number of replacements 1262system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use 1263system.iocache.tags.total_refs 0 # Total number of references to valid blocks. --- 84 unchanged lines hidden --- | 1256system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1257system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1258system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1259system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) 1260system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1261system.iocache.tags.replacements 36424 # number of replacements 1262system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use 1263system.iocache.tags.total_refs 0 # Total number of references to valid blocks. --- 84 unchanged lines hidden --- |