| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.614572 # Number of seconds simulated 4sim_ticks 2614571564500 # Number of ticks simulated 5final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.902619 # Number of seconds simulated 4sim_ticks 2902619131000 # Number of ticks simulated 5final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 393660 # Simulator instruction rate (inst/s) 8host_op_rate 470163 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17100811132 # Simulator tick rate (ticks/s) 10host_mem_usage 408168 # Number of bytes of host memory used 11host_seconds 152.89 # Real time elapsed on the host 12sim_insts 60187274 # Number of instructions simulated 13sim_ops 71883961 # Number of ops (including micro ops) simulated | 7host_inst_rate 744858 # Simulator instruction rate (inst/s) 8host_op_rate 898074 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19216925045 # Simulator tick rate (ticks/s) 10host_mem_usage 553548 # Number of bytes of host memory used 11host_seconds 151.05 # Real time elapsed on the host 12sim_insts 112506996 # Number of instructions simulated 13sim_ops 135649573 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory | 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 704648 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9109336 # Number of bytes read from this memory 21system.physmem.bytes_read::total 132497824 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 704648 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 704648 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3720832 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6736904 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory 25system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory 28system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 17222 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142359 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15495012 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 58138 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 812156 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 46922943 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 269508 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3484065 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 50676687 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 269508 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 269508 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1423113 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1153563 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2576676 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1423113 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 46922943 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 269508 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4637627 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53253363 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15495012 # Number of read requests accepted 55system.physmem.writeReqs 812156 # Number of write requests accepted 56system.physmem.readBursts 15495012 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 812156 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 991563904 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 116864 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6748800 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 132497824 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 6736904 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 1826 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706685 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 968097 # Per bank write bursts 67system.physmem.perBankRdBursts::1 967810 # Per bank write bursts 68system.physmem.perBankRdBursts::2 967673 # Per bank write bursts 69system.physmem.perBankRdBursts::3 967915 # Per bank write bursts 70system.physmem.perBankRdBursts::4 974446 # Per bank write bursts 71system.physmem.perBankRdBursts::5 968066 # Per bank write bursts 72system.physmem.perBankRdBursts::6 967653 # Per bank write bursts 73system.physmem.perBankRdBursts::7 967482 # Per bank write bursts 74system.physmem.perBankRdBursts::8 968460 # Per bank write bursts 75system.physmem.perBankRdBursts::9 968209 # Per bank write bursts 76system.physmem.perBankRdBursts::10 967967 # Per bank write bursts 77system.physmem.perBankRdBursts::11 967960 # Per bank write bursts 78system.physmem.perBankRdBursts::12 967930 # Per bank write bursts 79system.physmem.perBankRdBursts::13 967880 # Per bank write bursts 80system.physmem.perBankRdBursts::14 967953 # Per bank write bursts 81system.physmem.perBankRdBursts::15 967685 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6670 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6386 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6320 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6360 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6634 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6864 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6659 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6574 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7028 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6769 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6571 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6645 # Per bank write bursts 94system.physmem.perBankWrBursts::12 6565 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6383 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6560 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6462 # Per bank write bursts | 31system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory 35system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 36system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 37system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory 38system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s) 50system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.readReqs 168277 # Number of read requests accepted 58system.physmem.writeReqs 122785 # Number of write requests accepted 59system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue 60system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue 61system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM 62system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue 63system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM 64system.physmem.bytesReadSys 10195464 # Total read bytes from the system interface side 65system.physmem.bytesWrittenSys 7595380 # Total written bytes from the system interface side 66system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue 67system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one 68system.physmem.neitherReadNorWriteReqs 4505 # Number of requests that are neither read nor write 69system.physmem.perBankRdBursts::0 9709 # Per bank write bursts 70system.physmem.perBankRdBursts::1 9253 # Per bank write bursts 71system.physmem.perBankRdBursts::2 10215 # Per bank write bursts 72system.physmem.perBankRdBursts::3 10266 # Per bank write bursts 73system.physmem.perBankRdBursts::4 18988 # Per bank write bursts 74system.physmem.perBankRdBursts::5 10225 # Per bank write bursts 75system.physmem.perBankRdBursts::6 10580 # Per bank write bursts 76system.physmem.perBankRdBursts::7 10353 # Per bank write bursts 77system.physmem.perBankRdBursts::8 9698 # Per bank write bursts 78system.physmem.perBankRdBursts::9 9938 # Per bank write bursts 79system.physmem.perBankRdBursts::10 9924 # Per bank write bursts 80system.physmem.perBankRdBursts::11 8855 # Per bank write bursts 81system.physmem.perBankRdBursts::12 9985 # Per bank write bursts 82system.physmem.perBankRdBursts::13 10410 # Per bank write bursts 83system.physmem.perBankRdBursts::14 9933 # Per bank write bursts 84system.physmem.perBankRdBursts::15 9763 # Per bank write bursts 85system.physmem.perBankWrBursts::0 7210 # Per bank write bursts 86system.physmem.perBankWrBursts::1 6831 # Per bank write bursts 87system.physmem.perBankWrBursts::2 8029 # Per bank write bursts 88system.physmem.perBankWrBursts::3 7890 # Per bank write bursts 89system.physmem.perBankWrBursts::4 7400 # Per bank write bursts 90system.physmem.perBankWrBursts::5 7418 # Per bank write bursts 91system.physmem.perBankWrBursts::6 7750 # Per bank write bursts 92system.physmem.perBankWrBursts::7 7625 # Per bank write bursts 93system.physmem.perBankWrBursts::8 7363 # Per bank write bursts 94system.physmem.perBankWrBursts::9 7566 # Per bank write bursts 95system.physmem.perBankWrBursts::10 7503 # Per bank write bursts 96system.physmem.perBankWrBursts::11 6751 # Per bank write bursts 97system.physmem.perBankWrBursts::12 7436 # Per bank write bursts 98system.physmem.perBankWrBursts::13 7741 # Per bank write bursts 99system.physmem.perBankWrBursts::14 7284 # Per bank write bursts 100system.physmem.perBankWrBursts::15 7101 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 101system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2614567301000 # Total gap between requests | 102system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 103system.physmem.totGap 2902618699500 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) | 104system.physmem.readPktSize::0 0 # Read request sizes (log2) 105system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 103system.physmem.readPktSize::2 6644 # Read request sizes (log2) 104system.physmem.readPktSize::3 15335434 # Read request sizes (log2) | 106system.physmem.readPktSize::2 9558 # Read request sizes (log2) 107system.physmem.readPktSize::3 14 # Read request sizes (log2) |
| 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 108system.physmem.readPktSize::4 0 # Read request sizes (log2) 109system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 152934 # Read request sizes (log2) | 110system.physmem.readPktSize::6 158705 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) | 111system.physmem.writePktSize::0 0 # Write request sizes (log2) 112system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) | 113system.physmem.writePktSize::2 4381 # Write request sizes (log2) |
| 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 114system.physmem.writePktSize::3 0 # Write request sizes (log2) 115system.physmem.writePktSize::4 0 # Write request sizes (log2) 116system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 58138 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1126447 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 970731 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 976234 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1093523 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 987097 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1054685 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2721121 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2624601 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3412795 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 139881 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 116829 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 107818 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 104436 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 19578 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 18770 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 18545 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see | 117system.physmem.writePktSize::6 118404 # Write request sizes (log2) 118system.physmem.rdQLenPdf::0 167256 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 571 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 135system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 157system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 3703 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3729 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6107 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6133 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6136 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6126 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 6125 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6125 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6125 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 6130 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6132 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6127 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6126 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6125 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6124 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6124 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 1027284 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 971.798163 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 905.747967 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 203.998959 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22800 2.22% 2.22% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 22532 2.19% 4.41% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 8422 0.82% 5.23% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2556 0.25% 5.48% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2545 0.25% 5.73% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1785 0.17% 5.90% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 8607 0.84% 6.74% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 981 0.10% 6.84% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 957056 93.16% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 1027284 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6124 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 2529.911822 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 116281.505657 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 6119 99.92% 99.92% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 6124 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6124 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.219138 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.190607 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 0.983110 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 2397 39.14% 39.14% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 24 0.39% 39.53% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 3669 59.91% 99.44% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 32 0.52% 99.97% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::total 6124 # Writes before turning the bus around for reads 243system.physmem.totQLat 400730693500 # Total ticks spent queuing 244system.physmem.totMemAccLat 691227931000 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 77465930000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 25864.96 # Average queueing delay per DRAM burst | 165system.physmem.wrQLenPdf::15 2070 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::16 2628 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::17 6016 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::18 6156 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::19 6193 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::20 6817 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::22 7564 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::23 8052 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::24 8864 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 8233 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 7730 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 7142 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 6957 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 6255 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 6112 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 6123 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::32 6074 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::33 239 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::34 234 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::39 123 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::45 142 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::50 70 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 214system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation 218system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation 228system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::mean 20.279379 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::gmean 18.638132 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::stdev 12.466375 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::16-19 5064 86.37% 86.37% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20-23 42 0.72% 87.09% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24-27 33 0.56% 87.65% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::28-31 216 3.68% 91.34% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32-35 215 3.67% 95.00% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::36-39 12 0.20% 95.21% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::40-43 16 0.27% 95.48% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::48-51 25 0.43% 96.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::52-55 3 0.05% 96.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::56-59 6 0.10% 96.18% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::60-63 4 0.07% 96.25% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::64-67 164 2.80% 99.04% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::68-71 4 0.07% 99.11% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::72-75 3 0.05% 99.16% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::76-79 2 0.03% 99.20% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::80-83 13 0.22% 99.42% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::96-99 5 0.09% 99.56% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::100-103 1 0.02% 99.57% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::104-107 3 0.05% 99.62% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::108-111 3 0.05% 99.68% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::112-115 2 0.03% 99.71% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads 271system.physmem.totQLat 1491787750 # Total ticks spent queuing 272system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM 273system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers 274system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst |
| 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 248system.physmem.avgMemAccLat 44614.96 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 379.25 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s | 276system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst 277system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s |
| 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 254system.physmem.busUtil 2.98 # Data bus utilization in percentage 255system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads | 282system.physmem.busUtil 0.05 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads |
| 256system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 284system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 257system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing 258system.physmem.avgWrQLen 28.13 # Average write queue length when enqueuing 259system.physmem.readRowHits 14482679 # Number of row buffer hits during reads 260system.physmem.writeRowHits 88673 # Number of row buffer hits during writes 261system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads 262system.physmem.writeRowHitRate 84.07 # Row buffer hit rate for writes 263system.physmem.avgGap 160332.39 # Average gap between requests 264system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined 265system.physmem.memoryStateTime::IDLE 2239359524750 # Time in different power states 266system.physmem.memoryStateTime::REF 87306180000 # Time in different power states | 285system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing 287system.physmem.readRowHits 138438 # Number of row buffer hits during reads 288system.physmem.writeRowHits 90000 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes 291system.physmem.avgGap 9972509.98 # Average gap between requests 292system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined 293system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states 294system.physmem.memoryStateTime::REF 96924620000 # Time in different power states |
| 267system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 295system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 268system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states | 296system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states |
| 269system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 297system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 270system.physmem.actEnergy::0 3884796720 # Energy for activate commands per rank (pJ) 271system.physmem.actEnergy::1 3881470320 # Energy for activate commands per rank (pJ) 272system.physmem.preEnergy::0 2119680750 # Energy for precharge commands per rank (pJ) 273system.physmem.preEnergy::1 2117865750 # Energy for precharge commands per rank (pJ) 274system.physmem.readEnergy::0 60443307600 # Energy for read commands per rank (pJ) 275system.physmem.readEnergy::1 60403543200 # Energy for read commands per rank (pJ) 276system.physmem.writeEnergy::0 339986160 # Energy for write commands per rank (pJ) 277system.physmem.writeEnergy::1 343329840 # Energy for write commands per rank (pJ) 278system.physmem.refreshEnergy::0 170770888080 # Energy for refresh commands per rank (pJ) 279system.physmem.refreshEnergy::1 170770888080 # Energy for refresh commands per rank (pJ) 280system.physmem.actBackEnergy::0 155970246555 # Energy for active background per rank (pJ) 281system.physmem.actBackEnergy::1 156681731385 # Energy for active background per rank (pJ) 282system.physmem.preBackEnergy::0 1431925089750 # Energy for precharge background per rank (pJ) 283system.physmem.preBackEnergy::1 1431300980250 # Energy for precharge background per rank (pJ) 284system.physmem.totalEnergy::0 1825453995615 # Total energy per rank (pJ) 285system.physmem.totalEnergy::1 1825499808825 # Total energy per rank (pJ) 286system.physmem.averagePower::0 698.185571 # Core power per rank (mW) 287system.physmem.averagePower::1 698.203093 # Core power per rank (mW) 288system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 289system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 290system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 291system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 292system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 293system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory | 298system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ) 299system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ) 300system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ) 301system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ) 302system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) 303system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) 304system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) 305system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) 306system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) 307system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) 308system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ) 309system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ) 310system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ) 311system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ) 312system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ) 313system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ) 314system.physmem.averagePower::0 669.480430 # Core power per rank (mW) 315system.physmem.averagePower::1 669.392372 # Core power per rank (mW) 316system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory |
| 294system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 295system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 296system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 297system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 298system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 299system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) | 322system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) |
| 300system.membus.trans_dist::ReadReq 16546657 # Transaction distribution 301system.membus.trans_dist::ReadResp 16546657 # Transaction distribution 302system.membus.trans_dist::WriteReq 763381 # Transaction distribution 303system.membus.trans_dist::WriteResp 763381 # Transaction distribution 304system.membus.trans_dist::Writeback 58138 # Transaction distribution 305system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution 306system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution 307system.membus.trans_dist::ReadExReq 132459 # Transaction distribution 308system.membus.trans_dist::ReadExResp 132459 # Transaction distribution 309system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 311system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes) 312system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894372 # Packet count per connected master and slave (bytes) 314system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281306 # Packet count per connected master and slave (bytes) 315system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count::total 34952154 # Packet count per connected master and slave (bytes) 318system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) 319system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 320system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) 321system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 322system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551336 # Cumulative packet size per connected master and slave (bytes) 323system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18949570 # Cumulative packet size per connected master and slave (bytes) 324system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 325system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) 326system.membus.pkt_size::total 141632962 # Cumulative packet size per connected master and slave (bytes) 327system.membus.snoops 0 # Total snoops (count) 328system.membus.snoop_fanout::samples 215583 # Request fanout histogram | 328system.membus.trans_dist::ReadReq 70650 # Transaction distribution 329system.membus.trans_dist::ReadResp 70650 # Transaction distribution 330system.membus.trans_dist::WriteReq 27618 # Transaction distribution 331system.membus.trans_dist::WriteResp 27618 # Transaction distribution 332system.membus.trans_dist::Writeback 82180 # Transaction distribution 333system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 334system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 335system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution 336system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 337system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution 338system.membus.trans_dist::ReadExReq 128451 # Transaction distribution 339system.membus.trans_dist::ReadExResp 128451 # Transaction distribution 340system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes) 345system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 346system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) 347system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes) 348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) 352system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes) 353system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 354system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 355system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes) 356system.membus.snoops 219 # Total snoops (count) 357system.membus.snoop_fanout::samples 281834 # Request fanout histogram |
| 329system.membus.snoop_fanout::mean 1 # Request fanout histogram 330system.membus.snoop_fanout::stdev 0 # Request fanout histogram 331system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 332system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 358system.membus.snoop_fanout::mean 1 # Request fanout histogram 359system.membus.snoop_fanout::stdev 0 # Request fanout histogram 360system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 361system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 333system.membus.snoop_fanout::1 215583 100.00% 100.00% # Request fanout histogram | 362system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram |
| 334system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 335system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 336system.membus.snoop_fanout::min_value 1 # Request fanout histogram 337system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 363system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 365system.membus.snoop_fanout::min_value 1 # Request fanout histogram 366system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 338system.membus.snoop_fanout::total 215583 # Request fanout histogram 339system.membus.reqLayer0.occupancy 1204828500 # Layer occupancy (ticks) | 367system.membus.snoop_fanout::total 281834 # Request fanout histogram 368system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) |
| 340system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 369system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 341system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) | 370system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) |
| 342system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 371system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 343system.membus.reqLayer2.occupancy 3334000 # Layer occupancy (ticks) | 372system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) |
| 344system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 373system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 345system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 346system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 347system.membus.reqLayer6.occupancy 17917176000 # Layer occupancy (ticks) 348system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 349system.membus.respLayer1.occupancy 4952454428 # Layer occupancy (ticks) 350system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 351system.membus.respLayer2.occupancy 37912905250 # Layer occupancy (ticks) 352system.membus.respLayer2.utilization 1.5 # Layer utilization (%) | 374system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) 375system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 376system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks) 377system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 378system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) 379system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 380system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 381system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 382system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 383system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 384system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 385system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 386system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 387system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 388system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 389system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 390system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 391system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 392system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 393system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 394system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 395system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 396system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 397system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 398system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 399system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 400system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 401system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 402system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 403system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 404system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 405system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 406system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 407system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 408system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 409system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 410system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 353system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). | 411system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| 354system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 355system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 356system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 357system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 358system.cf0.dma_write_txs 0 # Number of DMA write transactions. 359system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution 360system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution 361system.iobus.trans_dist::WriteReq 8182 # Transaction distribution 362system.iobus.trans_dist::WriteResp 8182 # Transaction distribution 363system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 532 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1040 # Packet count per connected master and slave (bytes) 367system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) | 412system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 413system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 414system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 415system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 416system.cf0.dma_write_txs 631 # Number of DMA write transactions. 417system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 418system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 419system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 420system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 421system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 422system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 423system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 424system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) |
| 368system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 425system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 369system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 370system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 371system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) | 426system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 427system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) |
| 372system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 373system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 374system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) | 428system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 429system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 430system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 375system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 376system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) | 431system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) |
| 377system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 432system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 378system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 379system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 380system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 381system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 382system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) | |
| 383system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) | 433system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 434system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 435system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) |
|
| 384system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) | 436system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 385system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 386system.iobus.pkt_count_system.bridge.master::total 2383082 # Packet count per connected master and slave (bytes) 387system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 388system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) 389system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes) 390system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) 394system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) | 437system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 438system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 439system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 440system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 441system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 442system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 443system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 444system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 445system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 446system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 447system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 448system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 449system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) |
| 395system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) | 450system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
| 396system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 398system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 451system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 452system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) |
| 399system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 400system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 401system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 453system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 454system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 455system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 402system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 403system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) | 456system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) |
| 404system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 457system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 405system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 406system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 407system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 408system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 409system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | |
| 410system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 458system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 459system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 460system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) |
|
| 411system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 461system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 412system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 413system.iobus.pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) 414system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 415system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) 416system.iobus.pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) 417system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) | 462system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 463system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 464system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 465system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 466system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 467system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 468system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 469system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 470system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 471system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) |
| 418system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 472system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 419system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) | 473system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) |
| 420system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 474system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 421system.iobus.reqLayer2.occupancy 532000 # Layer occupancy (ticks) | 475system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) |
| 422system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 476system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 423system.iobus.reqLayer3.occupancy 526000 # Layer occupancy (ticks) | 477system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) |
| 424system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 478system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 425system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 426system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 427system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 428system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 429system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) | 479system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) |
| 430system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 480system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 431system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) | 481system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) |
| 432system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 482system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 433system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 434system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 435system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) | 483system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) |
| 436system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 484system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 437system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 438system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 439system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 440system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) | |
| 441system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 442system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 485system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 486system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 443system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) | 487system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) |
| 444system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 445system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 446system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 488system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 489system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 490system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 447system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) | 491system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) |
| 448system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 449system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 450system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 451system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 452system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 492system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 493system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 494system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 495system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 496system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 453system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) | 497system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) |
| 454system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 455system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 456system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 457system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 458system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 498system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 499system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 500system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 501system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 502system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 459system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 460system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 461system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) | 503system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) |
| 462system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 504system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 463system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) 464system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 465system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks) 466system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 467system.iobus.respLayer1.occupancy 38695381750 # Layer occupancy (ticks) 468system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) | 505system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 506system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 507system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 508system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 509system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 510system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 511system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) 512system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 513system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 514system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 515system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 516system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 517system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) 518system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 469system.cpu_clk_domain.clock 500 # Clock period in ticks 470system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 471system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 472system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 473system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 474system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 475system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 476system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 485system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 486system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 487system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 488system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 489system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 490system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 491system.cpu.dtb.inst_hits 0 # ITB inst hits 492system.cpu.dtb.inst_misses 0 # ITB inst misses | 519system.cpu_clk_domain.clock 500 # Clock period in ticks 520system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 521system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 522system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 523system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 524system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 525system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 526system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 535system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 536system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 537system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 538system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 539system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 540system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 541system.cpu.dtb.inst_hits 0 # ITB inst hits 542system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 493system.cpu.dtb.read_hits 13160242 # DTB read hits 494system.cpu.dtb.read_misses 7329 # DTB read misses 495system.cpu.dtb.write_hits 11228050 # DTB write hits 496system.cpu.dtb.write_misses 2212 # DTB write misses 497system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 498system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 499system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 500system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 501system.cpu.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB | 543system.cpu.dtb.read_hits 24532668 # DTB read hits 544system.cpu.dtb.read_misses 8148 # DTB read misses 545system.cpu.dtb.write_hits 19614514 # DTB write hits 546system.cpu.dtb.write_misses 1410 # DTB write misses 547system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 548system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 549system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 550system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 551system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB |
| 502system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 552system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 503system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch | 553system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch |
| 504system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 554system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 505system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 506system.cpu.dtb.read_accesses 13167571 # DTB read accesses 507system.cpu.dtb.write_accesses 11230262 # DTB write accesses | 555system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 556system.cpu.dtb.read_accesses 24540816 # DTB read accesses 557system.cpu.dtb.write_accesses 19615924 # DTB write accesses |
| 508system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 558system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 509system.cpu.dtb.hits 24388292 # DTB hits 510system.cpu.dtb.misses 9541 # DTB misses 511system.cpu.dtb.accesses 24397833 # DTB accesses | 559system.cpu.dtb.hits 44147182 # DTB hits 560system.cpu.dtb.misses 9558 # DTB misses 561system.cpu.dtb.accesses 44156740 # DTB accesses |
| 512system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 513system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 514system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 515system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 516system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 517system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 518system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 519system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 525system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 526system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 527system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 528system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 529system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 530system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 531system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 532system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 562system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 563system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 564system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 565system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 566system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 567system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 568system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 569system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 575system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 576system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 577system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 578system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 579system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 580system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 581system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 582system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 533system.cpu.itb.inst_hits 61481095 # ITB inst hits 534system.cpu.itb.inst_misses 4471 # ITB inst misses | 583system.cpu.itb.inst_hits 115605897 # ITB inst hits 584system.cpu.itb.inst_misses 4762 # ITB inst misses |
| 535system.cpu.itb.read_hits 0 # DTB read hits 536system.cpu.itb.read_misses 0 # DTB read misses 537system.cpu.itb.write_hits 0 # DTB write hits 538system.cpu.itb.write_misses 0 # DTB write misses | 585system.cpu.itb.read_hits 0 # DTB read hits 586system.cpu.itb.read_misses 0 # DTB read misses 587system.cpu.itb.write_hits 0 # DTB write hits 588system.cpu.itb.write_misses 0 # DTB write misses |
| 539system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 540system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 541system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 542system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 543system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB | 589system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 590system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 591system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 592system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 593system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB |
| 544system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 545system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 546system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 547system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 548system.cpu.itb.read_accesses 0 # DTB read accesses 549system.cpu.itb.write_accesses 0 # DTB write accesses | 594system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 595system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 596system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 597system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 598system.cpu.itb.read_accesses 0 # DTB read accesses 599system.cpu.itb.write_accesses 0 # DTB write accesses |
| 550system.cpu.itb.inst_accesses 61485566 # ITB inst accesses 551system.cpu.itb.hits 61481095 # DTB hits 552system.cpu.itb.misses 4471 # DTB misses 553system.cpu.itb.accesses 61485566 # DTB accesses 554system.cpu.numCycles 5229143129 # number of cpu cycles simulated | 600system.cpu.itb.inst_accesses 115610659 # ITB inst accesses 601system.cpu.itb.hits 115605897 # DTB hits 602system.cpu.itb.misses 4762 # DTB misses 603system.cpu.itb.accesses 115610659 # DTB accesses 604system.cpu.numCycles 5805238262 # number of cpu cycles simulated |
| 555system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 556system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 605system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 606system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 557system.cpu.committedInsts 60187274 # Number of instructions committed 558system.cpu.committedOps 71883961 # Number of ops (including micro ops) committed 559system.cpu.num_int_alu_accesses 64248492 # Number of integer alu accesses 560system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 561system.cpu.num_func_calls 2139801 # number of times a function call or return occured 562system.cpu.num_conditional_control_insts 7549047 # number of instructions that are conditional controls 563system.cpu.num_int_insts 64248492 # number of integer instructions 564system.cpu.num_fp_insts 10269 # number of float instructions 565system.cpu.num_int_register_reads 116110622 # number of times the integer registers were read 566system.cpu.num_int_register_writes 42863098 # number of times the integer registers were written 567system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 568system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 569system.cpu.num_cc_register_reads 257769006 # number of times the CC registers were read 570system.cpu.num_cc_register_writes 28995258 # number of times the CC registers were written 571system.cpu.num_mem_refs 25244235 # number of memory refs 572system.cpu.num_load_insts 13512788 # Number of load instructions 573system.cpu.num_store_insts 11731447 # Number of store instructions 574system.cpu.num_idle_cycles 4584209782.584247 # Number of idle cycles 575system.cpu.num_busy_cycles 644933346.415753 # Number of busy cycles 576system.cpu.not_idle_fraction 0.123334 # Percentage of non-idle cycles 577system.cpu.idle_fraction 0.876666 # Percentage of idle cycles 578system.cpu.Branches 10306630 # Number of branches fetched 579system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction 580system.cpu.op_class::IntAlu 47577014 65.23% 65.27% # Class of executed instruction 581system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction 582system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction 583system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction 584system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction 585system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction 586system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction 587system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction 588system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction 589system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction 590system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction 591system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction 592system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction 593system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction 594system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction 595system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction 596system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction 597system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction 598system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction 599system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction 600system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction 601system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction 602system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction 603system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction 604system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction 605system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Class of executed instruction 606system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction 607system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction 608system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction 609system.cpu.op_class::MemRead 13512788 18.53% 83.92% # Class of executed instruction 610system.cpu.op_class::MemWrite 11731447 16.08% 100.00% # Class of executed instruction | 607system.cpu.committedInsts 112506996 # Number of instructions committed 608system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed 609system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses 610system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 611system.cpu.num_func_calls 9898964 # number of times a function call or return occured 612system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls 613system.cpu.num_int_insts 119948924 # number of integer instructions 614system.cpu.num_fp_insts 11161 # number of float instructions 615system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read 616system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written 617system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 618system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 619system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read 620system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written 621system.cpu.num_mem_refs 45428231 # number of memory refs 622system.cpu.num_load_insts 24855392 # Number of load instructions 623system.cpu.num_store_insts 20572839 # Number of store instructions 624system.cpu.num_idle_cycles 5386456122.024144 # Number of idle cycles 625system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles 626system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles 627system.cpu.idle_fraction 0.927861 # Percentage of idle cycles 628system.cpu.Branches 25929456 # Number of branches fetched 629system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 630system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction 631system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction 632system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 633system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 634system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 635system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 636system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 637system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 638system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 639system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction 640system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction 641system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction 642system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction 643system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction 644system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction 645system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction 646system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction 647system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 648system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 649system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 650system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 651system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 652system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 653system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 654system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 655system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction 656system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 657system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 658system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 659system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction 660system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction |
| 611system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 612system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 661system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 662system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 613system.cpu.op_class::total 72939427 # Class of executed instruction | 663system.cpu.op_class::total 138771626 # Class of executed instruction |
| 614system.cpu.kern.inst.arm 0 # number of arm instructions executed | 664system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 615system.cpu.kern.inst.quiesce 83004 # number of quiesce instructions executed 616system.cpu.icache.tags.replacements 855897 # number of replacements 617system.cpu.icache.tags.tagsinuse 510.877214 # Cycle average of tags in use 618system.cpu.icache.tags.total_refs 60624686 # Total number of references to valid blocks. 619system.cpu.icache.tags.sampled_refs 856409 # Sample count of references to valid blocks. 620system.cpu.icache.tags.avg_refs 70.789408 # Average number of references to valid blocks. 621system.cpu.icache.tags.warmup_cycle 19623933250 # Cycle when the warmup percentage was hit. 622system.cpu.icache.tags.occ_blocks::cpu.inst 510.877214 # Average occupied blocks per requestor 623system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy 624system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy | 665system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed 666system.cpu.icache.tags.replacements 1699818 # number of replacements 667system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use 668system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. 672system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor 673system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy |
| 625system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 675system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 626system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 627system.cpu.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 628system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id 629system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id | 676system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 678system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 679system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id |
| 630system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 680system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 631system.cpu.icache.tags.tag_accesses 62337504 # Number of tag accesses 632system.cpu.icache.tags.data_accesses 62337504 # Number of data accesses 633system.cpu.icache.ReadReq_hits::cpu.inst 60624686 # number of ReadReq hits 634system.cpu.icache.ReadReq_hits::total 60624686 # number of ReadReq hits 635system.cpu.icache.demand_hits::cpu.inst 60624686 # number of demand (read+write) hits 636system.cpu.icache.demand_hits::total 60624686 # number of demand (read+write) hits 637system.cpu.icache.overall_hits::cpu.inst 60624686 # number of overall hits 638system.cpu.icache.overall_hits::total 60624686 # number of overall hits 639system.cpu.icache.ReadReq_misses::cpu.inst 856409 # number of ReadReq misses 640system.cpu.icache.ReadReq_misses::total 856409 # number of ReadReq misses 641system.cpu.icache.demand_misses::cpu.inst 856409 # number of demand (read+write) misses 642system.cpu.icache.demand_misses::total 856409 # number of demand (read+write) misses 643system.cpu.icache.overall_misses::cpu.inst 856409 # number of overall misses 644system.cpu.icache.overall_misses::total 856409 # number of overall misses 645system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766778500 # number of ReadReq miss cycles 646system.cpu.icache.ReadReq_miss_latency::total 11766778500 # number of ReadReq miss cycles 647system.cpu.icache.demand_miss_latency::cpu.inst 11766778500 # number of demand (read+write) miss cycles 648system.cpu.icache.demand_miss_latency::total 11766778500 # number of demand (read+write) miss cycles 649system.cpu.icache.overall_miss_latency::cpu.inst 11766778500 # number of overall miss cycles 650system.cpu.icache.overall_miss_latency::total 11766778500 # number of overall miss cycles 651system.cpu.icache.ReadReq_accesses::cpu.inst 61481095 # number of ReadReq accesses(hits+misses) 652system.cpu.icache.ReadReq_accesses::total 61481095 # number of ReadReq accesses(hits+misses) 653system.cpu.icache.demand_accesses::cpu.inst 61481095 # number of demand (read+write) accesses 654system.cpu.icache.demand_accesses::total 61481095 # number of demand (read+write) accesses 655system.cpu.icache.overall_accesses::cpu.inst 61481095 # number of overall (read+write) accesses 656system.cpu.icache.overall_accesses::total 61481095 # number of overall (read+write) accesses 657system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013930 # miss rate for ReadReq accesses 658system.cpu.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses 659system.cpu.icache.demand_miss_rate::cpu.inst 0.013930 # miss rate for demand accesses 660system.cpu.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses 661system.cpu.icache.overall_miss_rate::cpu.inst 0.013930 # miss rate for overall accesses 662system.cpu.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses 663system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13739.671699 # average ReadReq miss latency 664system.cpu.icache.ReadReq_avg_miss_latency::total 13739.671699 # average ReadReq miss latency 665system.cpu.icache.demand_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency 666system.cpu.icache.demand_avg_miss_latency::total 13739.671699 # average overall miss latency 667system.cpu.icache.overall_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency 668system.cpu.icache.overall_avg_miss_latency::total 13739.671699 # average overall miss latency | 681system.cpu.icache.tags.tag_accesses 117306233 # Number of tag accesses 682system.cpu.icache.tags.data_accesses 117306233 # Number of data accesses 683system.cpu.icache.ReadReq_hits::cpu.inst 113905561 # number of ReadReq hits 684system.cpu.icache.ReadReq_hits::total 113905561 # number of ReadReq hits 685system.cpu.icache.demand_hits::cpu.inst 113905561 # number of demand (read+write) hits 686system.cpu.icache.demand_hits::total 113905561 # number of demand (read+write) hits 687system.cpu.icache.overall_hits::cpu.inst 113905561 # number of overall hits 688system.cpu.icache.overall_hits::total 113905561 # number of overall hits 689system.cpu.icache.ReadReq_misses::cpu.inst 1700336 # number of ReadReq misses 690system.cpu.icache.ReadReq_misses::total 1700336 # number of ReadReq misses 691system.cpu.icache.demand_misses::cpu.inst 1700336 # number of demand (read+write) misses 692system.cpu.icache.demand_misses::total 1700336 # number of demand (read+write) misses 693system.cpu.icache.overall_misses::cpu.inst 1700336 # number of overall misses 694system.cpu.icache.overall_misses::total 1700336 # number of overall misses 695system.cpu.icache.ReadReq_miss_latency::cpu.inst 23243215000 # number of ReadReq miss cycles 696system.cpu.icache.ReadReq_miss_latency::total 23243215000 # number of ReadReq miss cycles 697system.cpu.icache.demand_miss_latency::cpu.inst 23243215000 # number of demand (read+write) miss cycles 698system.cpu.icache.demand_miss_latency::total 23243215000 # number of demand (read+write) miss cycles 699system.cpu.icache.overall_miss_latency::cpu.inst 23243215000 # number of overall miss cycles 700system.cpu.icache.overall_miss_latency::total 23243215000 # number of overall miss cycles 701system.cpu.icache.ReadReq_accesses::cpu.inst 115605897 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.ReadReq_accesses::total 115605897 # number of ReadReq accesses(hits+misses) 703system.cpu.icache.demand_accesses::cpu.inst 115605897 # number of demand (read+write) accesses 704system.cpu.icache.demand_accesses::total 115605897 # number of demand (read+write) accesses 705system.cpu.icache.overall_accesses::cpu.inst 115605897 # number of overall (read+write) accesses 706system.cpu.icache.overall_accesses::total 115605897 # number of overall (read+write) accesses 707system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014708 # miss rate for ReadReq accesses 708system.cpu.icache.ReadReq_miss_rate::total 0.014708 # miss rate for ReadReq accesses 709system.cpu.icache.demand_miss_rate::cpu.inst 0.014708 # miss rate for demand accesses 710system.cpu.icache.demand_miss_rate::total 0.014708 # miss rate for demand accesses 711system.cpu.icache.overall_miss_rate::cpu.inst 0.014708 # miss rate for overall accesses 712system.cpu.icache.overall_miss_rate::total 0.014708 # miss rate for overall accesses 713system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.777620 # average ReadReq miss latency 714system.cpu.icache.ReadReq_avg_miss_latency::total 13669.777620 # average ReadReq miss latency 715system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency 716system.cpu.icache.demand_avg_miss_latency::total 13669.777620 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency 718system.cpu.icache.overall_avg_miss_latency::total 13669.777620 # average overall miss latency |
| 669system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 670system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 672system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 674system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.icache.fast_writes 0 # number of fast writes performed 676system.cpu.icache.cache_copies 0 # number of cache copies performed | 719system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.icache.fast_writes 0 # number of fast writes performed 726system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 677system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856409 # number of ReadReq MSHR misses 678system.cpu.icache.ReadReq_mshr_misses::total 856409 # number of ReadReq MSHR misses 679system.cpu.icache.demand_mshr_misses::cpu.inst 856409 # number of demand (read+write) MSHR misses 680system.cpu.icache.demand_mshr_misses::total 856409 # number of demand (read+write) MSHR misses 681system.cpu.icache.overall_mshr_misses::cpu.inst 856409 # number of overall MSHR misses 682system.cpu.icache.overall_mshr_misses::total 856409 # number of overall MSHR misses 683system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049953500 # number of ReadReq MSHR miss cycles 684system.cpu.icache.ReadReq_mshr_miss_latency::total 10049953500 # number of ReadReq MSHR miss cycles 685system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049953500 # number of demand (read+write) MSHR miss cycles 686system.cpu.icache.demand_mshr_miss_latency::total 10049953500 # number of demand (read+write) MSHR miss cycles 687system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049953500 # number of overall MSHR miss cycles 688system.cpu.icache.overall_mshr_miss_latency::total 10049953500 # number of overall MSHR miss cycles 689system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 440846250 # number of ReadReq MSHR uncacheable cycles 690system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles 691system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 440846250 # number of overall MSHR uncacheable cycles 692system.cpu.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles 693system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for ReadReq accesses 694system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses 695system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for demand accesses 696system.cpu.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses 697system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for overall accesses 698system.cpu.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses 699system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11734.992860 # average ReadReq mshr miss latency 700system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11734.992860 # average ReadReq mshr miss latency 701system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11734.992860 # average overall mshr miss latency 702system.cpu.icache.demand_avg_mshr_miss_latency::total 11734.992860 # average overall mshr miss latency 703system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11734.992860 # average overall mshr miss latency 704system.cpu.icache.overall_avg_mshr_miss_latency::total 11734.992860 # average overall mshr miss latency | 727system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses 728system.cpu.icache.ReadReq_mshr_misses::total 1700336 # number of ReadReq MSHR misses 729system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 # number of demand (read+write) MSHR misses 730system.cpu.icache.demand_mshr_misses::total 1700336 # number of demand (read+write) MSHR misses 731system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses 732system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses 733system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835992000 # number of ReadReq MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_latency::total 19835992000 # number of ReadReq MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles 738system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles 739system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles 740system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles 741system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles 742system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles 743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses 745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses 746system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses 747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses 748system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency |
| 705system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 706system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 707system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 708system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 709system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 755system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 756system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 757system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 758system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 759system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 710system.cpu.l2cache.tags.replacements 62827 # number of replacements 711system.cpu.l2cache.tags.tagsinuse 50749.017881 # Cycle average of tags in use 712system.cpu.l2cache.tags.total_refs 1679035 # Total number of references to valid blocks. 713system.cpu.l2cache.tags.sampled_refs 128209 # Sample count of references to valid blocks. 714system.cpu.l2cache.tags.avg_refs 13.096077 # Average number of references to valid blocks. 715system.cpu.l2cache.tags.warmup_cycle 2564785024500 # Cycle when the warmup percentage was hit. 716system.cpu.l2cache.tags.occ_blocks::writebacks 37681.898715 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884636 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000702 # Average occupied blocks per requestor 719system.cpu.l2cache.tags.occ_blocks::cpu.inst 6996.424673 # Average occupied blocks per requestor 720system.cpu.l2cache.tags.occ_blocks::cpu.data 6066.809153 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_percent::writebacks 0.574980 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy | 760system.cpu.l2cache.tags.replacements 88869 # number of replacements 761system.cpu.l2cache.tags.tagsinuse 64932.369340 # Cycle average of tags in use 762system.cpu.l2cache.tags.total_refs 2760846 # Total number of references to valid blocks. 763system.cpu.l2cache.tags.sampled_refs 154135 # Sample count of references to valid blocks. 764system.cpu.l2cache.tags.avg_refs 17.911869 # Average number of references to valid blocks. 765system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 766system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822165 # Average occupied blocks per requestor 767system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809354 # Average occupied blocks per requestor 768system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012212 # Average occupied blocks per requestor 769system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724019 # Average occupied blocks per requestor 770system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001590 # Average occupied blocks per requestor 771system.cpu.l2cache.tags.occ_percent::writebacks 0.773221 # Average percentage of cache occupancy 772system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy |
| 723system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 773system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 724system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106757 # Average percentage of cache occupancy 725system.cpu.l2cache.tags.occ_percent::cpu.data 0.092572 # Average percentage of cache occupancy 726system.cpu.l2cache.tags.occ_percent::total 0.774369 # Average percentage of cache occupancy 727system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 728system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id 729system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 730system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 731system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id 732system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id 733system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7027 # Occupied blocks per task id 734system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56159 # Occupied blocks per task id 735system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 736system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id 737system.cpu.l2cache.tags.tag_accesses 17118836 # Number of tag accesses 738system.cpu.l2cache.tags.data_accesses 17118836 # Number of data accesses 739system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7538 # number of ReadReq hits 740system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3114 # number of ReadReq hits 741system.cpu.l2cache.ReadReq_hits::cpu.inst 844199 # number of ReadReq hits 742system.cpu.l2cache.ReadReq_hits::cpu.data 368983 # number of ReadReq hits 743system.cpu.l2cache.ReadReq_hits::total 1223834 # number of ReadReq hits 744system.cpu.l2cache.Writeback_hits::writebacks 595027 # number of Writeback hits 745system.cpu.l2cache.Writeback_hits::total 595027 # number of Writeback hits 746system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 747system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 748system.cpu.l2cache.ReadExReq_hits::cpu.data 113476 # number of ReadExReq hits 749system.cpu.l2cache.ReadExReq_hits::total 113476 # number of ReadExReq hits 750system.cpu.l2cache.demand_hits::cpu.dtb.walker 7538 # number of demand (read+write) hits 751system.cpu.l2cache.demand_hits::cpu.itb.walker 3114 # number of demand (read+write) hits 752system.cpu.l2cache.demand_hits::cpu.inst 844199 # number of demand (read+write) hits 753system.cpu.l2cache.demand_hits::cpu.data 482459 # number of demand (read+write) hits 754system.cpu.l2cache.demand_hits::total 1337310 # number of demand (read+write) hits 755system.cpu.l2cache.overall_hits::cpu.dtb.walker 7538 # number of overall hits 756system.cpu.l2cache.overall_hits::cpu.itb.walker 3114 # number of overall hits 757system.cpu.l2cache.overall_hits::cpu.inst 844199 # number of overall hits 758system.cpu.l2cache.overall_hits::cpu.data 482459 # number of overall hits 759system.cpu.l2cache.overall_hits::total 1337310 # number of overall hits 760system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses | 774system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146190 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::cpu.data 0.071320 # Average percentage of cache occupancy 776system.cpu.l2cache.tags.occ_percent::total 0.990789 # Average percentage of cache occupancy 777system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 778system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id 779system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 780system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id 785system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 786system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995804 # Percentage of cache occupancy per task id 787system.cpu.l2cache.tags.tag_accesses 26241966 # Number of tag accesses 788system.cpu.l2cache.tags.data_accesses 26241966 # Number of data accesses 789system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7097 # number of ReadReq hits 790system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3700 # number of ReadReq hits 791system.cpu.l2cache.ReadReq_hits::cpu.inst 1682273 # number of ReadReq hits 792system.cpu.l2cache.ReadReq_hits::cpu.data 514822 # number of ReadReq hits 793system.cpu.l2cache.ReadReq_hits::total 2207892 # number of ReadReq hits 794system.cpu.l2cache.Writeback_hits::writebacks 686231 # number of Writeback hits 795system.cpu.l2cache.Writeback_hits::total 686231 # number of Writeback hits 796system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 797system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 798system.cpu.l2cache.ReadExReq_hits::cpu.data 166049 # number of ReadExReq hits 799system.cpu.l2cache.ReadExReq_hits::total 166049 # number of ReadExReq hits 800system.cpu.l2cache.demand_hits::cpu.dtb.walker 7097 # number of demand (read+write) hits 801system.cpu.l2cache.demand_hits::cpu.itb.walker 3700 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.inst 1682273 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::cpu.data 680871 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::total 2373941 # number of demand (read+write) hits 805system.cpu.l2cache.overall_hits::cpu.dtb.walker 7097 # number of overall hits 806system.cpu.l2cache.overall_hits::cpu.itb.walker 3700 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.inst 1682273 # number of overall hits 808system.cpu.l2cache.overall_hits::cpu.data 680871 # number of overall hits 809system.cpu.l2cache.overall_hits::total 2373941 # number of overall hits 810system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses |
| 761system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 811system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 762system.cpu.l2cache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses 763system.cpu.l2cache.ReadReq_misses::cpu.data 9872 # number of ReadReq misses 764system.cpu.l2cache.ReadReq_misses::total 20475 # number of ReadReq misses 765system.cpu.l2cache.UpgradeReq_misses::cpu.data 2895 # number of UpgradeReq misses 766system.cpu.l2cache.UpgradeReq_misses::total 2895 # number of UpgradeReq misses 767system.cpu.l2cache.ReadExReq_misses::cpu.data 134075 # number of ReadExReq misses 768system.cpu.l2cache.ReadExReq_misses::total 134075 # number of ReadExReq misses 769system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses | 812system.cpu.l2cache.ReadReq_misses::cpu.inst 18039 # number of ReadReq misses 813system.cpu.l2cache.ReadReq_misses::cpu.data 12191 # number of ReadReq misses 814system.cpu.l2cache.ReadReq_misses::total 30239 # number of ReadReq misses 815system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses 816system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses 817system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 818system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 819system.cpu.l2cache.ReadExReq_misses::cpu.data 130235 # number of ReadExReq misses 820system.cpu.l2cache.ReadExReq_misses::total 130235 # number of ReadExReq misses 821system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses |
| 770system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 822system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 771system.cpu.l2cache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses 772system.cpu.l2cache.demand_misses::cpu.data 143947 # number of demand (read+write) misses 773system.cpu.l2cache.demand_misses::total 154550 # number of demand (read+write) misses 774system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses | 823system.cpu.l2cache.demand_misses::cpu.inst 18039 # number of demand (read+write) misses 824system.cpu.l2cache.demand_misses::cpu.data 142426 # number of demand (read+write) misses 825system.cpu.l2cache.demand_misses::total 160474 # number of demand (read+write) misses 826system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses |
| 775system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 827system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 776system.cpu.l2cache.overall_misses::cpu.inst 10596 # number of overall misses 777system.cpu.l2cache.overall_misses::cpu.data 143947 # number of overall misses 778system.cpu.l2cache.overall_misses::total 154550 # number of overall misses 779system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles 780system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles 781system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 749772500 # number of ReadReq miss cycles 782system.cpu.l2cache.ReadReq_miss_latency::cpu.data 732753250 # number of ReadReq miss cycles 783system.cpu.l2cache.ReadReq_miss_latency::total 1482981000 # number of ReadReq miss cycles 784system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 346985 # number of UpgradeReq miss cycles 785system.cpu.l2cache.UpgradeReq_miss_latency::total 346985 # number of UpgradeReq miss cycles 786system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9334508634 # number of ReadExReq miss cycles 787system.cpu.l2cache.ReadExReq_miss_latency::total 9334508634 # number of ReadExReq miss cycles 788system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles 789system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles 790system.cpu.l2cache.demand_miss_latency::cpu.inst 749772500 # number of demand (read+write) miss cycles 791system.cpu.l2cache.demand_miss_latency::cpu.data 10067261884 # number of demand (read+write) miss cycles 792system.cpu.l2cache.demand_miss_latency::total 10817489634 # number of demand (read+write) miss cycles 793system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles 794system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles 795system.cpu.l2cache.overall_miss_latency::cpu.inst 749772500 # number of overall miss cycles 796system.cpu.l2cache.overall_miss_latency::cpu.data 10067261884 # number of overall miss cycles 797system.cpu.l2cache.overall_miss_latency::total 10817489634 # number of overall miss cycles 798system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7543 # number of ReadReq accesses(hits+misses) 799system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3116 # number of ReadReq accesses(hits+misses) 800system.cpu.l2cache.ReadReq_accesses::cpu.inst 854795 # number of ReadReq accesses(hits+misses) 801system.cpu.l2cache.ReadReq_accesses::cpu.data 378855 # number of ReadReq accesses(hits+misses) 802system.cpu.l2cache.ReadReq_accesses::total 1244309 # number of ReadReq accesses(hits+misses) 803system.cpu.l2cache.Writeback_accesses::writebacks 595027 # number of Writeback accesses(hits+misses) 804system.cpu.l2cache.Writeback_accesses::total 595027 # number of Writeback accesses(hits+misses) 805system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2921 # number of UpgradeReq accesses(hits+misses) 806system.cpu.l2cache.UpgradeReq_accesses::total 2921 # number of UpgradeReq accesses(hits+misses) 807system.cpu.l2cache.ReadExReq_accesses::cpu.data 247551 # number of ReadExReq accesses(hits+misses) 808system.cpu.l2cache.ReadExReq_accesses::total 247551 # number of ReadExReq accesses(hits+misses) 809system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7543 # number of demand (read+write) accesses 810system.cpu.l2cache.demand_accesses::cpu.itb.walker 3116 # number of demand (read+write) accesses 811system.cpu.l2cache.demand_accesses::cpu.inst 854795 # number of demand (read+write) accesses 812system.cpu.l2cache.demand_accesses::cpu.data 626406 # number of demand (read+write) accesses 813system.cpu.l2cache.demand_accesses::total 1491860 # number of demand (read+write) accesses 814system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7543 # number of overall (read+write) accesses 815system.cpu.l2cache.overall_accesses::cpu.itb.walker 3116 # number of overall (read+write) accesses 816system.cpu.l2cache.overall_accesses::cpu.inst 854795 # number of overall (read+write) accesses 817system.cpu.l2cache.overall_accesses::cpu.data 626406 # number of overall (read+write) accesses 818system.cpu.l2cache.overall_accesses::total 1491860 # number of overall (read+write) accesses 819system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses 820system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000642 # miss rate for ReadReq accesses 821system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012396 # miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026057 # miss rate for ReadReq accesses 823system.cpu.l2cache.ReadReq_miss_rate::total 0.016455 # miss rate for ReadReq accesses 824system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991099 # miss rate for UpgradeReq accesses 825system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991099 # miss rate for UpgradeReq accesses 826system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541606 # miss rate for ReadExReq accesses 827system.cpu.l2cache.ReadExReq_miss_rate::total 0.541606 # miss rate for ReadExReq accesses 828system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses 829system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000642 # miss rate for demand accesses 830system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012396 # miss rate for demand accesses 831system.cpu.l2cache.demand_miss_rate::cpu.data 0.229798 # miss rate for demand accesses 832system.cpu.l2cache.demand_miss_rate::total 0.103596 # miss rate for demand accesses 833system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses 834system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000642 # miss rate for overall accesses 835system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012396 # miss rate for overall accesses 836system.cpu.l2cache.overall_miss_rate::cpu.data 0.229798 # miss rate for overall accesses 837system.cpu.l2cache.overall_miss_rate::total 0.103596 # miss rate for overall accesses 838system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency 839system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency 840system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70759.956587 # average ReadReq miss latency 841system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74225.410251 # average ReadReq miss latency 842system.cpu.l2cache.ReadReq_avg_miss_latency::total 72428.864469 # average ReadReq miss latency 843system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.856649 # average UpgradeReq miss latency 844system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.856649 # average UpgradeReq miss latency 845system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69621.544911 # average ReadExReq miss latency 846system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69621.544911 # average ReadExReq miss latency 847system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 848system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency 849system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70759.956587 # average overall miss latency 850system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69937.281666 # average overall miss latency 851system.cpu.l2cache.demand_avg_miss_latency::total 69993.462530 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 853system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency 854system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70759.956587 # average overall miss latency 855system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69937.281666 # average overall miss latency 856system.cpu.l2cache.overall_avg_miss_latency::total 69993.462530 # average overall miss latency | 828system.cpu.l2cache.overall_misses::cpu.inst 18039 # number of overall misses 829system.cpu.l2cache.overall_misses::cpu.data 142426 # number of overall misses 830system.cpu.l2cache.overall_misses::total 160474 # number of overall misses 831system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 567750 # number of ReadReq miss cycles 832system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 833system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312883000 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918689000 # number of ReadReq miss cycles 835system.cpu.l2cache.ReadReq_miss_latency::total 2232289250 # number of ReadReq miss cycles 836system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 # number of UpgradeReq miss cycles 837system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles 838system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles 839system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles 840system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles 841system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles 842system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles 846system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles 847system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 849system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles 852system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) 854system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) 855system.cpu.l2cache.ReadReq_accesses::cpu.data 527013 # number of ReadReq accesses(hits+misses) 856system.cpu.l2cache.ReadReq_accesses::total 2238131 # number of ReadReq accesses(hits+misses) 857system.cpu.l2cache.Writeback_accesses::writebacks 686231 # number of Writeback accesses(hits+misses) 858system.cpu.l2cache.Writeback_accesses::total 686231 # number of Writeback accesses(hits+misses) 859system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2742 # number of UpgradeReq accesses(hits+misses) 860system.cpu.l2cache.UpgradeReq_accesses::total 2742 # number of UpgradeReq accesses(hits+misses) 861system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 862system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 863system.cpu.l2cache.ReadExReq_accesses::cpu.data 296284 # number of ReadExReq accesses(hits+misses) 864system.cpu.l2cache.ReadExReq_accesses::total 296284 # number of ReadExReq accesses(hits+misses) 865system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7104 # number of demand (read+write) accesses 866system.cpu.l2cache.demand_accesses::cpu.itb.walker 3702 # number of demand (read+write) accesses 867system.cpu.l2cache.demand_accesses::cpu.inst 1700312 # number of demand (read+write) accesses 868system.cpu.l2cache.demand_accesses::cpu.data 823297 # number of demand (read+write) accesses 869system.cpu.l2cache.demand_accesses::total 2534415 # number of demand (read+write) accesses 870system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7104 # number of overall (read+write) accesses 871system.cpu.l2cache.overall_accesses::cpu.itb.walker 3702 # number of overall (read+write) accesses 872system.cpu.l2cache.overall_accesses::cpu.inst 1700312 # number of overall (read+write) accesses 873system.cpu.l2cache.overall_accesses::cpu.data 823297 # number of overall (read+write) accesses 874system.cpu.l2cache.overall_accesses::total 2534415 # number of overall (read+write) accesses 875system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000985 # miss rate for ReadReq accesses 876system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000540 # miss rate for ReadReq accesses 877system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010609 # miss rate for ReadReq accesses 878system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023132 # miss rate for ReadReq accesses 879system.cpu.l2cache.ReadReq_miss_rate::total 0.013511 # miss rate for ReadReq accesses 880system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991612 # miss rate for UpgradeReq accesses 881system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991612 # miss rate for UpgradeReq accesses 882system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 883system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 884system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439561 # miss rate for ReadExReq accesses 885system.cpu.l2cache.ReadExReq_miss_rate::total 0.439561 # miss rate for ReadExReq accesses 886system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000985 # miss rate for demand accesses 887system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000540 # miss rate for demand accesses 888system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010609 # miss rate for demand accesses 889system.cpu.l2cache.demand_miss_rate::cpu.data 0.172995 # miss rate for demand accesses 890system.cpu.l2cache.demand_miss_rate::total 0.063318 # miss rate for demand accesses 891system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000985 # miss rate for overall accesses 892system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000540 # miss rate for overall accesses 893system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010609 # miss rate for overall accesses 894system.cpu.l2cache.overall_miss_rate::cpu.data 0.172995 # miss rate for overall accesses 895system.cpu.l2cache.overall_miss_rate::total 0.063318 # miss rate for overall accesses 896system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857 # average ReadReq miss latency 897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143 # average ReadReq miss latency 901system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency 903system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency 904system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency 905system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency 906system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency 907system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 908system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 909system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency 910system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency 911system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency 912system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 913system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 914system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency 916system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency |
| 857system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 858system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 859system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 860system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 861system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 862system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 863system.cpu.l2cache.fast_writes 0 # number of fast writes performed 864system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 917system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 918system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 919system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 920system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 921system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 922system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 923system.cpu.l2cache.fast_writes 0 # number of fast writes performed 924system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 865system.cpu.l2cache.writebacks::writebacks 58138 # number of writebacks 866system.cpu.l2cache.writebacks::total 58138 # number of writebacks 867system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses | 925system.cpu.l2cache.writebacks::writebacks 82180 # number of writebacks 926system.cpu.l2cache.writebacks::total 82180 # number of writebacks 927system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses |
| 868system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 928system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 869system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses 870system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9872 # number of ReadReq MSHR misses 871system.cpu.l2cache.ReadReq_mshr_misses::total 20475 # number of ReadReq MSHR misses 872system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2895 # number of UpgradeReq MSHR misses 873system.cpu.l2cache.UpgradeReq_mshr_misses::total 2895 # number of UpgradeReq MSHR misses 874system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134075 # number of ReadExReq MSHR misses 875system.cpu.l2cache.ReadExReq_mshr_misses::total 134075 # number of ReadExReq MSHR misses 876system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses | 929system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18039 # number of ReadReq MSHR misses 930system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12191 # number of ReadReq MSHR misses 931system.cpu.l2cache.ReadReq_mshr_misses::total 30239 # number of ReadReq MSHR misses 932system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2719 # number of UpgradeReq MSHR misses 933system.cpu.l2cache.UpgradeReq_mshr_misses::total 2719 # number of UpgradeReq MSHR misses 934system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 935system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 936system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130235 # number of ReadExReq MSHR misses 937system.cpu.l2cache.ReadExReq_mshr_misses::total 130235 # number of ReadExReq MSHR misses 938system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses |
| 877system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 939system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 878system.cpu.l2cache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.data 143947 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.demand_mshr_misses::total 154550 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses | 940system.cpu.l2cache.demand_mshr_misses::cpu.inst 18039 # number of demand (read+write) MSHR misses 941system.cpu.l2cache.demand_mshr_misses::cpu.data 142426 # number of demand (read+write) MSHR misses 942system.cpu.l2cache.demand_mshr_misses::total 160474 # number of demand (read+write) MSHR misses 943system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses |
| 882system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 944system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 883system.cpu.l2cache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses 884system.cpu.l2cache.overall_mshr_misses::cpu.data 143947 # number of overall MSHR misses 885system.cpu.l2cache.overall_mshr_misses::total 154550 # number of overall MSHR misses 886system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles | 945system.cpu.l2cache.overall_mshr_misses::cpu.inst 18039 # number of overall MSHR misses 946system.cpu.l2cache.overall_mshr_misses::cpu.data 142426 # number of overall MSHR misses 947system.cpu.l2cache.overall_mshr_misses::total 160474 # number of overall MSHR misses 948system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 480750 # number of ReadReq MSHR miss cycles |
| 887system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles | 949system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles |
| 888system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 617083500 # number of ReadReq MSHR miss cycles 889system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 609612750 # number of ReadReq MSHR miss cycles 890system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1227064000 # number of ReadReq MSHR miss cycles 891system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28955895 # number of UpgradeReq MSHR miss cycles 892system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28955895 # number of UpgradeReq MSHR miss cycles 893system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7657225866 # number of ReadExReq MSHR miss cycles 894system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7657225866 # number of ReadExReq MSHR miss cycles 895system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles | 950system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087047500 # number of ReadReq MSHR miss cycles 951system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766535000 # number of ReadReq MSHR miss cycles 952system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1854188250 # number of ReadReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles 955system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 956system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles 957system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles 958system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles 959system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles |
| 896system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles | 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles |
| 897system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 617083500 # number of demand (read+write) MSHR miss cycles 898system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8266838616 # number of demand (read+write) MSHR miss cycles 899system.cpu.l2cache.demand_mshr_miss_latency::total 8884289866 # number of demand (read+write) MSHR miss cycles 900system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles | 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles 962system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles |
| 901system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles | 965system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles |
| 902system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 617083500 # number of overall MSHR miss cycles 903system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8266838616 # number of overall MSHR miss cycles 904system.cpu.l2cache.overall_mshr_miss_latency::total 8884289866 # number of overall MSHR miss cycles 905system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 349507750 # number of ReadReq MSHR uncacheable cycles 906system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166662160750 # number of ReadReq MSHR uncacheable cycles 907system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167011668500 # number of ReadReq MSHR uncacheable cycles 908system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16705919061 # number of WriteReq MSHR uncacheable cycles 909system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16705919061 # number of WriteReq MSHR uncacheable cycles 910system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349507750 # number of overall MSHR uncacheable cycles 911system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183368079811 # number of overall MSHR uncacheable cycles 912system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183717587561 # number of overall MSHR uncacheable cycles 913system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for ReadReq accesses 914system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for ReadReq accesses 915system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for ReadReq accesses 916system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026057 # mshr miss rate for ReadReq accesses 917system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016455 # mshr miss rate for ReadReq accesses 918system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991099 # mshr miss rate for UpgradeReq accesses 919system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991099 # mshr miss rate for UpgradeReq accesses 920system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541606 # mshr miss rate for ReadExReq accesses 921system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541606 # mshr miss rate for ReadExReq accesses 922system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for demand accesses 923system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for demand accesses 924system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for demand accesses 925system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229798 # mshr miss rate for demand accesses 926system.cpu.l2cache.demand_mshr_miss_rate::total 0.103596 # mshr miss rate for demand accesses 927system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for overall accesses 928system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for overall accesses 929system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for overall accesses 930system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229798 # mshr miss rate for overall accesses 931system.cpu.l2cache.overall_mshr_miss_rate::total 0.103596 # mshr miss rate for overall accesses 932system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency | 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles 967system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles 968system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles 969system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles 970system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles 971system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles 972system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles 973system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles 974system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles 975system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles 976system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles 977system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses 978system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023132 # mshr miss rate for ReadReq accesses 981system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013511 # mshr miss rate for ReadReq accesses 982system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991612 # mshr miss rate for UpgradeReq accesses 983system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991612 # mshr miss rate for UpgradeReq accesses 984system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 985system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 986system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439561 # mshr miss rate for ReadExReq accesses 987system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439561 # mshr miss rate for ReadExReq accesses 988system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for demand accesses 989system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for demand accesses 990system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for demand accesses 991system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for demand accesses 992system.cpu.l2cache.demand_mshr_miss_rate::total 0.063318 # mshr miss rate for demand accesses 993system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for overall accesses 994system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for overall accesses 995system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for overall accesses 996system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for overall accesses 997system.cpu.l2cache.overall_mshr_miss_rate::total 0.063318 # mshr miss rate for overall accesses 998system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average ReadReq mshr miss latency |
| 933system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency | 999system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency |
| 934system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58237.400906 # average ReadReq mshr miss latency 935system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61751.696718 # average ReadReq mshr miss latency 936system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59929.865690 # average ReadReq mshr miss latency 937system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.036269 # average UpgradeReq mshr miss latency 938system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.036269 # average UpgradeReq mshr miss latency 939system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57111.511214 # average ReadExReq mshr miss latency 940system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57111.511214 # average ReadExReq mshr miss latency 941system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency | 1000system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359 # average ReadReq mshr miss latency 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467 # average ReadReq mshr miss latency 1002system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712 # average ReadReq mshr miss latency 1003system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency 1004system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency 1005system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1006system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1007system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency 1008system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency |
| 942system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 943system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58237.400906 # average overall mshr miss latency 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57429.738834 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57484.890754 # average overall mshr miss latency 946system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency | 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency 1013system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency |
| 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 948system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58237.400906 # average overall mshr miss latency 949system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57429.738834 # average overall mshr miss latency 950system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57484.890754 # average overall mshr miss latency | 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency 1017system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency 1018system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency |
| 951system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 952system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 953system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 954system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 955system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 956system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 957system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 958system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 959system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1019system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1020system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1021system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1022system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1023system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1024system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1025system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1026system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1027system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 960system.cpu.dcache.tags.replacements 625894 # number of replacements 961system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use 962system.cpu.dcache.tags.total_refs 21786154 # Total number of references to valid blocks. 963system.cpu.dcache.tags.sampled_refs 626406 # Sample count of references to valid blocks. 964system.cpu.dcache.tags.avg_refs 34.779606 # Average number of references to valid blocks. 965system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. 966system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor 967system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy 968system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy | 1028system.cpu.dcache.tags.replacements 822747 # number of replacements 1029system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use 1030system.cpu.dcache.tags.total_refs 43252597 # Total number of references to valid blocks. 1031system.cpu.dcache.tags.sampled_refs 823259 # Sample count of references to valid blocks. 1032system.cpu.dcache.tags.avg_refs 52.538262 # Average number of references to valid blocks. 1033system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. 1034system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor 1035system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy 1036system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy |
| 969system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1037system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 970system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 971system.cpu.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 972system.cpu.dcache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id | 1038system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1039system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 1040system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 1041system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
| 973system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1042system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 974system.cpu.dcache.tags.tag_accesses 90404594 # Number of tag accesses 975system.cpu.dcache.tags.data_accesses 90404594 # Number of data accesses 976system.cpu.dcache.ReadReq_hits::cpu.data 11249411 # number of ReadReq hits 977system.cpu.dcache.ReadReq_hits::total 11249411 # number of ReadReq hits 978system.cpu.dcache.WriteReq_hits::cpu.data 9965441 # number of WriteReq hits 979system.cpu.dcache.WriteReq_hits::total 9965441 # number of WriteReq hits 980system.cpu.dcache.SoftPFReq_hits::cpu.data 84252 # number of SoftPFReq hits 981system.cpu.dcache.SoftPFReq_hits::total 84252 # number of SoftPFReq hits 982system.cpu.dcache.LoadLockedReq_hits::cpu.data 236461 # number of LoadLockedReq hits 983system.cpu.dcache.LoadLockedReq_hits::total 236461 # number of LoadLockedReq hits 984system.cpu.dcache.StoreCondReq_hits::cpu.data 247668 # number of StoreCondReq hits 985system.cpu.dcache.StoreCondReq_hits::total 247668 # number of StoreCondReq hits 986system.cpu.dcache.demand_hits::cpu.data 21214852 # number of demand (read+write) hits 987system.cpu.dcache.demand_hits::total 21214852 # number of demand (read+write) hits 988system.cpu.dcache.overall_hits::cpu.data 21299104 # number of overall hits 989system.cpu.dcache.overall_hits::total 21299104 # number of overall hits 990system.cpu.dcache.ReadReq_misses::cpu.data 294699 # number of ReadReq misses 991system.cpu.dcache.ReadReq_misses::total 294699 # number of ReadReq misses 992system.cpu.dcache.WriteReq_misses::cpu.data 255299 # number of WriteReq misses 993system.cpu.dcache.WriteReq_misses::total 255299 # number of WriteReq misses 994system.cpu.dcache.SoftPFReq_misses::cpu.data 100108 # number of SoftPFReq misses 995system.cpu.dcache.SoftPFReq_misses::total 100108 # number of SoftPFReq misses 996system.cpu.dcache.LoadLockedReq_misses::cpu.data 11208 # number of LoadLockedReq misses 997system.cpu.dcache.LoadLockedReq_misses::total 11208 # number of LoadLockedReq misses 998system.cpu.dcache.demand_misses::cpu.data 549998 # number of demand (read+write) misses 999system.cpu.dcache.demand_misses::total 549998 # number of demand (read+write) misses 1000system.cpu.dcache.overall_misses::cpu.data 650106 # number of overall misses 1001system.cpu.dcache.overall_misses::total 650106 # number of overall misses 1002system.cpu.dcache.ReadReq_miss_latency::cpu.data 4039018749 # number of ReadReq miss cycles 1003system.cpu.dcache.ReadReq_miss_latency::total 4039018749 # number of ReadReq miss cycles 1004system.cpu.dcache.WriteReq_miss_latency::cpu.data 11552022511 # number of WriteReq miss cycles 1005system.cpu.dcache.WriteReq_miss_latency::total 11552022511 # number of WriteReq miss cycles 1006system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154983250 # number of LoadLockedReq miss cycles 1007system.cpu.dcache.LoadLockedReq_miss_latency::total 154983250 # number of LoadLockedReq miss cycles 1008system.cpu.dcache.demand_miss_latency::cpu.data 15591041260 # number of demand (read+write) miss cycles 1009system.cpu.dcache.demand_miss_latency::total 15591041260 # number of demand (read+write) miss cycles 1010system.cpu.dcache.overall_miss_latency::cpu.data 15591041260 # number of overall miss cycles 1011system.cpu.dcache.overall_miss_latency::total 15591041260 # number of overall miss cycles 1012system.cpu.dcache.ReadReq_accesses::cpu.data 11544110 # number of ReadReq accesses(hits+misses) 1013system.cpu.dcache.ReadReq_accesses::total 11544110 # number of ReadReq accesses(hits+misses) 1014system.cpu.dcache.WriteReq_accesses::cpu.data 10220740 # number of WriteReq accesses(hits+misses) 1015system.cpu.dcache.WriteReq_accesses::total 10220740 # number of WriteReq accesses(hits+misses) 1016system.cpu.dcache.SoftPFReq_accesses::cpu.data 184360 # number of SoftPFReq accesses(hits+misses) 1017system.cpu.dcache.SoftPFReq_accesses::total 184360 # number of SoftPFReq accesses(hits+misses) 1018system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247669 # number of LoadLockedReq accesses(hits+misses) 1019system.cpu.dcache.LoadLockedReq_accesses::total 247669 # number of LoadLockedReq accesses(hits+misses) 1020system.cpu.dcache.StoreCondReq_accesses::cpu.data 247668 # number of StoreCondReq accesses(hits+misses) 1021system.cpu.dcache.StoreCondReq_accesses::total 247668 # number of StoreCondReq accesses(hits+misses) 1022system.cpu.dcache.demand_accesses::cpu.data 21764850 # number of demand (read+write) accesses 1023system.cpu.dcache.demand_accesses::total 21764850 # number of demand (read+write) accesses 1024system.cpu.dcache.overall_accesses::cpu.data 21949210 # number of overall (read+write) accesses 1025system.cpu.dcache.overall_accesses::total 21949210 # number of overall (read+write) accesses 1026system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025528 # miss rate for ReadReq accesses 1027system.cpu.dcache.ReadReq_miss_rate::total 0.025528 # miss rate for ReadReq accesses 1028system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024979 # miss rate for WriteReq accesses 1029system.cpu.dcache.WriteReq_miss_rate::total 0.024979 # miss rate for WriteReq accesses 1030system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.543003 # miss rate for SoftPFReq accesses 1031system.cpu.dcache.SoftPFReq_miss_rate::total 0.543003 # miss rate for SoftPFReq accesses 1032system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045254 # miss rate for LoadLockedReq accesses 1033system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045254 # miss rate for LoadLockedReq accesses 1034system.cpu.dcache.demand_miss_rate::cpu.data 0.025270 # miss rate for demand accesses 1035system.cpu.dcache.demand_miss_rate::total 0.025270 # miss rate for demand accesses 1036system.cpu.dcache.overall_miss_rate::cpu.data 0.029619 # miss rate for overall accesses 1037system.cpu.dcache.overall_miss_rate::total 0.029619 # miss rate for overall accesses 1038system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13705.573310 # average ReadReq miss latency 1039system.cpu.dcache.ReadReq_avg_miss_latency::total 13705.573310 # average ReadReq miss latency 1040system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45248.992401 # average WriteReq miss latency 1041system.cpu.dcache.WriteReq_avg_miss_latency::total 45248.992401 # average WriteReq miss latency 1042system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13827.913098 # average LoadLockedReq miss latency 1043system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13827.913098 # average LoadLockedReq miss latency 1044system.cpu.dcache.demand_avg_miss_latency::cpu.data 28347.450827 # average overall miss latency 1045system.cpu.dcache.demand_avg_miss_latency::total 28347.450827 # average overall miss latency 1046system.cpu.dcache.overall_avg_miss_latency::cpu.data 23982.306362 # average overall miss latency 1047system.cpu.dcache.overall_avg_miss_latency::total 23982.306362 # average overall miss latency | 1043system.cpu.dcache.tags.tag_accesses 177194873 # Number of tag accesses 1044system.cpu.dcache.tags.data_accesses 177194873 # Number of data accesses 1045system.cpu.dcache.ReadReq_hits::cpu.data 23122385 # number of ReadReq hits 1046system.cpu.dcache.ReadReq_hits::total 23122385 # number of ReadReq hits 1047system.cpu.dcache.WriteReq_hits::cpu.data 18831357 # number of WriteReq hits 1048system.cpu.dcache.WriteReq_hits::total 18831357 # number of WriteReq hits 1049system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits 1050system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits 1051system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits 1052system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits 1053system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits 1054system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits 1055system.cpu.dcache.demand_hits::cpu.data 41953742 # number of demand (read+write) hits 1056system.cpu.dcache.demand_hits::total 41953742 # number of demand (read+write) hits 1057system.cpu.dcache.overall_hits::cpu.data 42345863 # number of overall hits 1058system.cpu.dcache.overall_hits::total 42345863 # number of overall hits 1059system.cpu.dcache.ReadReq_misses::cpu.data 402167 # number of ReadReq misses 1060system.cpu.dcache.ReadReq_misses::total 402167 # number of ReadReq misses 1061system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses 1062system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses 1063system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses 1064system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses 1065system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses 1066system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses 1067system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1068system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 1069system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses 1070system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses 1071system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses 1072system.cpu.dcache.overall_misses::total 820348 # number of overall misses 1073system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles 1074system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles 1075system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles 1076system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles 1077system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles 1078system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles 1079system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles 1080system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles 1081system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles 1082system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles 1083system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles 1084system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles 1085system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) 1086system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) 1087system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) 1088system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses) 1089system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) 1090system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) 1091system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) 1092system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) 1093system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses) 1094system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses) 1095system.cpu.dcache.demand_accesses::cpu.data 42654935 # number of demand (read+write) accesses 1096system.cpu.dcache.demand_accesses::total 42654935 # number of demand (read+write) accesses 1097system.cpu.dcache.overall_accesses::cpu.data 43166211 # number of overall (read+write) accesses 1098system.cpu.dcache.overall_accesses::total 43166211 # number of overall (read+write) accesses 1099system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses 1100system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses 1101system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses 1102system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses 1103system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses 1104system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses 1105system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses 1106system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses 1107system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 1108system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 1109system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses 1110system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses 1111system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses 1112system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses 1113system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency 1114system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency 1115system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency 1116system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency 1117system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency 1118system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency 1119system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency 1120system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency 1121system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency 1122system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency 1123system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency 1124system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency |
| 1048system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 1049system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1125system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 1126system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1050system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked | 1127system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked |
| 1051system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1128system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1052system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked | 1129system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked |
| 1053system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1054system.cpu.dcache.fast_writes 0 # number of fast writes performed 1055system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1130system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1131system.cpu.dcache.fast_writes 0 # number of fast writes performed 1132system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1056system.cpu.dcache.writebacks::writebacks 595027 # number of writebacks 1057system.cpu.dcache.writebacks::total 595027 # number of writebacks 1058system.cpu.dcache.ReadReq_mshr_hits::cpu.data 533 # number of ReadReq MSHR hits 1059system.cpu.dcache.ReadReq_mshr_hits::total 533 # number of ReadReq MSHR hits 1060system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4827 # number of WriteReq MSHR hits 1061system.cpu.dcache.WriteReq_mshr_hits::total 4827 # number of WriteReq MSHR hits 1062system.cpu.dcache.demand_mshr_hits::cpu.data 5360 # number of demand (read+write) MSHR hits 1063system.cpu.dcache.demand_mshr_hits::total 5360 # number of demand (read+write) MSHR hits 1064system.cpu.dcache.overall_mshr_hits::cpu.data 5360 # number of overall MSHR hits 1065system.cpu.dcache.overall_mshr_hits::total 5360 # number of overall MSHR hits 1066system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294166 # number of ReadReq MSHR misses 1067system.cpu.dcache.ReadReq_mshr_misses::total 294166 # number of ReadReq MSHR misses 1068system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250472 # number of WriteReq MSHR misses 1069system.cpu.dcache.WriteReq_mshr_misses::total 250472 # number of WriteReq MSHR misses 1070system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 73481 # number of SoftPFReq MSHR misses 1071system.cpu.dcache.SoftPFReq_mshr_misses::total 73481 # number of SoftPFReq MSHR misses 1072system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11208 # number of LoadLockedReq MSHR misses 1073system.cpu.dcache.LoadLockedReq_mshr_misses::total 11208 # number of LoadLockedReq MSHR misses 1074system.cpu.dcache.demand_mshr_misses::cpu.data 544638 # number of demand (read+write) MSHR misses 1075system.cpu.dcache.demand_mshr_misses::total 544638 # number of demand (read+write) MSHR misses 1076system.cpu.dcache.overall_mshr_misses::cpu.data 618119 # number of overall MSHR misses 1077system.cpu.dcache.overall_mshr_misses::total 618119 # number of overall MSHR misses 1078system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3444363000 # number of ReadReq MSHR miss cycles 1079system.cpu.dcache.ReadReq_mshr_miss_latency::total 3444363000 # number of ReadReq MSHR miss cycles 1080system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10784804239 # number of WriteReq MSHR miss cycles 1081system.cpu.dcache.WriteReq_mshr_miss_latency::total 10784804239 # number of WriteReq MSHR miss cycles 1082system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1224587250 # number of SoftPFReq MSHR miss cycles 1083system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1224587250 # number of SoftPFReq MSHR miss cycles 1084system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132510750 # number of LoadLockedReq MSHR miss cycles 1085system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132510750 # number of LoadLockedReq MSHR miss cycles 1086system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14229167239 # number of demand (read+write) MSHR miss cycles 1087system.cpu.dcache.demand_mshr_miss_latency::total 14229167239 # number of demand (read+write) MSHR miss cycles 1088system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15453754489 # number of overall MSHR miss cycles 1089system.cpu.dcache.overall_mshr_miss_latency::total 15453754489 # number of overall MSHR miss cycles 1090system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182056011250 # number of ReadReq MSHR uncacheable cycles 1091system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182056011250 # number of ReadReq MSHR uncacheable cycles 1092system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242438939 # number of WriteReq MSHR uncacheable cycles 1093system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242438939 # number of WriteReq MSHR uncacheable cycles 1094system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208298450189 # number of overall MSHR uncacheable cycles 1095system.cpu.dcache.overall_mshr_uncacheable_latency::total 208298450189 # number of overall MSHR uncacheable cycles 1096system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025482 # mshr miss rate for ReadReq accesses 1097system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025482 # mshr miss rate for ReadReq accesses 1098system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses 1099system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses 1100system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398573 # mshr miss rate for SoftPFReq accesses 1101system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398573 # mshr miss rate for SoftPFReq accesses 1102system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045254 # mshr miss rate for LoadLockedReq accesses 1103system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045254 # mshr miss rate for LoadLockedReq accesses 1104system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025024 # mshr miss rate for demand accesses 1105system.cpu.dcache.demand_mshr_miss_rate::total 0.025024 # mshr miss rate for demand accesses 1106system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028161 # mshr miss rate for overall accesses 1107system.cpu.dcache.overall_mshr_miss_rate::total 0.028161 # mshr miss rate for overall accesses 1108system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11708.909255 # average ReadReq mshr miss latency 1109system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11708.909255 # average ReadReq mshr miss latency 1110system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43057.923596 # average WriteReq mshr miss latency 1111system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43057.923596 # average WriteReq mshr miss latency 1112system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16665.359072 # average SoftPFReq mshr miss latency 1113system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16665.359072 # average SoftPFReq mshr miss latency 1114system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11822.872056 # average LoadLockedReq mshr miss latency 1115system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056 # average LoadLockedReq mshr miss latency 1116system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26125.917103 # average overall mshr miss latency 1117system.cpu.dcache.demand_avg_mshr_miss_latency::total 26125.917103 # average overall mshr miss latency 1118system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25001.261066 # average overall mshr miss latency 1119system.cpu.dcache.overall_avg_mshr_miss_latency::total 25001.261066 # average overall mshr miss latency | 1133system.cpu.dcache.writebacks::writebacks 686231 # number of writebacks 1134system.cpu.dcache.writebacks::total 686231 # number of writebacks 1135system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits 1136system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits 1137system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits 1138system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits 1139system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits 1140system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits 1141system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits 1142system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits 1143system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401540 # number of ReadReq MSHR misses 1144system.cpu.dcache.ReadReq_mshr_misses::total 401540 # number of ReadReq MSHR misses 1145system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses 1146system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses 1147system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses 1148system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses 1149system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses 1150system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses 1151system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1152system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 1153system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses 1154system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses 1155system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses 1156system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses 1157system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles 1158system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles 1159system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles 1160system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles 1161system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles 1162system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles 1163system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles 1164system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles 1165system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles 1166system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles 1167system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles 1168system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles 1169system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles 1170system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles 1171system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles 1172system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles 1173system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles 1174system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles 1175system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles 1176system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles 1177system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses 1178system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses 1179system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses 1180system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses 1181system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses 1182system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses 1183system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses 1184system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses 1185system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 1186system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 1187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses 1188system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses 1189system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses 1190system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses 1191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency 1192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency 1193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency 1194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency 1195system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency 1196system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency 1197system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency 1198system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency 1199system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency 1200system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency 1201system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency 1202system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency 1203system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency 1204system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency |
| 1120system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1121system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1122system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1123system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1124system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1125system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1126system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1205system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1206system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1207system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1208system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1209system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1210system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1211system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1127system.cpu.toL2Bus.trans_dist::ReadReq 2453657 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadResp 2453657 # Transaction distribution 1129system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution 1130system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::Writeback 595027 # Transaction distribution 1132system.cpu.toL2Bus.trans_dist::UpgradeReq 2921 # Transaction distribution 1133system.cpu.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution 1134system.cpu.toL2Bus.trans_dist::ReadExReq 247551 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::ReadExResp 247551 # Transaction distribution 1136system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724466 # Packet count per connected master and slave (bytes) 1137system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748697 # Packet count per connected master and slave (bytes) 1138system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12042 # Packet count per connected master and slave (bytes) 1139system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes) 1140system.cpu.toL2Bus.pkt_count::total 7511457 # Packet count per connected master and slave (bytes) 1141system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54733404 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83586150 # Cumulative packet size per connected master and slave (bytes) 1143system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12464 # Cumulative packet size per connected master and slave (bytes) 1144system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) 1145system.cpu.toL2Bus.pkt_size::total 138362190 # Cumulative packet size per connected master and slave (bytes) 1146system.cpu.toL2Bus.snoops 18590 # Total snoops (count) 1147system.cpu.toL2Bus.snoop_fanout::samples 2108398 # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 1212system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution 1214system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution 1221system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution 1222system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution 1223system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes) 1224system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) 1225system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) 1226system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) 1227system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes) 1228system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes) 1229system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) 1230system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) 1232system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes) 1233system.cpu.toL2Bus.snoops 52963 # Total snoops (count) 1234system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram 1236system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram |
| 1150system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1152system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1154system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1155system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1237system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1238system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1239system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1240system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1241system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1242system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1156system.cpu.toL2Bus.snoop_fanout::5 2108398 100.00% 100.00% # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 1243system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram 1244system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram |
| 1158system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram | 1245system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1246system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram |
| 1160system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::total 2108398 # Request fanout histogram 1162system.cpu.toL2Bus.reqLayer0.occupancy 3007986500 # Layer occupancy (ticks) | 1247system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1248system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram 1249system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks) |
| 1163system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1250system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1164system.cpu.toL2Bus.respLayer0.occupancy 1294797750 # Layer occupancy (ticks) 1165system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1166system.cpu.toL2Bus.respLayer1.occupancy 2533255572 # Layer occupancy (ticks) 1167system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1168system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) | 1251system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1252system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1253system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks) 1254system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1255system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks) 1256system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1257system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) |
| 1169system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1258system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1170system.cpu.toL2Bus.respLayer3.occupancy 18709500 # Layer occupancy (ticks) | 1259system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) |
| 1171system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1260system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1172system.iocache.tags.replacements 0 # number of replacements 1173system.iocache.tags.tagsinuse 0 # Cycle average of tags in use | 1261system.iocache.tags.replacements 36424 # number of replacements 1262system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use |
| 1174system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1263system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1175system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1176system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1177system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1178system.iocache.tags.tag_accesses 0 # Number of tag accesses 1179system.iocache.tags.data_accesses 0 # Number of data accesses | 1264system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1265system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1266system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit. 1267system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor 1268system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy 1269system.iocache.tags.occ_percent::total 0.070837 # Average percentage of cache occupancy 1270system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1271system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1272system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1273system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1274system.iocache.tags.data_accesses 328122 # Number of data accesses 1275system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1276system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1277system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1278system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1279system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1280system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1281system.iocache.overall_misses::realview.ide 234 # number of overall misses 1282system.iocache.overall_misses::total 234 # number of overall misses 1283system.iocache.ReadReq_miss_latency::realview.ide 28038377 # number of ReadReq miss cycles 1284system.iocache.ReadReq_miss_latency::total 28038377 # number of ReadReq miss cycles 1285system.iocache.demand_miss_latency::realview.ide 28038377 # number of demand (read+write) miss cycles 1286system.iocache.demand_miss_latency::total 28038377 # number of demand (read+write) miss cycles 1287system.iocache.overall_miss_latency::realview.ide 28038377 # number of overall miss cycles 1288system.iocache.overall_miss_latency::total 28038377 # number of overall miss cycles 1289system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1290system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1291system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1292system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1293system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1294system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1295system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1296system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1297system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1298system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1299system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1300system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1301system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1302system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1303system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932 # average ReadReq miss latency 1304system.iocache.ReadReq_avg_miss_latency::total 119822.123932 # average ReadReq miss latency 1305system.iocache.demand_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency 1306system.iocache.demand_avg_miss_latency::total 119822.123932 # average overall miss latency 1307system.iocache.overall_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency 1308system.iocache.overall_avg_miss_latency::total 119822.123932 # average overall miss latency |
| 1180system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1184system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1309system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1310system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1311system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1312system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1313system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1314system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1186system.iocache.fast_writes 0 # number of fast writes performed | 1315system.iocache.fast_writes 36224 # number of fast writes performed |
| 1187system.iocache.cache_copies 0 # number of cache copies performed | 1316system.iocache.cache_copies 0 # number of cache copies performed |
| 1188system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of ReadReq MSHR uncacheable cycles 1189system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750 # number of ReadReq MSHR uncacheable cycles 1190system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of overall MSHR uncacheable cycles 1191system.iocache.overall_mshr_uncacheable_latency::total 1760318460750 # number of overall MSHR uncacheable cycles 1192system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1193system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1194system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1195system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1317system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1318system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1319system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1320system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1321system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1322system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1323system.iocache.ReadReq_mshr_miss_latency::realview.ide 15869377 # number of ReadReq MSHR miss cycles 1324system.iocache.ReadReq_mshr_miss_latency::total 15869377 # number of ReadReq MSHR miss cycles 1325system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2206856981 # number of WriteInvalidateReq MSHR miss cycles 1326system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2206856981 # number of WriteInvalidateReq MSHR miss cycles 1327system.iocache.demand_mshr_miss_latency::realview.ide 15869377 # number of demand (read+write) MSHR miss cycles 1328system.iocache.demand_mshr_miss_latency::total 15869377 # number of demand (read+write) MSHR miss cycles 1329system.iocache.overall_mshr_miss_latency::realview.ide 15869377 # number of overall MSHR miss cycles 1330system.iocache.overall_mshr_miss_latency::total 15869377 # number of overall MSHR miss cycles 1331system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1332system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1333system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1334system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1335system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1336system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1337system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427 # average ReadReq mshr miss latency 1338system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency 1339system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1340system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1341system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1342system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency 1343system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1344system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency |
| 1196system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1197 1198---------- End Simulation Statistics ---------- | 1345system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1346 1347---------- End Simulation Statistics ---------- |