| stats.txt (10220:9eab5efc02e8) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.616230 # Number of seconds simulated 4sim_ticks 2616229847000 # Number of ticks simulated 5final_tick 2616229847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.614581 # Number of seconds simulated 4sim_ticks 2614581252500 # Number of ticks simulated 5final_tick 2614581252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 375445 # Simulator instruction rate (inst/s) 8host_op_rate 477768 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16316419265 # Simulator tick rate (ticks/s) 10host_mem_usage 464828 # Number of bytes of host memory used 11host_seconds 160.34 # Real time elapsed on the host 12sim_insts 60200042 # Number of instructions simulated 13sim_ops 76606857 # Number of ops (including micro ops) simulated | 7host_inst_rate 331710 # Simulator instruction rate (inst/s) 8host_op_rate 396174 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14409825510 # Simulator tick rate (ticks/s) 10host_mem_usage 433940 # Number of bytes of host memory used 11host_seconds 181.44 # Real time elapsed on the host 12sim_insts 60186875 # Number of instructions simulated 13sim_ops 71883476 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 22system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 27system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) | |
| 28system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 16system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 31system.physmem.bytes_read::cpu.inst 703560 # Number of bytes read from this memory 32system.physmem.bytes_read::cpu.data 9089944 # Number of bytes read from this memory 33system.physmem.bytes_read::total 132477344 # Number of bytes read from this memory 34system.physmem.bytes_inst_read::cpu.inst 703560 # Number of instructions bytes read from this memory 35system.physmem.bytes_inst_read::total 703560 # Number of instructions bytes read from this memory 36system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory | 19system.physmem.bytes_read::cpu.inst 704520 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9109080 # Number of bytes read from this memory 21system.physmem.bytes_read::total 132497440 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 704520 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 704520 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3720512 # Number of bytes written to this memory |
| 37system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory |
| 38system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory | 26system.physmem.bytes_written::total 6736584 # Number of bytes written to this memory |
| 39system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 27system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 42system.physmem.num_reads::cpu.inst 17205 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu.data 142066 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 15494702 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142355 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15495006 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 58133 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory |
| 47system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory 48system.physmem.bw_read::realview.clcd 46893201 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.num_writes::total 812151 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 46922769 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) |
| 51system.physmem.bw_read::cpu.inst 268921 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu.data 3474444 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50636737 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu.inst 268921 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::total 268921 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_write::writebacks 1416658 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu.data 1152831 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2569490 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1416658 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46893201 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3483954 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 50676352 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1422986 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1153558 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2576544 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1422986 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 46922769 # Total bandwidth to/from this memory (bytes/s) |
| 61system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) |
| 63system.physmem.bw_total::cpu.inst 268921 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu.data 4627275 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::total 53206227 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.readReqs 15494702 # Number of read requests accepted 67system.physmem.writeReqs 811929 # Number of write requests accepted 68system.physmem.readBursts 15494702 # Number of DRAM read bursts, including those serviced by the write queue 69system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue 70system.physmem.bytesReadDRAM 991533248 # Total number of bytes read from DRAM 71system.physmem.bytesReadWrQ 127680 # Total number of bytes read from write queue 72system.physmem.bytesWritten 6729728 # Total number of bytes written to DRAM 73system.physmem.bytesReadSys 132477344 # Total read bytes from the system interface side 74system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side 75system.physmem.servicedByWrQ 1995 # Number of DRAM read bursts serviced by the write queue 76system.physmem.mergedWrBursts 706751 # Number of DRAM write bursts merged with an existing one 77system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write 78system.physmem.perBankRdBursts::0 967982 # Per bank write bursts 79system.physmem.perBankRdBursts::1 967715 # Per bank write bursts 80system.physmem.perBankRdBursts::2 967669 # Per bank write bursts 81system.physmem.perBankRdBursts::3 967754 # Per bank write bursts 82system.physmem.perBankRdBursts::4 974564 # Per bank write bursts 83system.physmem.perBankRdBursts::5 968184 # Per bank write bursts 84system.physmem.perBankRdBursts::6 967779 # Per bank write bursts 85system.physmem.perBankRdBursts::7 967692 # Per bank write bursts 86system.physmem.perBankRdBursts::8 968544 # Per bank write bursts 87system.physmem.perBankRdBursts::9 968137 # Per bank write bursts 88system.physmem.perBankRdBursts::10 967949 # Per bank write bursts 89system.physmem.perBankRdBursts::11 967746 # Per bank write bursts 90system.physmem.perBankRdBursts::12 967851 # Per bank write bursts 91system.physmem.perBankRdBursts::13 967741 # Per bank write bursts 92system.physmem.perBankRdBursts::14 967800 # Per bank write bursts 93system.physmem.perBankRdBursts::15 967600 # Per bank write bursts 94system.physmem.perBankWrBursts::0 6503 # Per bank write bursts 95system.physmem.perBankWrBursts::1 6305 # Per bank write bursts 96system.physmem.perBankWrBursts::2 6309 # Per bank write bursts 97system.physmem.perBankWrBursts::3 6231 # Per bank write bursts 98system.physmem.perBankWrBursts::4 6800 # Per bank write bursts 99system.physmem.perBankWrBursts::5 6982 # Per bank write bursts 100system.physmem.perBankWrBursts::6 6786 # Per bank write bursts 101system.physmem.perBankWrBursts::7 6777 # Per bank write bursts 102system.physmem.perBankWrBursts::8 7080 # Per bank write bursts 103system.physmem.perBankWrBursts::9 6733 # Per bank write bursts 104system.physmem.perBankWrBursts::10 6548 # Per bank write bursts 105system.physmem.perBankWrBursts::11 6441 # Per bank write bursts 106system.physmem.perBankWrBursts::12 6486 # Per bank write bursts 107system.physmem.perBankWrBursts::13 6281 # Per bank write bursts 108system.physmem.perBankWrBursts::14 6425 # Per bank write bursts 109system.physmem.perBankWrBursts::15 6465 # Per bank write bursts | 51system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4637512 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53252896 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15495006 # Number of read requests accepted 55system.physmem.writeReqs 812151 # Number of write requests accepted 56system.physmem.readBursts 15495006 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 812151 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 991553920 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 126464 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6744512 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 132497440 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 6736584 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 1976 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706747 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 968147 # Per bank write bursts 67system.physmem.perBankRdBursts::1 967810 # Per bank write bursts 68system.physmem.perBankRdBursts::2 967673 # Per bank write bursts 69system.physmem.perBankRdBursts::3 967915 # Per bank write bursts 70system.physmem.perBankRdBursts::4 974375 # Per bank write bursts 71system.physmem.perBankRdBursts::5 968054 # Per bank write bursts 72system.physmem.perBankRdBursts::6 967653 # Per bank write bursts 73system.physmem.perBankRdBursts::7 967480 # Per bank write bursts 74system.physmem.perBankRdBursts::8 968459 # Per bank write bursts 75system.physmem.perBankRdBursts::9 968209 # Per bank write bursts 76system.physmem.perBankRdBursts::10 967967 # Per bank write bursts 77system.physmem.perBankRdBursts::11 967960 # Per bank write bursts 78system.physmem.perBankRdBursts::12 967929 # Per bank write bursts 79system.physmem.perBankRdBursts::13 967878 # Per bank write bursts 80system.physmem.perBankRdBursts::14 967953 # Per bank write bursts 81system.physmem.perBankRdBursts::15 967568 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6652 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6388 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6319 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6364 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6622 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6858 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6646 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6573 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7007 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6769 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6571 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6647 # Per bank write bursts 94system.physmem.perBankWrBursts::12 6565 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6381 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6555 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6466 # Per bank write bursts |
| 110system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 111system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 112system.physmem.totGap 2616225486000 # Total gap between requests | 100system.physmem.totGap 2614576987500 # Total gap between requests |
| 113system.physmem.readPktSize::0 0 # Read request sizes (log2) 114system.physmem.readPktSize::1 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 115system.physmem.readPktSize::2 6664 # Read request sizes (log2) 116system.physmem.readPktSize::3 15335424 # Read request sizes (log2) | 103system.physmem.readPktSize::2 6644 # Read request sizes (log2) 104system.physmem.readPktSize::3 15335434 # Read request sizes (log2) |
| 117system.physmem.readPktSize::4 0 # Read request sizes (log2) 118system.physmem.readPktSize::5 0 # Read request sizes (log2) | 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 119system.physmem.readPktSize::6 152614 # Read request sizes (log2) | 107system.physmem.readPktSize::6 152928 # Read request sizes (log2) |
| 120system.physmem.writePktSize::0 0 # Write request sizes (log2) 121system.physmem.writePktSize::1 0 # Write request sizes (log2) 122system.physmem.writePktSize::2 754018 # Write request sizes (log2) 123system.physmem.writePktSize::3 0 # Write request sizes (log2) 124system.physmem.writePktSize::4 0 # Write request sizes (log2) 125system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 126system.physmem.writePktSize::6 57911 # Write request sizes (log2) 127system.physmem.rdQLenPdf::0 1126567 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 970563 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 976518 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1090618 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 986596 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1051326 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 2724005 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 2632042 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 3421723 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 136210 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 113171 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 104737 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 101252 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 19730 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 18895 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 18668 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 86 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 58133 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1126497 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 970808 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 976433 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1092616 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 986699 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1053397 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2722203 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2628336 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3415970 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 138177 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 115073 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 106569 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 103082 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 19658 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 18818 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 18605 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see |
| 144system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 174system.physmem.wrQLenPdf::15 3804 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 3835 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 6081 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 6095 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 6100 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 6096 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 6099 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 6095 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 6098 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 6095 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 6095 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 6095 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 6101 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 6096 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 6095 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 6094 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::32 6094 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::15 3716 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6110 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6121 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6124 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6122 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6122 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6122 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 6123 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6121 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6120 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 6124 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6124 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6121 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6121 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6120 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6121 # What write queue length does an incoming req see |
| 192system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 215system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 180system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 223system.physmem.bytesPerActivate::samples 1027354 # Bytes accessed per row activation 224system.physmem.bytesPerActivate::mean 971.683544 # Bytes accessed per row activation 225system.physmem.bytesPerActivate::gmean 905.447521 # Bytes accessed per row activation 226system.physmem.bytesPerActivate::stdev 204.224200 # Bytes accessed per row activation 227system.physmem.bytesPerActivate::0-127 22943 2.23% 2.23% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::128-255 22460 2.19% 4.42% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::256-383 8461 0.82% 5.24% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::384-511 2563 0.25% 5.49% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::512-639 2504 0.24% 5.74% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::640-767 1783 0.17% 5.91% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::768-895 8706 0.85% 6.76% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::896-1023 969 0.09% 6.85% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::1024-1151 956965 93.15% 100.00% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::total 1027354 # Bytes accessed per row activation 237system.physmem.rdPerTurnAround::samples 6094 # Reads before turning the bus around for writes 238system.physmem.rdPerTurnAround::mean 2542.286675 # Reads before turning the bus around for writes 239system.physmem.rdPerTurnAround::stdev 118884.715097 # Reads before turning the bus around for writes 240system.physmem.rdPerTurnAround::0-524287 6090 99.93% 99.93% # Reads before turning the bus around for writes 241system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes 242system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes | 211system.physmem.bytesPerActivate::samples 1027240 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 971.825895 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 905.842120 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 203.903622 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22776 2.22% 2.22% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 22448 2.19% 4.40% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 8450 0.82% 5.23% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2555 0.25% 5.47% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2575 0.25% 5.72% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1819 0.18% 5.90% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 8664 0.84% 6.74% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 942 0.09% 6.84% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 957011 93.16% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 1027240 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6120 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 2531.539869 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 116318.280129 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 6115 99.92% 99.92% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes |
| 243system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes | 231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 244system.physmem.rdPerTurnAround::total 6094 # Reads before turning the bus around for writes 245system.physmem.wrPerTurnAround::samples 6094 # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::mean 17.255005 # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::gmean 17.227328 # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::stdev 0.967528 # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::16 2261 37.10% 37.10% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::17 29 0.48% 37.58% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::18 3794 62.26% 99.84% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::19 9 0.15% 99.98% # Writes before turning the bus around for reads | 232system.physmem.rdPerTurnAround::total 6120 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6120 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.219444 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.191199 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 0.977796 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 2386 38.99% 38.99% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 19 0.31% 39.30% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 3702 60.49% 99.79% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 12 0.20% 99.98% # Writes before turning the bus around for reads |
| 253system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads | 241system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads |
| 254system.physmem.wrPerTurnAround::total 6094 # Writes before turning the bus around for reads 255system.physmem.totQLat 400062590250 # Total ticks spent queuing 256system.physmem.totMemAccLat 690550846500 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 77463535000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 25822.64 # Average queueing delay per DRAM burst | 242system.physmem.wrPerTurnAround::total 6120 # Writes before turning the bus around for reads 243system.physmem.totQLat 400457727500 # Total ticks spent queuing 244system.physmem.totMemAccLat 690952040000 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 77465150000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 25847.61 # Average queueing delay per DRAM burst |
| 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 260system.physmem.avgMemAccLat 44572.64 # Average memory access latency per DRAM burst 261system.physmem.avgRdBW 378.99 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 50.64 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s | 248system.physmem.avgMemAccLat 44597.61 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 379.24 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s |
| 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 2.98 # Data bus utilization in percentage 267system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 2.98 # Data bus utilization in percentage 255system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads 256system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 269system.physmem.avgRdQLen 6.59 # Average read queue length when enqueuing 270system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing 271system.physmem.readRowHits 14482119 # Number of row buffer hits during reads 272system.physmem.writeRowHits 88386 # Number of row buffer hits during writes | 257system.physmem.avgRdQLen 6.67 # Average read queue length when enqueuing 258system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing 259system.physmem.readRowHits 14482583 # Number of row buffer hits during reads 260system.physmem.writeRowHits 88590 # Number of row buffer hits during writes |
| 273system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads | 261system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads |
| 274system.physmem.writeRowHitRate 84.03 # Row buffer hit rate for writes 275system.physmem.avgGap 160439.36 # Average gap between requests | 262system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes 263system.physmem.avgGap 160333.10 # Average gap between requests |
| 276system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined | 264system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined |
| 277system.physmem.memoryStateTime::IDLE 2245273695250 # Time in different power states 278system.physmem.memoryStateTime::REF 87361560000 # Time in different power states | 265system.physmem.memoryStateTime::IDLE 2239817846000 # Time in different power states 266system.physmem.memoryStateTime::REF 87306440000 # Time in different power states |
| 279system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 267system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 280system.physmem.memoryStateTime::ACT 283591722250 # Time in different power states | 268system.physmem.memoryStateTime::ACT 287452006500 # Time in different power states |
| 281system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 269system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 282system.membus.throughput 54122917 # Throughput (bytes/s) 283system.membus.trans_dist::ReadReq 16546592 # Transaction distribution 284system.membus.trans_dist::ReadResp 16546592 # Transaction distribution 285system.membus.trans_dist::WriteReq 763385 # Transaction distribution 286system.membus.trans_dist::WriteResp 763385 # Transaction distribution 287system.membus.trans_dist::Writeback 57911 # Transaction distribution 288system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution 289system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution 290system.membus.trans_dist::ReadExReq 132219 # Transaction distribution 291system.membus.trans_dist::ReadExResp 132219 # Transaction distribution 292system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383090 # Packet count per connected master and slave (bytes) | 270system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 271system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 272system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 273system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 274system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 275system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 276system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 277system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 278system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 279system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 280system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 281system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 282system.membus.throughput 54170150 # Throughput (bytes/s) 283system.membus.trans_dist::ReadReq 16546653 # Transaction distribution 284system.membus.trans_dist::ReadResp 16546653 # Transaction distribution 285system.membus.trans_dist::WriteReq 763381 # Transaction distribution 286system.membus.trans_dist::WriteResp 763381 # Transaction distribution 287system.membus.trans_dist::Writeback 58133 # Transaction distribution 288system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution 289system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution 290system.membus.trans_dist::ReadExReq 132457 # Transaction distribution 291system.membus.trans_dist::ReadExResp 132457 # Transaction distribution 292system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes) |
| 293system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) | 293system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) |
| 294system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) | 294system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes) |
| 295system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) | 295system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) |
| 296system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893535 # Packet count per connected master and slave (bytes) 297system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280487 # Packet count per connected master and slave (bytes) | 296system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894355 # Packet count per connected master and slave (bytes) 297system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281289 # Packet count per connected master and slave (bytes) |
| 298system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 299system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) | 298system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 299system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) |
| 300system.membus.pkt_count::total 34951335 # Packet count per connected master and slave (bytes) 301system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390546 # Cumulative packet size per connected master and slave (bytes) | 300system.membus.pkt_count::total 34952137 # Packet count per connected master and slave (bytes) 301system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) |
| 302system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) | 302system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) |
| 303system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) | 303system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) |
| 304system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) | 304system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) |
| 305system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516328 # Cumulative packet size per connected master and slave (bytes) 306system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914598 # Cumulative packet size per connected master and slave (bytes) | 305system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16550632 # Cumulative packet size per connected master and slave (bytes) 306system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18948866 # Cumulative packet size per connected master and slave (bytes) |
| 307system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 308system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) | 307system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 308system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) |
| 309system.membus.tot_pkt_size::total 141597990 # Cumulative packet size per connected master and slave (bytes) 310system.membus.data_through_bus 141597990 # Total data (bytes) | 309system.membus.tot_pkt_size::total 141632258 # Cumulative packet size per connected master and slave (bytes) 310system.membus.data_through_bus 141632258 # Total data (bytes) |
| 311system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 311system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 312system.membus.reqLayer0.occupancy 1206224000 # Layer occupancy (ticks) | 312system.membus.reqLayer0.occupancy 1207280500 # Layer occupancy (ticks) |
| 313system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 314system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 315system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 313system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 314system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 315system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 316system.membus.reqLayer2.occupancy 3616500 # Layer occupancy (ticks) | 316system.membus.reqLayer2.occupancy 3534000 # Layer occupancy (ticks) |
| 317system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 318system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 319system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 317system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 318system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 319system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 320system.membus.reqLayer6.occupancy 17911182500 # Layer occupancy (ticks) | 320system.membus.reqLayer6.occupancy 17916889500 # Layer occupancy (ticks) |
| 321system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 321system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 322system.membus.respLayer1.occupancy 4951111812 # Layer occupancy (ticks) | 322system.membus.respLayer1.occupancy 4952195664 # Layer occupancy (ticks) |
| 323system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 323system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 324system.membus.respLayer2.occupancy 37928474750 # Layer occupancy (ticks) 325system.membus.respLayer2.utilization 1.4 # Layer utilization (%) | 324system.membus.respLayer2.occupancy 37921268500 # Layer occupancy (ticks) 325system.membus.respLayer2.utilization 1.5 # Layer utilization (%) |
| 326system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 327system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 328system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 329system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 330system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 331system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 326system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 327system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 328system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 329system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 330system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 331system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 332system.iobus.throughput 47806938 # Throughput (bytes/s) 333system.iobus.trans_dist::ReadReq 16518786 # Transaction distribution 334system.iobus.trans_dist::ReadResp 16518786 # Transaction distribution 335system.iobus.trans_dist::WriteReq 8183 # Transaction distribution 336system.iobus.trans_dist::WriteResp 8183 # Transaction distribution | 332system.iobus.throughput 47837076 # Throughput (bytes/s) 333system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution 334system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution 335system.iobus.trans_dist::WriteReq 8182 # Transaction distribution 336system.iobus.trans_dist::WriteResp 8182 # Transaction distribution |
| 337system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) | 337system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) |
| 338system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) 339system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 340system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) | 338system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) 339system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 532 # Packet count per connected master and slave (bytes) 340system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1040 # Packet count per connected master and slave (bytes) |
| 341system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 342system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 343system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 344system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 345system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 346system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 347system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 349system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 350system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 341system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 342system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 343system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 344system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 345system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 346system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 347system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 349system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 350system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 360system.iobus.pkt_count_system.bridge.master::total 2383090 # Packet count per connected master and slave (bytes) | 360system.iobus.pkt_count_system.bridge.master::total 2383082 # Packet count per connected master and slave (bytes) |
| 361system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) | 361system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) |
| 363system.iobus.pkt_count::total 33053938 # Packet count per connected master and slave (bytes) | 363system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes) |
| 364system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) | 364system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) |
| 365system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) 366system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 367system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) | 365system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) 366system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) 367system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) |
| 368system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 369system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 368system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 369system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 387system.iobus.tot_pkt_size_system.bridge.master::total 2390546 # Cumulative packet size per connected master and slave (bytes) | 387system.iobus.tot_pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) |
| 388system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) | 388system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) |
| 390system.iobus.tot_pkt_size::total 125073938 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.data_through_bus 125073938 # Total data (bytes) | 390system.iobus.tot_pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.data_through_bus 125073922 # Total data (bytes) |
| 392system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 393system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 392system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 393system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 394system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) | 394system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) |
| 395system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 395system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 396system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) | 396system.iobus.reqLayer2.occupancy 532000 # Layer occupancy (ticks) |
| 397system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 397system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 398system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) | 398system.iobus.reqLayer3.occupancy 526000 # Layer occupancy (ticks) |
| 399system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 400system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 401system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 402system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 403system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 404system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 405system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 406system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) --- 25 unchanged lines hidden (view full) --- 432system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 433system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 434system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 435system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 436system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 437system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 438system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 439system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) | 399system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 400system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 401system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 402system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 403system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 404system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 405system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 406system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) --- 25 unchanged lines hidden (view full) --- 432system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 433system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 434system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 435system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 436system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 437system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 438system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 439system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) |
| 440system.iobus.respLayer0.occupancy 2374907000 # Layer occupancy (ticks) | 440system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks) |
| 441system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 441system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 442system.iobus.respLayer1.occupancy 38686102250 # Layer occupancy (ticks) | 442system.iobus.respLayer1.occupancy 38692913500 # Layer occupancy (ticks) |
| 443system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 444system.cpu_clk_domain.clock 500 # Clock period in ticks 445system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 446system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 447system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 448system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 449system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 450system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses --- 9 unchanged lines hidden (view full) --- 460system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 461system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 462system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 463system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 464system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 465system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 466system.cpu.dtb.inst_hits 0 # ITB inst hits 467system.cpu.dtb.inst_misses 0 # ITB inst misses | 443system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 444system.cpu_clk_domain.clock 500 # Clock period in ticks 445system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 446system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 447system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 448system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 449system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 450system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses --- 9 unchanged lines hidden (view full) --- 460system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 461system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 462system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 463system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 464system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 465system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 466system.cpu.dtb.inst_hits 0 # ITB inst hits 467system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 468system.cpu.dtb.read_hits 14996190 # DTB read hits 469system.cpu.dtb.read_misses 7339 # DTB read misses 470system.cpu.dtb.write_hits 11230344 # DTB write hits 471system.cpu.dtb.write_misses 2214 # DTB write misses | 468system.cpu.dtb.read_hits 13160128 # DTB read hits 469system.cpu.dtb.read_misses 7329 # DTB read misses 470system.cpu.dtb.write_hits 11227968 # DTB write hits 471system.cpu.dtb.write_misses 2212 # DTB write misses |
| 472system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 473system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 474system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 475system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 472system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 473system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 474system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 475system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 476system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB | 476system.cpu.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB |
| 477system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 477system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 478system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch | 478system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch |
| 479system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 480system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 479system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 480system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 481system.cpu.dtb.read_accesses 15003529 # DTB read accesses 482system.cpu.dtb.write_accesses 11232558 # DTB write accesses | 481system.cpu.dtb.read_accesses 13167457 # DTB read accesses 482system.cpu.dtb.write_accesses 11230180 # DTB write accesses |
| 483system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 483system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 484system.cpu.dtb.hits 26226534 # DTB hits 485system.cpu.dtb.misses 9553 # DTB misses 486system.cpu.dtb.accesses 26236087 # DTB accesses | 484system.cpu.dtb.hits 24388096 # DTB hits 485system.cpu.dtb.misses 9541 # DTB misses 486system.cpu.dtb.accesses 24397637 # DTB accesses |
| 487system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 488system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 489system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 490system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 491system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 492system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 493system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 494system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 500system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 501system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 502system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 503system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 504system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 505system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 506system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 507system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 487system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 488system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 489system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 490system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 491system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 492system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 493system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 494system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 500system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 501system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 502system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 503system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 504system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 505system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 506system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 507system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 508system.cpu.itb.inst_hits 61493913 # ITB inst hits | 508system.cpu.itb.inst_hits 61480692 # ITB inst hits |
| 509system.cpu.itb.inst_misses 4471 # ITB inst misses 510system.cpu.itb.read_hits 0 # DTB read hits 511system.cpu.itb.read_misses 0 # DTB read misses 512system.cpu.itb.write_hits 0 # DTB write hits 513system.cpu.itb.write_misses 0 # DTB write misses 514system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 515system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 517system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 518system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB 519system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu.itb.read_accesses 0 # DTB read accesses 524system.cpu.itb.write_accesses 0 # DTB write accesses | 509system.cpu.itb.inst_misses 4471 # ITB inst misses 510system.cpu.itb.read_hits 0 # DTB read hits 511system.cpu.itb.read_misses 0 # DTB read misses 512system.cpu.itb.write_hits 0 # DTB write hits 513system.cpu.itb.write_misses 0 # DTB write misses 514system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 515system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 517system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 518system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB 519system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu.itb.read_accesses 0 # DTB read accesses 524system.cpu.itb.write_accesses 0 # DTB write accesses |
| 525system.cpu.itb.inst_accesses 61498384 # ITB inst accesses 526system.cpu.itb.hits 61493913 # DTB hits | 525system.cpu.itb.inst_accesses 61485163 # ITB inst accesses 526system.cpu.itb.hits 61480692 # DTB hits |
| 527system.cpu.itb.misses 4471 # DTB misses | 527system.cpu.itb.misses 4471 # DTB misses |
| 528system.cpu.itb.accesses 61498384 # DTB accesses 529system.cpu.numCycles 5232459694 # number of cpu cycles simulated | 528system.cpu.itb.accesses 61485163 # DTB accesses 529system.cpu.numCycles 5229162505 # number of cpu cycles simulated |
| 530system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 531system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 530system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 531system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 532system.cpu.committedInsts 60200042 # Number of instructions committed 533system.cpu.committedOps 76606857 # Number of ops (including micro ops) committed 534system.cpu.num_int_alu_accesses 69208585 # Number of integer alu accesses | 532system.cpu.committedInsts 60186875 # Number of instructions committed 533system.cpu.committedOps 71883476 # Number of ops (including micro ops) committed 534system.cpu.num_int_alu_accesses 64248071 # Number of integer alu accesses |
| 535system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses | 535system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses |
| 536system.cpu.num_func_calls 2140468 # number of times a function call or return occured 537system.cpu.num_conditional_control_insts 7948679 # number of instructions that are conditional controls 538system.cpu.num_int_insts 69208585 # number of integer instructions | 536system.cpu.num_func_calls 2139776 # number of times a function call or return occured 537system.cpu.num_conditional_control_insts 7549008 # number of instructions that are conditional controls 538system.cpu.num_int_insts 64248071 # number of integer instructions |
| 539system.cpu.num_fp_insts 10269 # number of float instructions | 539system.cpu.num_fp_insts 10269 # number of float instructions |
| 540system.cpu.num_int_register_reads 401368270 # number of times the integer registers were read 541system.cpu.num_int_register_writes 74518872 # number of times the integer registers were written | 540system.cpu.num_int_register_reads 116109819 # number of times the integer registers were read 541system.cpu.num_int_register_writes 42862791 # number of times the integer registers were written |
| 542system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 543system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 542system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 543system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 544system.cpu.num_mem_refs 27394017 # number of memory refs 545system.cpu.num_load_insts 15660224 # Number of load instructions 546system.cpu.num_store_insts 11733793 # Number of store instructions 547system.cpu.num_idle_cycles 4581582300.610249 # Number of idle cycles 548system.cpu.num_busy_cycles 650877393.389751 # Number of busy cycles 549system.cpu.not_idle_fraction 0.124392 # Percentage of non-idle cycles 550system.cpu.idle_fraction 0.875608 # Percentage of idle cycles 551system.cpu.Branches 10308802 # Number of branches fetched | 544system.cpu.num_cc_register_reads 257767219 # number of times the CC registers were read 545system.cpu.num_cc_register_writes 28995131 # number of times the CC registers were written 546system.cpu.num_mem_refs 25244051 # number of memory refs 547system.cpu.num_load_insts 13512687 # Number of load instructions 548system.cpu.num_store_insts 11731364 # Number of store instructions 549system.cpu.num_idle_cycles 4584182254.578246 # Number of idle cycles 550system.cpu.num_busy_cycles 644980250.421753 # Number of busy cycles 551system.cpu.not_idle_fraction 0.123343 # Percentage of non-idle cycles 552system.cpu.idle_fraction 0.876657 # Percentage of idle cycles 553system.cpu.Branches 10306559 # Number of branches fetched |
| 552system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction | 554system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction |
| 553system.cpu.op_class::IntAlu 50389316 64.68% 64.72% # Class of executed instruction 554system.cpu.op_class::IntMult 87585 0.11% 64.83% # Class of executed instruction 555system.cpu.op_class::IntDiv 0 0.00% 64.83% # Class of executed instruction 556system.cpu.op_class::FloatAdd 0 0.00% 64.83% # Class of executed instruction 557system.cpu.op_class::FloatCmp 0 0.00% 64.83% # Class of executed instruction 558system.cpu.op_class::FloatCvt 0 0.00% 64.83% # Class of executed instruction 559system.cpu.op_class::FloatMult 0 0.00% 64.83% # Class of executed instruction 560system.cpu.op_class::FloatDiv 0 0.00% 64.83% # Class of executed instruction 561system.cpu.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction 562system.cpu.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction 563system.cpu.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction 564system.cpu.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction 565system.cpu.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction 566system.cpu.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction 567system.cpu.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction 568system.cpu.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction 569system.cpu.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction 570system.cpu.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction 571system.cpu.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction 572system.cpu.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction 573system.cpu.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction 574system.cpu.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction 575system.cpu.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction 576system.cpu.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction 577system.cpu.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction 578system.cpu.op_class::SimdFloatMisc 2109 0.00% 64.84% # Class of executed instruction 579system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction 580system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction 581system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction 582system.cpu.op_class::MemRead 15660224 20.10% 84.94% # Class of executed instruction 583system.cpu.op_class::MemWrite 11733793 15.06% 100.00% # Class of executed instruction | 555system.cpu.op_class::IntAlu 47576706 65.23% 65.27% # Class of executed instruction 556system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction 557system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction 558system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction 559system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction 560system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction 561system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction 562system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction 563system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction 564system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction 565system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction 566system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction 567system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction 568system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction 569system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction 570system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction 571system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction 572system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction 573system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction 574system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction 575system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction 576system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction 577system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction 578system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction 579system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction 580system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Class of executed instruction 581system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction 582system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction 583system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction 584system.cpu.op_class::MemRead 13512687 18.53% 83.92% # Class of executed instruction 585system.cpu.op_class::MemWrite 11731364 16.08% 100.00% # Class of executed instruction |
| 584system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 585system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 586system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 587system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 586system.cpu.op_class::total 77901545 # Class of executed instruction | 588system.cpu.op_class::total 72938935 # Class of executed instruction |
| 587system.cpu.kern.inst.arm 0 # number of arm instructions executed | 589system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 588system.cpu.kern.inst.quiesce 83017 # number of quiesce instructions executed 589system.cpu.icache.tags.replacements 856351 # number of replacements 590system.cpu.icache.tags.tagsinuse 510.866135 # Cycle average of tags in use 591system.cpu.icache.tags.total_refs 60637050 # Total number of references to valid blocks. 592system.cpu.icache.tags.sampled_refs 856863 # Sample count of references to valid blocks. 593system.cpu.icache.tags.avg_refs 70.766330 # Average number of references to valid blocks. 594system.cpu.icache.tags.warmup_cycle 20005377250 # Cycle when the warmup percentage was hit. 595system.cpu.icache.tags.occ_blocks::cpu.inst 510.866135 # Average occupied blocks per requestor 596system.cpu.icache.tags.occ_percent::cpu.inst 0.997785 # Average percentage of cache occupancy 597system.cpu.icache.tags.occ_percent::total 0.997785 # Average percentage of cache occupancy | 590system.cpu.kern.inst.quiesce 83001 # number of quiesce instructions executed 591system.cpu.icache.tags.replacements 855859 # number of replacements 592system.cpu.icache.tags.tagsinuse 510.877209 # Cycle average of tags in use 593system.cpu.icache.tags.total_refs 60624321 # Total number of references to valid blocks. 594system.cpu.icache.tags.sampled_refs 856371 # Sample count of references to valid blocks. 595system.cpu.icache.tags.avg_refs 70.792123 # Average number of references to valid blocks. 596system.cpu.icache.tags.warmup_cycle 19627747250 # Cycle when the warmup percentage was hit. 597system.cpu.icache.tags.occ_blocks::cpu.inst 510.877209 # Average occupied blocks per requestor 598system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy 599system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy |
| 598system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 600system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 599system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 600system.cpu.icache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id 601system.cpu.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id | 601system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 603system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id 604system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id |
| 603system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 605system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 604system.cpu.icache.tags.tag_accesses 62350776 # Number of tag accesses 605system.cpu.icache.tags.data_accesses 62350776 # Number of data accesses 606system.cpu.icache.ReadReq_hits::cpu.inst 60637050 # number of ReadReq hits 607system.cpu.icache.ReadReq_hits::total 60637050 # number of ReadReq hits 608system.cpu.icache.demand_hits::cpu.inst 60637050 # number of demand (read+write) hits 609system.cpu.icache.demand_hits::total 60637050 # number of demand (read+write) hits 610system.cpu.icache.overall_hits::cpu.inst 60637050 # number of overall hits 611system.cpu.icache.overall_hits::total 60637050 # number of overall hits 612system.cpu.icache.ReadReq_misses::cpu.inst 856863 # number of ReadReq misses 613system.cpu.icache.ReadReq_misses::total 856863 # number of ReadReq misses 614system.cpu.icache.demand_misses::cpu.inst 856863 # number of demand (read+write) misses 615system.cpu.icache.demand_misses::total 856863 # number of demand (read+write) misses 616system.cpu.icache.overall_misses::cpu.inst 856863 # number of overall misses 617system.cpu.icache.overall_misses::total 856863 # number of overall misses 618system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766560750 # number of ReadReq miss cycles 619system.cpu.icache.ReadReq_miss_latency::total 11766560750 # number of ReadReq miss cycles 620system.cpu.icache.demand_miss_latency::cpu.inst 11766560750 # number of demand (read+write) miss cycles 621system.cpu.icache.demand_miss_latency::total 11766560750 # number of demand (read+write) miss cycles 622system.cpu.icache.overall_miss_latency::cpu.inst 11766560750 # number of overall miss cycles 623system.cpu.icache.overall_miss_latency::total 11766560750 # number of overall miss cycles 624system.cpu.icache.ReadReq_accesses::cpu.inst 61493913 # number of ReadReq accesses(hits+misses) 625system.cpu.icache.ReadReq_accesses::total 61493913 # number of ReadReq accesses(hits+misses) 626system.cpu.icache.demand_accesses::cpu.inst 61493913 # number of demand (read+write) accesses 627system.cpu.icache.demand_accesses::total 61493913 # number of demand (read+write) accesses 628system.cpu.icache.overall_accesses::cpu.inst 61493913 # number of overall (read+write) accesses 629system.cpu.icache.overall_accesses::total 61493913 # number of overall (read+write) accesses 630system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses 631system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses 632system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses 633system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses 634system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses 635system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses 636system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751 # average ReadReq miss latency 637system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751 # average ReadReq miss latency 638system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency 639system.cpu.icache.demand_avg_miss_latency::total 13732.137751 # average overall miss latency 640system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency 641system.cpu.icache.overall_avg_miss_latency::total 13732.137751 # average overall miss latency | 606system.cpu.icache.tags.tag_accesses 62337063 # Number of tag accesses 607system.cpu.icache.tags.data_accesses 62337063 # Number of data accesses 608system.cpu.icache.ReadReq_hits::cpu.inst 60624321 # number of ReadReq hits 609system.cpu.icache.ReadReq_hits::total 60624321 # number of ReadReq hits 610system.cpu.icache.demand_hits::cpu.inst 60624321 # number of demand (read+write) hits 611system.cpu.icache.demand_hits::total 60624321 # number of demand (read+write) hits 612system.cpu.icache.overall_hits::cpu.inst 60624321 # number of overall hits 613system.cpu.icache.overall_hits::total 60624321 # number of overall hits 614system.cpu.icache.ReadReq_misses::cpu.inst 856371 # number of ReadReq misses 615system.cpu.icache.ReadReq_misses::total 856371 # number of ReadReq misses 616system.cpu.icache.demand_misses::cpu.inst 856371 # number of demand (read+write) misses 617system.cpu.icache.demand_misses::total 856371 # number of demand (read+write) misses 618system.cpu.icache.overall_misses::cpu.inst 856371 # number of overall misses 619system.cpu.icache.overall_misses::total 856371 # number of overall misses 620system.cpu.icache.ReadReq_miss_latency::cpu.inst 11763954000 # number of ReadReq miss cycles 621system.cpu.icache.ReadReq_miss_latency::total 11763954000 # number of ReadReq miss cycles 622system.cpu.icache.demand_miss_latency::cpu.inst 11763954000 # number of demand (read+write) miss cycles 623system.cpu.icache.demand_miss_latency::total 11763954000 # number of demand (read+write) miss cycles 624system.cpu.icache.overall_miss_latency::cpu.inst 11763954000 # number of overall miss cycles 625system.cpu.icache.overall_miss_latency::total 11763954000 # number of overall miss cycles 626system.cpu.icache.ReadReq_accesses::cpu.inst 61480692 # number of ReadReq accesses(hits+misses) 627system.cpu.icache.ReadReq_accesses::total 61480692 # number of ReadReq accesses(hits+misses) 628system.cpu.icache.demand_accesses::cpu.inst 61480692 # number of demand (read+write) accesses 629system.cpu.icache.demand_accesses::total 61480692 # number of demand (read+write) accesses 630system.cpu.icache.overall_accesses::cpu.inst 61480692 # number of overall (read+write) accesses 631system.cpu.icache.overall_accesses::total 61480692 # number of overall (read+write) accesses 632system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013929 # miss rate for ReadReq accesses 633system.cpu.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses 634system.cpu.icache.demand_miss_rate::cpu.inst 0.013929 # miss rate for demand accesses 635system.cpu.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses 636system.cpu.icache.overall_miss_rate::cpu.inst 0.013929 # miss rate for overall accesses 637system.cpu.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses 638system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13736.983153 # average ReadReq miss latency 639system.cpu.icache.ReadReq_avg_miss_latency::total 13736.983153 # average ReadReq miss latency 640system.cpu.icache.demand_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency 641system.cpu.icache.demand_avg_miss_latency::total 13736.983153 # average overall miss latency 642system.cpu.icache.overall_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency 643system.cpu.icache.overall_avg_miss_latency::total 13736.983153 # average overall miss latency |
| 642system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 643system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 647system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.icache.fast_writes 0 # number of fast writes performed 649system.cpu.icache.cache_copies 0 # number of cache copies performed | 644system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.icache.fast_writes 0 # number of fast writes performed 651system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 650system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856863 # number of ReadReq MSHR misses 651system.cpu.icache.ReadReq_mshr_misses::total 856863 # number of ReadReq MSHR misses 652system.cpu.icache.demand_mshr_misses::cpu.inst 856863 # number of demand (read+write) MSHR misses 653system.cpu.icache.demand_mshr_misses::total 856863 # number of demand (read+write) MSHR misses 654system.cpu.icache.overall_mshr_misses::cpu.inst 856863 # number of overall MSHR misses 655system.cpu.icache.overall_mshr_misses::total 856863 # number of overall MSHR misses 656system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10048829250 # number of ReadReq MSHR miss cycles 657system.cpu.icache.ReadReq_mshr_miss_latency::total 10048829250 # number of ReadReq MSHR miss cycles 658system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10048829250 # number of demand (read+write) MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::total 10048829250 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10048829250 # number of overall MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::total 10048829250 # number of overall MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 441046000 # number of ReadReq MSHR uncacheable cycles 663system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 441046000 # number of ReadReq MSHR uncacheable cycles 664system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 441046000 # number of overall MSHR uncacheable cycles 665system.cpu.icache.overall_mshr_uncacheable_latency::total 441046000 # number of overall MSHR uncacheable cycles 666system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for ReadReq accesses 667system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013934 # mshr miss rate for ReadReq accesses 668system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for demand accesses 669system.cpu.icache.demand_mshr_miss_rate::total 0.013934 # mshr miss rate for demand accesses 670system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for overall accesses 671system.cpu.icache.overall_mshr_miss_rate::total 0.013934 # mshr miss rate for overall accesses 672system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11727.463142 # average ReadReq mshr miss latency 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11727.463142 # average ReadReq mshr miss latency 674system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency 676system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency | 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856371 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 856371 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 856371 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 856371 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 856371 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 856371 # number of overall MSHR misses 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10047194000 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 10047194000 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10047194000 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 10047194000 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10047194000 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 10047194000 # number of overall MSHR miss cycles 664system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 440846250 # number of ReadReq MSHR uncacheable cycles 665system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles 666system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 440846250 # number of overall MSHR uncacheable cycles 667system.cpu.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles 668system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for ReadReq accesses 669system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses 670system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for demand accesses 671system.cpu.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses 672system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for overall accesses 673system.cpu.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11732.291262 # average ReadReq mshr miss latency 675system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11732.291262 # average ReadReq mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11732.291262 # average overall mshr miss latency 677system.cpu.icache.demand_avg_mshr_miss_latency::total 11732.291262 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11732.291262 # average overall mshr miss latency 679system.cpu.icache.overall_avg_mshr_miss_latency::total 11732.291262 # average overall mshr miss latency |
| 678system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 679system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 680system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 681system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 682system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 680system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 681system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 682system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 683system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 684system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 683system.cpu.l2cache.tags.replacements 62506 # number of replacements 684system.cpu.l2cache.tags.tagsinuse 50753.322403 # Cycle average of tags in use 685system.cpu.l2cache.tags.total_refs 1682121 # Total number of references to valid blocks. 686system.cpu.l2cache.tags.sampled_refs 127886 # Sample count of references to valid blocks. 687system.cpu.l2cache.tags.avg_refs 13.153285 # Average number of references to valid blocks. 688system.cpu.l2cache.tags.warmup_cycle 2565374310000 # Cycle when the warmup percentage was hit. 689system.cpu.l2cache.tags.occ_blocks::writebacks 37717.253716 # Average occupied blocks per requestor 690system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884318 # Average occupied blocks per requestor 691system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor 692system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.225103 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.958564 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_percent::writebacks 0.575520 # Average percentage of cache occupancy | 685system.cpu.l2cache.tags.replacements 62821 # number of replacements 686system.cpu.l2cache.tags.tagsinuse 50750.711022 # Cycle average of tags in use 687system.cpu.l2cache.tags.total_refs 1678966 # Total number of references to valid blocks. 688system.cpu.l2cache.tags.sampled_refs 128205 # Sample count of references to valid blocks. 689system.cpu.l2cache.tags.avg_refs 13.095948 # Average number of references to valid blocks. 690system.cpu.l2cache.tags.warmup_cycle 2564782857000 # Cycle when the warmup percentage was hit. 691system.cpu.l2cache.tags.occ_blocks::writebacks 37685.579713 # Average occupied blocks per requestor 692system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884636 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000702 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_blocks::cpu.inst 6996.394812 # Average occupied blocks per requestor 695system.cpu.l2cache.tags.occ_blocks::cpu.data 6064.851159 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_percent::writebacks 0.575036 # Average percentage of cache occupancy |
| 695system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 696system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 697system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 697system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106708 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::total 0.774434 # Average percentage of cache occupancy | 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106757 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.092542 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.774394 # Average percentage of cache occupancy |
| 700system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id | 702system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id |
| 701system.cpu.l2cache.tags.occ_task_id_blocks::1024 65376 # Occupied blocks per task id | 703system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id |
| 702system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id | 704system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id |
| 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2163 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6647 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56517 # Occupied blocks per task id | 705system.cpu.l2cache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id 708system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7024 # Occupied blocks per task id 709system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56164 # Occupied blocks per task id |
| 708system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id | 710system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id |
| 709system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997559 # Percentage of cache occupancy per task id 710system.cpu.l2cache.tags.tag_accesses 17140869 # Number of tag accesses 711system.cpu.l2cache.tags.data_accesses 17140869 # Number of data accesses 712system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8713 # number of ReadReq hits 713system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3537 # number of ReadReq hits 714system.cpu.l2cache.ReadReq_hits::cpu.inst 844650 # number of ReadReq hits 715system.cpu.l2cache.ReadReq_hits::cpu.data 369794 # number of ReadReq hits 716system.cpu.l2cache.ReadReq_hits::total 1226694 # number of ReadReq hits 717system.cpu.l2cache.Writeback_hits::writebacks 595396 # number of Writeback hits 718system.cpu.l2cache.Writeback_hits::total 595396 # number of Writeback hits | 711system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id 712system.cpu.l2cache.tags.tag_accesses 17117724 # Number of tag accesses 713system.cpu.l2cache.tags.data_accesses 17117724 # Number of data accesses 714system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7538 # number of ReadReq hits 715system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3113 # number of ReadReq hits 716system.cpu.l2cache.ReadReq_hits::cpu.inst 844162 # number of ReadReq hits 717system.cpu.l2cache.ReadReq_hits::cpu.data 368945 # number of ReadReq hits 718system.cpu.l2cache.ReadReq_hits::total 1223758 # number of ReadReq hits 719system.cpu.l2cache.Writeback_hits::writebacks 594981 # number of Writeback hits 720system.cpu.l2cache.Writeback_hits::total 594981 # number of Writeback hits |
| 719system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 720system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits | 721system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 722system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits |
| 721system.cpu.l2cache.ReadExReq_hits::cpu.data 113396 # number of ReadExReq hits 722system.cpu.l2cache.ReadExReq_hits::total 113396 # number of ReadExReq hits 723system.cpu.l2cache.demand_hits::cpu.dtb.walker 8713 # number of demand (read+write) hits 724system.cpu.l2cache.demand_hits::cpu.itb.walker 3537 # number of demand (read+write) hits 725system.cpu.l2cache.demand_hits::cpu.inst 844650 # number of demand (read+write) hits 726system.cpu.l2cache.demand_hits::cpu.data 483190 # number of demand (read+write) hits 727system.cpu.l2cache.demand_hits::total 1340090 # number of demand (read+write) hits 728system.cpu.l2cache.overall_hits::cpu.dtb.walker 8713 # number of overall hits 729system.cpu.l2cache.overall_hits::cpu.itb.walker 3537 # number of overall hits 730system.cpu.l2cache.overall_hits::cpu.inst 844650 # number of overall hits 731system.cpu.l2cache.overall_hits::cpu.data 483190 # number of overall hits 732system.cpu.l2cache.overall_hits::total 1340090 # number of overall hits | 723system.cpu.l2cache.ReadExReq_hits::cpu.data 113467 # number of ReadExReq hits 724system.cpu.l2cache.ReadExReq_hits::total 113467 # number of ReadExReq hits 725system.cpu.l2cache.demand_hits::cpu.dtb.walker 7538 # number of demand (read+write) hits 726system.cpu.l2cache.demand_hits::cpu.itb.walker 3113 # number of demand (read+write) hits 727system.cpu.l2cache.demand_hits::cpu.inst 844162 # number of demand (read+write) hits 728system.cpu.l2cache.demand_hits::cpu.data 482412 # number of demand (read+write) hits 729system.cpu.l2cache.demand_hits::total 1337225 # number of demand (read+write) hits 730system.cpu.l2cache.overall_hits::cpu.dtb.walker 7538 # number of overall hits 731system.cpu.l2cache.overall_hits::cpu.itb.walker 3113 # number of overall hits 732system.cpu.l2cache.overall_hits::cpu.inst 844162 # number of overall hits 733system.cpu.l2cache.overall_hits::cpu.data 482412 # number of overall hits 734system.cpu.l2cache.overall_hits::total 1337225 # number of overall hits |
| 733system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 734system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 735system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 736system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 735system.cpu.l2cache.ReadReq_misses::cpu.inst 10579 # number of ReadReq misses 736system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses 737system.cpu.l2cache.ReadReq_misses::total 20395 # number of ReadReq misses 738system.cpu.l2cache.UpgradeReq_misses::cpu.data 2902 # number of UpgradeReq misses 739system.cpu.l2cache.UpgradeReq_misses::total 2902 # number of UpgradeReq misses 740system.cpu.l2cache.ReadExReq_misses::cpu.data 133833 # number of ReadExReq misses 741system.cpu.l2cache.ReadExReq_misses::total 133833 # number of ReadExReq misses | 737system.cpu.l2cache.ReadReq_misses::cpu.inst 10594 # number of ReadReq misses 738system.cpu.l2cache.ReadReq_misses::cpu.data 9870 # number of ReadReq misses 739system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses 740system.cpu.l2cache.UpgradeReq_misses::cpu.data 2896 # number of UpgradeReq misses 741system.cpu.l2cache.UpgradeReq_misses::total 2896 # number of UpgradeReq misses 742system.cpu.l2cache.ReadExReq_misses::cpu.data 134072 # number of ReadExReq misses 743system.cpu.l2cache.ReadExReq_misses::total 134072 # number of ReadExReq misses |
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| 747system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 748system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 749system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 750system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 749system.cpu.l2cache.overall_misses::cpu.inst 10579 # number of overall misses 750system.cpu.l2cache.overall_misses::cpu.data 143642 # number of overall misses 751system.cpu.l2cache.overall_misses::total 154228 # number of overall misses | 751system.cpu.l2cache.overall_misses::cpu.inst 10594 # number of overall misses 752system.cpu.l2cache.overall_misses::cpu.data 143942 # number of overall misses 753system.cpu.l2cache.overall_misses::total 154543 # number of overall misses |
| 752system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles 753system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles | 754system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles 755system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles |
| 754system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 743832250 # number of ReadReq miss cycles 755system.cpu.l2cache.ReadReq_miss_latency::cpu.data 729584000 # number of ReadReq miss cycles 756system.cpu.l2cache.ReadReq_miss_latency::total 1473871500 # number of ReadReq miss cycles 757system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles 758system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles 759system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9271605886 # number of ReadExReq miss cycles 760system.cpu.l2cache.ReadExReq_miss_latency::total 9271605886 # number of ReadExReq miss cycles | 756system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747419500 # number of ReadReq miss cycles 757system.cpu.l2cache.ReadReq_miss_latency::cpu.data 738260250 # number of ReadReq miss cycles 758system.cpu.l2cache.ReadReq_miss_latency::total 1486135000 # number of ReadReq miss cycles 759system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 352485 # number of UpgradeReq miss cycles 760system.cpu.l2cache.UpgradeReq_miss_latency::total 352485 # number of UpgradeReq miss cycles 761system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9313218885 # number of ReadExReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::total 9313218885 # number of ReadExReq miss cycles |
| 761system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles 762system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles | 763system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles |
| 763system.cpu.l2cache.demand_miss_latency::cpu.inst 743832250 # number of demand (read+write) miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.data 10001189886 # number of demand (read+write) miss cycles 765system.cpu.l2cache.demand_miss_latency::total 10745477386 # number of demand (read+write) miss cycles | 765system.cpu.l2cache.demand_miss_latency::cpu.inst 747419500 # number of demand (read+write) miss cycles 766system.cpu.l2cache.demand_miss_latency::cpu.data 10051479135 # number of demand (read+write) miss cycles 767system.cpu.l2cache.demand_miss_latency::total 10799353885 # number of demand (read+write) miss cycles |
| 766system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles 767system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles | 768system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles |
| 768system.cpu.l2cache.overall_miss_latency::cpu.inst 743832250 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.data 10001189886 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::total 10745477386 # number of overall miss cycles 771system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8718 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3539 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.ReadReq_accesses::cpu.inst 855229 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.ReadReq_accesses::cpu.data 379603 # number of ReadReq accesses(hits+misses) 775system.cpu.l2cache.ReadReq_accesses::total 1247089 # number of ReadReq accesses(hits+misses) 776system.cpu.l2cache.Writeback_accesses::writebacks 595396 # number of Writeback accesses(hits+misses) 777system.cpu.l2cache.Writeback_accesses::total 595396 # number of Writeback accesses(hits+misses) 778system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2928 # number of UpgradeReq accesses(hits+misses) 779system.cpu.l2cache.UpgradeReq_accesses::total 2928 # number of UpgradeReq accesses(hits+misses) 780system.cpu.l2cache.ReadExReq_accesses::cpu.data 247229 # number of ReadExReq accesses(hits+misses) 781system.cpu.l2cache.ReadExReq_accesses::total 247229 # number of ReadExReq accesses(hits+misses) 782system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8718 # number of demand (read+write) accesses 783system.cpu.l2cache.demand_accesses::cpu.itb.walker 3539 # number of demand (read+write) accesses 784system.cpu.l2cache.demand_accesses::cpu.inst 855229 # number of demand (read+write) accesses 785system.cpu.l2cache.demand_accesses::cpu.data 626832 # number of demand (read+write) accesses 786system.cpu.l2cache.demand_accesses::total 1494318 # number of demand (read+write) accesses 787system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8718 # number of overall (read+write) accesses 788system.cpu.l2cache.overall_accesses::cpu.itb.walker 3539 # number of overall (read+write) accesses 789system.cpu.l2cache.overall_accesses::cpu.inst 855229 # number of overall (read+write) accesses 790system.cpu.l2cache.overall_accesses::cpu.data 626832 # number of overall (read+write) accesses 791system.cpu.l2cache.overall_accesses::total 1494318 # number of overall (read+write) accesses 792system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses 793system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses 794system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012370 # miss rate for ReadReq accesses 795system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025840 # miss rate for ReadReq accesses 796system.cpu.l2cache.ReadReq_miss_rate::total 0.016354 # miss rate for ReadReq accesses 797system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991120 # miss rate for UpgradeReq accesses 798system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991120 # miss rate for UpgradeReq accesses 799system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541332 # miss rate for ReadExReq accesses 800system.cpu.l2cache.ReadExReq_miss_rate::total 0.541332 # miss rate for ReadExReq accesses 801system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses 802system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses 803system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012370 # miss rate for demand accesses 804system.cpu.l2cache.demand_miss_rate::cpu.data 0.229155 # miss rate for demand accesses 805system.cpu.l2cache.demand_miss_rate::total 0.103210 # miss rate for demand accesses 806system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses 807system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses 808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012370 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.data 0.229155 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::total 0.103210 # miss rate for overall accesses | 770system.cpu.l2cache.overall_miss_latency::cpu.inst 747419500 # number of overall miss cycles 771system.cpu.l2cache.overall_miss_latency::cpu.data 10051479135 # number of overall miss cycles 772system.cpu.l2cache.overall_miss_latency::total 10799353885 # number of overall miss cycles 773system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7543 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3115 # number of ReadReq accesses(hits+misses) 775system.cpu.l2cache.ReadReq_accesses::cpu.inst 854756 # number of ReadReq accesses(hits+misses) 776system.cpu.l2cache.ReadReq_accesses::cpu.data 378815 # number of ReadReq accesses(hits+misses) 777system.cpu.l2cache.ReadReq_accesses::total 1244229 # number of ReadReq accesses(hits+misses) 778system.cpu.l2cache.Writeback_accesses::writebacks 594981 # number of Writeback accesses(hits+misses) 779system.cpu.l2cache.Writeback_accesses::total 594981 # number of Writeback accesses(hits+misses) 780system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2922 # number of UpgradeReq accesses(hits+misses) 781system.cpu.l2cache.UpgradeReq_accesses::total 2922 # number of UpgradeReq accesses(hits+misses) 782system.cpu.l2cache.ReadExReq_accesses::cpu.data 247539 # number of ReadExReq accesses(hits+misses) 783system.cpu.l2cache.ReadExReq_accesses::total 247539 # number of ReadExReq accesses(hits+misses) 784system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7543 # number of demand (read+write) accesses 785system.cpu.l2cache.demand_accesses::cpu.itb.walker 3115 # number of demand (read+write) accesses 786system.cpu.l2cache.demand_accesses::cpu.inst 854756 # number of demand (read+write) accesses 787system.cpu.l2cache.demand_accesses::cpu.data 626354 # number of demand (read+write) accesses 788system.cpu.l2cache.demand_accesses::total 1491768 # number of demand (read+write) accesses 789system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7543 # number of overall (read+write) accesses 790system.cpu.l2cache.overall_accesses::cpu.itb.walker 3115 # number of overall (read+write) accesses 791system.cpu.l2cache.overall_accesses::cpu.inst 854756 # number of overall (read+write) accesses 792system.cpu.l2cache.overall_accesses::cpu.data 626354 # number of overall (read+write) accesses 793system.cpu.l2cache.overall_accesses::total 1491768 # number of overall (read+write) accesses 794system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses 795system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000642 # miss rate for ReadReq accesses 796system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012394 # miss rate for ReadReq accesses 797system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026055 # miss rate for ReadReq accesses 798system.cpu.l2cache.ReadReq_miss_rate::total 0.016453 # miss rate for ReadReq accesses 799system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991102 # miss rate for UpgradeReq accesses 800system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991102 # miss rate for UpgradeReq accesses 801system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541620 # miss rate for ReadExReq accesses 802system.cpu.l2cache.ReadExReq_miss_rate::total 0.541620 # miss rate for ReadExReq accesses 803system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses 804system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000642 # miss rate for demand accesses 805system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012394 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::cpu.data 0.229809 # miss rate for demand accesses 807system.cpu.l2cache.demand_miss_rate::total 0.103597 # miss rate for demand accesses 808system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000642 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012394 # miss rate for overall accesses 811system.cpu.l2cache.overall_miss_rate::cpu.data 0.229809 # miss rate for overall accesses 812system.cpu.l2cache.overall_miss_rate::total 0.103597 # miss rate for overall accesses |
| 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency 812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency | 813system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency 814system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency |
| 813system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70312.151432 # average ReadReq miss latency 814system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74379.039657 # average ReadReq miss latency 815system.cpu.l2cache.ReadReq_avg_miss_latency::total 72266.315273 # average ReadReq miss latency 816system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.950379 # average UpgradeReq miss latency 817system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.950379 # average UpgradeReq miss latency 818system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69277.426987 # average ReadExReq miss latency 819system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69277.426987 # average ReadExReq miss latency | 815system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70551.208231 # average ReadReq miss latency 816system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74798.404255 # average ReadReq miss latency 817system.cpu.l2cache.ReadReq_avg_miss_latency::total 72597.088564 # average ReadReq miss latency 818system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 121.714434 # average UpgradeReq miss latency 819system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 121.714434 # average UpgradeReq miss latency 820system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69464.309364 # average ReadExReq miss latency 821system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69464.309364 # average ReadExReq miss latency |
| 820system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 821system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency | 822system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 823system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency |
| 822system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency 823system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency 824system.cpu.l2cache.demand_avg_miss_latency::total 69672.675429 # average overall miss latency | 824system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70551.208231 # average overall miss latency 825system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69830.064436 # average overall miss latency 826system.cpu.l2cache.demand_avg_miss_latency::total 69879.282044 # average overall miss latency |
| 825system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 826system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency | 827system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 828system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency |
| 827system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency 828system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency 829system.cpu.l2cache.overall_avg_miss_latency::total 69672.675429 # average overall miss latency | 829system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70551.208231 # average overall miss latency 830system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69830.064436 # average overall miss latency 831system.cpu.l2cache.overall_avg_miss_latency::total 69879.282044 # average overall miss latency |
| 830system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 831system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 832system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 833system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 834system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 835system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 836system.cpu.l2cache.fast_writes 0 # number of fast writes performed 837system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 832system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 833system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 834system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 835system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 836system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 837system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 838system.cpu.l2cache.fast_writes 0 # number of fast writes performed 839system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 838system.cpu.l2cache.writebacks::writebacks 57911 # number of writebacks 839system.cpu.l2cache.writebacks::total 57911 # number of writebacks | 840system.cpu.l2cache.writebacks::writebacks 58133 # number of writebacks 841system.cpu.l2cache.writebacks::total 58133 # number of writebacks |
| 840system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 841system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 842system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 843system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 842system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10579 # number of ReadReq MSHR misses 843system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses 844system.cpu.l2cache.ReadReq_mshr_misses::total 20395 # number of ReadReq MSHR misses 845system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2902 # number of UpgradeReq MSHR misses 846system.cpu.l2cache.UpgradeReq_mshr_misses::total 2902 # number of UpgradeReq MSHR misses 847system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133833 # number of ReadExReq MSHR misses 848system.cpu.l2cache.ReadExReq_mshr_misses::total 133833 # number of ReadExReq MSHR misses | 844system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10594 # number of ReadReq MSHR misses 845system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9870 # number of ReadReq MSHR misses 846system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses 847system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2896 # number of UpgradeReq MSHR misses 848system.cpu.l2cache.UpgradeReq_mshr_misses::total 2896 # number of UpgradeReq MSHR misses 849system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134072 # number of ReadExReq MSHR misses 850system.cpu.l2cache.ReadExReq_mshr_misses::total 134072 # number of ReadExReq MSHR misses |
| 849system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 851system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 852system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 851system.cpu.l2cache.demand_mshr_misses::cpu.inst 10579 # number of demand (read+write) MSHR misses 852system.cpu.l2cache.demand_mshr_misses::cpu.data 143642 # number of demand (read+write) MSHR misses 853system.cpu.l2cache.demand_mshr_misses::total 154228 # number of demand (read+write) MSHR misses | 853system.cpu.l2cache.demand_mshr_misses::cpu.inst 10594 # number of demand (read+write) MSHR misses 854system.cpu.l2cache.demand_mshr_misses::cpu.data 143942 # number of demand (read+write) MSHR misses 855system.cpu.l2cache.demand_mshr_misses::total 154543 # number of demand (read+write) MSHR misses |
| 854system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 855system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 856system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 857system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 856system.cpu.l2cache.overall_mshr_misses::cpu.inst 10579 # number of overall MSHR misses 857system.cpu.l2cache.overall_mshr_misses::cpu.data 143642 # number of overall MSHR misses 858system.cpu.l2cache.overall_mshr_misses::total 154228 # number of overall MSHR misses | 858system.cpu.l2cache.overall_mshr_misses::cpu.inst 10594 # number of overall MSHR misses 859system.cpu.l2cache.overall_mshr_misses::cpu.data 143942 # number of overall MSHR misses 860system.cpu.l2cache.overall_mshr_misses::total 154543 # number of overall MSHR misses |
| 859system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles | 861system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles 862system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles |
| 861system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 611350250 # number of ReadReq MSHR miss cycles 862system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 606711500 # number of ReadReq MSHR miss cycles 863system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1218429500 # number of ReadReq MSHR miss cycles 864system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29025902 # number of UpgradeReq MSHR miss cycles 865system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29025902 # number of UpgradeReq MSHR miss cycles 866system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7597036114 # number of ReadExReq MSHR miss cycles 867system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7597036114 # number of ReadExReq MSHR miss cycles | 863system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 614859500 # number of ReadReq MSHR miss cycles 864system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 614969250 # number of ReadReq MSHR miss cycles 865system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1230196500 # number of ReadReq MSHR miss cycles 866system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28966896 # number of UpgradeReq MSHR miss cycles 867system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28966896 # number of UpgradeReq MSHR miss cycles 868system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7636042115 # number of ReadExReq MSHR miss cycles 869system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7636042115 # number of ReadExReq MSHR miss cycles |
| 868system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles 869system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles | 870system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles 871system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles |
| 870system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611350250 # number of demand (read+write) MSHR miss cycles 871system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8203747614 # number of demand (read+write) MSHR miss cycles 872system.cpu.l2cache.demand_mshr_miss_latency::total 8815465614 # number of demand (read+write) MSHR miss cycles | 872system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 614859500 # number of demand (read+write) MSHR miss cycles 873system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8251011365 # number of demand (read+write) MSHR miss cycles 874system.cpu.l2cache.demand_mshr_miss_latency::total 8866238615 # number of demand (read+write) MSHR miss cycles |
| 873system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles 874system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles | 875system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles 876system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles |
| 875system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611350250 # number of overall MSHR miss cycles 876system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8203747614 # number of overall MSHR miss cycles 877system.cpu.l2cache.overall_mshr_miss_latency::total 8815465614 # number of overall MSHR miss cycles 878system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 349718500 # number of ReadReq MSHR uncacheable cycles 879system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664427750 # number of ReadReq MSHR uncacheable cycles 880system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014146250 # number of ReadReq MSHR uncacheable cycles 881system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706100672 # number of WriteReq MSHR uncacheable cycles 882system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706100672 # number of WriteReq MSHR uncacheable cycles 883system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349718500 # number of overall MSHR uncacheable cycles 884system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370528422 # number of overall MSHR uncacheable cycles 885system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720246922 # number of overall MSHR uncacheable cycles 886system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 887system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025840 # mshr miss rate for ReadReq accesses 890system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016354 # mshr miss rate for ReadReq accesses 891system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991120 # mshr miss rate for UpgradeReq accesses 892system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991120 # mshr miss rate for UpgradeReq accesses 893system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541332 # mshr miss rate for ReadExReq accesses 894system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541332 # mshr miss rate for ReadExReq accesses 895system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses 896system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses 897system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for demand accesses 898system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for demand accesses 899system.cpu.l2cache.demand_mshr_miss_rate::total 0.103210 # mshr miss rate for demand accesses 900system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 901system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses 902system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for overall accesses 903system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for overall accesses 904system.cpu.l2cache.overall_mshr_miss_rate::total 0.103210 # mshr miss rate for overall accesses | 877system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 614859500 # number of overall MSHR miss cycles 878system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8251011365 # number of overall MSHR miss cycles 879system.cpu.l2cache.overall_mshr_miss_latency::total 8866238615 # number of overall MSHR miss cycles 880system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 349507750 # number of ReadReq MSHR uncacheable cycles 881system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664674250 # number of ReadReq MSHR uncacheable cycles 882system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014182000 # number of ReadReq MSHR uncacheable cycles 883system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16705839575 # number of WriteReq MSHR uncacheable cycles 884system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16705839575 # number of WriteReq MSHR uncacheable cycles 885system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349507750 # number of overall MSHR uncacheable cycles 886system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370513825 # number of overall MSHR uncacheable cycles 887system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720021575 # number of overall MSHR uncacheable cycles 888system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for ReadReq accesses 890system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026055 # mshr miss rate for ReadReq accesses 892system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016453 # mshr miss rate for ReadReq accesses 893system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991102 # mshr miss rate for UpgradeReq accesses 894system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991102 # mshr miss rate for UpgradeReq accesses 895system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541620 # mshr miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541620 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for demand accesses 898system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for demand accesses 899system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for demand accesses 900system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229809 # mshr miss rate for demand accesses 901system.cpu.l2cache.demand_mshr_miss_rate::total 0.103597 # mshr miss rate for demand accesses 902system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for overall accesses 903system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for overall accesses 904system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for overall accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229809 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::total 0.103597 # mshr miss rate for overall accesses |
| 905system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency 906system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency | 907system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency 908system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency |
| 907system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57789.039607 # average ReadReq mshr miss latency 908system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61852.533388 # average ReadReq mshr miss latency 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59741.578818 # average ReadReq mshr miss latency 910system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.033770 # average UpgradeReq mshr miss latency 911system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.033770 # average UpgradeReq mshr miss latency 912system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56765.043853 # average ReadExReq mshr miss latency 913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56765.043853 # average ReadExReq mshr miss latency | 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58038.465169 # average ReadReq mshr miss latency 910system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62306.914894 # average ReadReq mshr miss latency 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60094.597235 # average ReadReq mshr miss latency 912system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.381215 # average UpgradeReq mshr miss latency 913system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.381215 # average UpgradeReq mshr miss latency 914system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56954.786346 # average ReadExReq mshr miss latency 915system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56954.786346 # average ReadExReq mshr miss latency |
| 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency | 918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58038.465169 # average overall mshr miss latency 919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57321.777973 # average overall mshr miss latency 920system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57370.690455 # average overall mshr miss latency |
| 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency 923system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency | 923system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58038.465169 # average overall mshr miss latency 924system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57321.777973 # average overall mshr miss latency 925system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57370.690455 # average overall mshr miss latency |
| 924system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 925system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 926system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 927system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 928system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 929system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 930system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 931system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 932system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 926system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 927system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 928system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 929system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 930system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 931system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 932system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 933system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 934system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 933system.cpu.dcache.tags.replacements 626320 # number of replacements 934system.cpu.dcache.tags.tagsinuse 511.875633 # Cycle average of tags in use 935system.cpu.dcache.tags.total_refs 23655948 # Total number of references to valid blocks. 936system.cpu.dcache.tags.sampled_refs 626832 # Sample count of references to valid blocks. 937system.cpu.dcache.tags.avg_refs 37.738897 # Average number of references to valid blocks. 938system.cpu.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. 939system.cpu.dcache.tags.occ_blocks::cpu.data 511.875633 # Average occupied blocks per requestor | 935system.cpu.dcache.tags.replacements 625842 # number of replacements 936system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use 937system.cpu.dcache.tags.total_refs 21786000 # Total number of references to valid blocks. 938system.cpu.dcache.tags.sampled_refs 626354 # Sample count of references to valid blocks. 939system.cpu.dcache.tags.avg_refs 34.782248 # Average number of references to valid blocks. 940system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. 941system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor |
| 940system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy 941system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy 942system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 942system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy 943system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy 944system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 943system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 944system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 945system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id 946system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 945system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 946system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id 947system.cpu.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id |
| 947system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 948system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 948system.cpu.dcache.tags.tag_accesses 97757952 # Number of tag accesses 949system.cpu.dcache.tags.data_accesses 97757952 # Number of data accesses 950system.cpu.dcache.ReadReq_hits::cpu.data 13196101 # number of ReadReq hits 951system.cpu.dcache.ReadReq_hits::total 13196101 # number of ReadReq hits 952system.cpu.dcache.WriteReq_hits::cpu.data 9972757 # number of WriteReq hits 953system.cpu.dcache.WriteReq_hits::total 9972757 # number of WriteReq hits 954system.cpu.dcache.LoadLockedReq_hits::cpu.data 236378 # number of LoadLockedReq hits 955system.cpu.dcache.LoadLockedReq_hits::total 236378 # number of LoadLockedReq hits 956system.cpu.dcache.StoreCondReq_hits::cpu.data 247784 # number of StoreCondReq hits 957system.cpu.dcache.StoreCondReq_hits::total 247784 # number of StoreCondReq hits 958system.cpu.dcache.demand_hits::cpu.data 23168858 # number of demand (read+write) hits 959system.cpu.dcache.demand_hits::total 23168858 # number of demand (read+write) hits 960system.cpu.dcache.overall_hits::cpu.data 23168858 # number of overall hits 961system.cpu.dcache.overall_hits::total 23168858 # number of overall hits 962system.cpu.dcache.ReadReq_misses::cpu.data 368196 # number of ReadReq misses 963system.cpu.dcache.ReadReq_misses::total 368196 # number of ReadReq misses 964system.cpu.dcache.WriteReq_misses::cpu.data 250157 # number of WriteReq misses 965system.cpu.dcache.WriteReq_misses::total 250157 # number of WriteReq misses 966system.cpu.dcache.LoadLockedReq_misses::cpu.data 11407 # number of LoadLockedReq misses 967system.cpu.dcache.LoadLockedReq_misses::total 11407 # number of LoadLockedReq misses 968system.cpu.dcache.demand_misses::cpu.data 618353 # number of demand (read+write) misses 969system.cpu.dcache.demand_misses::total 618353 # number of demand (read+write) misses 970system.cpu.dcache.overall_misses::cpu.data 618353 # number of overall misses 971system.cpu.dcache.overall_misses::total 618353 # number of overall misses 972system.cpu.dcache.ReadReq_miss_latency::cpu.data 5410361250 # number of ReadReq miss cycles 973system.cpu.dcache.ReadReq_miss_latency::total 5410361250 # number of ReadReq miss cycles 974system.cpu.dcache.WriteReq_miss_latency::cpu.data 11271639016 # number of WriteReq miss cycles 975system.cpu.dcache.WriteReq_miss_latency::total 11271639016 # number of WriteReq miss cycles 976system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158326750 # number of LoadLockedReq miss cycles 977system.cpu.dcache.LoadLockedReq_miss_latency::total 158326750 # number of LoadLockedReq miss cycles 978system.cpu.dcache.demand_miss_latency::cpu.data 16682000266 # number of demand (read+write) miss cycles 979system.cpu.dcache.demand_miss_latency::total 16682000266 # number of demand (read+write) miss cycles 980system.cpu.dcache.overall_miss_latency::cpu.data 16682000266 # number of overall miss cycles 981system.cpu.dcache.overall_miss_latency::total 16682000266 # number of overall miss cycles 982system.cpu.dcache.ReadReq_accesses::cpu.data 13564297 # number of ReadReq accesses(hits+misses) 983system.cpu.dcache.ReadReq_accesses::total 13564297 # number of ReadReq accesses(hits+misses) 984system.cpu.dcache.WriteReq_accesses::cpu.data 10222914 # number of WriteReq accesses(hits+misses) 985system.cpu.dcache.WriteReq_accesses::total 10222914 # number of WriteReq accesses(hits+misses) 986system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247785 # number of LoadLockedReq accesses(hits+misses) 987system.cpu.dcache.LoadLockedReq_accesses::total 247785 # number of LoadLockedReq accesses(hits+misses) 988system.cpu.dcache.StoreCondReq_accesses::cpu.data 247784 # number of StoreCondReq accesses(hits+misses) 989system.cpu.dcache.StoreCondReq_accesses::total 247784 # number of StoreCondReq accesses(hits+misses) 990system.cpu.dcache.demand_accesses::cpu.data 23787211 # number of demand (read+write) accesses 991system.cpu.dcache.demand_accesses::total 23787211 # number of demand (read+write) accesses 992system.cpu.dcache.overall_accesses::cpu.data 23787211 # number of overall (read+write) accesses 993system.cpu.dcache.overall_accesses::total 23787211 # number of overall (read+write) accesses 994system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027144 # miss rate for ReadReq accesses 995system.cpu.dcache.ReadReq_miss_rate::total 0.027144 # miss rate for ReadReq accesses 996system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses 997system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses 998system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046036 # miss rate for LoadLockedReq accesses 999system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046036 # miss rate for LoadLockedReq accesses 1000system.cpu.dcache.demand_miss_rate::cpu.data 0.025995 # miss rate for demand accesses 1001system.cpu.dcache.demand_miss_rate::total 0.025995 # miss rate for demand accesses 1002system.cpu.dcache.overall_miss_rate::cpu.data 0.025995 # miss rate for overall accesses 1003system.cpu.dcache.overall_miss_rate::total 0.025995 # miss rate for overall accesses 1004system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14694.242333 # average ReadReq miss latency 1005system.cpu.dcache.ReadReq_avg_miss_latency::total 14694.242333 # average ReadReq miss latency 1006system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45058.259477 # average WriteReq miss latency 1007system.cpu.dcache.WriteReq_avg_miss_latency::total 45058.259477 # average WriteReq miss latency 1008system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13879.788726 # average LoadLockedReq miss latency 1009system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13879.788726 # average LoadLockedReq miss latency 1010system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency 1011system.cpu.dcache.demand_avg_miss_latency::total 26978.118107 # average overall miss latency 1012system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency 1013system.cpu.dcache.overall_avg_miss_latency::total 26978.118107 # average overall miss latency 1014system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 949system.cpu.dcache.tags.tag_accesses 90403758 # Number of tag accesses 950system.cpu.dcache.tags.data_accesses 90403758 # Number of data accesses 951system.cpu.dcache.ReadReq_hits::cpu.data 11249339 # number of ReadReq hits 952system.cpu.dcache.ReadReq_hits::total 11249339 # number of ReadReq hits 953system.cpu.dcache.WriteReq_hits::cpu.data 9965366 # number of WriteReq hits 954system.cpu.dcache.WriteReq_hits::total 9965366 # number of WriteReq hits 955system.cpu.dcache.SoftPFReq_hits::cpu.data 84253 # number of SoftPFReq hits 956system.cpu.dcache.SoftPFReq_hits::total 84253 # number of SoftPFReq hits 957system.cpu.dcache.LoadLockedReq_hits::cpu.data 236457 # number of LoadLockedReq hits 958system.cpu.dcache.LoadLockedReq_hits::total 236457 # number of LoadLockedReq hits 959system.cpu.dcache.StoreCondReq_hits::cpu.data 247663 # number of StoreCondReq hits 960system.cpu.dcache.StoreCondReq_hits::total 247663 # number of StoreCondReq hits 961system.cpu.dcache.demand_hits::cpu.data 21214705 # number of demand (read+write) hits 962system.cpu.dcache.demand_hits::total 21214705 # number of demand (read+write) hits 963system.cpu.dcache.overall_hits::cpu.data 21298958 # number of overall hits 964system.cpu.dcache.overall_hits::total 21298958 # number of overall hits 965system.cpu.dcache.ReadReq_misses::cpu.data 294663 # number of ReadReq misses 966system.cpu.dcache.ReadReq_misses::total 294663 # number of ReadReq misses 967system.cpu.dcache.WriteReq_misses::cpu.data 255297 # number of WriteReq misses 968system.cpu.dcache.WriteReq_misses::total 255297 # number of WriteReq misses 969system.cpu.dcache.SoftPFReq_misses::cpu.data 100106 # number of SoftPFReq misses 970system.cpu.dcache.SoftPFReq_misses::total 100106 # number of SoftPFReq misses 971system.cpu.dcache.LoadLockedReq_misses::cpu.data 11207 # number of LoadLockedReq misses 972system.cpu.dcache.LoadLockedReq_misses::total 11207 # number of LoadLockedReq misses 973system.cpu.dcache.demand_misses::cpu.data 549960 # number of demand (read+write) misses 974system.cpu.dcache.demand_misses::total 549960 # number of demand (read+write) misses 975system.cpu.dcache.overall_misses::cpu.data 650066 # number of overall misses 976system.cpu.dcache.overall_misses::total 650066 # number of overall misses 977system.cpu.dcache.ReadReq_miss_latency::cpu.data 4040384999 # number of ReadReq miss cycles 978system.cpu.dcache.ReadReq_miss_latency::total 4040384999 # number of ReadReq miss cycles 979system.cpu.dcache.WriteReq_miss_latency::cpu.data 11533122261 # number of WriteReq miss cycles 980system.cpu.dcache.WriteReq_miss_latency::total 11533122261 # number of WriteReq miss cycles 981system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155182000 # number of LoadLockedReq miss cycles 982system.cpu.dcache.LoadLockedReq_miss_latency::total 155182000 # number of LoadLockedReq miss cycles 983system.cpu.dcache.demand_miss_latency::cpu.data 15573507260 # number of demand (read+write) miss cycles 984system.cpu.dcache.demand_miss_latency::total 15573507260 # number of demand (read+write) miss cycles 985system.cpu.dcache.overall_miss_latency::cpu.data 15573507260 # number of overall miss cycles 986system.cpu.dcache.overall_miss_latency::total 15573507260 # number of overall miss cycles 987system.cpu.dcache.ReadReq_accesses::cpu.data 11544002 # number of ReadReq accesses(hits+misses) 988system.cpu.dcache.ReadReq_accesses::total 11544002 # number of ReadReq accesses(hits+misses) 989system.cpu.dcache.WriteReq_accesses::cpu.data 10220663 # number of WriteReq accesses(hits+misses) 990system.cpu.dcache.WriteReq_accesses::total 10220663 # number of WriteReq accesses(hits+misses) 991system.cpu.dcache.SoftPFReq_accesses::cpu.data 184359 # number of SoftPFReq accesses(hits+misses) 992system.cpu.dcache.SoftPFReq_accesses::total 184359 # number of SoftPFReq accesses(hits+misses) 993system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247664 # number of LoadLockedReq accesses(hits+misses) 994system.cpu.dcache.LoadLockedReq_accesses::total 247664 # number of LoadLockedReq accesses(hits+misses) 995system.cpu.dcache.StoreCondReq_accesses::cpu.data 247663 # number of StoreCondReq accesses(hits+misses) 996system.cpu.dcache.StoreCondReq_accesses::total 247663 # number of StoreCondReq accesses(hits+misses) 997system.cpu.dcache.demand_accesses::cpu.data 21764665 # number of demand (read+write) accesses 998system.cpu.dcache.demand_accesses::total 21764665 # number of demand (read+write) accesses 999system.cpu.dcache.overall_accesses::cpu.data 21949024 # number of overall (read+write) accesses 1000system.cpu.dcache.overall_accesses::total 21949024 # number of overall (read+write) accesses 1001system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025525 # miss rate for ReadReq accesses 1002system.cpu.dcache.ReadReq_miss_rate::total 0.025525 # miss rate for ReadReq accesses 1003system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024979 # miss rate for WriteReq accesses 1004system.cpu.dcache.WriteReq_miss_rate::total 0.024979 # miss rate for WriteReq accesses 1005system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.542995 # miss rate for SoftPFReq accesses 1006system.cpu.dcache.SoftPFReq_miss_rate::total 0.542995 # miss rate for SoftPFReq accesses 1007system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses 1008system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses 1009system.cpu.dcache.demand_miss_rate::cpu.data 0.025268 # miss rate for demand accesses 1010system.cpu.dcache.demand_miss_rate::total 0.025268 # miss rate for demand accesses 1011system.cpu.dcache.overall_miss_rate::cpu.data 0.029617 # miss rate for overall accesses 1012system.cpu.dcache.overall_miss_rate::total 0.029617 # miss rate for overall accesses 1013system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13711.884421 # average ReadReq miss latency 1014system.cpu.dcache.ReadReq_avg_miss_latency::total 13711.884421 # average ReadReq miss latency 1015system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45175.314481 # average WriteReq miss latency 1016system.cpu.dcache.WriteReq_avg_miss_latency::total 45175.314481 # average WriteReq miss latency 1017system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13846.881413 # average LoadLockedReq miss latency 1018system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413 # average LoadLockedReq miss latency 1019system.cpu.dcache.demand_avg_miss_latency::cpu.data 28317.527202 # average overall miss latency 1020system.cpu.dcache.demand_avg_miss_latency::total 28317.527202 # average overall miss latency 1021system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401 # average overall miss latency 1022system.cpu.dcache.overall_avg_miss_latency::total 23956.809401 # average overall miss latency 1023system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked |
| 1015system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1024system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1016system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 1025system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked |
| 1017system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1026system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1018system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1027system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked |
| 1019system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1020system.cpu.dcache.fast_writes 0 # number of fast writes performed 1021system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1028system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1029system.cpu.dcache.fast_writes 0 # number of fast writes performed 1030system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1022system.cpu.dcache.writebacks::writebacks 595396 # number of writebacks 1023system.cpu.dcache.writebacks::total 595396 # number of writebacks 1024system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368196 # number of ReadReq MSHR misses 1025system.cpu.dcache.ReadReq_mshr_misses::total 368196 # number of ReadReq MSHR misses 1026system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250157 # number of WriteReq MSHR misses 1027system.cpu.dcache.WriteReq_mshr_misses::total 250157 # number of WriteReq MSHR misses 1028system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11407 # number of LoadLockedReq MSHR misses 1029system.cpu.dcache.LoadLockedReq_mshr_misses::total 11407 # number of LoadLockedReq MSHR misses 1030system.cpu.dcache.demand_mshr_misses::cpu.data 618353 # number of demand (read+write) MSHR misses 1031system.cpu.dcache.demand_mshr_misses::total 618353 # number of demand (read+write) MSHR misses 1032system.cpu.dcache.overall_mshr_misses::cpu.data 618353 # number of overall MSHR misses 1033system.cpu.dcache.overall_mshr_misses::total 618353 # number of overall MSHR misses 1034system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4671668750 # number of ReadReq MSHR miss cycles 1035system.cpu.dcache.ReadReq_mshr_miss_latency::total 4671668750 # number of ReadReq MSHR miss cycles 1036system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10721268984 # number of WriteReq MSHR miss cycles 1037system.cpu.dcache.WriteReq_mshr_miss_latency::total 10721268984 # number of WriteReq MSHR miss cycles 1038system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135458250 # number of LoadLockedReq MSHR miss cycles 1039system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135458250 # number of LoadLockedReq MSHR miss cycles 1040system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15392937734 # number of demand (read+write) MSHR miss cycles 1041system.cpu.dcache.demand_mshr_miss_latency::total 15392937734 # number of demand (read+write) MSHR miss cycles 1042system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15392937734 # number of overall MSHR miss cycles 1043system.cpu.dcache.overall_mshr_miss_latency::total 15392937734 # number of overall MSHR miss cycles 1044system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250 # number of ReadReq MSHR uncacheable cycles 1045system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250 # number of ReadReq MSHR uncacheable cycles 1046system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242925328 # number of WriteReq MSHR uncacheable cycles 1047system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242925328 # number of WriteReq MSHR uncacheable cycles 1048system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578 # number of overall MSHR uncacheable cycles 1049system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578 # number of overall MSHR uncacheable cycles 1050system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027144 # mshr miss rate for ReadReq accesses 1051system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027144 # mshr miss rate for ReadReq accesses 1052system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses 1053system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses 1054system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046036 # mshr miss rate for LoadLockedReq accesses 1055system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046036 # mshr miss rate for LoadLockedReq accesses 1056system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for demand accesses 1057system.cpu.dcache.demand_mshr_miss_rate::total 0.025995 # mshr miss rate for demand accesses 1058system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for overall accesses 1059system.cpu.dcache.overall_mshr_miss_rate::total 0.025995 # mshr miss rate for overall accesses 1060system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302 # average ReadReq mshr miss latency 1061system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302 # average ReadReq mshr miss latency 1062system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011 # average WriteReq mshr miss latency 1063system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011 # average WriteReq mshr miss latency 1064system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958 # average LoadLockedReq mshr miss latency 1065system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958 # average LoadLockedReq mshr miss latency 1066system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency 1067system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency 1068system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency 1069system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency | 1031system.cpu.dcache.writebacks::writebacks 594981 # number of writebacks 1032system.cpu.dcache.writebacks::total 594981 # number of writebacks 1033system.cpu.dcache.ReadReq_mshr_hits::cpu.data 534 # number of ReadReq MSHR hits 1034system.cpu.dcache.ReadReq_mshr_hits::total 534 # number of ReadReq MSHR hits 1035system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4836 # number of WriteReq MSHR hits 1036system.cpu.dcache.WriteReq_mshr_hits::total 4836 # number of WriteReq MSHR hits 1037system.cpu.dcache.demand_mshr_hits::cpu.data 5370 # number of demand (read+write) MSHR hits 1038system.cpu.dcache.demand_mshr_hits::total 5370 # number of demand (read+write) MSHR hits 1039system.cpu.dcache.overall_mshr_hits::cpu.data 5370 # number of overall MSHR hits 1040system.cpu.dcache.overall_mshr_hits::total 5370 # number of overall MSHR hits 1041system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294129 # number of ReadReq MSHR misses 1042system.cpu.dcache.ReadReq_mshr_misses::total 294129 # number of ReadReq MSHR misses 1043system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250461 # number of WriteReq MSHR misses 1044system.cpu.dcache.WriteReq_mshr_misses::total 250461 # number of WriteReq MSHR misses 1045system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 73479 # number of SoftPFReq MSHR misses 1046system.cpu.dcache.SoftPFReq_mshr_misses::total 73479 # number of SoftPFReq MSHR misses 1047system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11207 # number of LoadLockedReq MSHR misses 1048system.cpu.dcache.LoadLockedReq_mshr_misses::total 11207 # number of LoadLockedReq MSHR misses 1049system.cpu.dcache.demand_mshr_misses::cpu.data 544590 # number of demand (read+write) MSHR misses 1050system.cpu.dcache.demand_mshr_misses::total 544590 # number of demand (read+write) MSHR misses 1051system.cpu.dcache.overall_mshr_misses::cpu.data 618069 # number of overall MSHR misses 1052system.cpu.dcache.overall_mshr_misses::total 618069 # number of overall MSHR misses 1053system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3445567250 # number of ReadReq MSHR miss cycles 1054system.cpu.dcache.ReadReq_mshr_miss_latency::total 3445567250 # number of ReadReq MSHR miss cycles 1055system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10763005489 # number of WriteReq MSHR miss cycles 1056system.cpu.dcache.WriteReq_mshr_miss_latency::total 10763005489 # number of WriteReq MSHR miss cycles 1057system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1228271500 # number of SoftPFReq MSHR miss cycles 1058system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1228271500 # number of SoftPFReq MSHR miss cycles 1059system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132710000 # number of LoadLockedReq MSHR miss cycles 1060system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132710000 # number of LoadLockedReq MSHR miss cycles 1061system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14208572739 # number of demand (read+write) MSHR miss cycles 1062system.cpu.dcache.demand_mshr_miss_latency::total 14208572739 # number of demand (read+write) MSHR miss cycles 1063system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15436844239 # number of overall MSHR miss cycles 1064system.cpu.dcache.overall_mshr_miss_latency::total 15436844239 # number of overall MSHR miss cycles 1065system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058544250 # number of ReadReq MSHR uncacheable cycles 1066system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250 # number of ReadReq MSHR uncacheable cycles 1067system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242551425 # number of WriteReq MSHR uncacheable cycles 1068system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242551425 # number of WriteReq MSHR uncacheable cycles 1069system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301095675 # number of overall MSHR uncacheable cycles 1070system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301095675 # number of overall MSHR uncacheable cycles 1071system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025479 # mshr miss rate for ReadReq accesses 1072system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025479 # mshr miss rate for ReadReq accesses 1073system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses 1074system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses 1075system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398565 # mshr miss rate for SoftPFReq accesses 1076system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398565 # mshr miss rate for SoftPFReq accesses 1077system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045251 # mshr miss rate for LoadLockedReq accesses 1078system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045251 # mshr miss rate for LoadLockedReq accesses 1079system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025022 # mshr miss rate for demand accesses 1080system.cpu.dcache.demand_mshr_miss_rate::total 0.025022 # mshr miss rate for demand accesses 1081system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028159 # mshr miss rate for overall accesses 1082system.cpu.dcache.overall_mshr_miss_rate::total 0.028159 # mshr miss rate for overall accesses 1083system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471 # average ReadReq mshr miss latency 1084system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471 # average ReadReq mshr miss latency 1085system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149 # average WriteReq mshr miss latency 1086system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149 # average WriteReq mshr miss latency 1087system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857 # average SoftPFReq mshr miss latency 1088system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857 # average SoftPFReq mshr miss latency 1089system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077 # average LoadLockedReq mshr miss latency 1090system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077 # average LoadLockedReq mshr miss latency 1091system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311 # average overall mshr miss latency 1092system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311 # average overall mshr miss latency 1093system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787 # average overall mshr miss latency 1094system.cpu.dcache.overall_avg_mshr_miss_latency::total 24975.923787 # average overall mshr miss latency |
| 1070system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1071system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1072system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1073system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1074system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1075system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1076system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1095system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1096system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1097system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1098system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1099system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1100system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1101system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1077system.cpu.toL2Bus.throughput 52982138 # Throughput (bytes/s) 1078system.cpu.toL2Bus.trans_dist::ReadReq 2454896 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::ReadResp 2454896 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution 1082system.cpu.toL2Bus.trans_dist::Writeback 595396 # Transaction distribution 1083system.cpu.toL2Bus.trans_dist::UpgradeReq 2928 # Transaction distribution 1084system.cpu.toL2Bus.trans_dist::UpgradeResp 2928 # Transaction distribution 1085system.cpu.toL2Bus.trans_dist::ReadExReq 247229 # Transaction distribution 1086system.cpu.toL2Bus.trans_dist::ReadExResp 247229 # Transaction distribution 1087system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725354 # Packet count per connected master and slave (bytes) 1088system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749970 # Packet count per connected master and slave (bytes) 1089system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12465 # Packet count per connected master and slave (bytes) 1090system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27449 # Packet count per connected master and slave (bytes) 1091system.cpu.toL2Bus.pkt_count::total 7515238 # Packet count per connected master and slave (bytes) 1092system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54761180 # Cumulative packet size per connected master and slave (bytes) 1093system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83637066 # Cumulative packet size per connected master and slave (bytes) 1094system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14156 # Cumulative packet size per connected master and slave (bytes) 1095system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34872 # Cumulative packet size per connected master and slave (bytes) 1096system.cpu.toL2Bus.tot_pkt_size::total 138447274 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu.toL2Bus.data_through_bus 138447274 # Total data (bytes) 1098system.cpu.toL2Bus.snoop_data_through_bus 166176 # Total snoop data (bytes) 1099system.cpu.toL2Bus.reqLayer0.occupancy 3009006000 # Layer occupancy (ticks) | 1102system.cpu.toL2Bus.throughput 52981595 # Throughput (bytes/s) 1103system.cpu.toL2Bus.trans_dist::ReadReq 2453579 # Transaction distribution 1104system.cpu.toL2Bus.trans_dist::ReadResp 2453579 # Transaction distribution 1105system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution 1106system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution 1107system.cpu.toL2Bus.trans_dist::Writeback 594981 # Transaction distribution 1108system.cpu.toL2Bus.trans_dist::UpgradeReq 2922 # Transaction distribution 1109system.cpu.toL2Bus.trans_dist::UpgradeResp 2922 # Transaction distribution 1110system.cpu.toL2Bus.trans_dist::ReadExReq 247539 # Transaction distribution 1111system.cpu.toL2Bus.trans_dist::ReadExResp 247539 # Transaction distribution 1112system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724389 # Packet count per connected master and slave (bytes) 1113system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748549 # Packet count per connected master and slave (bytes) 1114system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12041 # Packet count per connected master and slave (bytes) 1115system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes) 1116system.cpu.toL2Bus.pkt_count::total 7511231 # Packet count per connected master and slave (bytes) 1117system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54730908 # Cumulative packet size per connected master and slave (bytes) 1118system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83579878 # Cumulative packet size per connected master and slave (bytes) 1119system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Cumulative packet size per connected master and slave (bytes) 1120system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) 1121system.cpu.toL2Bus.tot_pkt_size::total 138353418 # Cumulative packet size per connected master and slave (bytes) 1122system.cpu.toL2Bus.data_through_bus 138353418 # Total data (bytes) 1123system.cpu.toL2Bus.snoop_data_through_bus 171268 # Total snoop data (bytes) 1124system.cpu.toL2Bus.reqLayer0.occupancy 3007873000 # Layer occupancy (ticks) |
| 1100system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1125system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1101system.cpu.toL2Bus.respLayer0.occupancy 1295477750 # Layer occupancy (ticks) | 1126system.cpu.toL2Bus.respLayer0.occupancy 1294746250 # Layer occupancy (ticks) |
| 1102system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1127system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1103system.cpu.toL2Bus.respLayer1.occupancy 2533767938 # Layer occupancy (ticks) | 1128system.cpu.toL2Bus.respLayer1.occupancy 2533153086 # Layer occupancy (ticks) |
| 1104system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1105system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1106system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1129system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1130system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1131system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1107system.cpu.toL2Bus.respLayer3.occupancy 18731500 # Layer occupancy (ticks) | 1132system.cpu.toL2Bus.respLayer3.occupancy 18709500 # Layer occupancy (ticks) |
| 1108system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1109system.iocache.tags.replacements 0 # number of replacements 1110system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1111system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1112system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1113system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1114system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1115system.iocache.tags.tag_accesses 0 # Number of tag accesses 1116system.iocache.tags.data_accesses 0 # Number of data accesses 1117system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1118system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1119system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1120system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1121system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1122system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1123system.iocache.fast_writes 0 # number of fast writes performed 1124system.iocache.cache_copies 0 # number of cache copies performed | 1133system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1134system.iocache.tags.replacements 0 # number of replacements 1135system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1136system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1137system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1138system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1139system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1140system.iocache.tags.tag_accesses 0 # Number of tag accesses 1141system.iocache.tags.data_accesses 0 # Number of data accesses 1142system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1143system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1144system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1145system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1146system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1147system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1148system.iocache.fast_writes 0 # number of fast writes performed 1149system.iocache.cache_copies 0 # number of cache copies performed |
| 1125system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of ReadReq MSHR uncacheable cycles 1126system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250 # number of ReadReq MSHR uncacheable cycles 1127system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of overall MSHR uncacheable cycles 1128system.iocache.overall_mshr_uncacheable_latency::total 1759698189250 # number of overall MSHR uncacheable cycles | 1150system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of ReadReq MSHR uncacheable cycles 1151system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500 # number of ReadReq MSHR uncacheable cycles 1152system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of overall MSHR uncacheable cycles 1153system.iocache.overall_mshr_uncacheable_latency::total 1760059764500 # number of overall MSHR uncacheable cycles |
| 1129system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1130system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1131system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1132system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1133system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1134 1135---------- End Simulation Statistics ---------- | 1154system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1155system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1156system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1157system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1158system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1159 1160---------- End Simulation Statistics ---------- |