| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.616536 # Number of seconds simulated 4sim_ticks 2616536215000 # Number of ticks simulated 5final_tick 2616536215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.616230 # Number of seconds simulated 4sim_ticks 2616229847000 # Number of ticks simulated 5final_tick 2616229847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 594955 # Simulator instruction rate (inst/s) 8host_op_rate 757104 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25859148121 # Simulator tick rate (ticks/s) 10host_mem_usage 420956 # Number of bytes of host memory used 11host_seconds 101.18 # Real time elapsed on the host 12sim_insts 60200059 # Number of instructions simulated 13sim_ops 76606878 # Number of ops (including micro ops) simulated | 7host_inst_rate 375445 # Simulator instruction rate (inst/s) 8host_op_rate 477768 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16316419265 # Simulator tick rate (ticks/s) 10host_mem_usage 464828 # Number of bytes of host memory used 11host_seconds 160.34 # Real time elapsed on the host 12sim_insts 60200042 # Number of instructions simulated 13sim_ops 76606857 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 22system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 27system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) |
|
| 16system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 28system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9089816 # Number of bytes read from this memory 21system.physmem.bytes_read::total 132477600 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3706240 # Number of bytes written to this memory | 31system.physmem.bytes_read::cpu.inst 703560 # Number of bytes read from this memory 32system.physmem.bytes_read::cpu.data 9089944 # Number of bytes read from this memory 33system.physmem.bytes_read::total 132477344 # Number of bytes read from this memory 34system.physmem.bytes_inst_read::cpu.inst 703560 # Number of instructions bytes read from this memory 35system.physmem.bytes_inst_read::total 703560 # Number of instructions bytes read from this memory 36system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory | 37system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 6722312 # Number of bytes written to this memory | 38system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory |
| 27system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 39system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142064 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15494706 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 57910 # Number of write requests responded to by this memory | 42system.physmem.num_reads::cpu.inst 17205 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu.data 142066 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 15494702 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory | 46system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 811928 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 46887710 # Total read bandwidth from this memory (bytes/s) | 47system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory 48system.physmem.bw_read::realview.clcd 46893201 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3473988 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 50630906 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1416468 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2569165 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1416468 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 46887710 # Total bandwidth to/from this memory (bytes/s) | 51system.physmem.bw_read::cpu.inst 268921 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu.data 3474444 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50636737 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu.inst 268921 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::total 268921 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_write::writebacks 1416658 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu.data 1152831 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2569490 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1416658 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46893201 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4626685 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53200071 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15494706 # Number of read requests accepted 55system.physmem.writeReqs 811928 # Number of write requests accepted 56system.physmem.readBursts 15494706 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 811928 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 991531648 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 129536 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6740736 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 132477600 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 6722312 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 2024 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706583 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 967775 # Per bank write bursts | 63system.physmem.bw_total::cpu.inst 268921 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu.data 4627275 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::total 53206227 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.readReqs 15494702 # Number of read requests accepted 67system.physmem.writeReqs 811929 # Number of write requests accepted 68system.physmem.readBursts 15494702 # Number of DRAM read bursts, including those serviced by the write queue 69system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue 70system.physmem.bytesReadDRAM 991533248 # Total number of bytes read from DRAM 71system.physmem.bytesReadWrQ 127680 # Total number of bytes read from write queue 72system.physmem.bytesWritten 6729728 # Total number of bytes written to DRAM 73system.physmem.bytesReadSys 132477344 # Total read bytes from the system interface side 74system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side 75system.physmem.servicedByWrQ 1995 # Number of DRAM read bursts serviced by the write queue 76system.physmem.mergedWrBursts 706751 # Number of DRAM write bursts merged with an existing one 77system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write 78system.physmem.perBankRdBursts::0 967982 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::1 967715 # Per bank write bursts | 79system.physmem.perBankRdBursts::1 967715 # Per bank write bursts |
| 68system.physmem.perBankRdBursts::2 967672 # Per bank write bursts 69system.physmem.perBankRdBursts::3 967748 # Per bank write bursts 70system.physmem.perBankRdBursts::4 974561 # Per bank write bursts 71system.physmem.perBankRdBursts::5 968173 # Per bank write bursts 72system.physmem.perBankRdBursts::6 967769 # Per bank write bursts 73system.physmem.perBankRdBursts::7 967703 # Per bank write bursts 74system.physmem.perBankRdBursts::8 968545 # Per bank write bursts | 80system.physmem.perBankRdBursts::2 967669 # Per bank write bursts 81system.physmem.perBankRdBursts::3 967754 # Per bank write bursts 82system.physmem.perBankRdBursts::4 974564 # Per bank write bursts 83system.physmem.perBankRdBursts::5 968184 # Per bank write bursts 84system.physmem.perBankRdBursts::6 967779 # Per bank write bursts 85system.physmem.perBankRdBursts::7 967692 # Per bank write bursts 86system.physmem.perBankRdBursts::8 968544 # Per bank write bursts |
| 75system.physmem.perBankRdBursts::9 968137 # Per bank write bursts 76system.physmem.perBankRdBursts::10 967949 # Per bank write bursts 77system.physmem.perBankRdBursts::11 967746 # Per bank write bursts 78system.physmem.perBankRdBursts::12 967851 # Per bank write bursts 79system.physmem.perBankRdBursts::13 967741 # Per bank write bursts 80system.physmem.perBankRdBursts::14 967800 # Per bank write bursts | 87system.physmem.perBankRdBursts::9 968137 # Per bank write bursts 88system.physmem.perBankRdBursts::10 967949 # Per bank write bursts 89system.physmem.perBankRdBursts::11 967746 # Per bank write bursts 90system.physmem.perBankRdBursts::12 967851 # Per bank write bursts 91system.physmem.perBankRdBursts::13 967741 # Per bank write bursts 92system.physmem.perBankRdBursts::14 967800 # Per bank write bursts |
| 81system.physmem.perBankRdBursts::15 967797 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6510 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6313 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6323 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6241 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6804 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6995 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6800 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6791 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7084 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6747 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6568 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6457 # Per bank write bursts 94system.physmem.perBankWrBursts::12 6495 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6295 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6428 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6473 # Per bank write bursts | 93system.physmem.perBankRdBursts::15 967600 # Per bank write bursts 94system.physmem.perBankWrBursts::0 6503 # Per bank write bursts 95system.physmem.perBankWrBursts::1 6305 # Per bank write bursts 96system.physmem.perBankWrBursts::2 6309 # Per bank write bursts 97system.physmem.perBankWrBursts::3 6231 # Per bank write bursts 98system.physmem.perBankWrBursts::4 6800 # Per bank write bursts 99system.physmem.perBankWrBursts::5 6982 # Per bank write bursts 100system.physmem.perBankWrBursts::6 6786 # Per bank write bursts 101system.physmem.perBankWrBursts::7 6777 # Per bank write bursts 102system.physmem.perBankWrBursts::8 7080 # Per bank write bursts 103system.physmem.perBankWrBursts::9 6733 # Per bank write bursts 104system.physmem.perBankWrBursts::10 6548 # Per bank write bursts 105system.physmem.perBankWrBursts::11 6441 # Per bank write bursts 106system.physmem.perBankWrBursts::12 6486 # Per bank write bursts 107system.physmem.perBankWrBursts::13 6281 # Per bank write bursts 108system.physmem.perBankWrBursts::14 6425 # Per bank write bursts 109system.physmem.perBankWrBursts::15 6465 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 110system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 111system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 100system.physmem.totGap 2616531854000 # Total gap between requests | 112system.physmem.totGap 2616225486000 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 6664 # Read request sizes (log2) 104system.physmem.readPktSize::3 15335424 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 113system.physmem.readPktSize::0 0 # Read request sizes (log2) 114system.physmem.readPktSize::1 0 # Read request sizes (log2) 115system.physmem.readPktSize::2 6664 # Read request sizes (log2) 116system.physmem.readPktSize::3 15335424 # Read request sizes (log2) 117system.physmem.readPktSize::4 0 # Read request sizes (log2) 118system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 152618 # Read request sizes (log2) | 119system.physmem.readPktSize::6 152614 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 120system.physmem.writePktSize::0 0 # Write request sizes (log2) 121system.physmem.writePktSize::1 0 # Write request sizes (log2) 122system.physmem.writePktSize::2 754018 # Write request sizes (log2) 123system.physmem.writePktSize::3 0 # Write request sizes (log2) 124system.physmem.writePktSize::4 0 # Write request sizes (log2) 125system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 57910 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1116573 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 960474 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 961347 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 975907 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 963056 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 965451 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2812276 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2805674 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3709925 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 42008 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 34639 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 36264 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 33338 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 31474 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 22310 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 21858 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see | 126system.physmem.writePktSize::6 57911 # Write request sizes (log2) 127system.physmem.rdQLenPdf::0 1126567 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 970563 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 976518 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1090618 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 986596 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1051326 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 2724005 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 2632042 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 3421723 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 136210 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 113171 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 104737 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 101252 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 19730 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 18895 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 18668 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 86 # What read queue length does an incoming req see |
| 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 144system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2478 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2541 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 3152 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 4807 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 4792 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 4786 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 4793 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 4827 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 4839 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 4834 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 5981 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 4975 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 4962 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 5804 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 4869 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 4878 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 4878 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 4793 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1099 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 1078 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 1070 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 1076 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 1063 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 1060 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 1060 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 1060 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 1060 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 1060 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 1060 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 1060 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 1060 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 1059 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 1059 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 1059 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 1059 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 1058 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 1058 # What write queue length does an incoming req see | 174system.physmem.wrQLenPdf::15 3804 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 3835 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 6081 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 6095 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 6100 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 6096 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 6099 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 6095 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 6098 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 6095 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 6095 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 6095 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 6101 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 6096 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 6095 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 6094 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::32 6094 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see |
| 201system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 213system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 211system.physmem.bytesPerActivate::samples 977394 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 1014.625651 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 1002.644045 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 87.222028 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 3543 0.36% 0.36% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 3286 0.34% 0.70% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 1787 0.18% 0.88% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 1165 0.12% 1.00% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 902 0.09% 1.09% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 711 0.07% 1.17% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 580 0.06% 1.23% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 432 0.04% 1.27% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 964988 98.73% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 977394 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 4784 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 3238.435619 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 134294.504205 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 4779 99.90% 99.90% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.06% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 4784 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 4784 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 22.015886 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 20.524536 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 9.242033 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 2224 46.49% 46.49% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 36 0.75% 47.24% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 227 4.74% 51.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 1224 25.59% 77.57% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 8 0.17% 77.74% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::21 4 0.08% 77.82% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 1 0.02% 77.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::33 1 0.02% 77.86% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::34 1 0.02% 77.88% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::39 945 19.75% 97.64% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::40 67 1.40% 99.04% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::41 15 0.31% 99.35% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::42 31 0.65% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 4784 # Writes before turning the bus around for reads 251system.physmem.totQLat 588095657500 # Total ticks spent queuing 252system.physmem.totMemAccLat 694960871250 # Total ticks spent from burst creation until serviced by the DRAM 253system.physmem.totBusLat 77463410000 # Total ticks spent in databus transfers 254system.physmem.totBankLat 29401803750 # Total ticks spent accessing banks 255system.physmem.avgQLat 37959.58 # Average queueing delay per DRAM burst 256system.physmem.avgBankLat 1897.79 # Average bank access latency per DRAM burst | 223system.physmem.bytesPerActivate::samples 1027354 # Bytes accessed per row activation 224system.physmem.bytesPerActivate::mean 971.683544 # Bytes accessed per row activation 225system.physmem.bytesPerActivate::gmean 905.447521 # Bytes accessed per row activation 226system.physmem.bytesPerActivate::stdev 204.224200 # Bytes accessed per row activation 227system.physmem.bytesPerActivate::0-127 22943 2.23% 2.23% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::128-255 22460 2.19% 4.42% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::256-383 8461 0.82% 5.24% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::384-511 2563 0.25% 5.49% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::512-639 2504 0.24% 5.74% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::640-767 1783 0.17% 5.91% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::768-895 8706 0.85% 6.76% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::896-1023 969 0.09% 6.85% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::1024-1151 956965 93.15% 100.00% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::total 1027354 # Bytes accessed per row activation 237system.physmem.rdPerTurnAround::samples 6094 # Reads before turning the bus around for writes 238system.physmem.rdPerTurnAround::mean 2542.286675 # Reads before turning the bus around for writes 239system.physmem.rdPerTurnAround::stdev 118884.715097 # Reads before turning the bus around for writes 240system.physmem.rdPerTurnAround::0-524287 6090 99.93% 99.93% # Reads before turning the bus around for writes 241system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes 242system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::total 6094 # Reads before turning the bus around for writes 245system.physmem.wrPerTurnAround::samples 6094 # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::mean 17.255005 # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::gmean 17.227328 # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::stdev 0.967528 # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::16 2261 37.10% 37.10% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::17 29 0.48% 37.58% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::18 3794 62.26% 99.84% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::19 9 0.15% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 6094 # Writes before turning the bus around for reads 255system.physmem.totQLat 400062590250 # Total ticks spent queuing 256system.physmem.totMemAccLat 690550846500 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 77463535000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 25822.64 # Average queueing delay per DRAM burst |
| 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 258system.physmem.avgMemAccLat 44857.36 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s 260system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s 261system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s | 260system.physmem.avgMemAccLat 44572.64 # Average memory access latency per DRAM burst 261system.physmem.avgRdBW 378.99 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 50.64 # Average system read bandwidth in MiByte/s |
| 262system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 2.98 # Data bus utilization in percentage 265system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 264system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 2.98 # Data bus utilization in percentage 267system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 267system.physmem.avgRdQLen 7.03 # Average read queue length when enqueuing 268system.physmem.avgWrQLen 29.46 # Average write queue length when enqueuing 269system.physmem.readRowHits 14490606 # Number of row buffer hits during reads 270system.physmem.writeRowHits 90101 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 85.53 # Row buffer hit rate for writes 273system.physmem.avgGap 160458.12 # Average gap between requests 274system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined 275system.physmem.prechargeAllPercent 3.85 # Percentage of time for which DRAM has all the banks in precharge state 276system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 277system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 278system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 279system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 280system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 281system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 282system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 283system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 284system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 285system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 286system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 287system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 288system.membus.throughput 54116651 # Throughput (bytes/s) 289system.membus.trans_dist::ReadReq 16546597 # Transaction distribution 290system.membus.trans_dist::ReadResp 16546597 # Transaction distribution | 269system.physmem.avgRdQLen 6.59 # Average read queue length when enqueuing 270system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing 271system.physmem.readRowHits 14482119 # Number of row buffer hits during reads 272system.physmem.writeRowHits 88386 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 84.03 # Row buffer hit rate for writes 275system.physmem.avgGap 160439.36 # Average gap between requests 276system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined 277system.physmem.memoryStateTime::IDLE 2245273695250 # Time in different power states 278system.physmem.memoryStateTime::REF 87361560000 # Time in different power states 279system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 280system.physmem.memoryStateTime::ACT 283591722250 # Time in different power states 281system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 282system.membus.throughput 54122917 # Throughput (bytes/s) 283system.membus.trans_dist::ReadReq 16546592 # Transaction distribution 284system.membus.trans_dist::ReadResp 16546592 # Transaction distribution |
| 291system.membus.trans_dist::WriteReq 763385 # Transaction distribution 292system.membus.trans_dist::WriteResp 763385 # Transaction distribution | 285system.membus.trans_dist::WriteReq 763385 # Transaction distribution 286system.membus.trans_dist::WriteResp 763385 # Transaction distribution |
| 293system.membus.trans_dist::Writeback 57910 # Transaction distribution 294system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution 295system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution 296system.membus.trans_dist::ReadExReq 132217 # Transaction distribution 297system.membus.trans_dist::ReadExResp 132217 # Transaction distribution 298system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes) | 287system.membus.trans_dist::Writeback 57911 # Transaction distribution 288system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution 289system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution 290system.membus.trans_dist::ReadExReq 132219 # Transaction distribution 291system.membus.trans_dist::ReadExResp 132219 # Transaction distribution 292system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383090 # Packet count per connected master and slave (bytes) |
| 299system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) | 293system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 294system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 295system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) |
| 302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893540 # Packet count per connected master and slave (bytes) 303system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280490 # Packet count per connected master and slave (bytes) | 296system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893535 # Packet count per connected master and slave (bytes) 297system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280487 # Packet count per connected master and slave (bytes) |
| 304system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) | 298system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 299system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) |
| 306system.membus.pkt_count::total 34951338 # Packet count per connected master and slave (bytes) 307system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes) | 300system.membus.pkt_count::total 34951335 # Packet count per connected master and slave (bytes) 301system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390546 # Cumulative packet size per connected master and slave (bytes) |
| 308system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 309system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) | 302system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 303system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 304system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) |
| 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516520 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914786 # Cumulative packet size per connected master and slave (bytes) | 305system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516328 # Cumulative packet size per connected master and slave (bytes) 306system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914598 # Cumulative packet size per connected master and slave (bytes) |
| 313system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) | 307system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 308system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) |
| 315system.membus.tot_pkt_size::total 141598178 # Cumulative packet size per connected master and slave (bytes) 316system.membus.data_through_bus 141598178 # Total data (bytes) | 309system.membus.tot_pkt_size::total 141597990 # Cumulative packet size per connected master and slave (bytes) 310system.membus.data_through_bus 141597990 # Total data (bytes) |
| 317system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 311system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 318system.membus.reqLayer0.occupancy 1206225000 # Layer occupancy (ticks) | 312system.membus.reqLayer0.occupancy 1206224000 # Layer occupancy (ticks) |
| 319system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 320system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 321system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 313system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 314system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 315system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 322system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) | 316system.membus.reqLayer2.occupancy 3616500 # Layer occupancy (ticks) |
| 323system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 324system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 325system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 317system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 318system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 319system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 326system.membus.reqLayer6.occupancy 17911294000 # Layer occupancy (ticks) | 320system.membus.reqLayer6.occupancy 17911182500 # Layer occupancy (ticks) |
| 327system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 321system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 328system.membus.respLayer1.occupancy 4951349139 # Layer occupancy (ticks) | 322system.membus.respLayer1.occupancy 4951111812 # Layer occupancy (ticks) |
| 329system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 323system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 330system.membus.respLayer2.occupancy 38238689000 # Layer occupancy (ticks) 331system.membus.respLayer2.utilization 1.5 # Layer utilization (%) | 324system.membus.respLayer2.occupancy 37928474750 # Layer occupancy (ticks) 325system.membus.respLayer2.utilization 1.4 # Layer utilization (%) |
| 332system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 333system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 334system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 335system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 336system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 337system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 326system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 327system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 328system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 329system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 330system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 331system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 338system.iobus.throughput 47801339 # Throughput (bytes/s) 339system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution 340system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution | 332system.iobus.throughput 47806938 # Throughput (bytes/s) 333system.iobus.trans_dist::ReadReq 16518786 # Transaction distribution 334system.iobus.trans_dist::ReadResp 16518786 # Transaction distribution |
| 341system.iobus.trans_dist::WriteReq 8183 # Transaction distribution 342system.iobus.trans_dist::WriteResp 8183 # Transaction distribution 343system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) | 335system.iobus.trans_dist::WriteReq 8183 # Transaction distribution 336system.iobus.trans_dist::WriteResp 8183 # Transaction distribution 337system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) |
| 344system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) | 338system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) |
| 345system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 346system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 347system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 349system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 350system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 358system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 360system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 361system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 339system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 340system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 341system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 342system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 343system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 344system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 345system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 346system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 352system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 366system.iobus.pkt_count_system.bridge.master::total 2383088 # Packet count per connected master and slave (bytes) | 360system.iobus.pkt_count_system.bridge.master::total 2383090 # Packet count per connected master and slave (bytes) |
| 367system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 368system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) | 361system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) |
| 369system.iobus.pkt_count::total 33053936 # Packet count per connected master and slave (bytes) | 363system.iobus.pkt_count::total 33053938 # Packet count per connected master and slave (bytes) |
| 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) | 364system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) |
| 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) | 365system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) |
| 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 388system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 366system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 367system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 368system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 369system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 393system.iobus.tot_pkt_size_system.bridge.master::total 2390542 # Cumulative packet size per connected master and slave (bytes) | 387system.iobus.tot_pkt_size_system.bridge.master::total 2390546 # Cumulative packet size per connected master and slave (bytes) |
| 394system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 395system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) | 388system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) |
| 396system.iobus.tot_pkt_size::total 125073934 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.data_through_bus 125073934 # Total data (bytes) | 390system.iobus.tot_pkt_size::total 125073938 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.data_through_bus 125073938 # Total data (bytes) |
| 398system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 399system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 392system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 393system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 400system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) | 394system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) |
| 401system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 402system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) 403system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 404system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) 405system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 406system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 407system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 408system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) --- 29 unchanged lines hidden (view full) --- 438system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 439system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 440system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 441system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 442system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 443system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 444system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 445system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) | 395system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 396system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) 397system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 398system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) 399system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 400system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 401system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 402system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) --- 29 unchanged lines hidden (view full) --- 432system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 433system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 434system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 435system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 436system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 437system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 438system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 439system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) |
| 446system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks) | 440system.iobus.respLayer0.occupancy 2374907000 # Layer occupancy (ticks) |
| 447system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 441system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 448system.iobus.respLayer1.occupancy 38265059000 # Layer occupancy (ticks) | 442system.iobus.respLayer1.occupancy 38686102250 # Layer occupancy (ticks) |
| 449system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 450system.cpu_clk_domain.clock 500 # Clock period in ticks 451system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 452system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 453system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 454system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 455system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 456system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses --- 9 unchanged lines hidden (view full) --- 466system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 467system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 468system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 469system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 470system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 471system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 472system.cpu.dtb.inst_hits 0 # ITB inst hits 473system.cpu.dtb.inst_misses 0 # ITB inst misses | 443system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 444system.cpu_clk_domain.clock 500 # Clock period in ticks 445system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 446system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 447system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 448system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 449system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 450system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses --- 9 unchanged lines hidden (view full) --- 460system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 461system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 462system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 463system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 464system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 465system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 466system.cpu.dtb.inst_hits 0 # ITB inst hits 467system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 474system.cpu.dtb.read_hits 14996179 # DTB read hits 475system.cpu.dtb.read_misses 7337 # DTB read misses 476system.cpu.dtb.write_hits 11230334 # DTB write hits 477system.cpu.dtb.write_misses 2213 # DTB write misses | 468system.cpu.dtb.read_hits 14996190 # DTB read hits 469system.cpu.dtb.read_misses 7339 # DTB read misses 470system.cpu.dtb.write_hits 11230344 # DTB write hits 471system.cpu.dtb.write_misses 2214 # DTB write misses |
| 478system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 479system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 480system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 481system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 472system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 473system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 474system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 475system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 482system.cpu.dtb.flush_entries 3411 # Number of entries that have been flushed from TLB | 476system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB |
| 483system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 477system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 484system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch | 478system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch |
| 485system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 486system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 479system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 480system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 487system.cpu.dtb.read_accesses 15003516 # DTB read accesses 488system.cpu.dtb.write_accesses 11232547 # DTB write accesses | 481system.cpu.dtb.read_accesses 15003529 # DTB read accesses 482system.cpu.dtb.write_accesses 11232558 # DTB write accesses |
| 489system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 483system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 490system.cpu.dtb.hits 26226513 # DTB hits 491system.cpu.dtb.misses 9550 # DTB misses 492system.cpu.dtb.accesses 26236063 # DTB accesses | 484system.cpu.dtb.hits 26226534 # DTB hits 485system.cpu.dtb.misses 9553 # DTB misses 486system.cpu.dtb.accesses 26236087 # DTB accesses |
| 493system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 494system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 495system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 496system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 497system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 498system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 499system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 500system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 506system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 509system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 510system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 511system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 512system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 513system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 487system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 488system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 489system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 490system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 491system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 492system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 493system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 494system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 500system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 501system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 502system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 503system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 504system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 505system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 506system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 507system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 514system.cpu.itb.inst_hits 61493932 # ITB inst hits | 508system.cpu.itb.inst_hits 61493913 # ITB inst hits |
| 515system.cpu.itb.inst_misses 4471 # ITB inst misses 516system.cpu.itb.read_hits 0 # DTB read hits 517system.cpu.itb.read_misses 0 # DTB read misses 518system.cpu.itb.write_hits 0 # DTB write hits 519system.cpu.itb.write_misses 0 # DTB write misses 520system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 521system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 522system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 523system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 524system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB 525system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 526system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 527system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 528system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 529system.cpu.itb.read_accesses 0 # DTB read accesses 530system.cpu.itb.write_accesses 0 # DTB write accesses | 509system.cpu.itb.inst_misses 4471 # ITB inst misses 510system.cpu.itb.read_hits 0 # DTB read hits 511system.cpu.itb.read_misses 0 # DTB read misses 512system.cpu.itb.write_hits 0 # DTB write hits 513system.cpu.itb.write_misses 0 # DTB write misses 514system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 515system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 517system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 518system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB 519system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu.itb.read_accesses 0 # DTB read accesses 524system.cpu.itb.write_accesses 0 # DTB write accesses |
| 531system.cpu.itb.inst_accesses 61498403 # ITB inst accesses 532system.cpu.itb.hits 61493932 # DTB hits | 525system.cpu.itb.inst_accesses 61498384 # ITB inst accesses 526system.cpu.itb.hits 61493913 # DTB hits |
| 533system.cpu.itb.misses 4471 # DTB misses | 527system.cpu.itb.misses 4471 # DTB misses |
| 534system.cpu.itb.accesses 61498403 # DTB accesses 535system.cpu.numCycles 5233072430 # number of cpu cycles simulated | 528system.cpu.itb.accesses 61498384 # DTB accesses 529system.cpu.numCycles 5232459694 # number of cpu cycles simulated |
| 536system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 537system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 530system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 531system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 538system.cpu.committedInsts 60200059 # Number of instructions committed 539system.cpu.committedOps 76606878 # Number of ops (including micro ops) committed 540system.cpu.num_int_alu_accesses 69208659 # Number of integer alu accesses | 532system.cpu.committedInsts 60200042 # Number of instructions committed 533system.cpu.committedOps 76606857 # Number of ops (including micro ops) committed 534system.cpu.num_int_alu_accesses 69208585 # Number of integer alu accesses |
| 541system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 542system.cpu.num_func_calls 2140468 # number of times a function call or return occured | 535system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 536system.cpu.num_func_calls 2140468 # number of times a function call or return occured |
| 543system.cpu.num_conditional_control_insts 7948676 # number of instructions that are conditional controls 544system.cpu.num_int_insts 69208659 # number of integer instructions | 537system.cpu.num_conditional_control_insts 7948679 # number of instructions that are conditional controls 538system.cpu.num_int_insts 69208585 # number of integer instructions |
| 545system.cpu.num_fp_insts 10269 # number of float instructions | 539system.cpu.num_fp_insts 10269 # number of float instructions |
| 546system.cpu.num_int_register_reads 401368432 # number of times the integer registers were read 547system.cpu.num_int_register_writes 74518953 # number of times the integer registers were written | 540system.cpu.num_int_register_reads 401368270 # number of times the integer registers were read 541system.cpu.num_int_register_writes 74518872 # number of times the integer registers were written |
| 548system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 549system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 542system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 543system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 550system.cpu.num_mem_refs 27394027 # number of memory refs 551system.cpu.num_load_insts 15660244 # Number of load instructions 552system.cpu.num_store_insts 11733783 # Number of store instructions 553system.cpu.num_idle_cycles 4581664281.608249 # Number of idle cycles 554system.cpu.num_busy_cycles 651408148.391751 # Number of busy cycles 555system.cpu.not_idle_fraction 0.124479 # Percentage of non-idle cycles 556system.cpu.idle_fraction 0.875521 # Percentage of idle cycles 557system.cpu.Branches 10308791 # Number of branches fetched | 544system.cpu.num_mem_refs 27394017 # number of memory refs 545system.cpu.num_load_insts 15660224 # Number of load instructions 546system.cpu.num_store_insts 11733793 # Number of store instructions 547system.cpu.num_idle_cycles 4581582300.610249 # Number of idle cycles 548system.cpu.num_busy_cycles 650877393.389751 # Number of busy cycles 549system.cpu.not_idle_fraction 0.124392 # Percentage of non-idle cycles 550system.cpu.idle_fraction 0.875608 # Percentage of idle cycles 551system.cpu.Branches 10308802 # Number of branches fetched 552system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction 553system.cpu.op_class::IntAlu 50389316 64.68% 64.72% # Class of executed instruction 554system.cpu.op_class::IntMult 87585 0.11% 64.83% # Class of executed instruction 555system.cpu.op_class::IntDiv 0 0.00% 64.83% # Class of executed instruction 556system.cpu.op_class::FloatAdd 0 0.00% 64.83% # Class of executed instruction 557system.cpu.op_class::FloatCmp 0 0.00% 64.83% # Class of executed instruction 558system.cpu.op_class::FloatCvt 0 0.00% 64.83% # Class of executed instruction 559system.cpu.op_class::FloatMult 0 0.00% 64.83% # Class of executed instruction 560system.cpu.op_class::FloatDiv 0 0.00% 64.83% # Class of executed instruction 561system.cpu.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction 562system.cpu.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction 563system.cpu.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction 564system.cpu.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction 565system.cpu.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction 566system.cpu.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction 567system.cpu.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction 568system.cpu.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction 569system.cpu.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction 570system.cpu.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction 571system.cpu.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction 572system.cpu.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction 573system.cpu.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction 574system.cpu.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction 575system.cpu.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction 576system.cpu.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction 577system.cpu.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction 578system.cpu.op_class::SimdFloatMisc 2109 0.00% 64.84% # Class of executed instruction 579system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction 580system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction 581system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction 582system.cpu.op_class::MemRead 15660224 20.10% 84.94% # Class of executed instruction 583system.cpu.op_class::MemWrite 11733793 15.06% 100.00% # Class of executed instruction 584system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 585system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 586system.cpu.op_class::total 77901545 # Class of executed instruction |
| 558system.cpu.kern.inst.arm 0 # number of arm instructions executed | 587system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 559system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed 560system.cpu.icache.tags.replacements 856277 # number of replacements 561system.cpu.icache.tags.tagsinuse 510.865256 # Cycle average of tags in use 562system.cpu.icache.tags.total_refs 60637143 # Total number of references to valid blocks. 563system.cpu.icache.tags.sampled_refs 856789 # Sample count of references to valid blocks. 564system.cpu.icache.tags.avg_refs 70.772551 # Average number of references to valid blocks. 565system.cpu.icache.tags.warmup_cycle 20019652250 # Cycle when the warmup percentage was hit. 566system.cpu.icache.tags.occ_blocks::cpu.inst 510.865256 # Average occupied blocks per requestor 567system.cpu.icache.tags.occ_percent::cpu.inst 0.997784 # Average percentage of cache occupancy 568system.cpu.icache.tags.occ_percent::total 0.997784 # Average percentage of cache occupancy | 588system.cpu.kern.inst.quiesce 83017 # number of quiesce instructions executed 589system.cpu.icache.tags.replacements 856351 # number of replacements 590system.cpu.icache.tags.tagsinuse 510.866135 # Cycle average of tags in use 591system.cpu.icache.tags.total_refs 60637050 # Total number of references to valid blocks. 592system.cpu.icache.tags.sampled_refs 856863 # Sample count of references to valid blocks. 593system.cpu.icache.tags.avg_refs 70.766330 # Average number of references to valid blocks. 594system.cpu.icache.tags.warmup_cycle 20005377250 # Cycle when the warmup percentage was hit. 595system.cpu.icache.tags.occ_blocks::cpu.inst 510.866135 # Average occupied blocks per requestor 596system.cpu.icache.tags.occ_percent::cpu.inst 0.997785 # Average percentage of cache occupancy 597system.cpu.icache.tags.occ_percent::total 0.997785 # Average percentage of cache occupancy |
| 569system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 570system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id | 598system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 599system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id |
| 571system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 572system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id | 600system.cpu.icache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id 601system.cpu.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id |
| 573system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 574system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 602system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 603system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 575system.cpu.icache.tags.tag_accesses 62350721 # Number of tag accesses 576system.cpu.icache.tags.data_accesses 62350721 # Number of data accesses 577system.cpu.icache.ReadReq_hits::cpu.inst 60637143 # number of ReadReq hits 578system.cpu.icache.ReadReq_hits::total 60637143 # number of ReadReq hits 579system.cpu.icache.demand_hits::cpu.inst 60637143 # number of demand (read+write) hits 580system.cpu.icache.demand_hits::total 60637143 # number of demand (read+write) hits 581system.cpu.icache.overall_hits::cpu.inst 60637143 # number of overall hits 582system.cpu.icache.overall_hits::total 60637143 # number of overall hits 583system.cpu.icache.ReadReq_misses::cpu.inst 856789 # number of ReadReq misses 584system.cpu.icache.ReadReq_misses::total 856789 # number of ReadReq misses 585system.cpu.icache.demand_misses::cpu.inst 856789 # number of demand (read+write) misses 586system.cpu.icache.demand_misses::total 856789 # number of demand (read+write) misses 587system.cpu.icache.overall_misses::cpu.inst 856789 # number of overall misses 588system.cpu.icache.overall_misses::total 856789 # number of overall misses 589system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768796500 # number of ReadReq miss cycles 590system.cpu.icache.ReadReq_miss_latency::total 11768796500 # number of ReadReq miss cycles 591system.cpu.icache.demand_miss_latency::cpu.inst 11768796500 # number of demand (read+write) miss cycles 592system.cpu.icache.demand_miss_latency::total 11768796500 # number of demand (read+write) miss cycles 593system.cpu.icache.overall_miss_latency::cpu.inst 11768796500 # number of overall miss cycles 594system.cpu.icache.overall_miss_latency::total 11768796500 # number of overall miss cycles 595system.cpu.icache.ReadReq_accesses::cpu.inst 61493932 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.ReadReq_accesses::total 61493932 # number of ReadReq accesses(hits+misses) 597system.cpu.icache.demand_accesses::cpu.inst 61493932 # number of demand (read+write) accesses 598system.cpu.icache.demand_accesses::total 61493932 # number of demand (read+write) accesses 599system.cpu.icache.overall_accesses::cpu.inst 61493932 # number of overall (read+write) accesses 600system.cpu.icache.overall_accesses::total 61493932 # number of overall (read+write) accesses 601system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses 602system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses 603system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses 604system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses 605system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses 606system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses 607system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.933234 # average ReadReq miss latency 608system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234 # average ReadReq miss latency 609system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency 610system.cpu.icache.demand_avg_miss_latency::total 13735.933234 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency 612system.cpu.icache.overall_avg_miss_latency::total 13735.933234 # average overall miss latency | 604system.cpu.icache.tags.tag_accesses 62350776 # Number of tag accesses 605system.cpu.icache.tags.data_accesses 62350776 # Number of data accesses 606system.cpu.icache.ReadReq_hits::cpu.inst 60637050 # number of ReadReq hits 607system.cpu.icache.ReadReq_hits::total 60637050 # number of ReadReq hits 608system.cpu.icache.demand_hits::cpu.inst 60637050 # number of demand (read+write) hits 609system.cpu.icache.demand_hits::total 60637050 # number of demand (read+write) hits 610system.cpu.icache.overall_hits::cpu.inst 60637050 # number of overall hits 611system.cpu.icache.overall_hits::total 60637050 # number of overall hits 612system.cpu.icache.ReadReq_misses::cpu.inst 856863 # number of ReadReq misses 613system.cpu.icache.ReadReq_misses::total 856863 # number of ReadReq misses 614system.cpu.icache.demand_misses::cpu.inst 856863 # number of demand (read+write) misses 615system.cpu.icache.demand_misses::total 856863 # number of demand (read+write) misses 616system.cpu.icache.overall_misses::cpu.inst 856863 # number of overall misses 617system.cpu.icache.overall_misses::total 856863 # number of overall misses 618system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766560750 # number of ReadReq miss cycles 619system.cpu.icache.ReadReq_miss_latency::total 11766560750 # number of ReadReq miss cycles 620system.cpu.icache.demand_miss_latency::cpu.inst 11766560750 # number of demand (read+write) miss cycles 621system.cpu.icache.demand_miss_latency::total 11766560750 # number of demand (read+write) miss cycles 622system.cpu.icache.overall_miss_latency::cpu.inst 11766560750 # number of overall miss cycles 623system.cpu.icache.overall_miss_latency::total 11766560750 # number of overall miss cycles 624system.cpu.icache.ReadReq_accesses::cpu.inst 61493913 # number of ReadReq accesses(hits+misses) 625system.cpu.icache.ReadReq_accesses::total 61493913 # number of ReadReq accesses(hits+misses) 626system.cpu.icache.demand_accesses::cpu.inst 61493913 # number of demand (read+write) accesses 627system.cpu.icache.demand_accesses::total 61493913 # number of demand (read+write) accesses 628system.cpu.icache.overall_accesses::cpu.inst 61493913 # number of overall (read+write) accesses 629system.cpu.icache.overall_accesses::total 61493913 # number of overall (read+write) accesses 630system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses 631system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses 632system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses 633system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses 634system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses 635system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses 636system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751 # average ReadReq miss latency 637system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751 # average ReadReq miss latency 638system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency 639system.cpu.icache.demand_avg_miss_latency::total 13732.137751 # average overall miss latency 640system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency 641system.cpu.icache.overall_avg_miss_latency::total 13732.137751 # average overall miss latency |
| 613system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 614system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 615system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 616system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 617system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 618system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu.icache.fast_writes 0 # number of fast writes performed 620system.cpu.icache.cache_copies 0 # number of cache copies performed | 642system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 643system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 647system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.icache.fast_writes 0 # number of fast writes performed 649system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 621system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856789 # number of ReadReq MSHR misses 622system.cpu.icache.ReadReq_mshr_misses::total 856789 # number of ReadReq MSHR misses 623system.cpu.icache.demand_mshr_misses::cpu.inst 856789 # number of demand (read+write) MSHR misses 624system.cpu.icache.demand_mshr_misses::total 856789 # number of demand (read+write) MSHR misses 625system.cpu.icache.overall_mshr_misses::cpu.inst 856789 # number of overall MSHR misses 626system.cpu.icache.overall_mshr_misses::total 856789 # number of overall MSHR misses 627system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051259500 # number of ReadReq MSHR miss cycles 628system.cpu.icache.ReadReq_mshr_miss_latency::total 10051259500 # number of ReadReq MSHR miss cycles 629system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051259500 # number of demand (read+write) MSHR miss cycles 630system.cpu.icache.demand_mshr_miss_latency::total 10051259500 # number of demand (read+write) MSHR miss cycles 631system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051259500 # number of overall MSHR miss cycles 632system.cpu.icache.overall_mshr_miss_latency::total 10051259500 # number of overall MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 442799750 # number of ReadReq MSHR uncacheable cycles 634system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 442799750 # number of ReadReq MSHR uncacheable cycles 635system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 442799750 # number of overall MSHR uncacheable cycles 636system.cpu.icache.overall_mshr_uncacheable_latency::total 442799750 # number of overall MSHR uncacheable cycles 637system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses 638system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses 639system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses 640system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses 641system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses 642system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses 643system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.312494 # average ReadReq mshr miss latency 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.312494 # average ReadReq mshr miss latency 645system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency 647system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency | 650system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856863 # number of ReadReq MSHR misses 651system.cpu.icache.ReadReq_mshr_misses::total 856863 # number of ReadReq MSHR misses 652system.cpu.icache.demand_mshr_misses::cpu.inst 856863 # number of demand (read+write) MSHR misses 653system.cpu.icache.demand_mshr_misses::total 856863 # number of demand (read+write) MSHR misses 654system.cpu.icache.overall_mshr_misses::cpu.inst 856863 # number of overall MSHR misses 655system.cpu.icache.overall_mshr_misses::total 856863 # number of overall MSHR misses 656system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10048829250 # number of ReadReq MSHR miss cycles 657system.cpu.icache.ReadReq_mshr_miss_latency::total 10048829250 # number of ReadReq MSHR miss cycles 658system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10048829250 # number of demand (read+write) MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::total 10048829250 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10048829250 # number of overall MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::total 10048829250 # number of overall MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 441046000 # 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average ReadReq mshr miss latency 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11727.463142 # average ReadReq mshr miss latency 674system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency 676system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency |
| 649system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 650system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 651system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 652system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 653system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 678system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 679system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 680system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 681system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 682system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 654system.cpu.l2cache.tags.replacements 62510 # number of replacements 655system.cpu.l2cache.tags.tagsinuse 50754.341814 # Cycle average of tags in use 656system.cpu.l2cache.tags.total_refs 1682268 # Total number of references to valid blocks. 657system.cpu.l2cache.tags.sampled_refs 127892 # Sample count of references to valid blocks. 658system.cpu.l2cache.tags.avg_refs 13.153817 # Average number of references to valid blocks. 659system.cpu.l2cache.tags.warmup_cycle 2565667436000 # Cycle when the warmup percentage was hit. 660system.cpu.l2cache.tags.occ_blocks::writebacks 37718.224228 # Average occupied blocks per requestor 661system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884316 # Average occupied blocks per requestor | 683system.cpu.l2cache.tags.replacements 62506 # number of replacements 684system.cpu.l2cache.tags.tagsinuse 50753.322403 # Cycle average of tags in use 685system.cpu.l2cache.tags.total_refs 1682121 # Total number of references to valid blocks. 686system.cpu.l2cache.tags.sampled_refs 127886 # Sample count of references to valid blocks. 687system.cpu.l2cache.tags.avg_refs 13.153285 # Average number of references to valid blocks. 688system.cpu.l2cache.tags.warmup_cycle 2565374310000 # Cycle when the warmup percentage was hit. 689system.cpu.l2cache.tags.occ_blocks::writebacks 37717.253716 # Average occupied blocks per requestor 690system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884318 # Average occupied blocks per requestor |
| 662system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor | 691system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor |
| 663system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.295627 # Average occupied blocks per requestor 664system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.936941 # Average occupied blocks per requestor 665system.cpu.l2cache.tags.occ_percent::writebacks 0.575534 # Average percentage of cache occupancy | 692system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.225103 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.958564 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_percent::writebacks 0.575520 # Average percentage of cache occupancy |
| 666system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 667system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 695system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 696system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 668system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106709 # Average percentage of cache occupancy | 697system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106708 # Average percentage of cache occupancy |
| 669system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy | 698system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy |
| 670system.cpu.l2cache.tags.occ_percent::total 0.774450 # Average percentage of cache occupancy | 699system.cpu.l2cache.tags.occ_percent::total 0.774434 # Average percentage of cache occupancy |
| 671system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id | 700system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id |
| 672system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id | 701system.cpu.l2cache.tags.occ_task_id_blocks::1024 65376 # Occupied blocks per task id |
| 673system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id | 702system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id |
| 674system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id | 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id |
| 675system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id | 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id |
| 676system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2162 # Occupied blocks per task id 677system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6903 # Occupied blocks per task id 678system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56263 # Occupied blocks per task id | 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2163 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6647 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56517 # Occupied blocks per task id |
| 679system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id | 708system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id |
| 680system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id 681system.cpu.l2cache.tags.tag_accesses 17138143 # Number of tag accesses 682system.cpu.l2cache.tags.data_accesses 17138143 # Number of data accesses 683system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8709 # number of ReadReq hits 684system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits 685system.cpu.l2cache.ReadReq_hits::cpu.inst 844568 # number of ReadReq hits 686system.cpu.l2cache.ReadReq_hits::cpu.data 369661 # number of ReadReq hits 687system.cpu.l2cache.ReadReq_hits::total 1226471 # number of ReadReq hits 688system.cpu.l2cache.Writeback_hits::writebacks 595273 # number of Writeback hits 689system.cpu.l2cache.Writeback_hits::total 595273 # number of Writeback hits | 709system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997559 # Percentage of cache occupancy per task id 710system.cpu.l2cache.tags.tag_accesses 17140869 # Number of tag accesses 711system.cpu.l2cache.tags.data_accesses 17140869 # Number of data accesses 712system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8713 # number of ReadReq hits 713system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3537 # number of ReadReq hits 714system.cpu.l2cache.ReadReq_hits::cpu.inst 844650 # number of ReadReq hits 715system.cpu.l2cache.ReadReq_hits::cpu.data 369794 # number of ReadReq hits 716system.cpu.l2cache.ReadReq_hits::total 1226694 # number of ReadReq hits 717system.cpu.l2cache.Writeback_hits::writebacks 595396 # number of Writeback hits 718system.cpu.l2cache.Writeback_hits::total 595396 # number of Writeback hits |
| 690system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 691system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits | 719system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 720system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits |
| 692system.cpu.l2cache.ReadExReq_hits::cpu.data 113398 # number of ReadExReq hits 693system.cpu.l2cache.ReadExReq_hits::total 113398 # number of ReadExReq hits 694system.cpu.l2cache.demand_hits::cpu.dtb.walker 8709 # number of demand (read+write) hits 695system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits 696system.cpu.l2cache.demand_hits::cpu.inst 844568 # number of demand (read+write) hits 697system.cpu.l2cache.demand_hits::cpu.data 483059 # number of demand (read+write) hits 698system.cpu.l2cache.demand_hits::total 1339869 # number of demand (read+write) hits 699system.cpu.l2cache.overall_hits::cpu.dtb.walker 8709 # number of overall hits 700system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits 701system.cpu.l2cache.overall_hits::cpu.inst 844568 # number of overall hits 702system.cpu.l2cache.overall_hits::cpu.data 483059 # number of overall hits 703system.cpu.l2cache.overall_hits::total 1339869 # number of overall hits | 721system.cpu.l2cache.ReadExReq_hits::cpu.data 113396 # number of ReadExReq hits 722system.cpu.l2cache.ReadExReq_hits::total 113396 # number of ReadExReq hits 723system.cpu.l2cache.demand_hits::cpu.dtb.walker 8713 # number of demand (read+write) hits 724system.cpu.l2cache.demand_hits::cpu.itb.walker 3537 # number of demand (read+write) hits 725system.cpu.l2cache.demand_hits::cpu.inst 844650 # number of demand (read+write) hits 726system.cpu.l2cache.demand_hits::cpu.data 483190 # number of demand (read+write) hits 727system.cpu.l2cache.demand_hits::total 1340090 # number of demand (read+write) hits 728system.cpu.l2cache.overall_hits::cpu.dtb.walker 8713 # number of overall hits 729system.cpu.l2cache.overall_hits::cpu.itb.walker 3537 # number of overall hits 730system.cpu.l2cache.overall_hits::cpu.inst 844650 # number of overall hits 731system.cpu.l2cache.overall_hits::cpu.data 483190 # number of overall hits 732system.cpu.l2cache.overall_hits::total 1340090 # number of overall hits |
| 704system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 705system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 733system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 734system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 706system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses | 735system.cpu.l2cache.ReadReq_misses::cpu.inst 10579 # number of ReadReq misses |
| 707system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses | 736system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses |
| 708system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses 709system.cpu.l2cache.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses 710system.cpu.l2cache.UpgradeReq_misses::total 2905 # number of UpgradeReq misses 711system.cpu.l2cache.ReadExReq_misses::cpu.data 133827 # number of ReadExReq misses 712system.cpu.l2cache.ReadExReq_misses::total 133827 # number of ReadExReq misses | 737system.cpu.l2cache.ReadReq_misses::total 20395 # number of ReadReq misses 738system.cpu.l2cache.UpgradeReq_misses::cpu.data 2902 # number of UpgradeReq misses 739system.cpu.l2cache.UpgradeReq_misses::total 2902 # number of UpgradeReq misses 740system.cpu.l2cache.ReadExReq_misses::cpu.data 133833 # number of ReadExReq misses 741system.cpu.l2cache.ReadExReq_misses::total 133833 # number of ReadExReq misses |
| 713system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 714system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 742system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 743system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 715system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses 716system.cpu.l2cache.demand_misses::cpu.data 143636 # number of demand (read+write) misses | 744system.cpu.l2cache.demand_misses::cpu.inst 10579 # number of demand (read+write) misses 745system.cpu.l2cache.demand_misses::cpu.data 143642 # number of demand (read+write) misses |
| 717system.cpu.l2cache.demand_misses::total 154228 # number of demand (read+write) misses 718system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 719system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 746system.cpu.l2cache.demand_misses::total 154228 # number of demand (read+write) misses 747system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 748system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 720system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses 721system.cpu.l2cache.overall_misses::cpu.data 143636 # number of overall misses | 749system.cpu.l2cache.overall_misses::cpu.inst 10579 # number of overall misses 750system.cpu.l2cache.overall_misses::cpu.data 143642 # number of overall misses |
| 722system.cpu.l2cache.overall_misses::total 154228 # number of overall misses | 751system.cpu.l2cache.overall_misses::total 154228 # number of overall misses |
| 723system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 397250 # number of ReadReq miss cycles | 752system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles |
| 724system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles | 753system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles |
| 725system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747154500 # number of ReadReq miss cycles 726system.cpu.l2cache.ReadReq_miss_latency::cpu.data 739313250 # number of ReadReq miss cycles 727system.cpu.l2cache.ReadReq_miss_latency::total 1487015000 # number of ReadReq miss cycles | 754system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 743832250 # number of ReadReq miss cycles 755system.cpu.l2cache.ReadReq_miss_latency::cpu.data 729584000 # number of ReadReq miss cycles 756system.cpu.l2cache.ReadReq_miss_latency::total 1473871500 # number of ReadReq miss cycles |
| 728system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles 729system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles | 757system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles 758system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles |
| 730system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9526600640 # number of ReadExReq miss cycles 731system.cpu.l2cache.ReadExReq_miss_latency::total 9526600640 # number of ReadExReq miss cycles 732system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 397250 # number of demand (read+write) miss cycles | 759system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9271605886 # number of ReadExReq miss cycles 760system.cpu.l2cache.ReadExReq_miss_latency::total 9271605886 # number of ReadExReq miss cycles 761system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles |
| 733system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles | 762system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles |
| 734system.cpu.l2cache.demand_miss_latency::cpu.inst 747154500 # number of demand (read+write) miss cycles 735system.cpu.l2cache.demand_miss_latency::cpu.data 10265913890 # number of demand (read+write) miss cycles 736system.cpu.l2cache.demand_miss_latency::total 11013615640 # number of demand (read+write) miss cycles 737system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 397250 # number of overall miss cycles | 763system.cpu.l2cache.demand_miss_latency::cpu.inst 743832250 # number of demand (read+write) miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.data 10001189886 # number of demand (read+write) miss cycles 765system.cpu.l2cache.demand_miss_latency::total 10745477386 # number of demand (read+write) miss cycles 766system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles |
| 738system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles | 767system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles |
| 739system.cpu.l2cache.overall_miss_latency::cpu.inst 747154500 # number of overall miss cycles 740system.cpu.l2cache.overall_miss_latency::cpu.data 10265913890 # number of overall miss cycles 741system.cpu.l2cache.overall_miss_latency::total 11013615640 # number of overall miss cycles 742system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8714 # number of ReadReq accesses(hits+misses) 743system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses) 744system.cpu.l2cache.ReadReq_accesses::cpu.inst 855153 # number of ReadReq accesses(hits+misses) 745system.cpu.l2cache.ReadReq_accesses::cpu.data 379470 # number of ReadReq accesses(hits+misses) 746system.cpu.l2cache.ReadReq_accesses::total 1246872 # number of ReadReq accesses(hits+misses) 747system.cpu.l2cache.Writeback_accesses::writebacks 595273 # number of Writeback accesses(hits+misses) 748system.cpu.l2cache.Writeback_accesses::total 595273 # number of Writeback accesses(hits+misses) 749system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2931 # number of UpgradeReq accesses(hits+misses) 750system.cpu.l2cache.UpgradeReq_accesses::total 2931 # number of UpgradeReq accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::cpu.data 247225 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.ReadExReq_accesses::total 247225 # number of ReadExReq accesses(hits+misses) 753system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8714 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses 755system.cpu.l2cache.demand_accesses::cpu.inst 855153 # number of demand (read+write) accesses 756system.cpu.l2cache.demand_accesses::cpu.data 626695 # number of demand (read+write) accesses 757system.cpu.l2cache.demand_accesses::total 1494097 # number of demand (read+write) accesses 758system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8714 # number of overall (read+write) accesses 759system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses 760system.cpu.l2cache.overall_accesses::cpu.inst 855153 # number of overall (read+write) accesses 761system.cpu.l2cache.overall_accesses::cpu.data 626695 # number of overall (read+write) accesses 762system.cpu.l2cache.overall_accesses::total 1494097 # number of overall (read+write) accesses | 768system.cpu.l2cache.overall_miss_latency::cpu.inst 743832250 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.data 10001189886 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::total 10745477386 # number of overall miss cycles 771system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8718 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3539 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.ReadReq_accesses::cpu.inst 855229 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.ReadReq_accesses::cpu.data 379603 # number of ReadReq accesses(hits+misses) 775system.cpu.l2cache.ReadReq_accesses::total 1247089 # number of ReadReq accesses(hits+misses) 776system.cpu.l2cache.Writeback_accesses::writebacks 595396 # number of Writeback accesses(hits+misses) 777system.cpu.l2cache.Writeback_accesses::total 595396 # number of Writeback accesses(hits+misses) 778system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2928 # number of UpgradeReq accesses(hits+misses) 779system.cpu.l2cache.UpgradeReq_accesses::total 2928 # number of UpgradeReq accesses(hits+misses) 780system.cpu.l2cache.ReadExReq_accesses::cpu.data 247229 # number of ReadExReq accesses(hits+misses) 781system.cpu.l2cache.ReadExReq_accesses::total 247229 # number of ReadExReq accesses(hits+misses) 782system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8718 # number of demand (read+write) accesses 783system.cpu.l2cache.demand_accesses::cpu.itb.walker 3539 # number of demand (read+write) accesses 784system.cpu.l2cache.demand_accesses::cpu.inst 855229 # number of demand (read+write) accesses 785system.cpu.l2cache.demand_accesses::cpu.data 626832 # number of demand (read+write) accesses 786system.cpu.l2cache.demand_accesses::total 1494318 # number of demand (read+write) accesses 787system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8718 # number of overall (read+write) accesses 788system.cpu.l2cache.overall_accesses::cpu.itb.walker 3539 # number of overall (read+write) accesses 789system.cpu.l2cache.overall_accesses::cpu.inst 855229 # number of overall (read+write) accesses 790system.cpu.l2cache.overall_accesses::cpu.data 626832 # number of overall (read+write) accesses 791system.cpu.l2cache.overall_accesses::total 1494318 # number of overall (read+write) accesses |
| 763system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses | 792system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses |
| 764system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses 765system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses 766system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025849 # miss rate for ReadReq accesses 767system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses 768system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991129 # miss rate for UpgradeReq accesses 769system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991129 # miss rate for UpgradeReq accesses 770system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541317 # miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_miss_rate::total 0.541317 # miss rate for ReadExReq accesses | 793system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses 794system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012370 # miss rate for ReadReq accesses 795system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025840 # miss rate for ReadReq accesses 796system.cpu.l2cache.ReadReq_miss_rate::total 0.016354 # miss rate for ReadReq accesses 797system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991120 # miss rate for UpgradeReq accesses 798system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991120 # miss rate for UpgradeReq accesses 799system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541332 # miss rate for ReadExReq accesses 800system.cpu.l2cache.ReadExReq_miss_rate::total 0.541332 # miss rate for ReadExReq accesses |
| 772system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses | 801system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses |
| 773system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses 774system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses 775system.cpu.l2cache.demand_miss_rate::cpu.data 0.229196 # miss rate for demand accesses 776system.cpu.l2cache.demand_miss_rate::total 0.103225 # miss rate for demand accesses | 802system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses 803system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012370 # miss rate for demand accesses 804system.cpu.l2cache.demand_miss_rate::cpu.data 0.229155 # miss rate for demand accesses 805system.cpu.l2cache.demand_miss_rate::total 0.103210 # miss rate for demand accesses |
| 777system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses | 806system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses |
| 778system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses 779system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses 780system.cpu.l2cache.overall_miss_rate::cpu.data 0.229196 # miss rate for overall accesses 781system.cpu.l2cache.overall_miss_rate::total 0.103225 # miss rate for overall accesses 782system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79450 # average ReadReq miss latency | 807system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses 808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012370 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.data 0.229155 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::total 0.103210 # miss rate for overall accesses 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency |
| 783system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency | 812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency |
| 784system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70586.159660 # average ReadReq miss latency 785system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75370.909369 # average ReadReq miss latency 786system.cpu.l2cache.ReadReq_avg_miss_latency::total 72889.319151 # average ReadReq miss latency 787system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.783133 # average UpgradeReq miss latency 788system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.783133 # average UpgradeReq miss latency 789system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71185.938861 # average ReadExReq miss latency 790system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71185.938861 # average ReadExReq miss latency 791system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency | 813system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70312.151432 # average ReadReq miss latency 814system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74379.039657 # average ReadReq miss latency 815system.cpu.l2cache.ReadReq_avg_miss_latency::total 72266.315273 # average ReadReq miss latency 816system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.950379 # average UpgradeReq miss latency 817system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.950379 # average UpgradeReq miss latency 818system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69277.426987 # average ReadExReq miss latency 819system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69277.426987 # average ReadExReq miss latency 820system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency |
| 792system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency | 821system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency |
| 793system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency 794system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::total 71411.258915 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency | 822system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency 823system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency 824system.cpu.l2cache.demand_avg_miss_latency::total 69672.675429 # average overall miss latency 825system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency |
| 797system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency | 826system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency |
| 798system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::total 71411.258915 # average overall miss latency | 827system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency 828system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency 829system.cpu.l2cache.overall_avg_miss_latency::total 69672.675429 # average overall miss latency |
| 801system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu.l2cache.fast_writes 0 # number of fast writes performed 808system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 830system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 831system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 832system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 833system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 834system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 835system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 836system.cpu.l2cache.fast_writes 0 # number of fast writes performed 837system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
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| 820system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 849system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
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| 829system.cpu.l2cache.overall_mshr_misses::total 154228 # number of overall MSHR misses | 858system.cpu.l2cache.overall_mshr_misses::total 154228 # number of overall MSHR misses |
| 830system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 335750 # number of ReadReq MSHR miss cycles | 859system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles |
| 831system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles | 860system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles |
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| 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 614626500 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8468464110 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 9083551360 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 335750 # number of overall MSHR miss cycles | 870system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611350250 # number of demand (read+write) MSHR miss cycles 871system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8203747614 # number of demand (read+write) MSHR miss cycles 872system.cpu.l2cache.demand_mshr_miss_latency::total 8815465614 # number of demand (read+write) MSHR miss cycles 873system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles |
| 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles | 874system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles |
| 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 614626500 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8468464110 # number of overall MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::total 9083551360 # number of overall MSHR miss cycles 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 351469750 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664489250 # number of ReadReq MSHR uncacheable cycles 851system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167015959000 # number of ReadReq MSHR uncacheable cycles 852system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706272596 # number of WriteReq MSHR uncacheable cycles 853system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706272596 # number of WriteReq MSHR uncacheable cycles 854system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 351469750 # number of overall MSHR uncacheable cycles 855system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370761846 # number of overall MSHR uncacheable cycles 856system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183722231596 # number of overall MSHR uncacheable cycles | 875system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611350250 # number of overall MSHR miss cycles 876system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8203747614 # number of overall MSHR miss cycles 877system.cpu.l2cache.overall_mshr_miss_latency::total 8815465614 # number of overall MSHR miss cycles 878system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 349718500 # number of ReadReq MSHR uncacheable cycles 879system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664427750 # number of ReadReq MSHR uncacheable cycles 880system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014146250 # number of ReadReq MSHR uncacheable cycles 881system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706100672 # number of WriteReq MSHR uncacheable cycles 882system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706100672 # number of WriteReq MSHR uncacheable cycles 883system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349718500 # number of overall MSHR uncacheable cycles 884system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370528422 # number of overall MSHR uncacheable cycles 885system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720246922 # number of overall MSHR uncacheable cycles |
| 857system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses | 886system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses |
| 858system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses 859system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses 860system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025849 # mshr miss rate for ReadReq accesses 861system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses 862system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991129 # mshr miss rate for UpgradeReq accesses 863system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991129 # mshr miss rate for UpgradeReq accesses 864system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541317 # mshr miss rate for ReadExReq accesses 865system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541317 # mshr miss rate for ReadExReq accesses | 887system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025840 # mshr miss rate for ReadReq accesses 890system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016354 # mshr miss rate for ReadReq accesses 891system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991120 # mshr miss rate for UpgradeReq accesses 892system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991120 # mshr miss rate for UpgradeReq accesses 893system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541332 # mshr miss rate for ReadExReq accesses 894system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541332 # mshr miss rate for ReadExReq accesses |
| 866system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses | 895system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses |
| 867system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses 868system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses 869system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for demand accesses 870system.cpu.l2cache.demand_mshr_miss_rate::total 0.103225 # mshr miss rate for demand accesses | 896system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses 897system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for demand accesses 898system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for demand accesses 899system.cpu.l2cache.demand_mshr_miss_rate::total 0.103210 # mshr miss rate for demand accesses |
| 871system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses | 900system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses |
| 872system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses 873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses 874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for overall accesses 875system.cpu.l2cache.overall_mshr_miss_rate::total 0.103225 # mshr miss rate for overall accesses 876system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average ReadReq mshr miss latency | 901system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses 902system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for overall accesses 903system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for overall accesses 904system.cpu.l2cache.overall_mshr_miss_rate::total 0.103210 # mshr miss rate for overall accesses 905system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency |
| 877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency | 906system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency |
| 878system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58065.800661 # average ReadReq mshr miss latency 879system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62844.046284 # average ReadReq mshr miss latency 880system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60365.888927 # average ReadReq mshr miss latency 881system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.376936 # average UpgradeReq mshr miss latency 882system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.376936 # average UpgradeReq mshr miss latency 883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.964798 # average ReadExReq mshr miss latency 884system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.964798 # average ReadExReq mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency | 907system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57789.039607 # average ReadReq mshr miss latency 908system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61852.533388 # average ReadReq mshr miss latency 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59741.578818 # average ReadReq mshr miss latency 910system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.033770 # average UpgradeReq mshr miss latency 911system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.033770 # average UpgradeReq mshr miss latency 912system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56765.043853 # average ReadExReq mshr miss latency 913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56765.043853 # average ReadExReq mshr miss latency 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency |
| 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency | 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency |
| 891system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency | 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency 923system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency |
| 895system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 896system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 897system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 898system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 899system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 900system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 901system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 902system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 903system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 924system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 925system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 926system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 927system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 928system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 929system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 930system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 931system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 932system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 904system.cpu.dcache.tags.replacements 626183 # number of replacements 905system.cpu.dcache.tags.tagsinuse 511.875243 # Cycle average of tags in use 906system.cpu.dcache.tags.total_refs 23656065 # Total number of references to valid blocks. 907system.cpu.dcache.tags.sampled_refs 626695 # Sample count of references to valid blocks. 908system.cpu.dcache.tags.avg_refs 37.747333 # Average number of references to valid blocks. 909system.cpu.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit. 910system.cpu.dcache.tags.occ_blocks::cpu.data 511.875243 # Average occupied blocks per requestor 911system.cpu.dcache.tags.occ_percent::cpu.data 0.999756 # Average percentage of cache occupancy 912system.cpu.dcache.tags.occ_percent::total 0.999756 # Average percentage of cache occupancy | 933system.cpu.dcache.tags.replacements 626320 # number of replacements 934system.cpu.dcache.tags.tagsinuse 511.875633 # Cycle average of tags in use 935system.cpu.dcache.tags.total_refs 23655948 # Total number of references to valid blocks. 936system.cpu.dcache.tags.sampled_refs 626832 # Sample count of references to valid blocks. 937system.cpu.dcache.tags.avg_refs 37.738897 # Average number of references to valid blocks. 938system.cpu.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. 939system.cpu.dcache.tags.occ_blocks::cpu.data 511.875633 # Average occupied blocks per requestor 940system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy 941system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy |
| 913system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 942system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 914system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 915system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 916system.cpu.dcache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id | 943system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 944system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 945system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id |
| 917system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 918system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 946system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 947system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 919system.cpu.dcache.tags.tag_accesses 97757735 # Number of tag accesses 920system.cpu.dcache.tags.data_accesses 97757735 # Number of data accesses 921system.cpu.dcache.ReadReq_hits::cpu.data 13196205 # number of ReadReq hits 922system.cpu.dcache.ReadReq_hits::total 13196205 # number of ReadReq hits 923system.cpu.dcache.WriteReq_hits::cpu.data 9972754 # number of WriteReq hits 924system.cpu.dcache.WriteReq_hits::total 9972754 # number of WriteReq hits 925system.cpu.dcache.LoadLockedReq_hits::cpu.data 236397 # number of LoadLockedReq hits 926system.cpu.dcache.LoadLockedReq_hits::total 236397 # number of LoadLockedReq hits 927system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits 928system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits 929system.cpu.dcache.demand_hits::cpu.data 23168959 # number of demand (read+write) hits 930system.cpu.dcache.demand_hits::total 23168959 # number of demand (read+write) hits 931system.cpu.dcache.overall_hits::cpu.data 23168959 # number of overall hits 932system.cpu.dcache.overall_hits::total 23168959 # number of overall hits 933system.cpu.dcache.ReadReq_misses::cpu.data 368088 # number of ReadReq misses 934system.cpu.dcache.ReadReq_misses::total 368088 # number of ReadReq misses 935system.cpu.dcache.WriteReq_misses::cpu.data 250156 # number of WriteReq misses 936system.cpu.dcache.WriteReq_misses::total 250156 # number of WriteReq misses 937system.cpu.dcache.LoadLockedReq_misses::cpu.data 11382 # number of LoadLockedReq misses 938system.cpu.dcache.LoadLockedReq_misses::total 11382 # number of LoadLockedReq misses 939system.cpu.dcache.demand_misses::cpu.data 618244 # number of demand (read+write) misses 940system.cpu.dcache.demand_misses::total 618244 # number of demand (read+write) misses 941system.cpu.dcache.overall_misses::cpu.data 618244 # number of overall misses 942system.cpu.dcache.overall_misses::total 618244 # number of overall misses 943system.cpu.dcache.ReadReq_miss_latency::cpu.data 5418733500 # number of ReadReq miss cycles 944system.cpu.dcache.ReadReq_miss_latency::total 5418733500 # number of ReadReq miss cycles 945system.cpu.dcache.WriteReq_miss_latency::cpu.data 11526229765 # number of WriteReq miss cycles 946system.cpu.dcache.WriteReq_miss_latency::total 11526229765 # number of WriteReq miss cycles 947system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157891250 # number of LoadLockedReq miss cycles 948system.cpu.dcache.LoadLockedReq_miss_latency::total 157891250 # number of LoadLockedReq miss cycles 949system.cpu.dcache.demand_miss_latency::cpu.data 16944963265 # number of demand (read+write) miss cycles 950system.cpu.dcache.demand_miss_latency::total 16944963265 # number of demand (read+write) miss cycles 951system.cpu.dcache.overall_miss_latency::cpu.data 16944963265 # number of overall miss cycles 952system.cpu.dcache.overall_miss_latency::total 16944963265 # number of overall miss cycles 953system.cpu.dcache.ReadReq_accesses::cpu.data 13564293 # number of ReadReq accesses(hits+misses) 954system.cpu.dcache.ReadReq_accesses::total 13564293 # number of ReadReq accesses(hits+misses) 955system.cpu.dcache.WriteReq_accesses::cpu.data 10222910 # number of WriteReq accesses(hits+misses) 956system.cpu.dcache.WriteReq_accesses::total 10222910 # number of WriteReq accesses(hits+misses) 957system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) 958system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) 959system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) 960system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) 961system.cpu.dcache.demand_accesses::cpu.data 23787203 # number of demand (read+write) accesses 962system.cpu.dcache.demand_accesses::total 23787203 # number of demand (read+write) accesses 963system.cpu.dcache.overall_accesses::cpu.data 23787203 # number of overall (read+write) accesses 964system.cpu.dcache.overall_accesses::total 23787203 # number of overall (read+write) accesses 965system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027137 # miss rate for ReadReq accesses 966system.cpu.dcache.ReadReq_miss_rate::total 0.027137 # miss rate for ReadReq accesses | 948system.cpu.dcache.tags.tag_accesses 97757952 # Number of tag accesses 949system.cpu.dcache.tags.data_accesses 97757952 # Number of data accesses 950system.cpu.dcache.ReadReq_hits::cpu.data 13196101 # number of ReadReq hits 951system.cpu.dcache.ReadReq_hits::total 13196101 # number of ReadReq hits 952system.cpu.dcache.WriteReq_hits::cpu.data 9972757 # number of WriteReq hits 953system.cpu.dcache.WriteReq_hits::total 9972757 # number of WriteReq hits 954system.cpu.dcache.LoadLockedReq_hits::cpu.data 236378 # number of LoadLockedReq hits 955system.cpu.dcache.LoadLockedReq_hits::total 236378 # number of LoadLockedReq hits 956system.cpu.dcache.StoreCondReq_hits::cpu.data 247784 # number of StoreCondReq hits 957system.cpu.dcache.StoreCondReq_hits::total 247784 # number of StoreCondReq hits 958system.cpu.dcache.demand_hits::cpu.data 23168858 # number of demand (read+write) hits 959system.cpu.dcache.demand_hits::total 23168858 # number of demand (read+write) hits 960system.cpu.dcache.overall_hits::cpu.data 23168858 # number of overall hits 961system.cpu.dcache.overall_hits::total 23168858 # number of overall hits 962system.cpu.dcache.ReadReq_misses::cpu.data 368196 # number of ReadReq misses 963system.cpu.dcache.ReadReq_misses::total 368196 # number of ReadReq misses 964system.cpu.dcache.WriteReq_misses::cpu.data 250157 # number of WriteReq misses 965system.cpu.dcache.WriteReq_misses::total 250157 # number of WriteReq misses 966system.cpu.dcache.LoadLockedReq_misses::cpu.data 11407 # number of LoadLockedReq misses 967system.cpu.dcache.LoadLockedReq_misses::total 11407 # number of LoadLockedReq misses 968system.cpu.dcache.demand_misses::cpu.data 618353 # number of demand (read+write) misses 969system.cpu.dcache.demand_misses::total 618353 # number of demand (read+write) misses 970system.cpu.dcache.overall_misses::cpu.data 618353 # number of overall misses 971system.cpu.dcache.overall_misses::total 618353 # number of overall misses 972system.cpu.dcache.ReadReq_miss_latency::cpu.data 5410361250 # number of ReadReq miss cycles 973system.cpu.dcache.ReadReq_miss_latency::total 5410361250 # number of ReadReq miss cycles 974system.cpu.dcache.WriteReq_miss_latency::cpu.data 11271639016 # number of WriteReq miss cycles 975system.cpu.dcache.WriteReq_miss_latency::total 11271639016 # number of WriteReq miss cycles 976system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158326750 # number of LoadLockedReq miss cycles 977system.cpu.dcache.LoadLockedReq_miss_latency::total 158326750 # number of LoadLockedReq miss cycles 978system.cpu.dcache.demand_miss_latency::cpu.data 16682000266 # number of demand (read+write) miss cycles 979system.cpu.dcache.demand_miss_latency::total 16682000266 # number of demand (read+write) miss cycles 980system.cpu.dcache.overall_miss_latency::cpu.data 16682000266 # number of overall miss cycles 981system.cpu.dcache.overall_miss_latency::total 16682000266 # number of overall miss cycles 982system.cpu.dcache.ReadReq_accesses::cpu.data 13564297 # number of ReadReq accesses(hits+misses) 983system.cpu.dcache.ReadReq_accesses::total 13564297 # number of ReadReq accesses(hits+misses) 984system.cpu.dcache.WriteReq_accesses::cpu.data 10222914 # number of WriteReq accesses(hits+misses) 985system.cpu.dcache.WriteReq_accesses::total 10222914 # number of WriteReq accesses(hits+misses) 986system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247785 # number of LoadLockedReq accesses(hits+misses) 987system.cpu.dcache.LoadLockedReq_accesses::total 247785 # number of LoadLockedReq accesses(hits+misses) 988system.cpu.dcache.StoreCondReq_accesses::cpu.data 247784 # number of StoreCondReq accesses(hits+misses) 989system.cpu.dcache.StoreCondReq_accesses::total 247784 # number of StoreCondReq accesses(hits+misses) 990system.cpu.dcache.demand_accesses::cpu.data 23787211 # number of demand (read+write) accesses 991system.cpu.dcache.demand_accesses::total 23787211 # number of demand (read+write) accesses 992system.cpu.dcache.overall_accesses::cpu.data 23787211 # number of overall (read+write) accesses 993system.cpu.dcache.overall_accesses::total 23787211 # number of overall (read+write) accesses 994system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027144 # miss rate for ReadReq accesses 995system.cpu.dcache.ReadReq_miss_rate::total 0.027144 # miss rate for ReadReq accesses |
| 967system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses 968system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses | 996system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses 997system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses |
| 969system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045936 # miss rate for LoadLockedReq accesses 970system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045936 # miss rate for LoadLockedReq accesses 971system.cpu.dcache.demand_miss_rate::cpu.data 0.025991 # miss rate for demand accesses 972system.cpu.dcache.demand_miss_rate::total 0.025991 # miss rate for demand accesses 973system.cpu.dcache.overall_miss_rate::cpu.data 0.025991 # miss rate for overall accesses 974system.cpu.dcache.overall_miss_rate::total 0.025991 # miss rate for overall accesses 975system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983 # average ReadReq miss latency 976system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983 # average ReadReq miss latency 977system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531 # average WriteReq miss latency 978system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531 # average WriteReq miss latency 979system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827 # average LoadLockedReq miss latency 980system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827 # average LoadLockedReq miss latency 981system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency 982system.cpu.dcache.demand_avg_miss_latency::total 27408.213044 # average overall miss latency 983system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency 984system.cpu.dcache.overall_avg_miss_latency::total 27408.213044 # average overall miss latency | 998system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046036 # miss rate for LoadLockedReq accesses 999system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046036 # miss rate for LoadLockedReq accesses 1000system.cpu.dcache.demand_miss_rate::cpu.data 0.025995 # miss rate for demand accesses 1001system.cpu.dcache.demand_miss_rate::total 0.025995 # miss rate for demand accesses 1002system.cpu.dcache.overall_miss_rate::cpu.data 0.025995 # miss rate for overall accesses 1003system.cpu.dcache.overall_miss_rate::total 0.025995 # miss rate for overall accesses 1004system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14694.242333 # average ReadReq miss latency 1005system.cpu.dcache.ReadReq_avg_miss_latency::total 14694.242333 # average ReadReq miss latency 1006system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45058.259477 # average WriteReq miss latency 1007system.cpu.dcache.WriteReq_avg_miss_latency::total 45058.259477 # average WriteReq miss latency 1008system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13879.788726 # average LoadLockedReq miss latency 1009system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13879.788726 # average LoadLockedReq miss latency 1010system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency 1011system.cpu.dcache.demand_avg_miss_latency::total 26978.118107 # average overall miss latency 1012system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency 1013system.cpu.dcache.overall_avg_miss_latency::total 26978.118107 # average overall miss latency |
| 985system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 986system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 987system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 988system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 989system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 990system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 991system.cpu.dcache.fast_writes 0 # number of fast writes performed 992system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1014system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1015system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1016system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1017system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1018system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1019system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1020system.cpu.dcache.fast_writes 0 # number of fast writes performed 1021system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 993system.cpu.dcache.writebacks::writebacks 595273 # number of writebacks 994system.cpu.dcache.writebacks::total 595273 # number of writebacks 995system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368088 # number of ReadReq MSHR misses 996system.cpu.dcache.ReadReq_mshr_misses::total 368088 # number of ReadReq MSHR misses 997system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250156 # number of WriteReq MSHR misses 998system.cpu.dcache.WriteReq_mshr_misses::total 250156 # number of WriteReq MSHR misses 999system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses 1000system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses 1001system.cpu.dcache.demand_mshr_misses::cpu.data 618244 # number of demand (read+write) MSHR misses 1002system.cpu.dcache.demand_mshr_misses::total 618244 # number of demand (read+write) MSHR misses 1003system.cpu.dcache.overall_mshr_misses::cpu.data 618244 # number of overall MSHR misses 1004system.cpu.dcache.overall_mshr_misses::total 618244 # number of overall MSHR misses 1005system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4680319500 # number of ReadReq MSHR miss cycles 1006system.cpu.dcache.ReadReq_mshr_miss_latency::total 4680319500 # number of ReadReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976351235 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976351235 # number of WriteReq MSHR miss cycles 1009system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135073750 # number of LoadLockedReq MSHR miss cycles 1010system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135073750 # number of LoadLockedReq MSHR miss cycles 1011system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15656670735 # number of demand (read+write) MSHR miss cycles 1012system.cpu.dcache.demand_mshr_miss_latency::total 15656670735 # number of demand (read+write) MSHR miss cycles 1013system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15656670735 # number of overall MSHR miss cycles 1014system.cpu.dcache.overall_mshr_miss_latency::total 15656670735 # number of overall MSHR miss cycles 1015system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058625250 # number of ReadReq MSHR uncacheable cycles 1016system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058625250 # number of ReadReq MSHR uncacheable cycles 1017system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242395404 # number of WriteReq MSHR uncacheable cycles 1018system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242395404 # number of WriteReq MSHR uncacheable cycles 1019system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301020654 # number of overall MSHR uncacheable cycles 1020system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301020654 # number of overall MSHR uncacheable cycles 1021system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027137 # mshr miss rate for ReadReq accesses 1022system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027137 # mshr miss rate for ReadReq accesses | 1022system.cpu.dcache.writebacks::writebacks 595396 # number of writebacks 1023system.cpu.dcache.writebacks::total 595396 # number of writebacks 1024system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368196 # number of ReadReq MSHR misses 1025system.cpu.dcache.ReadReq_mshr_misses::total 368196 # number of ReadReq MSHR misses 1026system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250157 # number of WriteReq MSHR misses 1027system.cpu.dcache.WriteReq_mshr_misses::total 250157 # number of WriteReq MSHR misses 1028system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11407 # number of LoadLockedReq MSHR misses 1029system.cpu.dcache.LoadLockedReq_mshr_misses::total 11407 # number of LoadLockedReq MSHR misses 1030system.cpu.dcache.demand_mshr_misses::cpu.data 618353 # number of demand (read+write) MSHR misses 1031system.cpu.dcache.demand_mshr_misses::total 618353 # number of demand (read+write) MSHR misses 1032system.cpu.dcache.overall_mshr_misses::cpu.data 618353 # number of overall MSHR misses 1033system.cpu.dcache.overall_mshr_misses::total 618353 # number of overall MSHR misses 1034system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4671668750 # number of ReadReq MSHR miss cycles 1035system.cpu.dcache.ReadReq_mshr_miss_latency::total 4671668750 # number of ReadReq MSHR miss cycles 1036system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10721268984 # number of WriteReq MSHR miss cycles 1037system.cpu.dcache.WriteReq_mshr_miss_latency::total 10721268984 # number of WriteReq MSHR miss cycles 1038system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135458250 # number of LoadLockedReq MSHR miss cycles 1039system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135458250 # number of LoadLockedReq MSHR miss cycles 1040system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15392937734 # number of demand (read+write) MSHR miss cycles 1041system.cpu.dcache.demand_mshr_miss_latency::total 15392937734 # number of demand (read+write) MSHR miss cycles 1042system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15392937734 # number of overall MSHR miss cycles 1043system.cpu.dcache.overall_mshr_miss_latency::total 15392937734 # number of overall MSHR miss cycles 1044system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250 # number of ReadReq MSHR uncacheable cycles 1045system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250 # number of ReadReq MSHR uncacheable cycles 1046system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242925328 # number of WriteReq MSHR uncacheable cycles 1047system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242925328 # number of WriteReq MSHR uncacheable cycles 1048system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578 # number of overall MSHR uncacheable cycles 1049system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578 # number of overall MSHR uncacheable cycles 1050system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027144 # mshr miss rate for ReadReq accesses 1051system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027144 # mshr miss rate for ReadReq accesses |
| 1023system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses 1024system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses | 1052system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses 1053system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses |
| 1025system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045936 # mshr miss rate for LoadLockedReq accesses 1026system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045936 # mshr miss rate for LoadLockedReq accesses 1027system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for demand accesses 1028system.cpu.dcache.demand_mshr_miss_rate::total 0.025991 # mshr miss rate for demand accesses 1029system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for overall accesses 1030system.cpu.dcache.overall_mshr_miss_rate::total 0.025991 # mshr miss rate for overall accesses 1031system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915 # average ReadReq mshr miss latency 1032system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915 # average ReadReq mshr miss latency 1033system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052 # average WriteReq mshr miss latency 1034system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052 # average WriteReq mshr miss latency 1035system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423 # average LoadLockedReq mshr miss latency 1036system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423 # average LoadLockedReq mshr miss latency 1037system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency 1038system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency 1039system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency 1040system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency | 1054system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046036 # mshr miss rate for LoadLockedReq accesses 1055system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046036 # mshr miss rate for LoadLockedReq accesses 1056system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for demand accesses 1057system.cpu.dcache.demand_mshr_miss_rate::total 0.025995 # mshr miss rate for demand accesses 1058system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for overall accesses 1059system.cpu.dcache.overall_mshr_miss_rate::total 0.025995 # mshr miss rate for overall accesses 1060system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302 # average ReadReq mshr miss latency 1061system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302 # average ReadReq mshr miss latency 1062system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011 # average WriteReq mshr miss latency 1063system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011 # average WriteReq mshr miss latency 1064system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958 # average LoadLockedReq mshr miss latency 1065system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958 # average LoadLockedReq mshr miss latency 1066system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency 1067system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency 1068system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency 1069system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency |
| 1041system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1042system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1043system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1044system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1045system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1046system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1047system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1070system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1071system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1072system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1073system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1074system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1075system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1076system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1048system.cpu.toL2Bus.throughput 52967752 # Throughput (bytes/s) 1049system.cpu.toL2Bus.trans_dist::ReadReq 2454681 # Transaction distribution 1050system.cpu.toL2Bus.trans_dist::ReadResp 2454681 # Transaction distribution | 1077system.cpu.toL2Bus.throughput 52982138 # Throughput (bytes/s) 1078system.cpu.toL2Bus.trans_dist::ReadReq 2454896 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::ReadResp 2454896 # Transaction distribution |
| 1051system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution 1052system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution | 1080system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution |
| 1053system.cpu.toL2Bus.trans_dist::Writeback 595273 # Transaction distribution 1054system.cpu.toL2Bus.trans_dist::UpgradeReq 2931 # Transaction distribution 1055system.cpu.toL2Bus.trans_dist::UpgradeResp 2931 # Transaction distribution 1056system.cpu.toL2Bus.trans_dist::ReadExReq 247225 # Transaction distribution 1057system.cpu.toL2Bus.trans_dist::ReadExResp 247225 # Transaction distribution 1058system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725204 # Packet count per connected master and slave (bytes) 1059system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749577 # Packet count per connected master and slave (bytes) 1060system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12461 # Packet count per connected master and slave (bytes) 1061system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27438 # Packet count per connected master and slave (bytes) 1062system.cpu.toL2Bus.pkt_count::total 7514680 # Packet count per connected master and slave (bytes) 1063system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54756316 # Cumulative packet size per connected master and slave (bytes) 1064system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83620422 # Cumulative packet size per connected master and slave (bytes) 1065system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14140 # Cumulative packet size per connected master and slave (bytes) 1066system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34856 # Cumulative packet size per connected master and slave (bytes) 1067system.cpu.toL2Bus.tot_pkt_size::total 138425734 # Cumulative packet size per connected master and slave (bytes) 1068system.cpu.toL2Bus.data_through_bus 138425734 # Total data (bytes) 1069system.cpu.toL2Bus.snoop_data_through_bus 166308 # Total snoop data (bytes) 1070system.cpu.toL2Bus.reqLayer0.occupancy 3008713250 # Layer occupancy (ticks) | 1082system.cpu.toL2Bus.trans_dist::Writeback 595396 # Transaction distribution 1083system.cpu.toL2Bus.trans_dist::UpgradeReq 2928 # Transaction distribution 1084system.cpu.toL2Bus.trans_dist::UpgradeResp 2928 # Transaction distribution 1085system.cpu.toL2Bus.trans_dist::ReadExReq 247229 # Transaction distribution 1086system.cpu.toL2Bus.trans_dist::ReadExResp 247229 # Transaction distribution 1087system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725354 # Packet count per connected master and slave (bytes) 1088system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749970 # Packet count per connected master and slave (bytes) 1089system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12465 # Packet count per connected master and slave (bytes) 1090system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27449 # Packet count per connected master and slave (bytes) 1091system.cpu.toL2Bus.pkt_count::total 7515238 # Packet count per connected master and slave (bytes) 1092system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54761180 # Cumulative packet size per connected master and slave (bytes) 1093system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83637066 # Cumulative packet size per connected master and slave (bytes) 1094system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14156 # Cumulative packet size per connected master and slave (bytes) 1095system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34872 # Cumulative packet size per connected master and slave (bytes) 1096system.cpu.toL2Bus.tot_pkt_size::total 138447274 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu.toL2Bus.data_through_bus 138447274 # Total data (bytes) 1098system.cpu.toL2Bus.snoop_data_through_bus 166176 # Total snoop data (bytes) 1099system.cpu.toL2Bus.reqLayer0.occupancy 3009006000 # Layer occupancy (ticks) |
| 1071system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1100system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1072system.cpu.toL2Bus.respLayer0.occupancy 1295332250 # Layer occupancy (ticks) | 1101system.cpu.toL2Bus.respLayer0.occupancy 1295477750 # Layer occupancy (ticks) |
| 1073system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1102system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1074system.cpu.toL2Bus.respLayer1.occupancy 2533285861 # Layer occupancy (ticks) | 1103system.cpu.toL2Bus.respLayer1.occupancy 2533767938 # Layer occupancy (ticks) |
| 1075system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1076system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1077system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1104system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1105system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1106system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1078system.cpu.toL2Bus.respLayer3.occupancy 18724250 # Layer occupancy (ticks) | 1107system.cpu.toL2Bus.respLayer3.occupancy 18731500 # Layer occupancy (ticks) |
| 1079system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1080system.iocache.tags.replacements 0 # number of replacements 1081system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1082system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1083system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1084system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1085system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1086system.iocache.tags.tag_accesses 0 # Number of tag accesses 1087system.iocache.tags.data_accesses 0 # Number of data accesses 1088system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1089system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1090system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1091system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1092system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1093system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1094system.iocache.fast_writes 0 # number of fast writes performed 1095system.iocache.cache_copies 0 # number of cache copies performed | 1108system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1109system.iocache.tags.replacements 0 # number of replacements 1110system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1111system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1112system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1113system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1114system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1115system.iocache.tags.tag_accesses 0 # Number of tag accesses 1116system.iocache.tags.data_accesses 0 # Number of data accesses 1117system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1118system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1119system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1120system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1121system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1122system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1123system.iocache.fast_writes 0 # number of fast writes performed 1124system.iocache.cache_copies 0 # number of cache copies performed |
| 1096system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of ReadReq MSHR uncacheable cycles 1097system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000 # number of ReadReq MSHR uncacheable cycles 1098system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of overall MSHR uncacheable cycles 1099system.iocache.overall_mshr_uncacheable_latency::total 1763840630000 # number of overall MSHR uncacheable cycles | 1125system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of ReadReq MSHR uncacheable cycles 1126system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250 # number of ReadReq MSHR uncacheable cycles 1127system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of overall MSHR uncacheable cycles 1128system.iocache.overall_mshr_uncacheable_latency::total 1759698189250 # number of overall MSHR uncacheable cycles |
| 1100system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1101system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1102system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1103system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1104system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1105 1106---------- End Simulation Statistics ---------- | 1129system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1130system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1131system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1132system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1133system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1134 1135---------- End Simulation Statistics ---------- |