| stats.txt (10036:80e84beef3bb) | stats.txt (10038:7eccd14e2610) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.616536 # Number of seconds simulated 4sim_ticks 2616536483000 # Number of ticks simulated 5final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.616536 # Number of seconds simulated 4sim_ticks 2616536483000 # Number of ticks simulated 5final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 577538 # Simulator instruction rate (inst/s) 8host_op_rate 734941 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25103147507 # Simulator tick rate (ticks/s) 10host_mem_usage 400220 # Number of bytes of host memory used 11host_seconds 104.23 # Real time elapsed on the host 12sim_insts 60197580 # Number of instructions simulated 13sim_ops 76603973 # Number of ops (including micro ops) simulated | 7host_inst_rate 506890 # Simulator instruction rate (inst/s) 8host_op_rate 645039 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22032386663 # Simulator tick rate (ticks/s) 10host_mem_usage 421264 # Number of bytes of host memory used 11host_seconds 118.76 # Real time elapsed on the host 12sim_insts 60197590 # Number of instructions simulated 13sim_ops 76603983 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory 21system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory | 19system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9089752 # Number of bytes read from this memory 21system.physmem.bytes_read::total 132477536 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory |
| 24system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 24system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142063 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15494705 # Number of read requests responded to by this memory |
| 33system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3473963 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 50630877 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) |
| 44system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) | 44system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15494693 # Number of read requests accepted | 51system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4626660 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53200016 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15494705 # Number of read requests accepted |
| 55system.physmem.writeReqs 811927 # Number of write requests accepted | 55system.physmem.writeReqs 811927 # Number of write requests accepted |
| 56system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue | 56system.physmem.readBursts 15494705 # Number of DRAM read bursts, including those serviced by the write queue |
| 57system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue | 57system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue |
| 58system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM | 58system.physmem.bytesReadDRAM 991556032 # Total number of bytes read from DRAM |
| 59system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM | 59system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM |
| 61system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side | 61system.physmem.bytesReadSys 132477536 # Total read bytes from the system interface side |
| 62system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 967983 # Per bank write bursts 67system.physmem.perBankRdBursts::1 967714 # Per bank write bursts 68system.physmem.perBankRdBursts::2 967672 # Per bank write bursts 69system.physmem.perBankRdBursts::3 967769 # Per bank write bursts 70system.physmem.perBankRdBursts::4 974609 # Per bank write bursts 71system.physmem.perBankRdBursts::5 968229 # Per bank write bursts 72system.physmem.perBankRdBursts::6 967807 # Per bank write bursts 73system.physmem.perBankRdBursts::7 967736 # Per bank write bursts 74system.physmem.perBankRdBursts::8 968546 # Per bank write bursts 75system.physmem.perBankRdBursts::9 968137 # Per bank write bursts 76system.physmem.perBankRdBursts::10 967949 # Per bank write bursts 77system.physmem.perBankRdBursts::11 967746 # Per bank write bursts 78system.physmem.perBankRdBursts::12 967851 # Per bank write bursts 79system.physmem.perBankRdBursts::13 967741 # Per bank write bursts | 62system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 967983 # Per bank write bursts 67system.physmem.perBankRdBursts::1 967714 # Per bank write bursts 68system.physmem.perBankRdBursts::2 967672 # Per bank write bursts 69system.physmem.perBankRdBursts::3 967769 # Per bank write bursts 70system.physmem.perBankRdBursts::4 974609 # Per bank write bursts 71system.physmem.perBankRdBursts::5 968229 # Per bank write bursts 72system.physmem.perBankRdBursts::6 967807 # Per bank write bursts 73system.physmem.perBankRdBursts::7 967736 # Per bank write bursts 74system.physmem.perBankRdBursts::8 968546 # Per bank write bursts 75system.physmem.perBankRdBursts::9 968137 # Per bank write bursts 76system.physmem.perBankRdBursts::10 967949 # Per bank write bursts 77system.physmem.perBankRdBursts::11 967746 # Per bank write bursts 78system.physmem.perBankRdBursts::12 967851 # Per bank write bursts 79system.physmem.perBankRdBursts::13 967741 # Per bank write bursts |
| 80system.physmem.perBankRdBursts::14 967766 # Per bank write bursts | 80system.physmem.perBankRdBursts::14 967778 # Per bank write bursts |
| 81system.physmem.perBankRdBursts::15 967796 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6610 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6410 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6422 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6344 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6906 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7096 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6901 # Per bank write bursts --- 6 unchanged lines hidden (view full) --- 95system.physmem.perBankWrBursts::13 6392 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6532 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6576 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2616532122000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) | 81system.physmem.perBankRdBursts::15 967796 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6610 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6410 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6422 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6344 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6906 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7096 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6901 # Per bank write bursts --- 6 unchanged lines hidden (view full) --- 95system.physmem.perBankWrBursts::13 6392 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6532 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6576 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2616532122000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 103system.physmem.readPktSize::2 6652 # Read request sizes (log2) | 103system.physmem.readPktSize::2 6664 # Read request sizes (log2) |
| 104system.physmem.readPktSize::3 15335424 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 152617 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 57909 # Write request sizes (log2) | 104system.physmem.readPktSize::3 15335424 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 152617 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 57909 # Write request sizes (log2) |
| 115system.physmem.rdQLenPdf::0 1246989 # What read queue length does an incoming req see | 115system.physmem.rdQLenPdf::0 1247001 # What read queue length does an incoming req see |
| 116system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 2684241 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 2677986 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2686359 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 54486 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 57692 # What read queue length does an incoming req see --- 47 unchanged lines hidden (view full) --- 171system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 116system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 2684241 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 2677986 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2686359 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 54486 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 57692 # What read queue length does an incoming req see --- 47 unchanged lines hidden (view full) --- 171system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 179system.physmem.bytesPerActivate::samples 89677 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::mean 11133.273058 # Bytes accessed per row activation 181system.physmem.bytesPerActivate::gmean 1028.792401 # Bytes accessed per row activation 182system.physmem.bytesPerActivate::stdev 16712.114180 # Bytes accessed per row activation 183system.physmem.bytesPerActivate::64-71 23203 25.87% 25.87% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::128-135 14561 16.24% 42.11% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::192-199 2861 3.19% 45.30% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::256-263 2042 2.28% 47.58% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::320-327 1356 1.51% 49.09% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::384-391 1217 1.36% 50.45% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::448-455 956 1.07% 51.51% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::512-519 1130 1.26% 52.77% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::576-583 649 0.72% 53.50% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::640-647 589 0.66% 54.15% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::704-711 514 0.57% 54.73% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::768-775 694 0.77% 55.50% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::832-839 336 0.37% 55.88% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-903 266 0.30% 56.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::960-967 214 0.24% 56.41% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.22% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1088-1095 152 0.17% 57.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1216-1223 137 0.15% 57.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1280-1287 157 0.18% 57.89% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1344-1351 104 0.12% 58.01% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.56% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.67% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1536-1543 181 0.20% 60.87% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.94% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1664-1671 57 0.06% 61.01% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.05% # Bytes accessed per row activation | 179system.physmem.bytesPerActivate::samples 89676 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::mean 11133.405772 # Bytes accessed per row activation 181system.physmem.bytesPerActivate::gmean 1028.811660 # Bytes accessed per row activation 182system.physmem.bytesPerActivate::stdev 16712.159564 # Bytes accessed per row activation 183system.physmem.bytesPerActivate::64-71 23202 25.87% 25.87% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::128-135 14564 16.24% 42.11% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::192-199 2857 3.19% 45.30% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::256-263 2044 2.28% 47.58% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::320-327 1359 1.52% 49.09% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::384-391 1218 1.36% 50.45% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::448-455 957 1.07% 51.52% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::512-519 1129 1.26% 52.78% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::576-583 646 0.72% 53.50% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::640-647 589 0.66% 54.16% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::704-711 513 0.57% 54.73% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::768-775 690 0.77% 55.50% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::832-839 338 0.38% 55.87% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-903 262 0.29% 56.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::960-967 213 0.24% 56.40% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.21% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1088-1095 156 0.17% 57.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1152-1159 151 0.17% 57.56% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1216-1223 136 0.15% 57.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1280-1287 156 0.17% 57.88% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1344-1351 102 0.11% 58.00% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1408-1415 2292 2.56% 60.55% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.66% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1600-1607 63 0.07% 60.93% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1664-1671 60 0.07% 61.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1728-1735 44 0.05% 61.05% # Bytes accessed per row activation |
| 210system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation | 210system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation |
| 211system.physmem.bytesPerActivate::1856-1863 31 0.03% 61.24% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.30% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2112-2119 17 0.02% 61.65% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2176-2183 32 0.04% 61.69% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2240-2247 11 0.01% 61.70% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2304-2311 93 0.10% 61.80% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.82% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2432-2439 15 0.02% 61.84% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2496-2503 26 0.03% 61.87% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2560-2567 91 0.10% 61.97% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.98% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2688-2695 14 0.02% 62.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.01% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.19% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2880-2887 12 0.01% 62.20% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::2944-2951 12 0.01% 62.22% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.23% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3072-3079 372 0.41% 62.64% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.66% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3200-3207 19 0.02% 62.68% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.70% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3328-3335 153 0.17% 62.87% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.88% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.90% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.91% # Bytes accessed per row activation | 211system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.23% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1920-1927 30 0.03% 61.26% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.29% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2048-2055 303 0.34% 61.63% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.65% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2176-2183 33 0.04% 61.69% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2240-2247 13 0.01% 61.70% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2304-2311 97 0.11% 61.81% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2368-2375 22 0.02% 61.83% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2432-2439 14 0.02% 61.85% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2496-2503 28 0.03% 61.88% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.98% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.98% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2688-2695 19 0.02% 62.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2752-2759 14 0.02% 62.02% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.20% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2880-2887 14 0.02% 62.21% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::2944-2951 9 0.01% 62.22% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.24% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3072-3079 370 0.41% 62.65% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3136-3143 11 0.01% 62.66% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3200-3207 17 0.02% 62.68% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3264-3271 15 0.02% 62.70% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.87% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3392-3399 14 0.02% 62.88% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.91% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.92% # Bytes accessed per row activation |
| 238system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation | 238system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation |
| 239system.physmem.bytesPerActivate::3648-3655 10 0.01% 63.04% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.06% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.10% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.21% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3968-3975 14 0.02% 63.23% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation | 239system.physmem.bytesPerActivate::3648-3655 12 0.01% 63.04% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.06% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3776-3783 37 0.04% 63.10% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.20% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3904-3911 13 0.01% 63.22% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4032-4039 11 0.01% 63.25% # Bytes accessed per row activation |
| 246system.physmem.bytesPerActivate::4096-4103 225 0.25% 63.50% # Bytes accessed per row activation | 246system.physmem.bytesPerActivate::4096-4103 225 0.25% 63.50% # Bytes accessed per row activation |
| 247system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.51% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4224-4231 11 0.01% 63.52% # Bytes accessed per row activation | 247system.physmem.bytesPerActivate::4160-4167 9 0.01% 63.51% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4224-4231 10 0.01% 63.52% # Bytes accessed per row activation |
| 249system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.52% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4352-4359 165 0.18% 63.71% # Bytes accessed per row activation | 249system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.52% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4352-4359 165 0.18% 63.71% # Bytes accessed per row activation |
| 251system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.72% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.73% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4608-4615 84 0.09% 63.83% # Bytes accessed per row activation | 251system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.71% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.72% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.74% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4608-4615 83 0.09% 63.83% # Bytes accessed per row activation |
| 255system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.84% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.84% # Bytes accessed per row activation | 255system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.84% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.84% # Bytes accessed per row activation |
| 257system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.86% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4864-4871 89 0.10% 63.96% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.96% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.98% # Bytes accessed per row activation | 257system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.85% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4864-4871 88 0.10% 63.95% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.96% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.97% # Bytes accessed per row activation |
| 261system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.98% # Bytes accessed per row activation | 261system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.98% # Bytes accessed per row activation |
| 262system.physmem.bytesPerActivate::5120-5127 434 0.48% 64.47% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.49% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.49% # Bytes accessed per row activation | 262system.physmem.bytesPerActivate::5120-5127 435 0.49% 64.47% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5184-5191 9 0.01% 64.48% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5248-5255 6 0.01% 64.48% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5312-5319 9 0.01% 64.49% # Bytes accessed per row activation |
| 266system.physmem.bytesPerActivate::5376-5383 26 0.03% 64.52% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.54% # Bytes accessed per row activation | 266system.physmem.bytesPerActivate::5376-5383 26 0.03% 64.52% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.54% # Bytes accessed per row activation |
| 268system.physmem.bytesPerActivate::5504-5511 65 0.07% 64.62% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.63% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.94% # Bytes accessed per row activation | 268system.physmem.bytesPerActivate::5504-5511 67 0.07% 64.62% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5568-5575 8 0.01% 64.63% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::5632-5639 280 0.31% 64.94% # Bytes accessed per row activation |
| 271system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.94% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.94% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5888-5895 72 0.08% 65.02% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.02% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6144-6151 269 0.30% 65.32% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.32% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.35% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.35% # Bytes accessed per row activation --- 7 unchanged lines hidden (view full) --- 286system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.07% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7424-7431 84 0.09% 66.16% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.16% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7680-7687 29 0.03% 66.20% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7936-7943 77 0.09% 66.28% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8192-8199 401 0.45% 66.73% # Bytes accessed per row activation | 271system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.94% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.94% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5888-5895 72 0.08% 65.02% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.02% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6144-6151 269 0.30% 65.32% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.32% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.35% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.35% # Bytes accessed per row activation --- 7 unchanged lines hidden (view full) --- 286system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.07% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7424-7431 84 0.09% 66.16% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.16% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7680-7687 29 0.03% 66.20% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7936-7943 77 0.09% 66.28% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8192-8199 401 0.45% 66.73% # Bytes accessed per row activation |
| 294system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation | 294system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.73% # Bytes accessed per row activation |
| 295system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.74% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.82% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::8704-8711 24 0.03% 66.85% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.85% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8960-8967 82 0.09% 66.94% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.94% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.95% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::9216-9223 407 0.45% 67.40% # Bytes accessed per row activation --- 112 unchanged lines hidden (view full) --- 415system.physmem.bytesPerActivate::24576-24583 398 0.44% 77.99% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.00% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::24832-24839 75 0.08% 78.08% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::25088-25095 20 0.02% 78.10% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::25344-25351 86 0.10% 78.20% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::25472-25479 3 0.00% 78.20% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation | 295system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.74% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.82% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::8704-8711 24 0.03% 66.85% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.85% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8960-8967 82 0.09% 66.94% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.94% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.95% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::9216-9223 407 0.45% 67.40% # Bytes accessed per row activation --- 112 unchanged lines hidden (view full) --- 415system.physmem.bytesPerActivate::24576-24583 398 0.44% 77.99% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.00% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::24832-24839 75 0.08% 78.08% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::25088-25095 20 0.02% 78.10% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::25344-25351 86 0.10% 78.20% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::25472-25479 3 0.00% 78.20% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation |
| 423system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation | 423system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.81% # Bytes accessed per row activation |
| 424system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::26112-26119 89 0.10% 78.92% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.92% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.92% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::26368-26375 21 0.02% 78.94% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::26496-26503 3 0.00% 78.95% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::26624-26631 271 0.30% 79.25% # Bytes accessed per row activation --- 19 unchanged lines hidden (view full) --- 451system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.66% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.66% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.76% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.76% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.76% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::29696-29703 347 0.39% 81.30% # Bytes accessed per row activation | 424system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::26112-26119 89 0.10% 78.92% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.92% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.92% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::26368-26375 21 0.02% 78.94% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::26496-26503 3 0.00% 78.95% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::26624-26631 271 0.30% 79.25% # Bytes accessed per row activation --- 19 unchanged lines hidden (view full) --- 451system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.66% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.66% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.76% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.76% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.76% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::29696-29703 347 0.39% 81.30% # Bytes accessed per row activation |
| 459system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.31% # Bytes accessed per row activation | 459system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.30% # Bytes accessed per row activation |
| 460system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.31% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::29952-29959 141 0.16% 81.46% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.47% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.47% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::30208-30215 71 0.08% 81.55% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.55% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.55% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::30464-30471 80 0.09% 81.64% # Bytes accessed per row activation --- 16 unchanged lines hidden (view full) --- 484system.physmem.bytesPerActivate::32768-32775 538 0.60% 83.66% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.66% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::33024-33031 86 0.10% 83.76% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::33280-33287 150 0.17% 83.93% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.93% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::33536-33543 80 0.09% 84.02% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::33792-33799 484 0.54% 84.56% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::34048-34055 12 0.01% 84.58% # Bytes accessed per row activation | 460system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.31% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::29952-29959 141 0.16% 81.46% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.47% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.47% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::30208-30215 71 0.08% 81.55% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.55% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.55% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::30464-30471 80 0.09% 81.64% # Bytes accessed per row activation --- 16 unchanged lines hidden (view full) --- 484system.physmem.bytesPerActivate::32768-32775 538 0.60% 83.66% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.66% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::33024-33031 86 0.10% 83.76% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::33280-33287 150 0.17% 83.93% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.93% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::33536-33543 80 0.09% 84.02% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::33792-33799 484 0.54% 84.56% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::34048-34055 12 0.01% 84.58% # Bytes accessed per row activation |
| 492system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.68% # Bytes accessed per row activation | 492system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.67% # Bytes accessed per row activation |
| 493system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::34560-34567 94 0.10% 84.78% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::34624-34631 3 0.00% 84.79% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.79% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::34816-34823 264 0.29% 85.08% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::35072-35079 79 0.09% 85.17% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.17% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.17% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::35328-35335 71 0.08% 85.25% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::35392-35399 1 0.00% 85.25% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.25% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.42% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.42% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.42% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::35840-35847 347 0.39% 85.81% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation | 493system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::34560-34567 94 0.10% 84.78% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::34624-34631 3 0.00% 84.79% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.79% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::34816-34823 264 0.29% 85.08% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::35072-35079 79 0.09% 85.17% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.17% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.17% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::35328-35335 71 0.08% 85.25% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::35392-35399 1 0.00% 85.25% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.25% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.42% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.42% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.42% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::35840-35847 347 0.39% 85.81% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation |
| 510system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.96% # Bytes accessed per row activation | 510system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.95% # Bytes accessed per row activation |
| 511system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.96% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::36352-36359 87 0.10% 86.05% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::36416-36423 1 0.00% 86.05% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::36608-36615 78 0.09% 86.14% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.14% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::36864-36871 204 0.23% 86.37% # Bytes accessed per row activation --- 89 unchanged lines hidden (view full) --- 608system.physmem.bytesPerActivate::48384-48391 100 0.11% 94.01% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::48640-48647 142 0.16% 94.17% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.25% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.34% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation | 511system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.96% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::36352-36359 87 0.10% 86.05% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::36416-36423 1 0.00% 86.05% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::36608-36615 78 0.09% 86.14% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.14% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::36864-36871 204 0.23% 86.37% # Bytes accessed per row activation --- 89 unchanged lines hidden (view full) --- 608system.physmem.bytesPerActivate::48384-48391 100 0.11% 94.01% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::48640-48647 142 0.16% 94.17% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.25% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.34% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation |
| 616system.physmem.bytesPerActivate::total 89677 # Bytes accessed per row activation 617system.physmem.totQLat 373683436750 # Total ticks spent queuing 618system.physmem.totMemAccLat 469596379250 # Total ticks spent from burst creation until serviced by the DRAM 619system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers 620system.physmem.totBankLat 18447687500 # Total ticks spent accessing banks 621system.physmem.avgQLat 24119.42 # Average queueing delay per DRAM burst 622system.physmem.avgBankLat 1190.71 # Average bank access latency per DRAM burst | 616system.physmem.bytesPerActivate::total 89676 # Bytes accessed per row activation 617system.physmem.totQLat 373682624750 # Total ticks spent queuing 618system.physmem.totMemAccLat 469595819750 # Total ticks spent from burst creation until serviced by the DRAM 619system.physmem.totBusLat 77465315000 # Total ticks spent in databus transfers 620system.physmem.totBankLat 18447880000 # Total ticks spent accessing banks 621system.physmem.avgQLat 24119.35 # Average queueing delay per DRAM burst 622system.physmem.avgBankLat 1190.72 # Average bank access latency per DRAM burst |
| 623system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 623system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 624system.physmem.avgMemAccLat 30310.13 # Average memory access latency per DRAM burst | 624system.physmem.avgMemAccLat 30310.07 # Average memory access latency per DRAM burst |
| 625system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s 626system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 627system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s 628system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s 629system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 630system.physmem.busUtil 2.98 # Data bus utilization in percentage 631system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads 632system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 633system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing 634system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing | 625system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s 626system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 627system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s 628system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s 629system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 630system.physmem.busUtil 2.98 # Data bus utilization in percentage 631system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads 632system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 633system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing 634system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing |
| 635system.physmem.readRowHits 15419160 # Number of row buffer hits during reads | 635system.physmem.readRowHits 15419173 # Number of row buffer hits during reads |
| 636system.physmem.writeRowHits 91146 # Number of row buffer hits during writes 637system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads 638system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes | 636system.physmem.writeRowHits 91146 # Number of row buffer hits during writes 637system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads 638system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes |
| 639system.physmem.avgGap 160458.28 # Average gap between requests | 639system.physmem.avgGap 160458.16 # Average gap between requests |
| 640system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined 641system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state 642system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 643system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 644system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 645system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 646system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 647system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 648system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 649system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 650system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 651system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 652system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 653system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) | 640system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined 641system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state 642system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 643system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 644system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 645system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 646system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 647system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 648system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 649system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 650system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 651system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 652system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 653system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) |
| 654system.membus.throughput 54116520 # Throughput (bytes/s) 655system.membus.trans_dist::ReadReq 16546551 # Transaction distribution 656system.membus.trans_dist::ReadResp 16546551 # Transaction distribution | 654system.membus.throughput 54116538 # Throughput (bytes/s) 655system.membus.trans_dist::ReadReq 16546563 # Transaction distribution 656system.membus.trans_dist::ReadResp 16546563 # Transaction distribution |
| 657system.membus.trans_dist::WriteReq 763368 # Transaction distribution 658system.membus.trans_dist::WriteResp 763368 # Transaction distribution 659system.membus.trans_dist::Writeback 57909 # Transaction distribution 660system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution 661system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution 662system.membus.trans_dist::ReadExReq 132216 # Transaction distribution 663system.membus.trans_dist::ReadExResp 132216 # Transaction distribution 664system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) 665system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 666system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 667system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) | 657system.membus.trans_dist::WriteReq 763368 # Transaction distribution 658system.membus.trans_dist::WriteResp 763368 # Transaction distribution 659system.membus.trans_dist::Writeback 57909 # Transaction distribution 660system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution 661system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution 662system.membus.trans_dist::ReadExReq 132216 # Transaction distribution 663system.membus.trans_dist::ReadExResp 132216 # Transaction distribution 664system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) 665system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 666system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 667system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) |
| 668system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes) | 668system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893537 # Packet count per connected master and slave (bytes) 669system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280385 # Packet count per connected master and slave (bytes) |
| 670system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 671system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) | 670system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 671system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) |
| 672system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes) | 672system.membus.pkt_count::total 34951233 # Packet count per connected master and slave (bytes) |
| 673system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) 674system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 675system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 676system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) | 673system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) 674system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 675system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 676system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) |
| 677system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes) 678system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes) | 677system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516392 # Cumulative packet size per connected master and slave (bytes) 678system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914505 # Cumulative packet size per connected master and slave (bytes) |
| 679system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 680system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) | 679system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 680system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) |
| 681system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes) 682system.membus.data_through_bus 141597849 # Total data (bytes) | 681system.membus.tot_pkt_size::total 141597897 # Cumulative packet size per connected master and slave (bytes) 682system.membus.data_through_bus 141597897 # Total data (bytes) |
| 683system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 684system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) 685system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 686system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 687system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 688system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) 689system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 690system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 691system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 683system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 684system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) 685system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 686system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 687system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 688system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) 689system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 690system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 691system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 692system.membus.reqLayer6.occupancy 17910610000 # Layer occupancy (ticks) | 692system.membus.reqLayer6.occupancy 17910622000 # Layer occupancy (ticks) |
| 693system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 693system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 694system.membus.respLayer1.occupancy 4950347835 # Layer occupancy (ticks) | 694system.membus.respLayer1.occupancy 4950375335 # Layer occupancy (ticks) |
| 695system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 696system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) 697system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 698system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 699system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 700system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 701system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 702system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. --- 106 unchanged lines hidden (view full) --- 809system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 810system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 811system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 812system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) 813system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 814system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) 815system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) 816system.cpu_clk_domain.clock 500 # Clock period in ticks | 695system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 696system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) 697system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 698system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 699system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 700system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 701system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 702system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. --- 106 unchanged lines hidden (view full) --- 809system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 810system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 811system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 812system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) 813system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 814system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) 815system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) 816system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 817system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 818system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 819system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 820system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 821system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 822system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 823system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 824system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 825system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 826system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 827system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 828system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 829system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 830system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 831system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 832system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 833system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 834system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 835system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 836system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 837system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 817system.cpu.dtb.inst_hits 0 # ITB inst hits 818system.cpu.dtb.inst_misses 0 # ITB inst misses | 838system.cpu.dtb.inst_hits 0 # ITB inst hits 839system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 819system.cpu.dtb.read_hits 14995644 # DTB read hits | 840system.cpu.dtb.read_hits 14995647 # DTB read hits |
| 820system.cpu.dtb.read_misses 7334 # DTB read misses 821system.cpu.dtb.write_hits 11230146 # DTB write hits 822system.cpu.dtb.write_misses 2212 # DTB write misses 823system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 824system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 825system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 826system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 841system.cpu.dtb.read_misses 7334 # DTB read misses 842system.cpu.dtb.write_hits 11230146 # DTB write hits 843system.cpu.dtb.write_misses 2212 # DTB write misses 844system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 845system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 846system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 847system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 827system.cpu.dtb.flush_entries 3498 # Number of entries that have been flushed from TLB | 848system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB |
| 828system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 829system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch 830system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 831system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 849system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 850system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch 851system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 852system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 832system.cpu.dtb.read_accesses 15002978 # DTB read accesses | 853system.cpu.dtb.read_accesses 15002981 # DTB read accesses |
| 833system.cpu.dtb.write_accesses 11232358 # DTB write accesses 834system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 854system.cpu.dtb.write_accesses 11232358 # DTB write accesses 855system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 835system.cpu.dtb.hits 26225790 # DTB hits | 856system.cpu.dtb.hits 26225793 # DTB hits |
| 836system.cpu.dtb.misses 9546 # DTB misses | 857system.cpu.dtb.misses 9546 # DTB misses |
| 837system.cpu.dtb.accesses 26235336 # DTB accesses | 858system.cpu.dtb.accesses 26235339 # DTB accesses 859system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 860system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 861system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 862system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 863system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 864system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 865system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 866system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 867system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 868system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 869system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 870system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 871system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 872system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 873system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 874system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 875system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 876system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 877system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 878system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 879system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 838system.cpu.itb.inst_hits 61491413 # ITB inst hits 839system.cpu.itb.inst_misses 4471 # ITB inst misses 840system.cpu.itb.read_hits 0 # DTB read hits 841system.cpu.itb.read_misses 0 # DTB read misses 842system.cpu.itb.write_hits 0 # DTB write hits 843system.cpu.itb.write_misses 0 # DTB write misses 844system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 845system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 846system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 847system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 880system.cpu.itb.inst_hits 61491413 # ITB inst hits 881system.cpu.itb.inst_misses 4471 # ITB inst misses 882system.cpu.itb.read_hits 0 # DTB read hits 883system.cpu.itb.read_misses 0 # DTB read misses 884system.cpu.itb.write_hits 0 # DTB write hits 885system.cpu.itb.write_misses 0 # DTB write misses 886system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 887system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 888system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 889system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 848system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB | 890system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB |
| 849system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 850system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 851system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 852system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 853system.cpu.itb.read_accesses 0 # DTB read accesses 854system.cpu.itb.write_accesses 0 # DTB write accesses 855system.cpu.itb.inst_accesses 61495884 # ITB inst accesses 856system.cpu.itb.hits 61491413 # DTB hits 857system.cpu.itb.misses 4471 # DTB misses 858system.cpu.itb.accesses 61495884 # DTB accesses 859system.cpu.numCycles 5233072966 # number of cpu cycles simulated 860system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 861system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 891system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 892system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 893system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 894system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 895system.cpu.itb.read_accesses 0 # DTB read accesses 896system.cpu.itb.write_accesses 0 # DTB write accesses 897system.cpu.itb.inst_accesses 61495884 # ITB inst accesses 898system.cpu.itb.hits 61491413 # DTB hits 899system.cpu.itb.misses 4471 # DTB misses 900system.cpu.itb.accesses 61495884 # DTB accesses 901system.cpu.numCycles 5233072966 # number of cpu cycles simulated 902system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 903system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 862system.cpu.committedInsts 60197580 # Number of instructions committed 863system.cpu.committedOps 76603973 # Number of ops (including micro ops) committed 864system.cpu.num_int_alu_accesses 68871033 # Number of integer alu accesses | 904system.cpu.committedInsts 60197590 # Number of instructions committed 905system.cpu.committedOps 76603983 # Number of ops (including micro ops) committed 906system.cpu.num_int_alu_accesses 69206189 # Number of integer alu accesses |
| 865system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 866system.cpu.num_func_calls 2140403 # number of times a function call or return occured | 907system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 908system.cpu.num_func_calls 2140403 # number of times a function call or return occured |
| 867system.cpu.num_conditional_control_insts 7948247 # number of instructions that are conditional controls 868system.cpu.num_int_insts 68871033 # number of integer instructions | 909system.cpu.num_conditional_control_insts 7948249 # number of instructions that are conditional controls 910system.cpu.num_int_insts 69206189 # number of integer instructions |
| 869system.cpu.num_fp_insts 10269 # number of float instructions | 911system.cpu.num_fp_insts 10269 # number of float instructions |
| 870system.cpu.num_int_register_reads 394768801 # number of times the integer registers were read 871system.cpu.num_int_register_writes 74180798 # number of times the integer registers were written | 912system.cpu.num_int_register_reads 401354573 # number of times the integer registers were read 913system.cpu.num_int_register_writes 74515956 # number of times the integer registers were written |
| 872system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 873system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 914system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 915system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 874system.cpu.num_mem_refs 27393280 # number of memory refs 875system.cpu.num_load_insts 15659727 # Number of load instructions | 916system.cpu.num_mem_refs 27393282 # number of memory refs 917system.cpu.num_load_insts 15659729 # Number of load instructions |
| 876system.cpu.num_store_insts 11733553 # Number of store instructions 877system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles 878system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles 879system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles 880system.cpu.idle_fraction 0.875495 # Percentage of idle cycles 881system.cpu.kern.inst.arm 0 # number of arm instructions executed 882system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed 883system.cpu.icache.tags.replacements 856260 # number of replacements | 918system.cpu.num_store_insts 11733553 # Number of store instructions 919system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles 920system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles 921system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles 922system.cpu.idle_fraction 0.875495 # Percentage of idle cycles 923system.cpu.kern.inst.arm 0 # number of arm instructions executed 924system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed 925system.cpu.icache.tags.replacements 856260 # number of replacements |
| 884system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use | 926system.cpu.icache.tags.tagsinuse 510.868407 # Cycle average of tags in use |
| 885system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. 886system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. 887system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. 888system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. | 927system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. 928system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. 929system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. 930system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. |
| 889system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor | 931system.cpu.icache.tags.occ_blocks::cpu.inst 510.868407 # Average occupied blocks per requestor |
| 890system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy 891system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy 892system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 893system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 894system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 895system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id 896system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 897system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 904system.cpu.icache.overall_hits::cpu.inst 60634641 # number of overall hits 905system.cpu.icache.overall_hits::total 60634641 # number of overall hits 906system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses 907system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses 908system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses 909system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses 910system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses 911system.cpu.icache.overall_misses::total 856772 # number of overall misses | 932system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy 933system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy 934system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 935system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 936system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 937system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id 938system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 939system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id --- 6 unchanged lines hidden (view full) --- 946system.cpu.icache.overall_hits::cpu.inst 60634641 # number of overall hits 947system.cpu.icache.overall_hits::total 60634641 # number of overall hits 948system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses 949system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses 950system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses 951system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses 952system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses 953system.cpu.icache.overall_misses::total 856772 # number of overall misses |
| 912system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773713250 # number of ReadReq miss cycles 913system.cpu.icache.ReadReq_miss_latency::total 11773713250 # number of ReadReq miss cycles 914system.cpu.icache.demand_miss_latency::cpu.inst 11773713250 # number of demand (read+write) miss cycles 915system.cpu.icache.demand_miss_latency::total 11773713250 # number of demand (read+write) miss cycles 916system.cpu.icache.overall_miss_latency::cpu.inst 11773713250 # number of overall miss cycles 917system.cpu.icache.overall_miss_latency::total 11773713250 # number of overall miss cycles | 954system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774021000 # number of ReadReq miss cycles 955system.cpu.icache.ReadReq_miss_latency::total 11774021000 # number of ReadReq miss cycles 956system.cpu.icache.demand_miss_latency::cpu.inst 11774021000 # number of demand (read+write) miss cycles 957system.cpu.icache.demand_miss_latency::total 11774021000 # number of demand (read+write) miss cycles 958system.cpu.icache.overall_miss_latency::cpu.inst 11774021000 # number of overall miss cycles 959system.cpu.icache.overall_miss_latency::total 11774021000 # number of overall miss cycles |
| 918system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) 919system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) 920system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses 921system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses 922system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses 923system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses 924system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses 925system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses 926system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses 927system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses 928system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses 929system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses | 960system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) 961system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) 962system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses 963system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses 964system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses 965system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses 966system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses 967system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses 968system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses 969system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses 970system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses 971system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses |
| 930system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.944473 # average ReadReq miss latency 931system.cpu.icache.ReadReq_avg_miss_latency::total 13741.944473 # average ReadReq miss latency 932system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency 933system.cpu.icache.demand_avg_miss_latency::total 13741.944473 # average overall miss latency 934system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency 935system.cpu.icache.overall_avg_miss_latency::total 13741.944473 # average overall miss latency | 972system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.303670 # average ReadReq miss latency 973system.cpu.icache.ReadReq_avg_miss_latency::total 13742.303670 # average ReadReq miss latency 974system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency 975system.cpu.icache.demand_avg_miss_latency::total 13742.303670 # average overall miss latency 976system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency 977system.cpu.icache.overall_avg_miss_latency::total 13742.303670 # average overall miss latency |
| 936system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 937system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 938system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 939system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 940system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 941system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 942system.cpu.icache.fast_writes 0 # number of fast writes performed 943system.cpu.icache.cache_copies 0 # number of cache copies performed 944system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856772 # number of ReadReq MSHR misses 945system.cpu.icache.ReadReq_mshr_misses::total 856772 # number of ReadReq MSHR misses 946system.cpu.icache.demand_mshr_misses::cpu.inst 856772 # number of demand (read+write) MSHR misses 947system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses 948system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses 949system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses | 978system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 979system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 980system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 981system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 982system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 983system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 984system.cpu.icache.fast_writes 0 # number of fast writes performed 985system.cpu.icache.cache_copies 0 # number of cache copies performed 986system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856772 # number of ReadReq MSHR misses 987system.cpu.icache.ReadReq_mshr_misses::total 856772 # number of ReadReq MSHR misses 988system.cpu.icache.demand_mshr_misses::cpu.inst 856772 # number of demand (read+write) MSHR misses 989system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses 990system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses 991system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses |
| 950system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056122750 # number of ReadReq MSHR miss cycles 951system.cpu.icache.ReadReq_mshr_miss_latency::total 10056122750 # number of ReadReq MSHR miss cycles 952system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056122750 # number of demand (read+write) MSHR miss cycles 953system.cpu.icache.demand_mshr_miss_latency::total 10056122750 # number of demand (read+write) MSHR miss cycles 954system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056122750 # number of overall MSHR miss cycles 955system.cpu.icache.overall_mshr_miss_latency::total 10056122750 # number of overall MSHR miss cycles 956system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles 957system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles 958system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles 959system.cpu.icache.overall_mshr_uncacheable_latency::total 435321250 # number of overall MSHR uncacheable cycles | 992system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056430000 # number of ReadReq MSHR miss cycles 993system.cpu.icache.ReadReq_mshr_miss_latency::total 10056430000 # number of ReadReq MSHR miss cycles 994system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056430000 # number of demand (read+write) MSHR miss cycles 995system.cpu.icache.demand_mshr_miss_latency::total 10056430000 # number of demand (read+write) MSHR miss cycles 996system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056430000 # number of overall MSHR miss cycles 997system.cpu.icache.overall_mshr_miss_latency::total 10056430000 # number of overall MSHR miss cycles 998system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435943750 # number of ReadReq MSHR uncacheable cycles 999system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435943750 # number of ReadReq MSHR uncacheable cycles 1000system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435943750 # number of overall MSHR uncacheable cycles 1001system.cpu.icache.overall_mshr_uncacheable_latency::total 435943750 # number of overall MSHR uncacheable cycles |
| 960system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses 961system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses 962system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses 963system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses 964system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses 965system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses | 1002system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses 1003system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses 1004system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses 1005system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses 1006system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses 1007system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses |
| 966system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.221513 # average ReadReq mshr miss latency 967system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.221513 # average ReadReq mshr miss latency 968system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency 969system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency 970system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency 971system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency | 1008system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.580126 # average ReadReq mshr miss latency 1009system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.580126 # average ReadReq mshr miss latency 1010system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency 1011system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency 1012system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency 1013system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency |
| 972system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 973system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 974system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 975system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 976system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 977system.cpu.l2cache.tags.replacements 62509 # number of replacements | 1014system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1015system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1016system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1017system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1018system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1019system.cpu.l2cache.tags.replacements 62509 # number of replacements |
| 978system.cpu.l2cache.tags.tagsinuse 50754.670351 # Cycle average of tags in use | 1020system.cpu.l2cache.tags.tagsinuse 50754.656257 # Cycle average of tags in use |
| 979system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. 980system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. 981system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. 982system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. | 1021system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. 1022system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. 1023system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. 1024system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. |
| 983system.cpu.l2cache.tags.occ_blocks::writebacks 37718.407530 # Average occupied blocks per requestor | 1025system.cpu.l2cache.tags.occ_blocks::writebacks 37718.394097 # Average occupied blocks per requestor |
| 984system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor 985system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor | 1026system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor 1027system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor |
| 986system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400299 # Average occupied blocks per requestor 987system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977449 # Average occupied blocks per requestor | 1028system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400068 # Average occupied blocks per requestor 1029system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977018 # Average occupied blocks per requestor |
| 988system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy 989system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 990system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 991system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy 992system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy 993system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy 994system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 995system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id --- 44 unchanged lines hidden (view full) --- 1040system.cpu.l2cache.demand_misses::total 154224 # number of demand (read+write) misses 1041system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 1042system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1043system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses 1044system.cpu.l2cache.overall_misses::cpu.data 143632 # number of overall misses 1045system.cpu.l2cache.overall_misses::total 154224 # number of overall misses 1046system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles 1047system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles | 1030system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy 1031system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 1032system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 1033system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy 1034system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy 1035system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy 1036system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 1037system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id --- 44 unchanged lines hidden (view full) --- 1082system.cpu.l2cache.demand_misses::total 154224 # number of demand (read+write) misses 1083system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 1084system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1085system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses 1086system.cpu.l2cache.overall_misses::cpu.data 143632 # number of overall misses 1087system.cpu.l2cache.overall_misses::total 154224 # number of overall misses 1088system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles 1089system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles |
| 1048system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752204750 # number of ReadReq miss cycles 1049system.cpu.l2cache.ReadReq_miss_latency::cpu.data 737637250 # number of ReadReq miss cycles 1050system.cpu.l2cache.ReadReq_miss_latency::total 1490297250 # number of ReadReq miss cycles | 1090system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752512000 # number of ReadReq miss cycles 1091system.cpu.l2cache.ReadReq_miss_latency::cpu.data 736932000 # number of ReadReq miss cycles 1092system.cpu.l2cache.ReadReq_miss_latency::total 1489899250 # number of ReadReq miss cycles |
| 1051system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles 1052system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles | 1093system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles 1094system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles |
| 1053system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9620282393 # number of ReadExReq miss cycles 1054system.cpu.l2cache.ReadExReq_miss_latency::total 9620282393 # number of ReadExReq miss cycles | 1095system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9619897393 # number of ReadExReq miss cycles 1096system.cpu.l2cache.ReadExReq_miss_latency::total 9619897393 # number of ReadExReq miss cycles |
| 1055system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles 1056system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles | 1097system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles 1098system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles |
| 1057system.cpu.l2cache.demand_miss_latency::cpu.inst 752204750 # number of demand (read+write) miss cycles 1058system.cpu.l2cache.demand_miss_latency::cpu.data 10357919643 # number of demand (read+write) miss cycles 1059system.cpu.l2cache.demand_miss_latency::total 11110579643 # number of demand (read+write) miss cycles | 1099system.cpu.l2cache.demand_miss_latency::cpu.inst 752512000 # number of demand (read+write) miss cycles 1100system.cpu.l2cache.demand_miss_latency::cpu.data 10356829393 # number of demand (read+write) miss cycles 1101system.cpu.l2cache.demand_miss_latency::total 11109796643 # number of demand (read+write) miss cycles |
| 1060system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles 1061system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles | 1102system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles 1103system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles |
| 1062system.cpu.l2cache.overall_miss_latency::cpu.inst 752204750 # number of overall miss cycles 1063system.cpu.l2cache.overall_miss_latency::cpu.data 10357919643 # number of overall miss cycles 1064system.cpu.l2cache.overall_miss_latency::total 11110579643 # number of overall miss cycles | 1104system.cpu.l2cache.overall_miss_latency::cpu.inst 752512000 # number of overall miss cycles 1105system.cpu.l2cache.overall_miss_latency::cpu.data 10356829393 # number of overall miss cycles 1106system.cpu.l2cache.overall_miss_latency::total 11109796643 # number of overall miss cycles |
| 1065system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) 1066system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) 1067system.cpu.l2cache.ReadReq_accesses::cpu.inst 855136 # number of ReadReq accesses(hits+misses) 1068system.cpu.l2cache.ReadReq_accesses::cpu.data 379440 # number of ReadReq accesses(hits+misses) 1069system.cpu.l2cache.ReadReq_accesses::total 1246820 # number of ReadReq accesses(hits+misses) 1070system.cpu.l2cache.Writeback_accesses::writebacks 595233 # number of Writeback accesses(hits+misses) 1071system.cpu.l2cache.Writeback_accesses::total 595233 # number of Writeback accesses(hits+misses) 1072system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2934 # number of UpgradeReq accesses(hits+misses) --- 26 unchanged lines hidden (view full) --- 1099system.cpu.l2cache.demand_miss_rate::total 0.103227 # miss rate for demand accesses 1100system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses 1101system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses 1102system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses 1103system.cpu.l2cache.overall_miss_rate::cpu.data 0.229206 # miss rate for overall accesses 1104system.cpu.l2cache.overall_miss_rate::total 0.103227 # miss rate for overall accesses 1105system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency 1106system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency | 1107system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) 1108system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) 1109system.cpu.l2cache.ReadReq_accesses::cpu.inst 855136 # number of ReadReq accesses(hits+misses) 1110system.cpu.l2cache.ReadReq_accesses::cpu.data 379440 # number of ReadReq accesses(hits+misses) 1111system.cpu.l2cache.ReadReq_accesses::total 1246820 # number of ReadReq accesses(hits+misses) 1112system.cpu.l2cache.Writeback_accesses::writebacks 595233 # number of Writeback accesses(hits+misses) 1113system.cpu.l2cache.Writeback_accesses::total 595233 # number of Writeback accesses(hits+misses) 1114system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2934 # number of UpgradeReq accesses(hits+misses) --- 26 unchanged lines hidden (view full) --- 1141system.cpu.l2cache.demand_miss_rate::total 0.103227 # miss rate for demand accesses 1142system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses 1143system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses 1144system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses 1145system.cpu.l2cache.overall_miss_rate::cpu.data 0.229206 # miss rate for overall accesses 1146system.cpu.l2cache.overall_miss_rate::total 0.103227 # miss rate for overall accesses 1147system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency 1148system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency |
| 1107system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71063.273500 # average ReadReq miss latency 1108system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75200.045876 # average ReadReq miss latency 1109system.cpu.l2cache.ReadReq_avg_miss_latency::total 73050.205872 # average ReadReq miss latency | 1149system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71092.300425 # average ReadReq miss latency 1150system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75128.147620 # average ReadReq miss latency 1151system.cpu.l2cache.ReadReq_avg_miss_latency::total 73030.697025 # average ReadReq miss latency |
| 1110system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency 1111system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency | 1152system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency 1153system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency |
| 1112system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71888.108868 # average ReadExReq miss latency 1113system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71888.108868 # average ReadExReq miss latency | 1154system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71885.231933 # average ReadExReq miss latency 1155system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71885.231933 # average ReadExReq miss latency |
| 1114system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 1115system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency | 1156system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 1157system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency |
| 1116system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency 1117system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency 1118system.cpu.l2cache.demand_avg_miss_latency::total 72041.832938 # average overall miss latency | 1158system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency 1159system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency 1160system.cpu.l2cache.demand_avg_miss_latency::total 72036.755907 # average overall miss latency |
| 1119system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 1120system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency | 1161system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency 1162system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency |
| 1121system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency 1122system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency 1123system.cpu.l2cache.overall_avg_miss_latency::total 72041.832938 # average overall miss latency | 1163system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency 1164system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency 1165system.cpu.l2cache.overall_avg_miss_latency::total 72036.755907 # average overall miss latency |
| 1124system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1125system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1126system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1127system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1128system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1129system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1130system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1131system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 1147system.cpu.l2cache.demand_mshr_misses::total 154224 # number of demand (read+write) MSHR misses 1148system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 1149system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1150system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses 1151system.cpu.l2cache.overall_mshr_misses::cpu.data 143632 # number of overall MSHR misses 1152system.cpu.l2cache.overall_mshr_misses::total 154224 # number of overall MSHR misses 1153system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles 1154system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles | 1166system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1167system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1168system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1169system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1170system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1171system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1172system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1173system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 1189system.cpu.l2cache.demand_mshr_misses::total 154224 # number of demand (read+write) MSHR misses 1190system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 1191system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1192system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses 1193system.cpu.l2cache.overall_mshr_misses::cpu.data 143632 # number of overall MSHR misses 1194system.cpu.l2cache.overall_mshr_misses::total 154224 # number of overall MSHR misses 1195system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles 1196system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles |
| 1155system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619637750 # number of ReadReq MSHR miss cycles 1156system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 614753750 # number of ReadReq MSHR miss cycles 1157system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1234759250 # number of ReadReq MSHR miss cycles | 1197system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619946000 # number of ReadReq MSHR miss cycles 1198system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 614046500 # number of ReadReq MSHR miss cycles 1199system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1234360250 # number of ReadReq MSHR miss cycles |
| 1158system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29085908 # number of UpgradeReq MSHR miss cycles 1159system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29085908 # number of UpgradeReq MSHR miss cycles | 1200system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29085908 # number of UpgradeReq MSHR miss cycles 1201system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29085908 # number of UpgradeReq MSHR miss cycles |
| 1160system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7945647607 # number of ReadExReq MSHR miss cycles 1161system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7945647607 # number of ReadExReq MSHR miss cycles | 1202system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7945262107 # number of ReadExReq MSHR miss cycles 1203system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7945262107 # number of ReadExReq MSHR miss cycles |
| 1162system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles 1163system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles | 1204system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles 1205system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles |
| 1164system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619637750 # number of demand (read+write) MSHR miss cycles 1165system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8560401357 # number of demand (read+write) MSHR miss cycles 1166system.cpu.l2cache.demand_mshr_miss_latency::total 9180406857 # number of demand (read+write) MSHR miss cycles | 1206system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619946000 # number of demand (read+write) MSHR miss cycles 1207system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8559308607 # number of demand (read+write) MSHR miss cycles 1208system.cpu.l2cache.demand_mshr_miss_latency::total 9179622357 # number of demand (read+write) MSHR miss cycles |
| 1167system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles 1168system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles | 1209system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles 1210system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles |
| 1169system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619637750 # number of overall MSHR miss cycles 1170system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8560401357 # number of overall MSHR miss cycles 1171system.cpu.l2cache.overall_mshr_miss_latency::total 9180406857 # number of overall MSHR miss cycles 1172system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 343871250 # number of ReadReq MSHR uncacheable cycles 1173system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166656947250 # number of ReadReq MSHR uncacheable cycles 1174system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167000818500 # number of ReadReq MSHR uncacheable cycles | 1211system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619946000 # number of overall MSHR miss cycles 1212system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8559308607 # number of overall MSHR miss cycles 1213system.cpu.l2cache.overall_mshr_miss_latency::total 9179622357 # number of overall MSHR miss cycles 1214system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 344358750 # number of ReadReq MSHR uncacheable cycles 1215system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657044750 # number of ReadReq MSHR uncacheable cycles 1216system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167001403500 # number of ReadReq MSHR uncacheable cycles |
| 1175system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702635150 # number of WriteReq MSHR uncacheable cycles 1176system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702635150 # number of WriteReq MSHR uncacheable cycles | 1217system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702635150 # number of WriteReq MSHR uncacheable cycles 1218system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702635150 # number of WriteReq MSHR uncacheable cycles |
| 1177system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 343871250 # number of overall MSHR uncacheable cycles 1178system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359582400 # number of overall MSHR uncacheable cycles 1179system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183703453650 # number of overall MSHR uncacheable cycles | 1219system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 344358750 # number of overall MSHR uncacheable cycles 1220system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359679900 # number of overall MSHR uncacheable cycles 1221system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183704038650 # number of overall MSHR uncacheable cycles |
| 1180system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 1181system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses 1182system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses 1183system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses 1184system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses 1185system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses 1186system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses 1187system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541331 # mshr miss rate for ReadExReq accesses --- 5 unchanged lines hidden (view full) --- 1193system.cpu.l2cache.demand_mshr_miss_rate::total 0.103227 # mshr miss rate for demand accesses 1194system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 1195system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses 1196system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses 1197system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses 1198system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses 1199system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency 1200system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency | 1222system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 1223system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses 1224system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses 1225system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses 1226system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses 1227system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses 1228system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses 1229system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541331 # mshr miss rate for ReadExReq accesses --- 5 unchanged lines hidden (view full) --- 1235system.cpu.l2cache.demand_mshr_miss_rate::total 0.103227 # mshr miss rate for demand accesses 1236system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 1237system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses 1238system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses 1239system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses 1240system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses 1241system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency 1242system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency |
| 1201system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58539.230043 # average ReadReq mshr miss latency 1202system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62672.418187 # average ReadReq mshr miss latency 1203system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60524.447331 # average ReadReq mshr miss latency | 1243system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58568.351441 # average ReadReq mshr miss latency 1244system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62600.316036 # average ReadReq mshr miss latency 1245system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60504.889466 # average ReadReq mshr miss latency |
| 1204system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency 1205system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency | 1246system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency 1247system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency |
| 1206system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59374.304918 # average ReadExReq mshr miss latency 1207system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59374.304918 # average ReadExReq mshr miss latency | 1248system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59371.424247 # average ReadExReq mshr miss latency 1249system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59371.424247 # average ReadExReq mshr miss latency |
| 1208system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 1209system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 1250system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 1251system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 1210system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency 1211system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency 1212system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency | 1252system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency 1253system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency 1254system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency |
| 1213system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 1214system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 1255system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency 1256system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 1215system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency 1216system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency 1217system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency | 1257system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency 1258system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency 1259system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency |
| 1218system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1219system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1220system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1221system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1222system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1223system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1224system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1225system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1226system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1227system.cpu.dcache.tags.replacements 626139 # number of replacements | 1260system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1261system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1262system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1263system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1264system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1265system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1266system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1267system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1268system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1269system.cpu.dcache.tags.replacements 626139 # number of replacements |
| 1228system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use | 1270system.cpu.dcache.tags.tagsinuse 511.876590 # Cycle average of tags in use |
| 1229system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. 1230system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. 1231system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. | 1271system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. 1272system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. 1273system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. |
| 1232system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. 1233system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor | 1274system.cpu.dcache.tags.warmup_cycle 664772250 # Cycle when the warmup percentage was hit. 1275system.cpu.dcache.tags.occ_blocks::cpu.data 511.876590 # Average occupied blocks per requestor |
| 1234system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy 1235system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy 1236system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1237system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 1238system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 1239system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id 1240system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1241system.cpu.dcache.tags.tag_accesses 97755015 # Number of tag accesses --- 15 unchanged lines hidden (view full) --- 1257system.cpu.dcache.WriteReq_misses::cpu.data 250145 # number of WriteReq misses 1258system.cpu.dcache.WriteReq_misses::total 250145 # number of WriteReq misses 1259system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses 1260system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses 1261system.cpu.dcache.demand_misses::cpu.data 618199 # number of demand (read+write) misses 1262system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses 1263system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses 1264system.cpu.dcache.overall_misses::total 618199 # number of overall misses | 1276system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy 1277system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy 1278system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1279system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 1280system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 1281system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id 1282system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1283system.cpu.dcache.tags.tag_accesses 97755015 # Number of tag accesses --- 15 unchanged lines hidden (view full) --- 1299system.cpu.dcache.WriteReq_misses::cpu.data 250145 # number of WriteReq misses 1300system.cpu.dcache.WriteReq_misses::total 250145 # number of WriteReq misses 1301system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses 1302system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses 1303system.cpu.dcache.demand_misses::cpu.data 618199 # number of demand (read+write) misses 1304system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses 1305system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses 1306system.cpu.dcache.overall_misses::total 618199 # number of overall misses |
| 1265system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416240000 # number of ReadReq miss cycles 1266system.cpu.dcache.ReadReq_miss_latency::total 5416240000 # number of ReadReq miss cycles 1267system.cpu.dcache.WriteReq_miss_latency::cpu.data 11622215515 # number of WriteReq miss cycles 1268system.cpu.dcache.WriteReq_miss_latency::total 11622215515 # number of WriteReq miss cycles 1269system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158376750 # number of LoadLockedReq miss cycles 1270system.cpu.dcache.LoadLockedReq_miss_latency::total 158376750 # number of LoadLockedReq miss cycles 1271system.cpu.dcache.demand_miss_latency::cpu.data 17038455515 # number of demand (read+write) miss cycles 1272system.cpu.dcache.demand_miss_latency::total 17038455515 # number of demand (read+write) miss cycles 1273system.cpu.dcache.overall_miss_latency::cpu.data 17038455515 # number of overall miss cycles 1274system.cpu.dcache.overall_miss_latency::total 17038455515 # number of overall miss cycles | 1307system.cpu.dcache.ReadReq_miss_latency::cpu.data 5415523000 # number of ReadReq miss cycles 1308system.cpu.dcache.ReadReq_miss_latency::total 5415523000 # number of ReadReq miss cycles 1309system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621830515 # number of WriteReq miss cycles 1310system.cpu.dcache.WriteReq_miss_latency::total 11621830515 # number of WriteReq miss cycles 1311system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158390000 # number of LoadLockedReq miss cycles 1312system.cpu.dcache.LoadLockedReq_miss_latency::total 158390000 # number of LoadLockedReq miss cycles 1313system.cpu.dcache.demand_miss_latency::cpu.data 17037353515 # number of demand (read+write) miss cycles 1314system.cpu.dcache.demand_miss_latency::total 17037353515 # number of demand (read+write) miss cycles 1315system.cpu.dcache.overall_miss_latency::cpu.data 17037353515 # number of overall miss cycles 1316system.cpu.dcache.overall_miss_latency::total 17037353515 # number of overall miss cycles |
| 1275system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) 1276system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) 1277system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) 1278system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses) 1279system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) 1280system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) 1281system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) 1282system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1289system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses 1290system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses 1291system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses 1292system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses 1293system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses 1294system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses 1295system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses 1296system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses | 1317system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) 1318system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) 1319system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) 1320system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses) 1321system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) 1322system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) 1323system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) 1324system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1331system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses 1332system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses 1333system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses 1334system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses 1335system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses 1336system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses 1337system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses 1338system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses |
| 1297system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14715.884082 # average ReadReq miss latency 1298system.cpu.dcache.ReadReq_avg_miss_latency::total 14715.884082 # average ReadReq miss latency 1299system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46461.914150 # average WriteReq miss latency 1300system.cpu.dcache.WriteReq_avg_miss_latency::total 46461.914150 # average WriteReq miss latency 1301system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.779554 # average LoadLockedReq miss latency 1302system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.779554 # average LoadLockedReq miss latency 1303system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency 1304system.cpu.dcache.demand_avg_miss_latency::total 27561.441405 # average overall miss latency 1305system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency 1306system.cpu.dcache.overall_avg_miss_latency::total 27561.441405 # average overall miss latency | 1339system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.935999 # average ReadReq miss latency 1340system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.935999 # average ReadReq miss latency 1341system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46460.375042 # average WriteReq miss latency 1342system.cpu.dcache.WriteReq_avg_miss_latency::total 46460.375042 # average WriteReq miss latency 1343system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13910.943264 # average LoadLockedReq miss latency 1344system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13910.943264 # average LoadLockedReq miss latency 1345system.cpu.dcache.demand_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency 1346system.cpu.dcache.demand_avg_miss_latency::total 27559.658807 # average overall miss latency 1347system.cpu.dcache.overall_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency 1348system.cpu.dcache.overall_avg_miss_latency::total 27559.658807 # average overall miss latency |
| 1307system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1308system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1309system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1310system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1311system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1312system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1313system.cpu.dcache.fast_writes 0 # number of fast writes performed 1314system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1319system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250145 # number of WriteReq MSHR misses 1320system.cpu.dcache.WriteReq_mshr_misses::total 250145 # number of WriteReq MSHR misses 1321system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses 1322system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses 1323system.cpu.dcache.demand_mshr_misses::cpu.data 618199 # number of demand (read+write) MSHR misses 1324system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses 1325system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses 1326system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses | 1349system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1350system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1351system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1352system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1353system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1354system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1355system.cpu.dcache.fast_writes 0 # number of fast writes performed 1356system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 1361system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250145 # number of WriteReq MSHR misses 1362system.cpu.dcache.WriteReq_mshr_misses::total 250145 # number of WriteReq MSHR misses 1363system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses 1364system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses 1365system.cpu.dcache.demand_mshr_misses::cpu.data 618199 # number of demand (read+write) MSHR misses 1366system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses 1367system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses 1368system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses |
| 1327system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677837000 # number of ReadReq MSHR miss cycles 1328system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677837000 # number of ReadReq MSHR miss cycles 1329system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069989485 # number of WriteReq MSHR miss cycles 1330system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069989485 # number of WriteReq MSHR miss cycles 1331system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135550250 # number of LoadLockedReq MSHR miss cycles 1332system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135550250 # number of LoadLockedReq MSHR miss cycles 1333system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747826485 # number of demand (read+write) MSHR miss cycles 1334system.cpu.dcache.demand_mshr_miss_latency::total 15747826485 # number of demand (read+write) MSHR miss cycles 1335system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747826485 # number of overall MSHR miss cycles 1336system.cpu.dcache.overall_mshr_miss_latency::total 15747826485 # number of overall MSHR miss cycles 1337system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles 1338system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles | 1369system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677118000 # number of ReadReq MSHR miss cycles 1370system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677118000 # number of ReadReq MSHR miss cycles 1371system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069604485 # number of WriteReq MSHR miss cycles 1372system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069604485 # number of WriteReq MSHR miss cycles 1373system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135564000 # number of LoadLockedReq MSHR miss cycles 1374system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135564000 # number of LoadLockedReq MSHR miss cycles 1375system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15746722485 # number of demand (read+write) MSHR miss cycles 1376system.cpu.dcache.demand_mshr_miss_latency::total 15746722485 # number of demand (read+write) MSHR miss cycles 1377system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15746722485 # number of overall MSHR miss cycles 1378system.cpu.dcache.overall_mshr_miss_latency::total 15746722485 # number of overall MSHR miss cycles 1379system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050737750 # number of ReadReq MSHR uncacheable cycles 1380system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050737750 # number of ReadReq MSHR uncacheable cycles |
| 1339system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles 1340system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles | 1381system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles 1382system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles |
| 1341system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles 1342system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles | 1383system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284890100 # number of overall MSHR uncacheable cycles 1384system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284890100 # number of overall MSHR uncacheable cycles |
| 1343system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses 1344system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses 1345system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses 1346system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses 1347system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses 1348system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses 1349system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses 1350system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses 1351system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses 1352system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses | 1385system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses 1386system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses 1387system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses 1388system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses 1389system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses 1390system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses 1391system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses 1392system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses 1393system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses 1394system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses |
| 1353system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12709.648584 # average ReadReq mshr miss latency 1354system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12709.648584 # average ReadReq mshr miss latency 1355system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44254.290452 # average WriteReq mshr miss latency 1356system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44254.290452 # average WriteReq mshr miss latency 1357system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.992974 # average LoadLockedReq mshr miss latency 1358system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.992974 # average LoadLockedReq mshr miss latency 1359system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency 1360system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency 1361system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency 1362system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency | 1395system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12707.695066 # average ReadReq mshr miss latency 1396system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12707.695066 # average ReadReq mshr miss latency 1397system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44252.751344 # average WriteReq mshr miss latency 1398system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44252.751344 # average WriteReq mshr miss latency 1399system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11906.200597 # average LoadLockedReq mshr miss latency 1400system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11906.200597 # average LoadLockedReq mshr miss latency 1401system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency 1402system.cpu.dcache.demand_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency 1403system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency 1404system.cpu.dcache.overall_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency |
| 1363system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1364system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1365system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1366system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1367system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1368system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1369system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1405system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1406system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1407system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1408system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1409system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1410system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1411system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1370system.cpu.toL2Bus.throughput 52965193 # Throughput (bytes/s) 1371system.cpu.toL2Bus.trans_dist::ReadReq 2454584 # Transaction distribution 1372system.cpu.toL2Bus.trans_dist::ReadResp 2454584 # Transaction distribution | 1412system.cpu.toL2Bus.throughput 52965212 # Throughput (bytes/s) 1413system.cpu.toL2Bus.trans_dist::ReadReq 2454596 # Transaction distribution 1414system.cpu.toL2Bus.trans_dist::ReadResp 2454596 # Transaction distribution |
| 1373system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution 1374system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution 1375system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution 1376system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution 1377system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution 1378system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution 1379system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution | 1415system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution 1416system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution 1417system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution 1418system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution 1419system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution 1420system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution 1421system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution |
| 1380system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725150 # Packet count per connected master and slave (bytes) 1381system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749349 # Packet count per connected master and slave (bytes) | 1422system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) 1423system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749353 # Packet count per connected master and slave (bytes) |
| 1382system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) 1383system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) | 1424system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) 1425system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) |
| 1384system.cpu.toL2Bus.pkt_count::total 7514389 # Packet count per connected master and slave (bytes) 1385system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755188 # Cumulative packet size per connected master and slave (bytes) 1386system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614885 # Cumulative packet size per connected master and slave (bytes) | 1426system.cpu.toL2Bus.pkt_count::total 7514413 # Packet count per connected master and slave (bytes) 1427system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) 1428system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614893 # Cumulative packet size per connected master and slave (bytes) |
| 1387system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) 1388system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) | 1429system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) 1430system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) |
| 1389system.cpu.toL2Bus.tot_pkt_size::total 138419049 # Cumulative packet size per connected master and slave (bytes) 1390system.cpu.toL2Bus.data_through_bus 138419049 # Total data (bytes) | 1431system.cpu.toL2Bus.tot_pkt_size::total 138419097 # Cumulative packet size per connected master and slave (bytes) 1432system.cpu.toL2Bus.data_through_bus 138419097 # Total data (bytes) |
| 1391system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) | 1433system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) |
| 1392system.cpu.toL2Bus.reqLayer0.occupancy 3008582500 # Layer occupancy (ticks) | 1434system.cpu.toL2Bus.reqLayer0.occupancy 3008588500 # Layer occupancy (ticks) |
| 1393system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1435system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1394system.cpu.toL2Bus.respLayer0.occupancy 1295439000 # Layer occupancy (ticks) | 1436system.cpu.toL2Bus.respLayer0.occupancy 1295451750 # Layer occupancy (ticks) |
| 1395system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1437system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1396system.cpu.toL2Bus.respLayer1.occupancy 2534381165 # Layer occupancy (ticks) | 1438system.cpu.toL2Bus.respLayer1.occupancy 2534384415 # Layer occupancy (ticks) |
| 1397system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1398system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1399system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1400system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) 1401system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1402system.iocache.tags.replacements 0 # number of replacements 1403system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1404system.iocache.tags.total_refs 0 # Total number of references to valid blocks. --- 24 unchanged lines hidden --- | 1439system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1440system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) 1441system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1442system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) 1443system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1444system.iocache.tags.replacements 0 # number of replacements 1445system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1446system.iocache.tags.total_refs 0 # Total number of references to valid blocks. --- 24 unchanged lines hidden --- |