| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.591419 # Number of seconds simulated 4sim_ticks 2591419000000 # Number of ticks simulated 5final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 555808 # Simulator instruction rate (inst/s) 8host_op_rate 709857 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24337050134 # Simulator tick rate (ticks/s) 10host_mem_usage 383104 # Number of bytes of host memory used 11host_seconds 106.48 # Real time elapsed on the host |
| 12sim_insts 59182652 # Number of instructions simulated 13sim_ops 75585847 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory 19system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s) 52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) |
| 64system.l2c.replacements 117210 # number of replacements 65system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use 66system.l2c.total_refs 1536782 # Total number of references to valid blocks. 67system.l2c.sampled_refs 146347 # Sample count of references to valid blocks. 68system.l2c.avg_refs 10.500946 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor --- 85 unchanged lines hidden (view full) --- 157system.l2c.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses 158system.l2c.overall_accesses::cpu.inst 854305 # number of overall (read+write) accesses 159system.l2c.overall_accesses::cpu.data 625721 # number of overall (read+write) accesses 160system.l2c.overall_accesses::total 1492315 # number of overall (read+write) accesses 161system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 # miss rate for ReadReq accesses 162system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses 163system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses 164system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses |
| 165system.l2c.ReadReq_miss_rate::total 0.025341 # miss rate for ReadReq accesses |
| 166system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses |
| 167system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses |
| 168system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses |
| 169system.l2c.ReadExReq_miss_rate::total 0.568473 # miss rate for ReadExReq accesses |
| 170system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses 171system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses 172system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses 173system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses |
| 174system.l2c.demand_miss_rate::total 0.115451 # miss rate for demand accesses |
| 175system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses 176system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses 177system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses 178system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses |
| 179system.l2c.overall_miss_rate::total 0.115451 # miss rate for overall accesses |
| 180system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency 181system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 182system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency 183system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency |
| 184system.l2c.ReadReq_avg_miss_latency::total 52155.074026 # average ReadReq miss latency |
| 185system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency |
| 186system.l2c.UpgradeReq_avg_miss_latency::total 362.243121 # average UpgradeReq miss latency |
| 187system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency |
| 188system.l2c.ReadExReq_avg_miss_latency::total 52071.302204 # average ReadExReq miss latency |
| 189system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 190system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 191system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency 192system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency |
| 193system.l2c.demand_avg_miss_latency::total 52086.639310 # average overall miss latency |
| 194system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 195system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 196system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency 197system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency |
| 198system.l2c.overall_avg_miss_latency::total 52086.639310 # average overall miss latency |
| 199system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 200system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 201system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 202system.l2c.blocked::no_targets 0 # number of cycles access was blocked 203system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 204system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 205system.l2c.fast_writes 0 # number of fast writes performed 206system.l2c.cache_copies 0 # number of cache copies performed --- 44 unchanged lines hidden (view full) --- 251system.l2c.WriteReq_mshr_uncacheable_latency::total 31207839500 # number of WriteReq MSHR uncacheable cycles 252system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles 253system.l2c.overall_mshr_uncacheable_latency::cpu.data 162752588500 # number of overall MSHR uncacheable cycles 254system.l2c.overall_mshr_uncacheable_latency::total 163017428500 # number of overall MSHR uncacheable cycles 255system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for ReadReq accesses 256system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses 257system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses 258system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses |
| 259system.l2c.ReadReq_mshr_miss_rate::total 0.025341 # mshr miss rate for ReadReq accesses |
| 260system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses |
| 261system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses |
| 262system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses |
| 263system.l2c.ReadExReq_mshr_miss_rate::total 0.568473 # mshr miss rate for ReadExReq accesses |
| 264system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses 265system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses 266system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses 267system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses |
| 268system.l2c.demand_mshr_miss_rate::total 0.115451 # mshr miss rate for demand accesses |
| 269system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses 270system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses 271system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses 272system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses |
| 273system.l2c.overall_mshr_miss_rate::total 0.115451 # mshr miss rate for overall accesses |
| 274system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 275system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 276system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency 277system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency |
| 278system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958 # average ReadReq mshr miss latency |
| 279system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency |
| 280system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779 # average UpgradeReq mshr miss latency |
| 281system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency |
| 282system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651 # average ReadExReq mshr miss latency |
| 283system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 284system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 285system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency 286system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency |
| 287system.l2c.demand_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency |
| 288system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 289system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 290system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency 291system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency |
| 292system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency |
| 293system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 294system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency |
| 295system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
| 296system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |
| 297system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
| 298system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 299system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency |
| 300system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
| 301system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 302system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 303system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 304system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 305system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 306system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 307system.cf0.dma_write_txs 0 # Number of DMA write transactions. 308system.cpu.dtb.inst_hits 0 # ITB inst hits --- 91 unchanged lines hidden (view full) --- 400system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles 401system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses) 402system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses) 403system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses 404system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses 405system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses 406system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses 407system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses |
| 408system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses |
| 409system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses |
| 410system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses |
| 411system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses |
| 412system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses |
| 413system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency |
| 414system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency |
| 415system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency |
| 416system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency |
| 417system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency |
| 418system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency |
| 419system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 420system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 422system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 424system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.cpu.icache.fast_writes 0 # number of fast writes performed 426system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 438system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles 439system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles 440system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles 441system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles 442system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles 443system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles 444system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles 445system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses |
| 446system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses |
| 447system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses |
| 448system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses |
| 449system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses |
| 450system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses |
| 451system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency |
| 452system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency |
| 453system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency |
| 454system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency |
| 455system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency |
| 456system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency |
| 457system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency |
| 458system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
| 459system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency |
| 460system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
| 461system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 462system.cpu.dcache.replacements 627094 # number of replacements 463system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use 464system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks. 465system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks. 466system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks. 467system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. 468system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 508system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses) 509system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses) 510system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses) 511system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses 512system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses 513system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses 514system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses 515system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses |
| 516system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses |
| 517system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses |
| 518system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses |
| 519system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses |
| 520system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses |
| 521system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses |
| 522system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses |
| 523system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses |
| 524system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses |
| 525system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency |
| 526system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency |
| 527system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency |
| 528system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency |
| 529system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency |
| 530system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency |
| 531system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency |
| 532system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency |
| 533system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency |
| 534system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency |
| 535system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 539system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 540system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 541system.cpu.dcache.fast_writes 0 # number of fast writes performed 542system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 564system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles 565system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles 566system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles 567system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles 568system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles 569system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles 570system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles 571system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses |
| 572system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses |
| 573system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses |
| 574system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses |
| 575system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses |
| 576system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses |
| 577system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses |
| 578system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses |
| 579system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses |
| 580system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses |
| 581system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency |
| 582system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency |
| 583system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency |
| 584system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency |
| 585system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency |
| 586system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency |
| 587system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency |
| 588system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency |
| 589system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency |
| 590system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency |
| 591system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency |
| 592system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
| 593system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |
| 594system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
| 595system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency |
| 596system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
| 597system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 598system.iocache.replacements 0 # number of replacements 599system.iocache.tagsinuse 0 # Cycle average of tags in use 600system.iocache.total_refs 0 # Total number of references to valid blocks. 601system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 602system.iocache.avg_refs nan # Average number of references to valid blocks. 603system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 604system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 609system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 610system.iocache.fast_writes 0 # number of fast writes performed 611system.iocache.cache_copies 0 # number of cache copies performed 612system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles 613system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles 614system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles 615system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles 616system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency |
| 617system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
| 618system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |
| 619system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
| 620system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 621 622---------- End Simulation Statistics ---------- |