3,5c3,5
< sim_seconds 2.594328 # Number of seconds simulated
< sim_ticks 2594327510000 # Number of ticks simulated
< final_tick 2594327510000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.629150 # Number of seconds simulated
> sim_ticks 2629149747000 # Number of ticks simulated
> final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,51c7,13
< host_inst_rate 600896 # Simulator instruction rate (inst/s)
< host_op_rate 764626 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 25897323777 # Simulator tick rate (ticks/s)
< host_mem_usage 390576 # Number of bytes of host memory used
< host_seconds 100.18 # Real time elapsed on the host
< sim_insts 60196191 # Number of instructions simulated
< sim_ops 76598245 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 704288 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9067216 # Number of bytes read from this memory
< system.physmem.bytes_read::total 132455344 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 704288 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 704288 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 3695616 # Number of bytes written to this memory
< system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6711688 # Number of bytes written to this memory
< system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 17207 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 141709 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15494347 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 57744 # Number of write requests responded to by this memory
< system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 811762 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 47289092 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 271472 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3495016 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 51055753 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 271472 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 271472 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1424499 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 1162564 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2587063 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1424499 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 47289092 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 271472 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4657580 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53642816 # Total bandwidth to/from this memory (bytes/s)
---
> host_inst_rate 820445 # Simulator instruction rate (inst/s)
> host_op_rate 1044003 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 35827378651 # Simulator tick rate (ticks/s)
> host_mem_usage 386004 # Number of bytes of host memory used
> host_seconds 73.38 # Real time elapsed on the host
> sim_insts 60207390 # Number of instructions simulated
> sim_ops 76612873 # Number of ops (including micro ops) simulated
64,76c26,76
< system.l2c.replacements 62159 # number of replacements
< system.l2c.tagsinuse 51417.185894 # Cycle average of tags in use
< system.l2c.total_refs 1682923 # Total number of references to valid blocks.
< system.l2c.sampled_refs 127542 # Sample count of references to valid blocks.
< system.l2c.avg_refs 13.195049 # Average number of references to valid blocks.
< system.l2c.warmup_cycle 2544924960000 # Cycle when the warmup percentage was hit.
< system.l2c.occ_blocks::writebacks 38023.288706 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.dtb.walker 3.884784 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.itb.walker 0.000558 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.inst 7004.395748 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 6385.616098 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.580189 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
---
> system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory
> system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory
> system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s)
> system.l2c.replacements 62933 # number of replacements
> system.l2c.tagsinuse 51862.510726 # Cycle average of tags in use
> system.l2c.total_refs 1683379 # Total number of references to valid blocks.
> system.l2c.sampled_refs 128318 # Sample count of references to valid blocks.
> system.l2c.avg_refs 13.118806 # Average number of references to valid blocks.
> system.l2c.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit.
> system.l2c.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy
78,87c78,87
< system.l2c.occ_percent::cpu.inst 0.106879 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.data 0.097437 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.784564 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu.dtb.walker 8754 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.itb.walker 3544 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.inst 843519 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.data 370124 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1225941 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 596001 # number of Writeback hits
< system.l2c.Writeback_hits::total 596001 # number of Writeback hits
---
> system.l2c.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.791359 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.data 370308 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1226888 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 596416 # number of Writeback hits
> system.l2c.Writeback_hits::total 596416 # number of Writeback hits
90,102c90,102
< system.l2c.ReadExReq_hits::cpu.data 114391 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 114391 # number of ReadExReq hits
< system.l2c.demand_hits::cpu.dtb.walker 8754 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.itb.walker 3544 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.inst 843519 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.data 484515 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1340332 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu.dtb.walker 8754 # number of overall hits
< system.l2c.overall_hits::cpu.itb.walker 3544 # number of overall hits
< system.l2c.overall_hits::cpu.inst 843519 # number of overall hits
< system.l2c.overall_hits::cpu.data 484515 # number of overall hits
< system.l2c.overall_hits::total 1340332 # number of overall hits
< system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
---
> system.l2c.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 113846 # number of ReadExReq hits
> system.l2c.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.inst 844195 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.data 484154 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1340734 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu.dtb.walker 8836 # number of overall hits
> system.l2c.overall_hits::cpu.itb.walker 3549 # number of overall hits
> system.l2c.overall_hits::cpu.inst 844195 # number of overall hits
> system.l2c.overall_hits::cpu.data 484154 # number of overall hits
> system.l2c.overall_hits::total 1340734 # number of overall hits
> system.l2c.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses
104,111c104,111
< system.l2c.ReadReq_misses::cpu.inst 10591 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.data 10247 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 20845 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu.data 2879 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 2879 # number of UpgradeReq misses
< system.l2c.ReadExReq_misses::cpu.data 133059 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 133059 # number of ReadExReq misses
< system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.data 10261 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 20880 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 2845 # number of UpgradeReq misses
> system.l2c.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 133824 # number of ReadExReq misses
> system.l2c.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses
113,116c113,116
< system.l2c.demand_misses::cpu.inst 10591 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.data 143306 # number of demand (read+write) misses
< system.l2c.demand_misses::total 153904 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses
---
> system.l2c.demand_misses::cpu.inst 10613 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.data 144085 # number of demand (read+write) misses
> system.l2c.demand_misses::total 154704 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu.dtb.walker 4 # number of overall misses
118,121c118,121
< system.l2c.overall_misses::cpu.inst 10591 # number of overall misses
< system.l2c.overall_misses::cpu.data 143306 # number of overall misses
< system.l2c.overall_misses::total 153904 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu.dtb.walker 260500 # number of ReadReq miss cycles
---
> system.l2c.overall_misses::cpu.inst 10613 # number of overall misses
> system.l2c.overall_misses::cpu.data 144085 # number of overall misses
> system.l2c.overall_misses::total 154704 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles
123,125c123,125
< system.l2c.ReadReq_miss_latency::cpu.inst 552260500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.data 533540500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1086165500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles
128,130c128,130
< system.l2c.ReadExReq_miss_latency::cpu.data 6923957000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 6923957000 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu.dtb.walker 260500 # number of demand (read+write) miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles
132,135c132,135
< system.l2c.demand_miss_latency::cpu.inst 552260500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.data 7457497500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 8010122500 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu.dtb.walker 260500 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles
137,180c137,180
< system.l2c.overall_miss_latency::cpu.inst 552260500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.data 7457497500 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 8010122500 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu.dtb.walker 8759 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.itb.walker 3546 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.inst 854110 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.data 380371 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1246786 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 596001 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 596001 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu.data 2905 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 2905 # number of UpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu.data 247450 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 247450 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu.dtb.walker 8759 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.itb.walker 3546 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.inst 854110 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.data 627821 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1494236 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu.dtb.walker 8759 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.itb.walker 3546 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.inst 854110 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.data 627821 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1494236 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000571 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000564 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.inst 0.012400 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.data 0.026939 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.016719 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu.data 0.991050 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.991050 # miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu.data 0.537721 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.537721 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu.dtb.walker 0.000571 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.itb.walker 0.000564 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.inst 0.012400 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.data 0.228259 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.102998 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu.dtb.walker 0.000571 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.itb.walker 0.000564 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.inst 0.012400 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.data 0.228259 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.102998 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52100 # average ReadReq miss latency
---
> system.l2c.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 8049111500 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1495438 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1495438 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.103451 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.103451 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
182,189c182,189
< system.l2c.ReadReq_avg_miss_latency::cpu.inst 52144.320650 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.data 52067.971113 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 52106.764212 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu.data 361.236540 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 361.236540 # average UpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu.data 52036.743099 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 52036.743099 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52100 # average overall miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
191,194c191,194
< system.l2c.demand_avg_miss_latency::cpu.inst 52144.320650 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.data 52038.976037 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 52046.226869 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52100 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 52029.110430 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
196,198c196,198
< system.l2c.overall_avg_miss_latency::cpu.inst 52144.320650 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.data 52038.976037 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 52046.226869 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 52029.110430 # average overall miss latency
207,209c207,209
< system.l2c.writebacks::writebacks 57744 # number of writebacks
< system.l2c.writebacks::total 57744 # number of writebacks
< system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
---
> system.l2c.writebacks::writebacks 58379 # number of writebacks
> system.l2c.writebacks::total 58379 # number of writebacks
> system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses
211,218c211,218
< system.l2c.ReadReq_mshr_misses::cpu.inst 10591 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.data 10247 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 20845 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu.data 2879 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 2879 # number of UpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu.data 133059 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 133059 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses
220,223c220,223
< system.l2c.demand_mshr_misses::cpu.inst 10591 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.data 143306 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 153904 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses
225,228c225,228
< system.l2c.overall_mshr_misses::cpu.inst 10591 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.data 143306 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 153904 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles
---
> system.l2c.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 154704 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles
230,237c230,237
< system.l2c.ReadReq_mshr_miss_latency::cpu.inst 425162000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.data 410573000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 836015000 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 115365000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 115365000 # number of UpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5327229000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 5327229000 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles
239,242c239,242
< system.l2c.demand_mshr_miss_latency::cpu.inst 425162000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.data 5737802000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 6163244000 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles
244,246c244,246
< system.l2c.overall_mshr_miss_latency::cpu.inst 425162000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.data 5737802000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 6163244000 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles
248,251c248,251
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131435179000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 131700019000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31197392500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 31197392500 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles
253,273c253,273
< system.l2c.overall_mshr_uncacheable_latency::cpu.data 162632571500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 162897411500 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026939 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.016719 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991050 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.991050 # mshr miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.537721 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.537721 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.data 0.228259 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.102998 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.data 0.228259 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.102998 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses
276,282c276,282
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.706921 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40067.629550 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 40106.260494 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40071.205280 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40071.205280 # average UpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40036.592790 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40036.592790 # average ReadExReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency
285,287c285,287
< system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
290,292c290,292
< system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
310,313c310,313
< system.cpu.dtb.read_hits 14995137 # DTB read hits
< system.cpu.dtb.read_misses 7357 # DTB read misses
< system.cpu.dtb.write_hits 11229787 # DTB write hits
< system.cpu.dtb.write_misses 2205 # DTB write misses
---
> system.cpu.dtb.read_hits 14998169 # DTB read hits
> system.cpu.dtb.read_misses 7372 # DTB read misses
> system.cpu.dtb.write_hits 11231565 # DTB write hits
> system.cpu.dtb.write_misses 2270 # DTB write misses
318c318
< system.cpu.dtb.flush_entries 3485 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
320c320
< system.cpu.dtb.prefetch_faults 182 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch
323,324c323,324
< system.cpu.dtb.read_accesses 15002494 # DTB read accesses
< system.cpu.dtb.write_accesses 11231992 # DTB write accesses
---
> system.cpu.dtb.read_accesses 15005541 # DTB read accesses
> system.cpu.dtb.write_accesses 11233835 # DTB write accesses
326,329c326,329
< system.cpu.dtb.hits 26224924 # DTB hits
< system.cpu.dtb.misses 9562 # DTB misses
< system.cpu.dtb.accesses 26234486 # DTB accesses
< system.cpu.itb.inst_hits 61490084 # ITB inst hits
---
> system.cpu.dtb.hits 26229734 # DTB hits
> system.cpu.dtb.misses 9642 # DTB misses
> system.cpu.dtb.accesses 26239376 # DTB accesses
> system.cpu.itb.inst_hits 61501359 # ITB inst hits
346,347c346,347
< system.cpu.itb.inst_accesses 61494555 # ITB inst accesses
< system.cpu.itb.hits 61490084 # DTB hits
---
> system.cpu.itb.inst_accesses 61505830 # ITB inst accesses
> system.cpu.itb.hits 61501359 # DTB hits
349,350c349,350
< system.cpu.itb.accesses 61494555 # DTB accesses
< system.cpu.numCycles 5188655020 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 61505830 # DTB accesses
> system.cpu.numCycles 5258299494 # number of cpu cycles simulated
353,355c353,355
< system.cpu.committedInsts 60196191 # Number of instructions committed
< system.cpu.committedOps 76598245 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 68865648 # Number of integer alu accesses
---
> system.cpu.committedInsts 60207390 # Number of instructions committed
> system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses
357,359c357,359
< system.cpu.num_func_calls 2139540 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 7910583 # number of instructions that are conditional controls
< system.cpu.num_int_insts 68865648 # number of integer instructions
---
> system.cpu.num_func_calls 2140176 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 7911775 # number of instructions that are conditional controls
> system.cpu.num_int_insts 68878830 # number of integer instructions
361,362c361,362
< system.cpu.num_int_register_reads 394743471 # number of times the integer registers were read
< system.cpu.num_int_register_writes 74177139 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read
> system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written
365,371c365,371
< system.cpu.num_mem_refs 27392126 # number of memory refs
< system.cpu.num_load_insts 15659006 # Number of load instructions
< system.cpu.num_store_insts 11733120 # Number of store instructions
< system.cpu.num_idle_cycles 4570211154.554238 # Number of idle cycles
< system.cpu.num_busy_cycles 618443865.445762 # Number of busy cycles
< system.cpu.not_idle_fraction 0.119192 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.880808 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 27397151 # number of memory refs
> system.cpu.num_load_insts 15662227 # Number of load instructions
> system.cpu.num_store_insts 11734924 # Number of store instructions
> system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles
> system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles
> system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.868680 # Percentage of idle cycles
373,418c373,418
< system.cpu.kern.inst.quiesce 82989 # number of quiesce instructions executed
< system.cpu.icache.replacements 855220 # number of replacements
< system.cpu.icache.tagsinuse 510.929118 # Cycle average of tags in use
< system.cpu.icache.total_refs 60634352 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 855732 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 70.856707 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 18856022000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.929118 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.997908 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.997908 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 60634352 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 60634352 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 60634352 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 60634352 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 60634352 # number of overall hits
< system.cpu.icache.overall_hits::total 60634352 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 855732 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 855732 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 855732 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 855732 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 855732 # number of overall misses
< system.cpu.icache.overall_misses::total 855732 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12556184500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12556184500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12556184500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12556184500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12556184500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12556184500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 61490084 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 61490084 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 61490084 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 61490084 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 61490084 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 61490084 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013917 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.013917 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.013917 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.013917 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14673.033730 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14673.033730 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14673.033730 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14673.033730 # average overall miss latency
---
> system.cpu.kern.inst.quiesce 83013 # number of quiesce instructions executed
> system.cpu.icache.replacements 855930 # number of replacements
> system.cpu.icache.tagsinuse 510.898307 # Cycle average of tags in use
> system.cpu.icache.total_refs 60644917 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 856442 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 70.810302 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 19819985000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.898307 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.997848 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.997848 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 60644917 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 60644917 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 60644917 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 60644917 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 60644917 # number of overall hits
> system.cpu.icache.overall_hits::total 60644917 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 856442 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 856442 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 856442 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 856442 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 856442 # number of overall misses
> system.cpu.icache.overall_misses::total 856442 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12566277500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12566277500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12566277500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12566277500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12566277500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12566277500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 61501359 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 61501359 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 61501359 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 61501359 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 61501359 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 61501359 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14672.654424 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14672.654424 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14672.654424 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14672.654424 # average overall miss latency
427,438c427,438
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855732 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 855732 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 855732 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 855732 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 855732 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 855732 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9987081500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9987081500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9987081500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9987081500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9987081500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9987081500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856442 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 856442 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 856442 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 856442 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 856442 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 856442 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9995044500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9995044500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9995044500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9995044500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9995044500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9995044500 # number of overall MSHR miss cycles
443,454c443,454
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013917 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.427770 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.427770 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency
460,464c460,464
< system.cpu.dcache.replacements 627309 # number of replacements
< system.cpu.dcache.tagsinuse 511.875626 # Cycle average of tags in use
< system.cpu.dcache.total_refs 23653426 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 627821 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 37.675430 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 627727 # number of replacements
> system.cpu.dcache.tagsinuse 511.877273 # Cycle average of tags in use
> system.cpu.dcache.total_refs 23657788 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 628239 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 37.657306 # Average number of references to valid blocks.
466,532c466,532
< system.cpu.dcache.occ_blocks::cpu.data 511.875626 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 13194612 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13194612 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 9972158 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 9972158 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 236094 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 236094 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 247657 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 247657 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 23166770 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 23166770 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 23166770 # number of overall hits
< system.cpu.dcache.overall_hits::total 23166770 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 368807 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 368807 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 250355 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 250355 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 11564 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 11564 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 619162 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 619162 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 619162 # number of overall misses
< system.cpu.dcache.overall_misses::total 619162 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5738700500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5738700500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9229453000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9229453000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171857500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 171857500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14968153500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14968153500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14968153500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14968153500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13563419 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13563419 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10222513 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10222513 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247658 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 247658 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 247657 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 247657 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 23785932 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 23785932 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 23785932 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 23785932 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027191 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.027191 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024491 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.024491 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046693 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046693 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.026031 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.026031 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.026031 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.026031 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 24174.858115 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 24174.858115 # average overall miss latency
---
> system.cpu.dcache.occ_blocks::cpu.data 511.877273 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.999760 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.999760 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 13196825 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13196825 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 9973191 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 9973191 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 236701 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236701 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 248200 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 248200 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 23170016 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 23170016 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 23170016 # number of overall hits
> system.cpu.dcache.overall_hits::total 23170016 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 369069 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 369069 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 250541 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 250541 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 619610 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 619610 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 619610 # number of overall misses
> system.cpu.dcache.overall_misses::total 619610 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5742174000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5742174000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9260838000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9260838000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170995500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 170995500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15003012000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15003012000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15003012000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15003012000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13565894 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13565894 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10223732 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10223732 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248201 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 248201 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 248200 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 248200 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 23789626 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 23789626 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 23789626 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 23789626 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027206 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.027206 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024506 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.024506 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046333 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046333 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.026045 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.026045 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.026045 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.026045 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15558.537834 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15558.537834 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36963.363282 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 36963.363282 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14869.173913 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14869.173913 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 24213.637611 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 24213.637611 # average overall miss latency
541,588c541,588
< system.cpu.dcache.writebacks::writebacks 596001 # number of writebacks
< system.cpu.dcache.writebacks::total 596001 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368807 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 368807 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250355 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 250355 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11564 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 11564 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 619162 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 619162 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 619162 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 619162 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4631124500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4631124500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8478310000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8478310000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137164000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137164000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13109434500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13109434500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13109434500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13109434500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40357680500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40357680500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027191 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027191 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024491 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046693 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046693 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.026031 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.026031 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks
> system.cpu.dcache.writebacks::total 596416 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 369069 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250541 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 250541 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 619610 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 619610 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 619610 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 619610 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4633803000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4633803000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509109000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509109000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136482000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136482000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13142912000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13142912000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13142912000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13142912000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41013343500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41013343500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027206 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027206 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046333 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046333 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.026045 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.026045 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency
610,613c610,613
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1342178832750 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles