3,5c3,5
< sim_seconds 2.603665 # Number of seconds simulated
< sim_ticks 2603664815000 # Number of ticks simulated
< final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.603674 # Number of seconds simulated
> sim_ticks 2603674284000 # Number of ticks simulated
> final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 536000 # Simulator instruction rate (inst/s)
< host_op_rate 682052 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 23183028791 # Simulator tick rate (ticks/s)
< host_mem_usage 404656 # Number of bytes of host memory used
< host_seconds 112.31 # Real time elapsed on the host
< sim_insts 60197643 # Number of instructions simulated
< sim_ops 76600583 # Number of ops (including micro ops) simulated
---
> host_inst_rate 271279 # Simulator instruction rate (inst/s)
> host_op_rate 345198 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 11733407598 # Simulator tick rate (ticks/s)
> host_mem_usage 403640 # Number of bytes of host memory used
> host_seconds 221.90 # Real time elapsed on the host
> sim_insts 60197457 # Number of instructions simulated
> sim_ops 76600355 # Number of ops (including micro ops) simulated
17,22c17,22
< system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
< system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
> system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
24c24
< system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
28,31c28,31
< system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
33,34c33,34
< system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s)
37,46c37,46
< system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s)
49,58c49,58
< system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15494089 # Total number of read requests seen
< system.physmem.writeReqs 811479 # Total number of write requests seen
< system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 991621696 # Total number of bytes read from memory
< system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
---
> system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15494095 # Total number of read requests seen
> system.physmem.writeReqs 811481 # Total number of write requests seen
> system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 991622080 # Total number of bytes read from memory
> system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
69c69
< system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis
75c75
< system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis
85c85
< system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis
91c91
< system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis
95c95
< system.physmem.totGap 2603660455000 # Total gap between requests
---
> system.physmem.totGap 2603669924000 # Total gap between requests
102,139c102,126
< system.physmem.readPktSize::6 152013 # Categorize read packet sizes
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 754018 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 57461 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see
---
> system.physmem.readPktSize::6 152019 # Categorize read packet sizes
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 754018 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 57463 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see
155,163c142,149
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see
172,173c158,159
< system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see
179,186c165,172
< system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
188,194c174,179
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests
< system.physmem.totBusLat 77468765000 # Total cycles spent in databus access
< system.physmem.totBankLat 17445216250 # Total cycles spent in bank access
< system.physmem.avgQLat 22041.64 # Average queueing delay per request
< system.physmem.avgBankLat 1125.95 # Average bank access latency per request
---
> system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests
> system.physmem.totBusLat 77468795000 # Total cycles spent in databus access
> system.physmem.totBankLat 17451610000 # Total cycles spent in bank access
> system.physmem.avgQLat 22040.37 # Average queueing delay per request
> system.physmem.avgBankLat 1126.36 # Average bank access latency per request
196,197c181,182
< system.physmem.avgMemAccLat 28167.59 # Average memory access latency
< system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgMemAccLat 28166.74 # Average memory access latency
> system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s
204,206c189,191
< system.physmem.avgWrQLen 12.39 # Average write queue length over time
< system.physmem.readRowHits 15418905 # Number of row buffer hits during reads
< system.physmem.writeRowHits 794060 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 12.40 # Average write queue length over time
> system.physmem.readRowHits 15418728 # Number of row buffer hits during reads
> system.physmem.writeRowHits 794030 # Number of row buffer hits during writes
209c194
< system.physmem.avgGap 159679.22 # Average gap between requests
---
> system.physmem.avgGap 159679.73 # Average gap between requests
230c215
< system.cpu.dtb.read_hits 14995667 # DTB read hits
---
> system.cpu.dtb.read_hits 14995645 # DTB read hits
232c217
< system.cpu.dtb.write_hits 11230865 # DTB write hits
---
> system.cpu.dtb.write_hits 11230857 # DTB write hits
243,244c228,229
< system.cpu.dtb.read_accesses 15002999 # DTB read accesses
< system.cpu.dtb.write_accesses 11233068 # DTB write accesses
---
> system.cpu.dtb.read_accesses 15002977 # DTB read accesses
> system.cpu.dtb.write_accesses 11233060 # DTB write accesses
246c231
< system.cpu.dtb.hits 26226532 # DTB hits
---
> system.cpu.dtb.hits 26226502 # DTB hits
248,249c233,234
< system.cpu.dtb.accesses 26236067 # DTB accesses
< system.cpu.itb.inst_hits 61491584 # ITB inst hits
---
> system.cpu.dtb.accesses 26236037 # DTB accesses
> system.cpu.itb.inst_hits 61491397 # ITB inst hits
266,267c251,252
< system.cpu.itb.inst_accesses 61496055 # ITB inst accesses
< system.cpu.itb.hits 61491584 # DTB hits
---
> system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
> system.cpu.itb.hits 61491397 # DTB hits
269,270c254,255
< system.cpu.itb.accesses 61496055 # DTB accesses
< system.cpu.numCycles 5207329630 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 61495868 # DTB accesses
> system.cpu.numCycles 5207348568 # number of cpu cycles simulated
273,275c258,260
< system.cpu.committedInsts 60197643 # Number of instructions committed
< system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses
---
> system.cpu.committedInsts 60197457 # Number of instructions committed
> system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses
277,279c262,264
< system.cpu.num_func_calls 2139730 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls
< system.cpu.num_int_insts 68868344 # number of integer instructions
---
> system.cpu.num_func_calls 2139722 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls
> system.cpu.num_int_insts 68868122 # number of integer instructions
281,282c266,267
< system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read
< system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
> system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written
285,291c270,276
< system.cpu.num_mem_refs 27393912 # number of memory refs
< system.cpu.num_load_insts 15659685 # Number of load instructions
< system.cpu.num_store_insts 11734227 # Number of store instructions
< system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles
< system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles
< system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.879355 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 27393871 # number of memory refs
> system.cpu.num_load_insts 15659652 # Number of load instructions
> system.cpu.num_store_insts 11734219 # Number of store instructions
> system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles
> system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles
> system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.879352 # Percentage of idle cycles
294,298c279,283
< system.cpu.icache.replacements 855486 # number of replacements
< system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use
< system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks.
---
> system.cpu.icache.replacements 855484 # number of replacements
> system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use
> system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks.
300c285
< system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor
303,326c288,311
< system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits
< system.cpu.icache.overall_hits::total 60635586 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses
< system.cpu.icache.overall_misses::total 855998 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits
> system.cpu.icache.overall_hits::total 60635401 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses
> system.cpu.icache.overall_misses::total 855996 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses
333,338c318,323
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13514.988388 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13514.988388 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13514.988388 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13514.988388 # average overall miss latency
347,358c332,343
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855998 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 855998 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 855998 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 855998 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 855998 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 855998 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9857308000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9857308000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9857308000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9857308000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9857308000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9857308000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855996 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 855996 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 855996 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 855996 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 855996 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 855996 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9856784000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9856784000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9856784000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9856784000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9856784000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9856784000 # number of overall MSHR miss cycles
369,374c354,359
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11515.573635 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11515.573635 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11514.988388 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11514.988388 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency
380,386c365,371
< system.cpu.l2cache.replacements 61906 # number of replacements
< system.cpu.l2cache.tagsinuse 50893.814517 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 1682715 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 127287 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 13.219850 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 2553152311000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 37867.919206 # Average occupied blocks per requestor
---
> system.cpu.l2cache.replacements 61912 # number of replacements
> system.cpu.l2cache.tagsinuse 50892.966587 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 1682705 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 13.219148 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 2553153097000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 37868.000507 # Average occupied blocks per requestor
389,391c374,376
< system.cpu.l2cache.occ_blocks::cpu.inst 6996.279505 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 6025.728892 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.577819 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::cpu.inst 6995.362387 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 6025.716777 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.577820 # Average percentage of cache occupancy
394c379
< system.cpu.l2cache.occ_percent::cpu.inst 0.106755 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::cpu.inst 0.106741 # Average percentage of cache occupancy
396c381
< system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::total 0.776565 # Average percentage of cache occupancy
399,403c384,388
< system.cpu.l2cache.ReadReq_hits::cpu.inst 843761 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 370335 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1226345 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 596039 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 596039 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 843754 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 370328 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1226331 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 596040 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 596040 # number of Writeback hits
406,407c391,392
< system.cpu.l2cache.ReadExReq_hits::cpu.data 114427 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 114427 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 114438 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 114438 # number of ReadExReq hits
410,412c395,397
< system.cpu.l2cache.demand_hits::cpu.inst 843761 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 484762 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1340772 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 843754 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 484766 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1340769 # number of demand (read+write) hits
415,417c400,402
< system.cpu.l2cache.overall_hits::cpu.inst 843761 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 484762 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1340772 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 843754 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 484766 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1340769 # number of overall hits
420,422c405,407
< system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses
429,431c414,416
< system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 143041 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 153648 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses
434,436c419,421
< system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 143041 # number of overall misses
< system.cpu.l2cache.overall_misses::total 153648 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses
> system.cpu.l2cache.overall_misses::total 153654 # number of overall misses
439,445c424,430
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 562062000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534519000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1097047500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075862000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6075862000 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 561610000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 535948000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1098024500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 462000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 462000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6083213000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6083213000 # number of ReadExReq miss cycles
448,450c433,435
< system.cpu.l2cache.demand_miss_latency::cpu.inst 562062000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6610381000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 7172909500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 561610000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6619161000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 7181237500 # number of demand (read+write) miss cycles
453,455c438,440
< system.cpu.l2cache.overall_miss_latency::cpu.inst 562062000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6610381000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 7172909500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 561610000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6619161000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 7181237500 # number of overall miss cycles
458,462c443,447
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 854360 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 380193 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1246810 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 596039 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 596039 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 854358 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 380187 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1246802 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 596040 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 596040 # number of Writeback accesses(hits+misses)
465,466c450,451
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 247610 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 247610 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 247621 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 247621 # number of ReadExReq accesses(hits+misses)
469,471c454,456
< system.cpu.l2cache.demand_accesses::cpu.inst 854360 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 627803 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1494420 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 854358 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 627808 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1494423 # number of demand (read+write) accesses
474,476c459,461
< system.cpu.l2cache.overall_accesses::cpu.inst 854360 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 627803 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1494420 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 854358 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 627808 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1494423 # number of overall (read+write) accesses
479,481c464,466
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012406 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025929 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses
484,485c469,470
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537874 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.537874 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537850 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.537850 # miss rate for ReadExReq accesses
488c473
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012406 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses
490c475
< system.cpu.l2cache.demand_miss_rate::total 0.102814 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.102818 # miss rate for demand accesses
493c478
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012406 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses
495c480
< system.cpu.l2cache.overall_miss_rate::total 0.102814 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::total 0.102818 # miss rate for overall accesses
498,504c483,489
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53029.719785 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54221.850274 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 53606.034693 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45620.402003 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45620.402003 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52962.089777 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54361.294249 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 53638.048947 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.695652 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.695652 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45675.596735 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45675.596735 # average ReadExReq miss latency
507,509c492,494
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 46684.040795 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 46736.417536 # average overall miss latency
512,514c497,499
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 46684.040795 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 46736.417536 # average overall miss latency
523,524c508,509
< system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks
< system.cpu.l2cache.writebacks::total 57461 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks
> system.cpu.l2cache.writebacks::total 57463 # number of writebacks
527,529c512,514
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses
536,538c521,523
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 143041 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 153648 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses
541,570c526,555
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 143041 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 153648 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253760 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113756 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430665051 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411778800 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 842811367 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28850324 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28850324 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4437954325 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4437954325 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253760 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113756 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430665051 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4849733125 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 5280765692 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253760 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113756 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430665051 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4849733125 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 5280765692 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209122550 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688445815 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166897568365 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9173753597 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9173753597 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209122550 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175862199412 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176071321962 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253755 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113753 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430132104 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413197859 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 843697471 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28847322 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28847322 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4445123890 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4445123890 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253755 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113753 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430132104 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4858321749 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 5288821361 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253755 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113753 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430132104 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4858321749 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 5288821361 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209116116 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166689052786 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166898168902 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175171345 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175171345 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209116116 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175864224131 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176073340247 # number of overall MSHR uncacheable cycles
573,575c558,560
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025929 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses
578,579c563,564
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537874 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537874 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537850 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537850 # mshr miss rate for ReadExReq accesses
582c567
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses
584c569
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.102814 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.102818 # mshr miss rate for demand accesses
587c572
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses
589,608c574,593
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.102814 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40632.611661 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41771.028606 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41183.062155 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10034.895304 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10034.895304 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33322.228250 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33322.228250 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.102818 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40563.193512 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41910.727153 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41214.277319 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10033.851130 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10033.851130 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33376.060683 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33376.060683 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency
618c603
< system.cpu.dcache.replacements 627291 # number of replacements
---
> system.cpu.dcache.replacements 627296 # number of replacements
620,622c605,607
< system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks.
---
> system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks.
627,632c612,617
< system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits
635,662c620,647
< system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits
< system.cpu.dcache.overall_hits::total 23168189 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses
< system.cpu.dcache.overall_misses::total 619303 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 23168154 # number of overall hits
> system.cpu.dcache.overall_hits::total 23168154 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 368785 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 368785 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 250522 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 250522 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 619307 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 619307 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 619307 # number of overall misses
> system.cpu.dcache.overall_misses::total 619307 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5224078000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5224078000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8042704500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8042704500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155711000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 155711000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13266782500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13266782500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13266782500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13266782500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses)
667,670c652,655
< system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses
673,676c658,661
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024504 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.024504 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses
681,690c666,675
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14165.646650 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14165.646650 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32103.785296 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 32103.785296 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13656.463778 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13656.463778 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 21421.980536 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency
699,726c684,711
< system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks
< system.cpu.dcache.writebacks::total 596039 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks
> system.cpu.dcache.writebacks::total 596040 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles
729,732c714,717
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses
737,746c722,731
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency
768,771c753,756
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles