3,5c3,5
< sim_seconds 2.603636 # Number of seconds simulated
< sim_ticks 2603636076000 # Number of ticks simulated
< final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.603635 # Number of seconds simulated
> sim_ticks 2603634694000 # Number of ticks simulated
> final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,25
< host_inst_rate 264193 # Simulator instruction rate (inst/s)
< host_op_rate 336182 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11426847777 # Simulator tick rate (ticks/s)
< host_mem_usage 395692 # Number of bytes of host memory used
< host_seconds 227.85 # Real time elapsed on the host
< sim_insts 60197128 # Number of instructions simulated
< sim_ops 76599899 # Number of ops (including micro ops) simulated
---
> host_inst_rate 156094 # Simulator instruction rate (inst/s)
> host_op_rate 198627 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 6751306864 # Simulator tick rate (ticks/s)
> host_mem_usage 397752 # Number of bytes of host memory used
> host_seconds 385.65 # Real time elapsed on the host
> sim_insts 60197457 # Number of instructions simulated
> sim_ops 76600355 # Number of ops (including micro ops) simulated
> system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
17,22c29,34
< system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
< system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
> system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
24c36
< system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
28,31c40,43
< system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
33,34c45,46
< system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s)
37,42c49,54
< system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s)
44,46c56,58
< system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s)
49,58c61,70
< system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15494089 # Total number of read requests seen
< system.physmem.writeReqs 811479 # Total number of write requests seen
< system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 991621696 # Total number of bytes read from memory
< system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
---
> system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15494095 # Total number of read requests seen
> system.physmem.writeReqs 811481 # Total number of write requests seen
> system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 991622080 # Total number of bytes read from memory
> system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
65c77
< system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis
76c88
< system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis
81c93
< system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis
92c104
< system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis
95c107
< system.physmem.totGap 2603631716000 # Total gap between requests
---
> system.physmem.totGap 2603630334000 # Total gap between requests
102c114
< system.physmem.readPktSize::6 152013 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 152019 # Categorize read packet sizes
111c123
< system.physmem.writePktSize::6 57461 # categorize write packet sizes
---
> system.physmem.writePktSize::6 57463 # categorize write packet sizes
123,139c135,151
< system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see
156,159c168,171
< system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see
172,173c184,185
< system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see
179,182c191,194
< system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
189,194c201,206
< system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests
< system.physmem.totBusLat 61975012000 # Total cycles spent in databus access
< system.physmem.totBankLat 216185438000 # Total cycles spent in bank access
< system.physmem.avgQLat 242.04 # Average queueing delay per request
< system.physmem.avgBankLat 13953.07 # Average bank access latency per request
---
> system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests
> system.physmem.totBusLat 61975036000 # Total cycles spent in databus access
> system.physmem.totBankLat 16863224000 # Total cycles spent in bank access
> system.physmem.avgQLat 18619.82 # Average queueing delay per request
> system.physmem.avgBankLat 1088.39 # Average bank access latency per request
196c208
< system.physmem.avgMemAccLat 18195.12 # Average memory access latency
---
> system.physmem.avgMemAccLat 23708.21 # Average memory access latency
203,221c215,221
< system.physmem.avgRdQLen 0.11 # Average read queue length over time
< system.physmem.avgWrQLen 12.38 # Average write queue length over time
< system.physmem.readRowHits 15449450 # Number of row buffer hits during reads
< system.physmem.writeRowHits 784611 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
< system.physmem.avgGap 159677.46 # Average gap between requests
< system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.avgRdQLen 0.14 # Average read queue length over time
> system.physmem.avgWrQLen 12.40 # Average write queue length over time
> system.physmem.readRowHits 15451886 # Number of row buffer hits during reads
> system.physmem.writeRowHits 785061 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes
> system.physmem.avgGap 159677.30 # Average gap between requests
230,232c230,232
< system.cpu.dtb.read_hits 14995523 # DTB read hits
< system.cpu.dtb.read_misses 7332 # DTB read misses
< system.cpu.dtb.write_hits 11230789 # DTB write hits
---
> system.cpu.dtb.read_hits 14995645 # DTB read hits
> system.cpu.dtb.read_misses 7331 # DTB read misses
> system.cpu.dtb.write_hits 11230857 # DTB write hits
243,244c243,244
< system.cpu.dtb.read_accesses 15002855 # DTB read accesses
< system.cpu.dtb.write_accesses 11232992 # DTB write accesses
---
> system.cpu.dtb.read_accesses 15002976 # DTB read accesses
> system.cpu.dtb.write_accesses 11233060 # DTB write accesses
246,249c246,249
< system.cpu.dtb.hits 26226312 # DTB hits
< system.cpu.dtb.misses 9535 # DTB misses
< system.cpu.dtb.accesses 26235847 # DTB accesses
< system.cpu.itb.inst_hits 61491068 # ITB inst hits
---
> system.cpu.dtb.hits 26226502 # DTB hits
> system.cpu.dtb.misses 9534 # DTB misses
> system.cpu.dtb.accesses 26236036 # DTB accesses
> system.cpu.itb.inst_hits 61491397 # ITB inst hits
266,267c266,267
< system.cpu.itb.inst_accesses 61495539 # ITB inst accesses
< system.cpu.itb.hits 61491068 # DTB hits
---
> system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
> system.cpu.itb.hits 61491397 # DTB hits
269,270c269,270
< system.cpu.itb.accesses 61495539 # DTB accesses
< system.cpu.numCycles 5207272152 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 61495868 # DTB accesses
> system.cpu.numCycles 5207269388 # number of cpu cycles simulated
273,275c273,275
< system.cpu.committedInsts 60197128 # Number of instructions committed
< system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses
---
> system.cpu.committedInsts 60197457 # Number of instructions committed
> system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses
277,279c277,279
< system.cpu.num_func_calls 2139710 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls
< system.cpu.num_int_insts 68867725 # number of integer instructions
---
> system.cpu.num_func_calls 2139722 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls
> system.cpu.num_int_insts 68868122 # number of integer instructions
281,282c281,282
< system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read
< system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
> system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written
285,291c285,291
< system.cpu.num_mem_refs 27393681 # number of memory refs
< system.cpu.num_load_insts 15659530 # Number of load instructions
< system.cpu.num_store_insts 11734151 # Number of store instructions
< system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles
< system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles
< system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.879363 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 27393871 # number of memory refs
> system.cpu.num_load_insts 15659652 # Number of load instructions
> system.cpu.num_store_insts 11734219 # Number of store instructions
> system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles
> system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles
> system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.879373 # Percentage of idle cycles
294,298c294,298
< system.cpu.icache.replacements 855500 # number of replacements
< system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use
< system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks.
---
> system.cpu.icache.replacements 855485 # number of replacements
> system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use
> system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks.
300c300
< system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor
303,326c303,326
< system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits
< system.cpu.icache.overall_hits::total 60635056 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses
< system.cpu.icache.overall_misses::total 856012 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits
> system.cpu.icache.overall_hits::total 60635400 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses
> system.cpu.icache.overall_misses::total 855997 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses
333,338c333,338
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency
347,358c347,358
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 855997 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 855997 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 855997 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 855997 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 855997 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9827690000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9827690000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9827690000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9827690000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9827690000 # number of overall MSHR miss cycles
369,374c369,374
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11480.986499 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11480.986499 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency
380,522c380,386
< system.cpu.dcache.replacements 627255 # number of replacements
< system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use
< system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 627767 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 37.680956 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 13195024 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13195024 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 9972994 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 9972994 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 236273 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 236273 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 247672 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 247672 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 23168018 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 23168018 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 23168018 # number of overall hits
< system.cpu.dcache.overall_hits::total 23168018 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 368763 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 368763 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 250502 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 250502 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 619265 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses
< system.cpu.dcache.overall_misses::total 619265 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205933000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5205933000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061519000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8061519000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154593000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 154593000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13267452000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13267452000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13267452000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13267452000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10223496 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247673 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 247673 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 247672 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 247672 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 23787283 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 23787283 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 23787283 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 23787283 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027187 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.027187 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046028 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046028 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14117.286713 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14117.286713 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.455637 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.455637 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.789474 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.789474 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 21424.514545 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21424.514545 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 596013 # number of writebacks
< system.cpu.dcache.writebacks::total 596013 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368763 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 368763 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250502 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 250502 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 619265 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468407000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468407000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560515000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560515000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131793000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131793000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028922000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12028922000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028922000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12028922000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182088074500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182088074500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708050000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708050000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200796124500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 200796124500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12117.286713 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12117.286713 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.455637 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.455637 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11560.789474 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11560.789474 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.l2cache.replacements 61906 # number of replacements
< system.cpu.l2cache.tagsinuse 50893.840705 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 1682733 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 13.219887 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 37868.665520 # Average occupied blocks per requestor
---
> system.cpu.l2cache.replacements 61912 # number of replacements
> system.cpu.l2cache.tagsinuse 50893.937876 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 1682687 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 13.219007 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 2553095791000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 37868.725267 # Average occupied blocks per requestor
525,527c389,391
< system.cpu.l2cache.occ_blocks::cpu.inst 6995.476581 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 6025.811619 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::cpu.inst 6995.530011 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 6025.795614 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.577831 # Average percentage of cache occupancy
531,533c395,397
< system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits
---
> system.cpu.l2cache.occ_percent::cpu.data 0.091946 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.776580 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8699 # number of ReadReq hits
535,539c399,403
< system.cpu.l2cache.ReadReq_hits::cpu.inst 843788 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1226343 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 843755 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 370324 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1226326 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 596029 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 596029 # number of Writeback hits
542,544c406,408
< system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 114426 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 114426 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 8699 # number of demand (read+write) hits
546,549c410,413
< system.cpu.l2cache.demand_hits::cpu.inst 843788 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1340761 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 843755 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 484750 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1340752 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 8699 # number of overall hits
551,553c415,417
< system.cpu.l2cache.overall_hits::cpu.inst 843788 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1340761 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 843755 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 484750 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1340752 # number of overall hits
556,562c420,426
< system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses
565,567c429,431
< system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 143044 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 153651 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses
570,572c434,436
< system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 143044 # number of overall misses
< system.cpu.l2cache.overall_misses::total 153651 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses
> system.cpu.l2cache.overall_misses::total 153654 # number of overall misses
575,581c439,445
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 536335000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 516987000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1053746500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102367500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6102367500 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 532505000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512702000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1045631500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 461000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 461000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6086440000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6086440000 # number of ReadExReq miss cycles
584,586c448,450
< system.cpu.l2cache.demand_miss_latency::cpu.inst 536335000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6619354500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 7156114000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 532505000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6599142000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 7132071500 # number of demand (read+write) miss cycles
589,592c453,456
< system.cpu.l2cache.overall_miss_latency::cpu.inst 536335000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6619354500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 7156114000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 532505000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6599142000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 7132071500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8704 # number of ReadReq accesses(hits+misses)
594,603c458,467
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 854387 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1246808 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 854359 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 380183 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1246797 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 596029 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 596029 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 247609 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 247609 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8704 # number of demand (read+write) accesses
605,608c469,472
< system.cpu.l2cache.demand_accesses::cpu.inst 854387 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1494412 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 854359 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 627792 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1494406 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8704 # number of overall (read+write) accesses
610,612c474,476
< system.cpu.l2cache.overall_accesses::cpu.inst 854387 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1494412 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 854359 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 627792 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1494406 # number of overall (read+write) accesses
615,621c479,485
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025931 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537899 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.537899 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537876 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.537876 # miss rate for ReadExReq accesses
624,626c488,490
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012405 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.227862 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.102817 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.227849 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.102819 # miss rate for demand accesses
629,631c493,495
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012405 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.227849 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.102819 # miss rate for overall accesses
634,640c498,504
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50602.415322 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52443.396226 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 51490.178353 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45818.385566 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45818.385566 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50217.370803 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52003.448626 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 51078.672268 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.347826 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.347826 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45699.826554 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45699.826554 # average ReadExReq miss latency
643,645c507,509
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 46573.819891 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 46416.438882 # average overall miss latency
648,650c512,514
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 46573.819891 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50217.370803 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46134.296221 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 46416.438882 # average overall miss latency
659,660c523,524
< system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks
< system.cpu.l2cache.writebacks::total 57461 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks
> system.cpu.l2cache.writebacks::total 57463 # number of writebacks
663,669c527,533
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses
672,674c536,538
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 143044 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 153651 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses
677,679c541,543
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses
682,688c546,552
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398671075 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 388940100 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 787933191 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28807316 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28807316 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371975723 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371975723 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 394778574 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 384642089 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 779742679 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28851319 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28851319 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4356126157 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4356126157 # number of ReadExReq MSHR miss cycles
691,693c555,557
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398671075 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4760915823 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 5159908914 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 394778574 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4740768246 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 5135868836 # number of demand (read+write) MSHR miss cycles
696,698c560,562
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398671075 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4760915823 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 5159908914 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 394778574 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4740768246 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 5135868836 # number of overall MSHR miss cycles
700,703c564,567
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166694484565 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166891951116 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175103106 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175103106 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166684815565 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166882282116 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9180297506 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9180297506 # number of WriteReq MSHR uncacheable cycles
705,706c569,570
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175865113071 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176062579622 # number of overall MSHR uncacheable cycles
709,715c573,579
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537876 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537876 # mshr miss rate for ReadExReq accesses
718,720c582,584
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.102819 # mshr miss rate for demand accesses
723,725c587,589
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.102819 # mshr miss rate for overall accesses
728,734c592,598
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37614.027267 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39454.260499 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38501.499682 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.402507 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.402507 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32826.090753 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32826.090753 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37229.212939 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39014.310681 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38090.111817 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10035.241391 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10035.241391 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32707.824249 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32707.824249 # average ReadExReq mshr miss latency
737,739c601,603
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency
742,744c606,608
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency
753a618,753
> system.cpu.dcache.replacements 627280 # number of replacements
> system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use
> system.cpu.dcache.total_refs 23655026 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 627792 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 37.679719 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 13195122 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13195122 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 9973048 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 9973048 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 23168170 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 23168170 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 23168170 # number of overall hits
> system.cpu.dcache.overall_hits::total 23168170 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 368781 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 368781 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 619291 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 619291 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 619291 # number of overall misses
> system.cpu.dcache.overall_misses::total 619291 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201704000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5201704000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8045775500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8045775500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154787000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 154787000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13247479500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13247479500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13247479500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13247479500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks
> system.cpu.dcache.writebacks::total 596029 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
768,771c768,771
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles