3,5c3,5
< sim_seconds 2.905318 # Number of seconds simulated
< sim_ticks 2905317504500 # Number of ticks simulated
< final_tick 2905317504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.905317 # Number of seconds simulated
> sim_ticks 2905316914500 # Number of ticks simulated
> final_tick 2905316914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 372777 # Simulator instruction rate (inst/s)
< host_op_rate 449455 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9630563349 # Simulator tick rate (ticks/s)
< host_mem_usage 568288 # Number of bytes of host memory used
< host_seconds 301.68 # Real time elapsed on the host
< sim_insts 112458065 # Number of instructions simulated
< sim_ops 135590016 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1074625 # Simulator instruction rate (inst/s)
> host_op_rate 1295669 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 27762631762 # Simulator tick rate (ticks/s)
> host_mem_usage 582724 # Number of bytes of host memory used
> host_seconds 104.65 # Real time elapsed on the host
> sim_insts 112457861 # Number of instructions simulated
> sim_ops 135589764 # Number of ops (including micro ops) simulated
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
20c20
< system.physmem.bytes_read::cpu.data 8969508 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 8969572 # Number of bytes read from this memory
22c22
< system.physmem.bytes_read::total 10157576 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 10157640 # Number of bytes read from this memory
25c25
< system.physmem.bytes_written::writebacks 7562112 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 7562240 # Number of bytes written to this memory
27c27
< system.physmem.bytes_written::total 7579636 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7579764 # Number of bytes written to this memory
31c31
< system.physmem.num_reads::cpu.data 140668 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 140669 # Number of read requests responded to by this memory
33,34c33,34
< system.physmem.num_reads::total 167685 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 118158 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 167686 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 118160 # Number of write requests responded to by this memory
36c36
< system.physmem.num_writes::total 122539 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 122541 # Number of write requests responded to by this memory
40c40
< system.physmem.bw_read::cpu.data 3087273 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 3087296 # Total read bandwidth from this memory (bytes/s)
42c42
< system.physmem.bw_read::total 3496202 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3496224 # Total read bandwidth from this memory (bytes/s)
45c45
< system.physmem.bw_write::writebacks 2602852 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 2602897 # Write bandwidth from this memory (bytes/s)
47,48c47,48
< system.physmem.bw_write::total 2608884 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2602852 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2608928 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2602897 # Total bandwidth to/from this memory (bytes/s)
52c52
< system.physmem.bw_total::cpu.data 3093305 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 3093327 # Total bandwidth to/from this memory (bytes/s)
54,59c54,59
< system.physmem.bw_total::total 6105086 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 167685 # Number of read requests accepted
< system.physmem.writeReqs 122539 # Number of write requests accepted
< system.physmem.readBursts 167685 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 122539 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10724096 # Total number of bytes read from DRAM
---
> system.physmem.bw_total::total 6105153 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 167686 # Number of read requests accepted
> system.physmem.writeReqs 122541 # Number of write requests accepted
> system.physmem.readBursts 167686 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 122541 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10724160 # Total number of bytes read from DRAM
61,63c61,63
< system.physmem.bytesWritten 7592512 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10157576 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7579636 # Total written bytes from the system interface side
---
> system.physmem.bytesWritten 7592640 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10157640 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7579764 # Total written bytes from the system interface side
67c67
< system.physmem.perBankRdBursts::0 9872 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9873 # Per bank write bursts
83c83
< system.physmem.perBankWrBursts::0 7135 # Per bank write bursts
---
> system.physmem.perBankWrBursts::0 7137 # Per bank write bursts
101c101
< system.physmem.totGap 2905317142500 # Total gap between requests
---
> system.physmem.totGap 2905316552500 # Total gap between requests
108c108
< system.physmem.readPktSize::6 158113 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 158114 # Read request sizes (log2)
115,116c115,116
< system.physmem.writePktSize::6 118158 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 166730 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 118160 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 166731 # What read queue length does an incoming req see
163,199c163,199
< system.physmem.wrQLenPdf::15 1865 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2795 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5970 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5900 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5840 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6278 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6661 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7382 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7196 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8302 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8797 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7093 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6644 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 378 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 299 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 224 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 209 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 164 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2821 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5995 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5894 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6231 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5852 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6586 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8226 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8867 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6554 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6505 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 449 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 379 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 287 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 223 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 280 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 243 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 174 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see
201,209c201,209
< system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 187 # What write queue length does an incoming req see
211,225c211,225
< system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 57710 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 317.389430 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 186.497805 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 335.903414 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 20578 35.66% 35.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14720 25.51% 61.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5637 9.77% 70.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3163 5.48% 76.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2413 4.18% 80.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1394 2.42% 83.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1275 2.21% 85.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 905 1.57% 86.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7625 13.21% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 57710 # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 57707 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 317.409257 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 186.502400 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 335.930049 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 20577 35.66% 35.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14716 25.50% 61.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5644 9.78% 70.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3157 5.47% 76.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2419 4.19% 80.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1386 2.40% 83.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1272 2.20% 85.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 912 1.58% 86.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7624 13.21% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 57707 # Bytes accessed per row activation
227,228c227,228
< system.physmem.rdPerTurnAround::mean 28.919917 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 588.859232 # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::mean 28.920090 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 588.859251 # Reads before turning the bus around for writes
233,245c233,246
< system.physmem.wrPerTurnAround::mean 20.475147 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.526106 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 14.995822 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5070 87.50% 87.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 36 0.62% 88.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 58 1.00% 89.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 41 0.71% 89.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 290 5.01% 94.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 32 0.55% 95.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 5 0.09% 95.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 8 0.14% 95.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 5 0.09% 95.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 2 0.03% 95.74% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::mean 20.475492 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.528054 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.935092 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5069 87.49% 87.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 41 0.71% 88.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 52 0.90% 89.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 288 4.97% 94.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 23 0.40% 95.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 16 0.28% 95.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 5 0.09% 95.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74% # Writes before turning the bus around for reads
257,258c258,260
< system.physmem.wrPerTurnAround::124-127 2 0.03% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 9 0.16% 99.52% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52% # Writes before turning the bus around for reads
264,269c266,270
< system.physmem.wrPerTurnAround::160-163 3 0.05% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.02% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads
271,274c272,275
< system.physmem.totQLat 4573778750 # Total ticks spent queuing
< system.physmem.totMemAccLat 7715603750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 837820000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 27295.71 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 4572629500 # Total ticks spent queuing
> system.physmem.totMemAccLat 7714473250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 837825000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 27288.69 # Average queueing delay per DRAM burst
276c277
< system.physmem.avgMemAccLat 46045.71 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 46038.69 # Average memory access latency per DRAM burst
286,288c287,289
< system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing
< system.physmem.readRowHits 138574 # Number of row buffer hits during reads
< system.physmem.writeRowHits 89912 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing
> system.physmem.readRowHits 138575 # Number of row buffer hits during reads
> system.physmem.writeRowHits 89917 # Number of row buffer hits during writes
291c292
< system.physmem.avgGap 10010602.65 # Average gap between requests
---
> system.physmem.avgGap 10010497.14 # Average gap between requests
293,313c294,314
< system.physmem_0.actEnergy 209951700 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 111591975 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 639486960 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 313377480 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 6673146480.000002 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 4797272190 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 415271520 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 13955015310 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 9412509120 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 682622001540 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 719151899205 # Total energy per rank (pJ)
< system.physmem_0.averagePower 247.529538 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 2893187374000 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 780943500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2837778000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 2838595786500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 24511740750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 7987774000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 30603481750 # Time in different power states
< system.physmem_1.actEnergy 202104840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 107417475 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 209944560 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 111588180 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 639494100 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 313387920 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 6674375760.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4793281050 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 418187520 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 13958691240 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 9415844160 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 682618118940 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 719155193400 # Total energy per rank (pJ)
> system.physmem_0.averagePower 247.530722 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 2893187924000 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 788400750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2838298000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 2838579624000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 24520427750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7978656750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 30611507250 # Time in different power states
> system.physmem_1.actEnergy 202090560 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 107409885 # Energy for precharge commands per rank (pJ)
316,331c317,332
< system.physmem_1.refreshEnergy 6671302560.000002 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 4519380090 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 410434080 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 13655969940 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 9525025920 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 682931246265 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 718886718750 # Total energy per rank (pJ)
< system.physmem_1.averagePower 247.438264 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 2894335381000 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 777927000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2837694000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 2839583336000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 24804588750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 7366436500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 29947522250 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.physmem_1.refreshEnergy 6670687920.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 4519112190 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 410472000 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 13651117530 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 9526323840 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 682932964665 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 718884016170 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.437384 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 2894335317000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 777922000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2837434000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 2839590532250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 24808008250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 7366175500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 29936842500 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
344,346c345,347
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
354c355
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
384c385
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
393,395c394,396
< system.cpu.dtb.walker.walkCompletionTime::mean 10013.804304 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 8464.395211 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 6610.536044 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::mean 10013.601299 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8464.254766 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 6610.467359 # Table walker service (enqueue to completion) latency
416c417
< system.cpu.dtb.read_hits 24519779 # DTB read hits
---
> system.cpu.dtb.read_hits 24519746 # DTB read hits
418c419
< system.cpu.dtb.write_hits 19605270 # DTB write hits
---
> system.cpu.dtb.write_hits 19605246 # DTB write hits
429,430c430,431
< system.cpu.dtb.read_accesses 24527919 # DTB read accesses
< system.cpu.dtb.write_accesses 19606683 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24527886 # DTB read accesses
> system.cpu.dtb.write_accesses 19606659 # DTB write accesses
432c433
< system.cpu.dtb.hits 44125049 # DTB hits
---
> system.cpu.dtb.hits 44124992 # DTB hits
434,435c435,436
< system.cpu.dtb.accesses 44134602 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.accesses 44134545 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
465c466
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
496c497
< system.cpu.itb.inst_hits 115555925 # ITB inst hits
---
> system.cpu.itb.inst_hits 115555708 # ITB inst hits
513,514c514,515
< system.cpu.itb.inst_accesses 115560688 # ITB inst accesses
< system.cpu.itb.hits 115555925 # DTB hits
---
> system.cpu.itb.inst_accesses 115560471 # ITB inst accesses
> system.cpu.itb.hits 115555708 # DTB hits
516c517
< system.cpu.itb.accesses 115560688 # DTB accesses
---
> system.cpu.itb.accesses 115560471 # DTB accesses
519,520c520,521
< system.cpu.pwrStateClkGateDist::mean 887473047.745383 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 17466686250.192787 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::mean 887473262.784960 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 17466686239.333317 # Distribution of time spent in the clock gated state
530,532c531,533
< system.cpu.pwrStateResidencyTicks::ON 214499223736 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818280764 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 5810635009 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 214497981736 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818932764 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 5810633829 # number of cpu cycles simulated
537,539c538,540
< system.cpu.committedInsts 112458065 # Number of instructions committed
< system.cpu.committedOps 135590016 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119895072 # Number of integer alu accesses
---
> system.cpu.committedInsts 112457861 # Number of instructions committed
> system.cpu.committedOps 135589764 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119894844 # Number of integer alu accesses
541,543c542,544
< system.cpu.num_func_calls 9894802 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 15230859 # number of instructions that are conditional controls
< system.cpu.num_int_insts 119895072 # number of integer instructions
---
> system.cpu.num_func_calls 9894754 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 15230835 # number of instructions that are conditional controls
> system.cpu.num_int_insts 119894844 # number of integer instructions
545,546c546,547
< system.cpu.num_int_register_reads 218056824 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82647475 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 218056368 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82647309 # number of times the integer registers were written
549,558c550,559
< system.cpu.num_cc_register_reads 489748178 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51895154 # number of times the CC registers were written
< system.cpu.num_mem_refs 45405351 # number of memory refs
< system.cpu.num_load_insts 24842092 # Number of load instructions
< system.cpu.num_store_insts 20563259 # Number of store instructions
< system.cpu.num_idle_cycles 5381636561.526148 # Number of idle cycles
< system.cpu.num_busy_cycles 428998447.473852 # Number of busy cycles
< system.cpu.not_idle_fraction 0.073830 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.926170 # Percentage of idle cycles
< system.cpu.Branches 25919628 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 489747242 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51895082 # number of times the CC registers were written
> system.cpu.num_mem_refs 45405279 # number of memory refs
> system.cpu.num_load_insts 24842044 # Number of load instructions
> system.cpu.num_store_insts 20563235 # Number of store instructions
> system.cpu.num_idle_cycles 5381637865.526148 # Number of idle cycles
> system.cpu.num_busy_cycles 428995963.473852 # Number of busy cycles
> system.cpu.not_idle_fraction 0.073829 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.926171 # Percentage of idle cycles
> system.cpu.Branches 25919556 # Number of branches fetched
560c561
< system.cpu.op_class::IntAlu 93180053 67.18% 67.18% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93179861 67.18% 67.18% # Class of executed instruction
591,592c592,593
< system.cpu.op_class::MemRead 24839384 17.91% 85.17% # Class of executed instruction
< system.cpu.op_class::MemWrite 20554681 14.82% 99.99% # Class of executed instruction
---
> system.cpu.op_class::MemRead 24839336 17.91% 85.17% # Class of executed instruction
> system.cpu.op_class::MemWrite 20554657 14.82% 99.99% # Class of executed instruction
597,599c598,600
< system.cpu.op_class::total 138710700 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 821158 # number of replacements
---
> system.cpu.op_class::total 138710436 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 821157 # number of replacements
601,603c602,604
< system.cpu.dcache.tags.total_refs 43232098 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 821670 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 52.614916 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 43232042 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 821669 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 52.614912 # Average number of references to valid blocks.
614,620c615,621
< system.cpu.dcache.tags.tag_accesses 177104923 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177104923 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 23110979 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23110979 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18822589 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18822589 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 177104694 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177104694 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 23110946 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23110946 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18822565 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18822565 # number of WriteReq hits
623,624c624,625
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443107 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443107 # number of LoadLockedReq hits
---
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443108 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443108 # number of LoadLockedReq hits
627,630c628,631
< system.cpu.dcache.demand_hits::cpu.data 41933568 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41933568 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42326041 # number of overall hits
< system.cpu.dcache.overall_hits::total 42326041 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 41933511 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41933511 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42325984 # number of overall hits
> system.cpu.dcache.overall_hits::total 42325984 # number of overall hits
637,638c638,639
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22807 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22807 # number of LoadLockedReq misses
---
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22806 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22806 # number of LoadLockedReq misses
645,650c646,651
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437634500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6437634500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 14441729500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 14441729500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297474000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 297474000 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437831500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6437831500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 14440805000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 14440805000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297461000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 297461000 # number of LoadLockedReq miss cycles
653,660c654,661
< system.cpu.dcache.demand_miss_latency::cpu.data 20879364000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20879364000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20879364000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20879364000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23512121 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23512121 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19121471 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19121471 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20878636500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20878636500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20878636500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20878636500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23512088 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23512088 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19121447 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19121447 # number of WriteReq accesses(hits+misses)
667,670c668,671
< system.cpu.dcache.demand_accesses::cpu.data 42633592 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42633592 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43144749 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43144749 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 42633535 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42633535 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43144692 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43144692 # number of overall (read+write) accesses
677,678c678,679
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048951 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048951 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048949 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048949 # miss rate for LoadLockedReq accesses
685,690c686,691
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.268444 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.268444 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48319.167765 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 48319.167765 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.100802 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.100802 # average LoadLockedReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.759542 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.759542 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48316.074571 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48316.074571 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.102692 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.102692 # average LoadLockedReq miss latency
693,696c694,697
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29826.640229 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29826.640229 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25502.821519 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 25502.821519 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29825.600979 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29825.600979 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25501.932924 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25501.932924 # average overall miss latency
703,704c704,705
< system.cpu.dcache.writebacks::writebacks 685618 # number of writebacks
< system.cpu.dcache.writebacks::total 685618 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 685616 # number of writebacks
> system.cpu.dcache.writebacks::total 685616 # number of writebacks
719,720c720,721
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8529 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8529 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8528 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8528 # number of LoadLockedReq MSHR misses
733,740c734,741
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6011986000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6011986000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14142847500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 14142847500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1587073500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1587073500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118989500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118989500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6012304000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6012304000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14141923000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 14141923000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1586831500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1586831500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118977500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118977500 # number of LoadLockedReq MSHR miss cycles
743,746c744,747
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154833500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 20154833500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741907000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 21741907000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154227000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 20154227000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741058500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 21741058500 # number of overall MSHR miss cycles
757,758c758,759
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018306 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018306 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018304 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018304 # mshr miss rate for LoadLockedReq accesses
765,772c766,773
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15013.675162 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15013.675162 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47319.167765 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47319.167765 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13604.147916 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13604.147916 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.166608 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.166608 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15014.469301 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15014.469301 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47316.074571 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47316.074571 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13602.073529 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13602.073529 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.395403 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.395403 # average LoadLockedReq mshr miss latency
775,778c776,779
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28820.781306 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 28820.781306 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26645.244903 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26645.244903 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28819.914030 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28819.914030 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26644.205045 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26644.205045 # average overall mshr miss latency
783,784c784,785
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1700061 # number of replacements
---
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1700062 # number of replacements
786,788c787,789
< system.cpu.icache.tags.total_refs 113855346 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1700573 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 66.951166 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 113855128 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1700574 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 66.950999 # Average number of references to valid blocks.
799,825c800,826
< system.cpu.icache.tags.tag_accesses 117256504 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 117256504 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 113855346 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 113855346 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 113855346 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 113855346 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 113855346 # number of overall hits
< system.cpu.icache.overall_hits::total 113855346 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1700579 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1700579 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1700579 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1700579 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1700579 # number of overall misses
< system.cpu.icache.overall_misses::total 1700579 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24045189500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24045189500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24045189500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24045189500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24045189500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24045189500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 115555925 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 115555925 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 115555925 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 115555925 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 115555925 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 115555925 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 117256288 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 117256288 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 113855128 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 113855128 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 113855128 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 113855128 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 113855128 # number of overall hits
> system.cpu.icache.overall_hits::total 113855128 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1700580 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1700580 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1700580 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1700580 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1700580 # number of overall misses
> system.cpu.icache.overall_misses::total 1700580 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24044969500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24044969500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24044969500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24044969500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24044969500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24044969500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 115555708 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 115555708 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 115555708 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 115555708 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 115555708 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 115555708 # number of overall (read+write) accesses
832,837c833,838
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.413400 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14139.413400 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14139.413400 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14139.413400 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.275718 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14139.275718 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14139.275718 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14139.275718 # average overall miss latency
844,851c845,852
< system.cpu.icache.writebacks::writebacks 1700061 # number of writebacks
< system.cpu.icache.writebacks::total 1700061 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700579 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1700579 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1700579 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1700579 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1700579 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1700579 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 1700062 # number of writebacks
> system.cpu.icache.writebacks::total 1700062 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700580 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1700580 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1700580 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1700580 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1700580 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1700580 # number of overall MSHR misses
856,861c857,862
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344610500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22344610500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344610500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22344610500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344610500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22344610500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344389500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22344389500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344389500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22344389500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344389500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22344389500 # number of overall MSHR miss cycles
872,877c873,878
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.413400 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.413400 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.275718 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.275718 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency
882,887c883,888
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 88597 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65011.992500 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4854150 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 154024 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 31.515543 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 88598 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65011.992508 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4854149 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 154025 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 31.515332 # Average number of references to valid blocks.
891,892c892,893
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.970202 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.930460 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.969504 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.931167 # Average occupied blocks per requestor
907,909c908,910
< system.cpu.l2cache.tags.tag_accesses 40276407 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 40276407 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.tag_accesses 40276408 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 40276408 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
913,914c914,915
< system.cpu.l2cache.WritebackDirty_hits::writebacks 685618 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 685618 # number of WritebackDirty hits
---
> system.cpu.l2cache.WritebackDirty_hits::writebacks 685616 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 685616 # number of WritebackDirty hits
919,924c920,925
< system.cpu.l2cache.ReadExReq_hits::cpu.data 167649 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 167649 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682585 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1682585 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513552 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 513552 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 167648 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 167648 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682586 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1682586 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513551 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 513551 # number of ReadSharedReq hits
927,929c928,930
< system.cpu.l2cache.demand_hits::cpu.inst 1682585 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 681201 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2371533 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1682586 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 681199 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2371532 # number of demand (read+write) hits
932,934c933,935
< system.cpu.l2cache.overall_hits::cpu.inst 1682585 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 681201 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2371533 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1682586 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 681199 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2371532 # number of overall hits
942,943c943,944
< system.cpu.l2cache.ReadExReq_misses::cpu.data 128426 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 128426 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 128427 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 128427 # number of ReadExReq misses
951,952c952,953
< system.cpu.l2cache.demand_misses::cpu.data 140498 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 158485 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 140499 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 158486 # number of demand (read+write) misses
956,957c957,958
< system.cpu.l2cache.overall_misses::cpu.data 140498 # number of overall misses
< system.cpu.l2cache.overall_misses::total 158485 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.data 140499 # number of overall misses
> system.cpu.l2cache.overall_misses::total 158486 # number of overall misses
965,970c966,971
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11900828000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 11900828000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066597500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066597500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1519988500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1519988500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11899913500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 11899913500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066366000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066366000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1520063000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1520063000 # number of ReadSharedReq miss cycles
973,975c974,976
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2066597500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13420816500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 15488748000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2066366000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13419976500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 15487676500 # number of demand (read+write) miss cycles
978,980c979,981
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2066597500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13420816500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 15488748000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2066366000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13419976500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 15487676500 # number of overall miss cycles
984,985c985,986
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 685618 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 685618 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 685616 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 685616 # number of WritebackDirty accesses(hits+misses)
994,997c995,998
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700563 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1700563 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525624 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 525624 # number of ReadSharedReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700564 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1700564 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525623 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 525623 # number of ReadSharedReq accesses(hits+misses)
1000,1001c1001,1002
< system.cpu.l2cache.demand_accesses::cpu.inst 1700563 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 821699 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1700564 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 821698 # number of demand (read+write) accesses
1005,1006c1006,1007
< system.cpu.l2cache.overall_accesses::cpu.inst 1700563 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 821699 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1700564 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 821698 # number of overall (read+write) accesses
1015,1016c1016,1017
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433762 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.433762 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433765 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.433765 # miss rate for ReadExReq accesses
1024c1025
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.170985 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.170986 # miss rate for demand accesses
1029c1030
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.170985 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.170986 # miss rate for overall accesses
1038,1043c1039,1044
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92666.812016 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92666.812016 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114951.468461 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114951.468461 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125910.246852 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125910.246852 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92658.969687 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92658.969687 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114938.591612 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114938.591612 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125916.418158 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125916.418158 # average ReadSharedReq miss latency
1046,1048c1047,1049
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 97730.056472 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 97722.678975 # average overall miss latency
1051,1053c1052,1054
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 97730.056472 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 97722.678975 # average overall miss latency
1060,1061c1061,1062
< system.cpu.l2cache.writebacks::writebacks 81968 # number of writebacks
< system.cpu.l2cache.writebacks::total 81968 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 81970 # number of writebacks
> system.cpu.l2cache.writebacks::total 81970 # number of writebacks
1069,1070c1070,1071
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128426 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 128426 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128427 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 128427 # number of ReadExReq MSHR misses
1078,1079c1079,1080
< system.cpu.l2cache.demand_mshr_misses::cpu.data 140498 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 158485 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 140499 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 158486 # number of demand (read+write) MSHR misses
1083,1084c1084,1085
< system.cpu.l2cache.overall_mshr_misses::cpu.data 140498 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 158485 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 140499 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 158486 # number of overall MSHR misses
1100,1105c1101,1106
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10616568000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10616568000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886817500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886817500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399268500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399268500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10615643500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10615643500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886586000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886586000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399343000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399343000 # number of ReadSharedReq MSHR miss cycles
1108,1110c1109,1111
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886817500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12015836500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 13903898000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886586000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12014986500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 13902816500 # number of demand (read+write) MSHR miss cycles
1113,1115c1114,1116
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886817500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12015836500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 13903898000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886586000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12014986500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 13902816500 # number of overall MSHR miss cycles
1129,1130c1130,1131
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433762 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433762 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433765 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433765 # mshr miss rate for ReadExReq accesses
1138c1139
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for demand accesses
1143c1144
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for overall accesses
1152,1157c1153,1158
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82666.812016 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82666.812016 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104951.468461 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104951.468461 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115910.246852 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115910.246852 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82658.969687 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82658.969687 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104938.591612 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104938.591612 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115916.418158 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115916.418158 # average ReadSharedReq mshr miss latency
1160,1162c1161,1163
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency
1165,1167c1166,1168
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency
1175,1178c1176,1179
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543364 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39292 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 222 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 222 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543358 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 227 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 227 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1180c1181
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1186c1187
< system.cpu.toL2Bus.trans_dist::WritebackClean 1700061 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackClean 1700062 # Transaction distribution
1193,1194c1194,1195
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700579 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 525821 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700580 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 525822 # Transaction distribution
1196,1197c1197,1199
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119247 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587819 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::InvalidateResp 14 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119250 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587830 # Packet count per connected master and slave (bytes)
1200,1202c1202,1204
< system.cpu.toL2Bus.pkt_count::total 7741888 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676024 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663645 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 7741902 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676152 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663453 # Cumulative packet size per connected master and slave (bytes)
1205,1210c1207,1212
< system.cpu.toL2Bus.pkt_size::total 314370693 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 112662 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 5336440 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 2713047 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.021691 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.145674 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size::total 314370629 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 112679 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 5336568 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 2713050 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.021694 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.145681 # Request fanout histogram
1212,1213c1214,1215
< system.cpu.toL2Bus.snoop_fanout::0 2654197 97.83% 97.83% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 58850 2.17% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2654194 97.83% 97.83% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 58856 2.17% 100.00% # Request fanout histogram
1218,1219c1220,1221
< system.cpu.toL2Bus.snoop_fanout::total 2713047 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4970034000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2713050 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4970033000 # Layer occupancy (ticks)
1221c1223
< system.cpu.toL2Bus.snoopLayer0.occupancy 347377 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 354876 # Layer occupancy (ticks)
1223c1225
< system.cpu.toL2Bus.respLayer0.occupancy 2559890500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2559892000 # Layer occupancy (ticks)
1225c1227
< system.cpu.toL2Bus.respLayer1.occupancy 1278885500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1278884000 # Layer occupancy (ticks)
1231c1233
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1282c1284
< system.iobus.reqLayer0.occupancy 46336000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks)
1320c1322
< system.iobus.reqLayer25.occupancy 187558131 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187507137 # Layer occupancy (ticks)
1326c1328
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1328c1330
< system.iocache.tags.tagsinuse 1.079865 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.079862 # Cycle average of tags in use
1333,1335c1335,1337
< system.iocache.tags.occ_blocks::realview.ide 1.079865 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.067492 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.067492 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_blocks::realview.ide 1.079862 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.067491 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.067491 # Average percentage of cache occupancy
1341c1343
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1350,1357c1352,1359
< system.iocache.ReadReq_miss_latency::realview.ide 34063377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 34063377 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4369997754 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4369997754 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4404061131 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4404061131 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4404061131 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4404061131 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4377262761 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4377262761 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4411329137 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4411329137 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4411329137 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4411329137 # number of overall miss cycles
1374,1381c1376,1383
< system.iocache.ReadReq_avg_miss_latency::realview.ide 162206.557143 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 162206.557143 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120638.188880 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 120638.188880 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 120877.782593 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 120877.782593 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120838.746715 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 120838.746715 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 121077.266756 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 121077.266756 # average overall miss latency
1398,1405c1400,1407
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 23563377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 23563377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2556779983 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2556779983 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2580343360 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2580343360 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2580343360 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2580343360 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564294505 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2564294505 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2587860881 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2587860881 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2587860881 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2587860881 # number of overall MSHR miss cycles
1414,1424c1416,1426
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112206.557143 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 112206.557143 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70582.486280 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70582.486280 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 319998 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 129556 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70789.932227 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70789.932227 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 320000 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 129537 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 496 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1428c1430
< system.membus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1433,1434c1435,1436
< system.membus.trans_dist::WritebackDirty 118158 # Transaction distribution
< system.membus.trans_dist::CleanEvict 6839 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 118160 # Transaction distribution
> system.membus.trans_dist::CleanEvict 6838 # Transaction distribution
1438,1439c1440,1441
< system.membus.trans_dist::ReadExReq 128316 # Transaction distribution
< system.membus.trans_dist::ReadExResp 128316 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 128317 # Transaction distribution
> system.membus.trans_dist::ReadExResp 128317 # Transaction distribution
1441a1444
> system.membus.trans_dist::InvalidateResp 4315 # Transaction distribution
1445,1446c1448,1449
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433106 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540698 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433109 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540701 # Packet count per connected master and slave (bytes)
1449c1452
< system.membus.pkt_count::total 613547 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 613550 # Packet count per connected master and slave (bytes)
1453,1454c1456,1457
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420092 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583445 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420284 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583637 # Cumulative packet size per connected master and slave (bytes)
1457,1458c1460,1461
< system.membus.pkt_size::total 17900565 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 474 # Total snoops (count)
---
> system.membus.pkt_size::total 17900757 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 4789 # Total snoops (count)
1460,1462c1463,1465
< system.membus.snoop_fanout::samples 262688 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.018375 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.134305 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 262689 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.018383 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.134332 # Request fanout histogram
1464,1465c1467,1468
< system.membus.snoop_fanout::0 257861 98.16% 98.16% # Request fanout histogram
< system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 257860 98.16% 98.16% # Request fanout histogram
> system.membus.snoop_fanout::1 4829 1.84% 100.00% # Request fanout histogram
1470,1471c1473,1474
< system.membus.snoop_fanout::total 262688 # Request fanout histogram
< system.membus.reqLayer0.occupancy 90466500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 262689 # Request fanout histogram
> system.membus.reqLayer0.occupancy 90467000 # Layer occupancy (ticks)
1477c1480
< system.membus.reqLayer5.occupancy 822811335 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 822822299 # Layer occupancy (ticks)
1479c1482
< system.membus.respLayer2.occupancy 948647750 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 948652750 # Layer occupancy (ticks)
1481c1484
< system.membus.respLayer3.occupancy 1085623 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 5614930 # Layer occupancy (ticks)
1483,1489c1486,1492
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1496,1497c1499,1500
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1529,1535c1532,1538
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1540,1551c1543,1554
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states