3,5c3,5
< sim_seconds 2.905298 # Number of seconds simulated
< sim_ticks 2905297782500 # Number of ticks simulated
< final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.905318 # Number of seconds simulated
> sim_ticks 2905317504500 # Number of ticks simulated
> final_tick 2905317504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1078702 # Simulator instruction rate (inst/s)
< host_op_rate 1300576 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 27866902585 # Simulator tick rate (ticks/s)
< host_mem_usage 582552 # Number of bytes of host memory used
< host_seconds 104.26 # Real time elapsed on the host
< sim_insts 112461365 # Number of instructions simulated
< sim_ops 135593151 # Number of ops (including micro ops) simulated
---
> host_inst_rate 372777 # Simulator instruction rate (inst/s)
> host_op_rate 449455 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9630563349 # Simulator tick rate (ticks/s)
> host_mem_usage 568288 # Number of bytes of host memory used
> host_seconds 301.68 # Real time elapsed on the host
> sim_insts 112458065 # Number of instructions simulated
> sim_ops 135590016 # Number of ops (including micro ops) simulated
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
19,20c19,20
< system.physmem.bytes_read::cpu.inst 1184612 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 8933156 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8969508 # Number of bytes read from this memory
22,25c22,25
< system.physmem.bytes_read::total 10119304 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1184612 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1184612 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7531136 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10157576 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7562112 # Number of bytes written to this memory
27c27
< system.physmem.bytes_written::total 7548660 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7579636 # Number of bytes written to this memory
30,31c30,31
< system.physmem.num_reads::cpu.inst 26963 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 140100 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 140668 # Number of read requests responded to by this memory
33,34c33,34
< system.physmem.num_reads::total 167087 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 117674 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 167685 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 118158 # Number of write requests responded to by this memory
36c36
< system.physmem.num_writes::total 122055 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 122539 # Number of write requests responded to by this memory
39,40c39,40
< system.physmem.bw_read::cpu.inst 407742 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3074782 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 408400 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3087273 # Total read bandwidth from this memory (bytes/s)
42,45c42,45
< system.physmem.bw_read::total 3483052 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 407742 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 407742 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2592208 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3496202 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 408400 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 408400 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2602852 # Write bandwidth from this memory (bytes/s)
47,48c47,48
< system.physmem.bw_write::total 2598240 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2592208 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2608884 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2602852 # Total bandwidth to/from this memory (bytes/s)
51,52c51,52
< system.physmem.bw_total::cpu.inst 407742 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3080813 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 408400 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3093305 # Total bandwidth to/from this memory (bytes/s)
54,64c54,64
< system.physmem.bw_total::total 6081292 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 167087 # Number of read requests accepted
< system.physmem.writeReqs 122055 # Number of write requests accepted
< system.physmem.readBursts 167087 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 122055 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10685312 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7561344 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10119304 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7548660 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 6105086 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 167685 # Number of read requests accepted
> system.physmem.writeReqs 122539 # Number of write requests accepted
> system.physmem.readBursts 167685 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 122539 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10724096 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7592512 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10157576 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7579636 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue
67,98c67,98
< system.physmem.perBankRdBursts::0 9954 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9813 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10094 # Per bank write bursts
< system.physmem.perBankRdBursts::3 9518 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18811 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10188 # Per bank write bursts
< system.physmem.perBankRdBursts::6 10467 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10858 # Per bank write bursts
< system.physmem.perBankRdBursts::8 9262 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10094 # Per bank write bursts
< system.physmem.perBankRdBursts::10 9505 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9184 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9983 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9847 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9958 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9422 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7103 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7218 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7869 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7374 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7424 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7558 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7579 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7921 # Per bank write bursts
< system.physmem.perBankWrBursts::8 6916 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7516 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7047 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7122 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7779 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7383 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7451 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6886 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9872 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9614 # Per bank write bursts
> system.physmem.perBankRdBursts::2 9963 # Per bank write bursts
> system.physmem.perBankRdBursts::3 9595 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18744 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9936 # Per bank write bursts
> system.physmem.perBankRdBursts::6 10635 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11205 # Per bank write bursts
> system.physmem.perBankRdBursts::8 9589 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10033 # Per bank write bursts
> system.physmem.perBankRdBursts::10 9283 # Per bank write bursts
> system.physmem.perBankRdBursts::11 8863 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10202 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10190 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10325 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9515 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7135 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7022 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7742 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7365 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7465 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7289 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7716 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8300 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7184 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7439 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6836 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6804 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7947 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7681 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7752 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6956 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
< system.physmem.totGap 2905297420500 # Total gap between requests
---
> system.physmem.numWrRetry 62 # Number of times write queue was full causing retry
> system.physmem.totGap 2905317142500 # Total gap between requests
108c108
< system.physmem.readPktSize::6 157515 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 158113 # Read request sizes (log2)
115,118c115,118
< system.physmem.writePktSize::6 117674 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 166128 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 554 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 118158 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 166730 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 559 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 263 # What read queue length does an incoming req see
163,229c163,229
< system.physmem.wrQLenPdf::15 1886 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2786 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5910 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5857 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5767 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6250 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6643 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8725 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7065 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6628 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6527 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 401 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 376 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 293 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 238 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 238 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 193 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 196 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 57323 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 318.311882 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 186.988870 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 336.470779 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 20402 35.59% 35.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14531 25.35% 60.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5716 9.97% 70.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3104 5.41% 76.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2370 4.13% 80.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1421 2.48% 82.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1241 2.16% 85.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 946 1.65% 86.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7592 13.24% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 57323 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5761 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.979865 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 590.542998 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 5760 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1865 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2795 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5970 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5900 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5840 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6278 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6661 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7382 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8302 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8797 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7093 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6644 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6509 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 378 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 157 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 124 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 240 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 57710 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 317.389430 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 186.497805 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 335.903414 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 20578 35.66% 35.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14720 25.51% 61.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5637 9.77% 70.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3163 5.48% 76.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2413 4.18% 80.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1394 2.42% 83.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1275 2.21% 85.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 905 1.57% 86.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7625 13.21% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 57710 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5794 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.919917 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 588.859232 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5793 99.98% 99.98% # Reads before turning the bus around for writes
231,264c231,261
< system.physmem.rdPerTurnAround::total 5761 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5761 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.507898 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.546505 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 15.055833 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5040 87.48% 87.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 23 0.40% 87.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 68 1.18% 89.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 38 0.66% 89.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 294 5.10% 94.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 33 0.57% 95.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 2 0.03% 95.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 7 0.12% 95.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 6 0.10% 95.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 3 0.05% 95.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 2 0.03% 95.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 5 0.09% 95.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 158 2.74% 98.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 4 0.07% 98.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 6 0.10% 98.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 3 0.05% 98.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 10 0.17% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 2 0.03% 99.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.02% 99.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 11 0.19% 99.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.03% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 3 0.05% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 8 0.14% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 7 0.12% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 4 0.07% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 4 0.07% 99.79% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5794 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5794 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.475147 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.526106 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.995822 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5070 87.50% 87.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 36 0.62% 88.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 58 1.00% 89.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 41 0.71% 89.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 290 5.01% 94.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 32 0.55% 95.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 5 0.09% 95.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 8 0.14% 95.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 5 0.09% 95.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 2 0.03% 95.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.03% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 9 0.16% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 6 0.10% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 5 0.09% 99.79% # Writes before turning the bus around for reads
266,268c263,265
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.03% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.05% 99.91% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 3 0.05% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads
270,277c267,274
< system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5761 # Writes before turning the bus around for reads
< system.physmem.totQLat 4504540500 # Total ticks spent queuing
< system.physmem.totMemAccLat 7635003000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 834790000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 26980.08 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::184-187 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5794 # Writes before turning the bus around for reads
> system.physmem.totQLat 4573778750 # Total ticks spent queuing
> system.physmem.totMemAccLat 7715603750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 837820000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 27295.71 # Average queueing delay per DRAM burst
279,283c276,280
< system.physmem.avgMemAccLat 45730.08 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.68 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 3.48 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 46045.71 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.69 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.61 # Average system write bandwidth in MiByte/s
289,334c286,331
< system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing
< system.physmem.readRowHits 138094 # Number of row buffer hits during reads
< system.physmem.writeRowHits 89686 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.71 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes
< system.physmem.avgGap 10047995.17 # Average gap between requests
< system.physmem.pageHitRate 79.89 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 210115920 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 111679260 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 640479420 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 313440120 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 6609223920.000002 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 4735061820 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 414343200 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 13903412640 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 9310120320 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 682719565725 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 718969243965 # Total energy per rank (pJ)
< system.physmem_0.averagePower 247.468348 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 2893307612500 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 778413000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2810438000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 2839095824500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 24245244750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 7877734000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 30490128250 # Time in different power states
< system.physmem_1.actEnergy 199177440 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 105861525 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 551600700 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 303282000 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 6621516720.000002 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 4536550200 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 409678080 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 13514783790 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 9490661760 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 682993594335 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 718728215280 # Total energy per rank (pJ)
< system.physmem_1.averagePower 247.385386 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 2894278953000 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 777246000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2816412000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 2839926040500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 24715420500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 7425105000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 29637558500 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing
> system.physmem.readRowHits 138574 # Number of row buffer hits during reads
> system.physmem.writeRowHits 89912 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.78 # Row buffer hit rate for writes
> system.physmem.avgGap 10010602.65 # Average gap between requests
> system.physmem.pageHitRate 79.83 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 209951700 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 111591975 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 639486960 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 313377480 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 6673146480.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4797272190 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 415271520 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 13955015310 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 9412509120 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 682622001540 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 719151899205 # Total energy per rank (pJ)
> system.physmem_0.averagePower 247.529538 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 2893187374000 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 780943500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2837778000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 2838595786500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 24511740750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7987774000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 30603481750 # Time in different power states
> system.physmem_1.actEnergy 202104840 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 107417475 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 556920000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 305886780 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 6671302560.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 4519380090 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 410434080 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 13655969940 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 9525025920 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 682931246265 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 718886718750 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.438264 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 2894335381000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 777927000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2837694000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 2839583336000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 24804588750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 7366436500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 29947522250 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
347,349c344,346
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
357c354
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
387,400c384,397
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 9547 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 9547 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1253 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8294 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 9547 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 9547 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 9547 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7383 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 9942.435324 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 8397.692517 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 6587.109188 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-16383 6605 89.46% 89.46% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::16384-32767 773 10.47% 99.93% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 9553 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 9553 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8297 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 9553 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 9553 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 9553 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7389 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 10013.804304 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8464.395211 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 6610.536044 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-16383 6588 89.16% 89.16% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93% # Table walker service (enqueue to completion) latency
403c400
< system.cpu.dtb.walker.walkCompletionTime::total 7383 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::total 7389 # Table walker service (enqueue to completion) latency
407,410c404,407
< system.cpu.dtb.walker.walkPageSizes::4K 6177 83.67% 83.67% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1206 16.33% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7383 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9547 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 6180 83.64% 83.64% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1209 16.36% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7389 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9553 # Table walker requests started/completed, data/inst
412,413c409,410
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9547 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7383 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9553 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7389 # Table walker requests started/completed, data/inst
415,416c412,413
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7383 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 16930 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7389 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 16942 # Table walker requests started/completed, data/inst
419,422c416,419
< system.cpu.dtb.read_hits 24520121 # DTB read hits
< system.cpu.dtb.read_misses 8133 # DTB read misses
< system.cpu.dtb.write_hits 19605715 # DTB write hits
< system.cpu.dtb.write_misses 1414 # DTB write misses
---
> system.cpu.dtb.read_hits 24519779 # DTB read hits
> system.cpu.dtb.read_misses 8140 # DTB read misses
> system.cpu.dtb.write_hits 19605270 # DTB write hits
> system.cpu.dtb.write_misses 1413 # DTB write misses
429c426
< system.cpu.dtb.prefetch_faults 1628 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
432,433c429,430
< system.cpu.dtb.read_accesses 24528254 # DTB read accesses
< system.cpu.dtb.write_accesses 19607129 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24527919 # DTB read accesses
> system.cpu.dtb.write_accesses 19606683 # DTB write accesses
435,438c432,435
< system.cpu.dtb.hits 44125836 # DTB hits
< system.cpu.dtb.misses 9547 # DTB misses
< system.cpu.dtb.accesses 44135383 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 44125049 # DTB hits
> system.cpu.dtb.misses 9553 # DTB misses
> system.cpu.dtb.accesses 44134602 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
468c465
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
477,479c474,476
< system.cpu.itb.walker.walkCompletionTime::mean 10156.853282 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 8221.468352 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7284.204444 # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkCompletionTime::mean 10180.341055 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 8232.055098 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7311.468363 # Table walker service (enqueue to completion) latency
481,482c478,479
< system.cpu.itb.walker.walkCompletionTime::8192-16383 769 24.74% 83.33% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 516 16.60% 99.94% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkCompletionTime::8192-16383 761 24.49% 83.08% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 524 16.86% 99.94% # Table walker service (enqueue to completion) latency
499c496
< system.cpu.itb.inst_hits 115559307 # ITB inst hits
---
> system.cpu.itb.inst_hits 115555925 # ITB inst hits
516,517c513,514
< system.cpu.itb.inst_accesses 115564070 # ITB inst accesses
< system.cpu.itb.hits 115559307 # DTB hits
---
> system.cpu.itb.inst_accesses 115560688 # ITB inst accesses
> system.cpu.itb.hits 115555925 # DTB hits
519,525c516,522
< system.cpu.itb.accesses 115564070 # DTB accesses
< system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 887205638.526871 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 17463817933.974155 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state
---
> system.cpu.itb.accesses 115560688 # DTB accesses
> system.cpu.numPwrStateTransitions 6064 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 3032 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 887473047.745383 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 17466686250.192787 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state
531,535c528,532
< system.cpu.pwrStateClkGateDist::max_value 499962880972 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 214403080848 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 5810595565 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::max_value 499963437276 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::total 3032 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 214499223736 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818280764 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 5810635009 # number of cpu cycles simulated
539,550c536,547
< system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
< system.cpu.committedInsts 112461365 # Number of instructions committed
< system.cpu.committedOps 135593151 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119897812 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 11226 # Number of float alu accesses
< system.cpu.num_func_calls 9894928 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 15231225 # number of instructions that are conditional controls
< system.cpu.num_int_insts 119897812 # number of integer instructions
< system.cpu.num_fp_insts 11226 # number of float instructions
< system.cpu.num_int_register_reads 218061607 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82648736 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 8514 # number of times the floating registers were read
---
> system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
> system.cpu.committedInsts 112458065 # Number of instructions committed
> system.cpu.committedOps 135590016 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119895072 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses
> system.cpu.num_func_calls 9894802 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 15230859 # number of instructions that are conditional controls
> system.cpu.num_int_insts 119895072 # number of integer instructions
> system.cpu.num_fp_insts 11290 # number of float instructions
> system.cpu.num_int_register_reads 218056824 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82647475 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read
552,561c549,558
< system.cpu.num_cc_register_reads 489758493 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51897030 # number of times the CC registers were written
< system.cpu.num_mem_refs 45406070 # number of memory refs
< system.cpu.num_load_insts 24842315 # Number of load instructions
< system.cpu.num_store_insts 20563755 # Number of store instructions
< system.cpu.num_idle_cycles 5381789403.302147 # Number of idle cycles
< system.cpu.num_busy_cycles 428806161.697852 # Number of busy cycles
< system.cpu.not_idle_fraction 0.073797 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.926203 # Percentage of idle cycles
< system.cpu.Branches 25920117 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 489748178 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51895154 # number of times the CC registers were written
> system.cpu.num_mem_refs 45405351 # number of memory refs
> system.cpu.num_load_insts 24842092 # Number of load instructions
> system.cpu.num_store_insts 20563259 # Number of store instructions
> system.cpu.num_idle_cycles 5381636561.526148 # Number of idle cycles
> system.cpu.num_busy_cycles 428998447.473852 # Number of busy cycles
> system.cpu.not_idle_fraction 0.073830 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.926170 # Percentage of idle cycles
> system.cpu.Branches 25919628 # Number of branches fetched
563,564c560,561
< system.cpu.op_class::IntAlu 93182494 67.18% 67.18% # Class of executed instruction
< system.cpu.op_class::IntMult 114558 0.08% 67.26% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93180053 67.18% 67.18% # Class of executed instruction
> system.cpu.op_class::IntMult 114520 0.08% 67.26% # Class of executed instruction
590c587
< system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Class of executed instruction
---
> system.cpu.op_class::SimdFloatMisc 8439 0.01% 67.27% # Class of executed instruction
594,595c591,592
< system.cpu.op_class::MemRead 24839607 17.91% 85.17% # Class of executed instruction
< system.cpu.op_class::MemWrite 20555241 14.82% 99.99% # Class of executed instruction
---
> system.cpu.op_class::MemRead 24839384 17.91% 85.17% # Class of executed instruction
> system.cpu.op_class::MemWrite 20554681 14.82% 99.99% # Class of executed instruction
597c594
< system.cpu.op_class::FloatMemWrite 8514 0.01% 100.00% # Class of executed instruction
---
> system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00% # Class of executed instruction
600,606c597,603
< system.cpu.op_class::total 138713890 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 821351 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.816254 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 43232645 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 821863 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 52.603226 # Average number of references to valid blocks.
---
> system.cpu.op_class::total 138710700 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 821158 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.816175 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 43232098 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 821670 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 52.614916 # Average number of references to valid blocks.
608c605
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.816254 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.816175 # Average occupied blocks per requestor
612,615c609,612
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
617,641c614,638
< system.cpu.dcache.tags.tag_accesses 177108261 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177108261 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 23111024 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23111024 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18823159 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18823159 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 392414 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 392414 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443071 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443071 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460161 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460161 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41934183 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41934183 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42326597 # number of overall hits
< system.cpu.dcache.overall_hits::total 42326597 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 401452 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 401452 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 298737 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 298737 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 118712 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 118712 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22861 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22861 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 177104923 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177104923 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 23110979 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23110979 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18822589 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18822589 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 392473 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 392473 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443107 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443107 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460141 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460141 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41933568 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41933568 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42326041 # number of overall hits
> system.cpu.dcache.overall_hits::total 42326041 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 401142 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 401142 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 298882 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 298882 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 118684 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 118684 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22807 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22807 # number of LoadLockedReq misses
644,653c641,650
< system.cpu.dcache.demand_misses::cpu.data 700189 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 700189 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 818901 # number of overall misses
< system.cpu.dcache.overall_misses::total 818901 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6440957000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6440957000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 14361709000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 14361709000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 300793500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 300793500 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 700024 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 700024 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 818708 # number of overall misses
> system.cpu.dcache.overall_misses::total 818708 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437634500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6437634500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 14441729500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 14441729500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297474000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 297474000 # number of LoadLockedReq miss cycles
656,681c653,678
< system.cpu.dcache.demand_miss_latency::cpu.data 20802666000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20802666000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20802666000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20802666000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23512476 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23512476 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19121896 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19121896 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511126 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511126 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465932 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465932 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460163 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460163 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42634372 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42634372 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43145498 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43145498 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017074 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.017074 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015623 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015623 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232256 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.232256 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.049065 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.049065 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20879364000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20879364000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20879364000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20879364000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23512121 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23512121 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19121471 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19121471 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511157 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511157 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465914 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465914 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460143 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460143 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42633592 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42633592 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43144749 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43144749 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232187 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.232187 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048951 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048951 # miss rate for LoadLockedReq accesses
684,693c681,690
< system.cpu.dcache.demand_miss_rate::cpu.data 0.016423 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.016423 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.018980 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.018980 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16044.152227 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16044.152227 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48074.758065 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 48074.758065 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13157.495298 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13157.495298 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.016420 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.016420 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.018976 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.018976 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.268444 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.268444 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48319.167765 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48319.167765 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.100802 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.100802 # average LoadLockedReq miss latency
696,699c693,696
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29710.072566 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 25403.151297 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29826.640229 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29826.640229 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25502.821519 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25502.821519 # average overall miss latency
706,723c703,720
< system.cpu.dcache.writebacks::writebacks 685561 # number of writebacks
< system.cpu.dcache.writebacks::total 685561 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 705 # number of ReadReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14335 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14335 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 705 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 705 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 705 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 705 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400747 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 400747 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298737 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298737 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116693 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 116693 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8526 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 685618 # number of writebacks
> system.cpu.dcache.writebacks::total 685618 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 708 # number of ReadReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 708 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 708 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 708 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 708 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400434 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 400434 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298882 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298882 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 116661 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8529 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8529 # number of LoadLockedReq MSHR misses
726,729c723,726
< system.cpu.dcache.demand_mshr_misses::cpu.data 699484 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 699484 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 816177 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 816177 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 699316 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 699316 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 815977 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 815977 # number of overall MSHR misses
736,743c733,740
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015919500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015919500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14062972000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 14062972000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1582474000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1582474000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 120274000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 120274000 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6011986000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6011986000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14142847500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 14142847500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1587073500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1587073500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118989500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118989500 # number of LoadLockedReq MSHR miss cycles
746,761c743,758
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20078891500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 20078891500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21661365500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 21661365500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284842500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284842500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284842500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284842500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017044 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017044 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228306 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228306 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018299 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018299 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154833500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 20154833500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741907000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 21741907000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284829000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284829000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284829000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284829000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017031 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017031 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228229 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228229 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018306 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018306 # mshr miss rate for LoadLockedReq accesses
764,775c761,772
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016407 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016407 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018917 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15011.764280 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15011.764280 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47074.758065 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47074.758065 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13561.001945 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13561.001945 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14106.732348 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14106.732348 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016403 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.018913 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15013.675162 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15013.675162 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47319.167765 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47319.167765 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13604.147916 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13604.147916 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.166608 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.166608 # average LoadLockedReq mshr miss latency
778,791c775,788
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28705.290614 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 28705.290614 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26540.034208 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26540.034208 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201838.348642 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201838.348642 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.938938 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.938938 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1700003 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.693079 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 113858786 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1700515 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 66.955473 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28820.781306 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28820.781306 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26645.244903 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26645.244903 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201837.915088 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201837.915088 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.709061 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.709061 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1700061 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.693087 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 113855346 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1700573 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 66.951166 # Average number of references to valid blocks.
793c790
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.693079 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.693087 # Average occupied blocks per requestor
797,798c794,795
< system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
802,840c799,837
< system.cpu.icache.tags.tag_accesses 117259828 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 117259828 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 113858786 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 113858786 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 113858786 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 113858786 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 113858786 # number of overall hits
< system.cpu.icache.overall_hits::total 113858786 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1700521 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1700521 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1700521 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1700521 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1700521 # number of overall misses
< system.cpu.icache.overall_misses::total 1700521 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24021238000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24021238000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24021238000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24021238000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24021238000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24021238000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 115559307 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 115559307 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 115559307 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 115559307 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 115559307 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 115559307 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14125.810854 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14125.810854 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 117256504 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 117256504 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 113855346 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 113855346 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 113855346 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 113855346 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 113855346 # number of overall hits
> system.cpu.icache.overall_hits::total 113855346 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1700579 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1700579 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1700579 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1700579 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1700579 # number of overall misses
> system.cpu.icache.overall_misses::total 1700579 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24045189500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24045189500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24045189500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24045189500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24045189500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24045189500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 115555925 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 115555925 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 115555925 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 115555925 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 115555925 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 115555925 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014717 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.014717 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.014717 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.014717 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.014717 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.014717 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.413400 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14139.413400 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14139.413400 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14139.413400 # average overall miss latency
847,854c844,851
< system.cpu.icache.writebacks::writebacks 1700003 # number of writebacks
< system.cpu.icache.writebacks::total 1700003 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700521 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1700521 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1700521 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1700521 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1700521 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1700521 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 1700061 # number of writebacks
> system.cpu.icache.writebacks::total 1700061 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700579 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1700579 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1700579 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1700579 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1700579 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1700579 # number of overall MSHR misses
859,864c856,861
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22320717000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22320717000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22320717000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22320717000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22320717000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22320717000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344610500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22344610500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344610500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22344610500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344610500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22344610500 # number of overall MSHR miss cycles
869,880c866,877
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014716 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.014716 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.014716 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13125.810854 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13125.810854 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014717 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.014717 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.014717 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.413400 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.413400 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency
885,895c882,892
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 88035 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65011.446283 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4854285 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 153426 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 31.639259 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 146352515000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050747 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041160 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9651.725117 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 55356.629260 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 88597 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65011.992500 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4854150 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 154024 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 31.515543 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 147534324000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041157 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.970202 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.930460 # Average occupied blocks per requestor
898,900c895,897
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147274 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.844675 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.991996 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147018 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.844939 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992004 # Average percentage of cache occupancy
902c899
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65422 # Occupied blocks per task id
905,907c902,904
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4355 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60952 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4349 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60996 # Occupied blocks per task id
909,937c906,934
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 40277345 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 40277345 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 4991 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2669 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 7660 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 685561 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 685561 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1667726 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1667726 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 2795 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 2795 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 168131 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 168131 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682557 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1682557 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513829 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 513829 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 4991 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 2669 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1682557 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 681960 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2372177 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 4991 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 2669 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1682557 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 681960 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2372177 # number of overall hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 40276407 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 40276407 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5063 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 7747 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 685618 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 685618 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1667781 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1667781 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 2789 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 167649 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 167649 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682585 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1682585 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513552 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 513552 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 5063 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2684 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1682585 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 681201 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2371533 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 5063 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2684 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1682585 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 681201 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2371533 # number of overall hits
941,942c938,939
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses
945,950c942,947
< system.cpu.l2cache.ReadExReq_misses::cpu.data 127792 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 127792 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17948 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 17948 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12137 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 12137 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 128426 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 128426 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 12072 # number of ReadSharedReq misses
953,955c950,952
< system.cpu.l2cache.demand_misses::cpu.inst 17948 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 139929 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 157886 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 140498 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 158485 # number of demand (read+write) misses
958,961c955,958
< system.cpu.l2cache.overall_misses::cpu.inst 17948 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 139929 # number of overall misses
< system.cpu.l2cache.overall_misses::total 157886 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 140498 # number of overall misses
> system.cpu.l2cache.overall_misses::total 158485 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000 # number of ReadReq miss cycles
963,965c960,962
< system.cpu.l2cache.ReadReq_miss_latency::total 1334500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 555500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 555500 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 1334000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 525000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 525000 # number of UpgradeReq miss cycles
968,974c965,971
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11816022500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 11816022500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2043061500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2043061500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1517166500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1517166500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11900828000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 11900828000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066597500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066597500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1519988500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1519988500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000 # number of demand (read+write) miss cycles
976,979c973,976
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2043061500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13333189000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 15377585000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2066597500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13420816500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 15488748000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000 # number of overall miss cycles
981,992c978,989
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2043061500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13333189000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 15377585000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 4998 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2671 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7669 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 685561 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 685561 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1667726 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1667726 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2814 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2814 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2066597500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13420816500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 15488748000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5070 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7756 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 685618 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 685618 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1667781 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1667781 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2807 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2807 # number of UpgradeReq accesses(hits+misses)
995,1015c992,1012
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 295923 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 295923 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700505 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1700505 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525966 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 525966 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 4998 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 2671 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1700505 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530063 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 4998 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 2671 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1700505 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530063 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001401 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000749 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.001174 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006752 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006752 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 296075 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 296075 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700563 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1700563 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525624 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 525624 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5070 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1700563 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 821699 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530018 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5070 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1700563 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 821699 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530018 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001160 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006413 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006413 # miss rate for UpgradeReq accesses
1018,1034c1015,1031
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.431842 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.431842 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010555 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010555 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001401 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000749 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010555 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.170253 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.062404 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001401 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000749 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010555 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.170253 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.062404 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164928.571429 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433762 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.433762 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010572 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010572 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022967 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022967 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010572 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.170985 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.062642 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010572 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.170985 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.062642 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857 # average ReadReq miss latency
1036,1038c1033,1035
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 148277.777778 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29236.842105 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29236.842105 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29166.666667 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29166.666667 # average UpgradeReq miss latency
1041,1047c1038,1044
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92462.928039 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92462.928039 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 113832.265433 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 113832.265433 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125003.419296 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125003.419296 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92666.812016 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92666.812016 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114951.468461 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114951.468461 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125910.246852 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125910.246852 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency
1049,1052c1046,1049
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 97396.760954 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 97730.056472 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency
1054,1056c1051,1053
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 97396.760954 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 97730.056472 # average overall miss latency
1063,1064c1060,1061
< system.cpu.l2cache.writebacks::writebacks 81484 # number of writebacks
< system.cpu.l2cache.writebacks::total 81484 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 81968 # number of writebacks
> system.cpu.l2cache.writebacks::total 81968 # number of writebacks
1068,1069c1065,1066
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
1072,1077c1069,1074
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127792 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 127792 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17948 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17948 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12137 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12137 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128426 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 128426 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072 # number of ReadSharedReq MSHR misses
1080,1082c1077,1079
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 17948 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 139929 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 157886 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 140498 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 158485 # number of demand (read+write) MSHR misses
1085,1087c1082,1084
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 17948 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 139929 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 157886 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 140498 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 158485 # number of overall MSHR misses
1096c1093
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084000 # number of ReadReq MSHR miss cycles
1098,1100c1095,1097
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 365500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 365500 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345000 # number of UpgradeReq MSHR miss cycles
1103,1109c1100,1106
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10538102500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10538102500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1863581500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1863581500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1395796500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1395796500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10616568000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10616568000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886817500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886817500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399268500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399268500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000 # number of demand (read+write) MSHR miss cycles
1111,1114c1108,1111
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1863581500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11933899000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 13798725000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886817500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12015836500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 13903898000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000 # number of overall MSHR miss cycles
1116,1118c1113,1115
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1863581500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11933899000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 13798725000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886817500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12015836500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 13903898000 # number of overall MSHR miss cycles
1120,1121c1117,1118
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895497500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527925500 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895484000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527912000 # number of ReadReq MSHR uncacheable cycles
1123,1129c1120,1126
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895497500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527925500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001174 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006752 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006752 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895484000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527912000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001160 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006413 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006413 # mshr miss rate for UpgradeReq accesses
1132,1148c1129,1145
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.431842 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.431842 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010555 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.062404 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.062404 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433762 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433762 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010572 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022967 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022967 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.062642 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.062642 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average ReadReq mshr miss latency
1150,1152c1147,1149
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19166.666667 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency
1155,1161c1152,1158
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82666.812016 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82666.812016 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104951.468461 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104951.468461 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115910.246852 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115910.246852 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency
1163,1166c1160,1163
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency
1168,1170c1165,1167
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency
1172,1173c1169,1170
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717 # average ReadReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.061276 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.609562 # average ReadReq mshr uncacheable latency
1175,1181c1172,1178
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 5065968 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543576 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 219 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 219 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100387.964650 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.366854 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 5065624 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543364 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39292 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 222 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 222 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1183,1185c1180,1182
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 67217 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2293895 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 67226 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2293620 # Transaction distribution
1188,1191c1185,1188
< system.cpu.toL2Bus.trans_dist::WritebackDirty 767045 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1700003 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 142341 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2814 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 767586 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1700061 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 142169 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2807 # Transaction distribution
1193,1197c1190,1194
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 295923 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 295923 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700521 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 526163 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2809 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 296075 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 296075 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700579 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 525821 # Transaction distribution
1199,1213c1196,1210
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119073 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2588406 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11887 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22839 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7742205 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217668600 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96672157 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10684 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 19992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 314371433 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 112178 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 5305776 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 2712615 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.021718 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.145761 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119247 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587819 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22920 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7741888 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676024 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663645 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20280 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 314370693 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 112662 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 5336440 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 2713047 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.021691 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.145674 # Request fanout histogram
1215,1216c1212,1213
< system.cpu.toL2Bus.snoop_fanout::0 2653703 97.83% 97.83% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 58912 2.17% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2654197 97.83% 97.83% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 58850 2.17% 100.00% # Request fanout histogram
1221,1222c1218,1219
< system.cpu.toL2Bus.snoop_fanout::total 2712615 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4970051500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2713047 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4970034000 # Layer occupancy (ticks)
1224c1221
< system.cpu.toL2Bus.snoopLayer0.occupancy 347876 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 347377 # Layer occupancy (ticks)
1226c1223
< system.cpu.toL2Bus.respLayer0.occupancy 2559803500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2559890500 # Layer occupancy (ticks)
1228c1225
< system.cpu.toL2Bus.respLayer1.occupancy 1279174000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1278885500 # Layer occupancy (ticks)
1232c1229
< system.cpu.toL2Bus.respLayer3.occupancy 17841000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 17850000 # Layer occupancy (ticks)
1234c1231
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
1285c1282
< system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 46336000 # Layer occupancy (ticks)
1319c1316
< system.iobus.reqLayer23.occupancy 6292000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6289000 # Layer occupancy (ticks)
1323c1320
< system.iobus.reqLayer25.occupancy 187581870 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187558131 # Layer occupancy (ticks)
1329c1326
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
1331c1328
< system.iocache.tags.tagsinuse 1.079755 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.079865 # Cycle average of tags in use
1335,1338c1332,1335
< system.iocache.tags.warmup_cycle 310620847000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.079755 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.067485 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.067485 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 310617748000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.079865 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.067492 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.067492 # Average percentage of cache occupancy
1344c1341
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
1353,1360c1350,1357
< system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4367688494 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4367688494 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4401754870 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4401754870 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4401754870 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4401754870 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 34063377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 34063377 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4369997754 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4369997754 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4404061131 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4404061131 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4404061131 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4404061131 # number of overall miss cycles
1377,1385c1374,1382
< system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 120814.482901 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 120814.482901 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 162206.557143 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 162206.557143 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120638.188880 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 120638.188880 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 120877.782593 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 120877.782593 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked
1387c1384
< system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
1389c1386
< system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked
1401,1408c1398,1405
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2554457612 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2554457612 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2578023988 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2578023988 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2578023988 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2578023988 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 23563377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 23563377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2556779983 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2556779983 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2580343360 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2580343360 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2580343360 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2580343360 # number of overall MSHR miss cycles
1417,1426c1414,1423
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 318841 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 128997 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112206.557143 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 112206.557143 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70582.486280 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70582.486280 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 319998 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 129556 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1431c1428
< system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
1433c1430
< system.membus.trans_dist::ReadResp 70464 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 70429 # Transaction distribution
1436,1437c1433,1434
< system.membus.trans_dist::WritebackDirty 117674 # Transaction distribution
< system.membus.trans_dist::CleanEvict 6761 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 118158 # Transaction distribution
> system.membus.trans_dist::CleanEvict 6839 # Transaction distribution
1441,1443c1438,1440
< system.membus.trans_dist::ReadExReq 127683 # Transaction distribution
< system.membus.trans_dist::ReadExResp 127683 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 30304 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 128316 # Transaction distribution
> system.membus.trans_dist::ReadExResp 128316 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 30269 # Transaction distribution
1448,1449c1445,1446
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431348 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 538940 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433106 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540698 # Packet count per connected master and slave (bytes)
1452c1449
< system.membus.pkt_count::total 611789 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 613547 # Packet count per connected master and slave (bytes)
1456,1457c1453,1454
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15350844 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15514197 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420092 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583445 # Cumulative packet size per connected master and slave (bytes)
1460c1457
< system.membus.pkt_size::total 17831317 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 17900565 # Cumulative packet size per connected master and slave (bytes)
1463,1465c1460,1462
< system.membus.snoop_fanout::samples 262090 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.018417 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.134455 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 262688 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.018375 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.134305 # Request fanout histogram
1467c1464
< system.membus.snoop_fanout::0 257263 98.16% 98.16% # Request fanout histogram
---
> system.membus.snoop_fanout::0 257861 98.16% 98.16% # Request fanout histogram
1473,1474c1470,1471
< system.membus.snoop_fanout::total 262090 # Request fanout histogram
< system.membus.reqLayer0.occupancy 90471500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 262688 # Request fanout histogram
> system.membus.reqLayer0.occupancy 90466500 # Layer occupancy (ticks)
1478c1475
< system.membus.reqLayer2.occupancy 1726500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1724500 # Layer occupancy (ticks)
1480c1477
< system.membus.reqLayer5.occupancy 819732726 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 822811335 # Layer occupancy (ticks)
1482c1479
< system.membus.respLayer2.occupancy 945419750 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 948647750 # Layer occupancy (ticks)
1484c1481
< system.membus.respLayer3.occupancy 1085624 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1085623 # Layer occupancy (ticks)
1486,1492c1483,1489
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
1499,1500c1496,1497
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
1532,1538c1529,1535
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
1543,1554c1540,1551
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states