3,5c3,5
< sim_seconds 2.903737 # Number of seconds simulated
< sim_ticks 2903736790500 # Number of ticks simulated
< final_tick 2903736790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.905298 # Number of seconds simulated
> sim_ticks 2905297782500 # Number of ticks simulated
> final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 515424 # Simulator instruction rate (inst/s)
< host_op_rate 621448 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 13306386787 # Simulator tick rate (ticks/s)
< host_mem_usage 582748 # Number of bytes of host memory used
< host_seconds 218.22 # Real time elapsed on the host
< sim_insts 112476413 # Number of instructions simulated
< sim_ops 135613231 # Number of ops (including micro ops) simulated
---
> host_inst_rate 483331 # Simulator instruction rate (inst/s)
> host_op_rate 582745 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 12486239543 # Simulator tick rate (ticks/s)
> host_mem_usage 580500 # Number of bytes of host memory used
> host_seconds 232.68 # Real time elapsed on the host
> sim_insts 112461365 # Number of instructions simulated
> sim_ops 135593151 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.dtb.walker 512 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
19,20c19,20
< system.physmem.bytes_read::cpu.inst 1188964 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9028260 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1184612 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8933156 # Number of bytes read from this memory
22,25c22,25
< system.physmem.bytes_read::total 10218824 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1188964 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1188964 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7618752 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10119304 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1184612 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1184612 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7531136 # Number of bytes written to this memory
27,28c27,28
< system.physmem.bytes_written::total 7636276 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 8 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 7548660 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
30,31c30,31
< system.physmem.num_reads::cpu.inst 27031 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 141586 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 26963 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 140100 # Number of read requests responded to by this memory
33,34c33,34
< system.physmem.num_reads::total 168642 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 119043 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 167087 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 117674 # Number of write requests responded to by this memory
36,37c36,37
< system.physmem.num_writes::total 123424 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 176 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 122055 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
39,49c39,49
< system.physmem.bw_read::cpu.inst 409460 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3109187 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3519198 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 409460 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 409460 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2623775 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2629810 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2623775 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 176 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 407742 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3074782 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3483052 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 407742 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 407742 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2592208 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2598240 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2592208 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
51,65c51,65
< system.physmem.bw_total::cpu.inst 409460 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3115222 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6149008 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 168642 # Number of read requests accepted
< system.physmem.writeReqs 123424 # Number of write requests accepted
< system.physmem.readBursts 168642 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 123424 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10783744 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7648256 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10218824 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7636276 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_total::cpu.inst 407742 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3080813 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6081292 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 167087 # Number of read requests accepted
> system.physmem.writeReqs 122055 # Number of write requests accepted
> system.physmem.readBursts 167087 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 122055 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10685312 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7561344 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10119304 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7548660 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
67,98c67,98
< system.physmem.perBankRdBursts::0 9943 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9648 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10560 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10245 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18706 # Per bank write bursts
< system.physmem.perBankRdBursts::5 9867 # Per bank write bursts
< system.physmem.perBankRdBursts::6 9999 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10271 # Per bank write bursts
< system.physmem.perBankRdBursts::8 9694 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10419 # Per bank write bursts
< system.physmem.perBankRdBursts::10 9828 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9028 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10140 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10489 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10151 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9508 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7397 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7199 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8385 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7801 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7213 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7134 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7314 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7590 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7388 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8015 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7407 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6899 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7622 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7751 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7507 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6882 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9954 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9813 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10094 # Per bank write bursts
> system.physmem.perBankRdBursts::3 9518 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18811 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10188 # Per bank write bursts
> system.physmem.perBankRdBursts::6 10467 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10858 # Per bank write bursts
> system.physmem.perBankRdBursts::8 9262 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10094 # Per bank write bursts
> system.physmem.perBankRdBursts::10 9505 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9184 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9983 # Per bank write bursts
> system.physmem.perBankRdBursts::13 9847 # Per bank write bursts
> system.physmem.perBankRdBursts::14 9958 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9422 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7103 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7218 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7869 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7374 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7424 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7558 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7579 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7921 # Per bank write bursts
> system.physmem.perBankWrBursts::8 6916 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7516 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7047 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7122 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7779 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7383 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7451 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6886 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
< system.physmem.totGap 2903736355000 # Total gap between requests
---
> system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
> system.physmem.totGap 2905297420500 # Total gap between requests
108c108
< system.physmem.readPktSize::6 159070 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 157515 # Read request sizes (log2)
115,118c115,118
< system.physmem.writePktSize::6 119043 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 167708 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 529 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 247 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 117674 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 166128 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 554 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see
163,229c163,229
< system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2984 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6096 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6314 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6034 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6526 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6858 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7572 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8704 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8960 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6955 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6927 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6384 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 130 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 60 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 58618 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 314.441571 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 184.322128 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 334.751512 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21316 36.36% 36.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14773 25.20% 61.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5607 9.57% 71.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3267 5.57% 76.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2505 4.27% 80.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1471 2.51% 83.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1045 1.78% 85.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1040 1.77% 87.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7594 12.96% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 58618 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5878 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.661279 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 584.674226 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 5877 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1886 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2786 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5910 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5857 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5767 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6643 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7223 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8271 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8725 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7065 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6628 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6527 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 401 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 376 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 293 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 238 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 238 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 204 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 186 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 214 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 57323 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 318.311882 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 186.988870 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 336.470779 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 20402 35.59% 35.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14531 25.35% 60.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5716 9.97% 70.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3104 5.41% 76.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2370 4.13% 80.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1421 2.48% 82.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1241 2.16% 85.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 946 1.65% 86.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7592 13.24% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 57323 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5761 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.979865 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 590.542998 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5760 99.98% 99.98% # Reads before turning the bus around for writes
231,261c231,265
< system.physmem.rdPerTurnAround::total 5878 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5878 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.330725 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.604611 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 13.460490 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5095 86.68% 86.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 41 0.70% 87.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 85 1.45% 88.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 37 0.63% 89.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 285 4.85% 94.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 59 1.00% 95.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 13 0.22% 95.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 14 0.24% 95.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 4 0.07% 95.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.10% 96.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 8 0.14% 96.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 168 2.86% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.05% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 2 0.03% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 6 0.10% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 7 0.12% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.02% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.02% 99.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 2 0.03% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 5 0.09% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 11 0.19% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.02% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 1 0.02% 99.81% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5761 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5761 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.507898 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.546505 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 15.055833 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5040 87.48% 87.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 23 0.40% 87.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 68 1.18% 89.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 38 0.66% 89.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 294 5.10% 94.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 33 0.57% 95.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 2 0.03% 95.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 7 0.12% 95.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 6 0.10% 95.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 3 0.05% 95.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 2 0.03% 95.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 5 0.09% 95.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 158 2.74% 98.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 4 0.07% 98.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 6 0.10% 98.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 3 0.05% 98.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 10 0.17% 98.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.03% 99.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 1 0.02% 99.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 11 0.19% 99.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.03% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 3 0.05% 99.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 8 0.14% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 7 0.12% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 4 0.07% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 4 0.07% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads
263,272c267,277
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 6 0.10% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5878 # Writes before turning the bus around for reads
< system.physmem.totQLat 1493636250 # Total ticks spent queuing
< system.physmem.totMemAccLat 4652936250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 842480000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 8864.52 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::156-159 2 0.03% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 3 0.05% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5761 # Writes before turning the bus around for reads
> system.physmem.totQLat 4504540500 # Total ticks spent queuing
> system.physmem.totMemAccLat 7635003000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 834790000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 26980.08 # Average queueing delay per DRAM burst
274,278c279,283
< system.physmem.avgMemAccLat 27614.52 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 45730.08 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.68 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 3.48 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s
284,319c289,334
< system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing
< system.physmem.readRowHits 138583 # Number of row buffer hits during reads
< system.physmem.writeRowHits 90798 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes
< system.physmem.avgGap 9942055.41 # Average gap between requests
< system.physmem.pageHitRate 79.64 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 226187640 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 123415875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 696064200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 389013840 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 86978464290 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1665943648500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1944014583705 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.487777 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2771286006000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 96962060000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 35486192750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 216964440 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 118383375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 618196800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 385372080 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 85605070095 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1667148388500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1943750164650 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.396712 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2773305848750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 96962060000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 33468782750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing
> system.physmem.readRowHits 138094 # Number of row buffer hits during reads
> system.physmem.writeRowHits 89686 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.71 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes
> system.physmem.avgGap 10047995.17 # Average gap between requests
> system.physmem.pageHitRate 79.89 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 210115920 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 111679260 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 640479420 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 313440120 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 6609223920.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4735061820 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 414343200 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 13903412640 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 9310120320 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 682719565725 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 718969243965 # Total energy per rank (pJ)
> system.physmem_0.averagePower 247.468348 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 2893307612500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 778413000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2810438000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 2839095824500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 24245244750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7877734000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 30490128250 # Time in different power states
> system.physmem_1.actEnergy 199177440 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 105861525 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 551600700 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 303282000 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 6621516720.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 4536550200 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 409678080 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 13514783790 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 9490661760 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 682993594335 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 718728215280 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.385386 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 2894278953000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 777246000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2816412000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 2839926040500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 24715420500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 7425105000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 29637558500 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
332,334c347,349
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
342c357
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
372,385c387,400
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 9520 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 9520 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1252 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8268 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 9520 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 9520 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 9520 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7356 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 8514.979061 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 6541.334463 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-16383 6558 89.15% 89.15% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::16384-32767 793 10.78% 99.93% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 9547 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 9547 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1253 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8294 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 9547 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 9547 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 9547 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7383 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 9942.435324 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8397.692517 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 6587.109188 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-16383 6605 89.46% 89.46% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::16384-32767 773 10.47% 99.93% # Table walker service (enqueue to completion) latency
388,395c403,410
< system.cpu.dtb.walker.walkCompletionTime::total 7356 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 6151 83.62% 83.62% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1205 16.38% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7356 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9520 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkCompletionTime::total 7383 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 6177 83.67% 83.67% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1206 16.33% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7383 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9547 # Table walker requests started/completed, data/inst
397,398c412,413
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9520 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7356 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9547 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7383 # Table walker requests started/completed, data/inst
400,401c415,416
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7356 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 16876 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7383 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 16930 # Table walker requests started/completed, data/inst
404,407c419,422
< system.cpu.dtb.read_hits 24525489 # DTB read hits
< system.cpu.dtb.read_misses 8109 # DTB read misses
< system.cpu.dtb.write_hits 19608938 # DTB write hits
< system.cpu.dtb.write_misses 1411 # DTB write misses
---
> system.cpu.dtb.read_hits 24520121 # DTB read hits
> system.cpu.dtb.read_misses 8133 # DTB read misses
> system.cpu.dtb.write_hits 19605715 # DTB write hits
> system.cpu.dtb.write_misses 1414 # DTB write misses
412c427
< system.cpu.dtb.flush_entries 4199 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB
414c429
< system.cpu.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 1628 # Number of TLB faults due to prefetch
417,418c432,433
< system.cpu.dtb.read_accesses 24533598 # DTB read accesses
< system.cpu.dtb.write_accesses 19610349 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24528254 # DTB read accesses
> system.cpu.dtb.write_accesses 19607129 # DTB write accesses
420,423c435,438
< system.cpu.dtb.hits 44134427 # DTB hits
< system.cpu.dtb.misses 9520 # DTB misses
< system.cpu.dtb.accesses 44143947 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 44125836 # DTB hits
> system.cpu.dtb.misses 9547 # DTB misses
> system.cpu.dtb.accesses 44135383 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
453,456c468,471
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.walks 4762 # Table walker walks requested
< system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.walks 4763 # Table walker walks requested
> system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
458,476c473,491
< system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 10273.897650 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 8288.299297 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7346.561217 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1812 58.32% 58.32% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 745 23.98% 82.30% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 548 17.64% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 10156.853282 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 8221.468352 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7284.204444 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::8192-16383 769 24.74% 83.33% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 516 16.60% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
478,479c493,494
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
481,485c496,500
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 115574516 # ITB inst hits
< system.cpu.itb.inst_misses 4762 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 115559307 # ITB inst hits
> system.cpu.itb.inst_misses 4763 # ITB inst misses
501,510c516,525
< system.cpu.itb.inst_accesses 115579278 # ITB inst accesses
< system.cpu.itb.hits 115574516 # DTB hits
< system.cpu.itb.misses 4762 # DTB misses
< system.cpu.itb.accesses 115579278 # DTB accesses
< system.cpu.numPwrStateTransitions 6062 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 3031 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 888232478.174860 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 17469824950.226959 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 2968 97.92% 97.92% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 57 1.88% 99.80% # Distribution of time spent in the clock gated state
---
> system.cpu.itb.inst_accesses 115564070 # ITB inst accesses
> system.cpu.itb.hits 115559307 # DTB hits
> system.cpu.itb.misses 4763 # DTB misses
> system.cpu.itb.accesses 115564070 # DTB accesses
> system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 887205638.526871 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 17463817933.974155 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state
516,520c531,535
< system.cpu.pwrStateClkGateDist::max_value 499964073052 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::total 3031 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 211504149152 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 5807473581 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::max_value 499962880972 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 214403080848 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 5810595565 # number of cpu cycles simulated
524,535c539,550
< system.cpu.kern.inst.quiesce 3031 # number of quiesce instructions executed
< system.cpu.committedInsts 112476413 # Number of instructions committed
< system.cpu.committedOps 135613231 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119916333 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
< system.cpu.num_func_calls 9896179 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 15232917 # number of instructions that are conditional controls
< system.cpu.num_int_insts 119916333 # number of integer instructions
< system.cpu.num_fp_insts 11161 # number of float instructions
< system.cpu.num_int_register_reads 218092554 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82663252 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
---
> system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
> system.cpu.committedInsts 112461365 # Number of instructions committed
> system.cpu.committedOps 135593151 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119897812 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 11226 # Number of float alu accesses
> system.cpu.num_func_calls 9894928 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 15231225 # number of instructions that are conditional controls
> system.cpu.num_int_insts 119897812 # number of integer instructions
> system.cpu.num_fp_insts 11226 # number of float instructions
> system.cpu.num_int_register_reads 218061607 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82648736 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 8514 # number of times the floating registers were read
537,546c552,561
< system.cpu.num_cc_register_reads 489835813 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51902110 # number of times the CC registers were written
< system.cpu.num_mem_refs 45414800 # number of memory refs
< system.cpu.num_load_insts 24847736 # Number of load instructions
< system.cpu.num_store_insts 20567064 # Number of store instructions
< system.cpu.num_idle_cycles 5384465282.694146 # Number of idle cycles
< system.cpu.num_busy_cycles 423008298.305854 # Number of busy cycles
< system.cpu.not_idle_fraction 0.072839 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.927161 # Percentage of idle cycles
< system.cpu.Branches 25923023 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 489758493 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51897030 # number of times the CC registers were written
> system.cpu.num_mem_refs 45406070 # number of memory refs
> system.cpu.num_load_insts 24842315 # Number of load instructions
> system.cpu.num_store_insts 20563755 # Number of store instructions
> system.cpu.num_idle_cycles 5381789403.302147 # Number of idle cycles
> system.cpu.num_busy_cycles 428806161.697852 # Number of busy cycles
> system.cpu.not_idle_fraction 0.073797 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.926203 # Percentage of idle cycles
> system.cpu.Branches 25920117 # Number of branches fetched
548,549c563,564
< system.cpu.op_class::IntAlu 93194210 67.17% 67.18% # Class of executed instruction
< system.cpu.op_class::IntMult 114540 0.08% 67.26% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93182494 67.18% 67.18% # Class of executed instruction
> system.cpu.op_class::IntMult 114558 0.08% 67.26% # Class of executed instruction
573,578c588,593
< system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction
< system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
< system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
< system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
< system.cpu.op_class::MemRead 24847736 17.91% 85.18% # Class of executed instruction
< system.cpu.op_class::MemWrite 20567064 14.82% 100.00% # Class of executed instruction
---
> system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Class of executed instruction
> system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction
> system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction
> system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction
> system.cpu.op_class::MemRead 24842315 17.91% 85.18% # Class of executed instruction
> system.cpu.op_class::MemWrite 20563755 14.82% 100.00% # Class of executed instruction
581,591c596,606
< system.cpu.op_class::total 138734340 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 819770 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.827215 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 43243016 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 820282 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 52.717256 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 1013099500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.827215 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999663 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy
---
> system.cpu.op_class::total 138713890 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 821351 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.816254 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 43232645 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 821863 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 52.603226 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.816254 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy
593,596c608,611
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
598,622c613,637
< system.cpu.dcache.tags.tag_accesses 177141047 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177141047 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 23117557 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23117557 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18826251 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18826251 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 392764 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 392764 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443415 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443415 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460277 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460277 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41943808 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41943808 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42336572 # number of overall hits
< system.cpu.dcache.overall_hits::total 42336572 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 400061 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 400061 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 298752 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 298752 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 118460 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 118460 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22645 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22645 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 177108261 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177108261 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 23111024 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23111024 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18823159 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18823159 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 392414 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 392414 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443071 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443071 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460161 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460161 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41934183 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41934183 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42326597 # number of overall hits
> system.cpu.dcache.overall_hits::total 42326597 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 401452 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 401452 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 298737 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 298737 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 118712 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 118712 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22861 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22861 # number of LoadLockedReq misses
625,634c640,649
< system.cpu.dcache.demand_misses::cpu.data 698813 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 698813 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 817273 # number of overall misses
< system.cpu.dcache.overall_misses::total 817273 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5967732500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5967732500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 12596392000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 12596392000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280149500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 280149500 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 700189 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 700189 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 818901 # number of overall misses
> system.cpu.dcache.overall_misses::total 818901 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6440957000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6440957000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 14361709000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 14361709000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 300793500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 300793500 # number of LoadLockedReq miss cycles
637,662c652,677
< system.cpu.dcache.demand_miss_latency::cpu.data 18564124500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 18564124500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 18564124500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 18564124500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23517618 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23517618 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19125003 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19125003 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511224 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511224 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466060 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466060 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460279 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460279 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42642621 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42642621 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43153845 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43153845 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017011 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.017011 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015621 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015621 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231718 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.231718 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048588 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048588 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20802666000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20802666000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20802666000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20802666000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23512476 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23512476 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19121896 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19121896 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511126 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511126 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465932 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465932 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460163 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460163 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42634372 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42634372 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43145498 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43145498 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017074 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.017074 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015623 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015623 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232256 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.232256 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.049065 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.049065 # miss rate for LoadLockedReq accesses
665,674c680,689
< system.cpu.dcache.demand_miss_rate::cpu.data 0.016388 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.016388 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.018939 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.018939 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.016423 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.016423 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.018980 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.018980 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16044.152227 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16044.152227 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48074.758065 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48074.758065 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13157.495298 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13157.495298 # average LoadLockedReq miss latency
677,680c692,695
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.224888 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26565.224888 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 22714.716502 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29710.072566 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25403.151297 # average overall miss latency
687,704c702,719
< system.cpu.dcache.writebacks::writebacks 683946 # number of writebacks
< system.cpu.dcache.writebacks::total 683946 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14146 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14146 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399381 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 399381 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298752 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298752 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116429 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 116429 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8499 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8499 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 685561 # number of writebacks
> system.cpu.dcache.writebacks::total 685561 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 705 # number of ReadReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14335 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14335 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 705 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 705 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 705 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 705 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400747 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 400747 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298737 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298737 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116693 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 116693 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8526 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses
707,710c722,725
< system.cpu.dcache.demand_mshr_misses::cpu.data 698133 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 698133 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 814562 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 814562 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 699484 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 699484 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 816177 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 816177 # number of overall MSHR misses
717,724c732,739
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5555392000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5555392000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12297640000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12297640000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1530002500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1530002500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 108858500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108858500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015919500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015919500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14062972000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 14062972000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1582474000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1582474000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 120274000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 120274000 # number of LoadLockedReq MSHR miss cycles
727,742c742,757
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17853032000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17853032000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19383034500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 19383034500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281205500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281205500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281205500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281205500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016982 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016982 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227746 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227746 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018236 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018236 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20078891500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 20078891500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21661365500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 21661365500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284842500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284842500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284842500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284842500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017044 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017044 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228306 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228306 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018299 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018299 # mshr miss rate for LoadLockedReq accesses
745,756c760,771
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016372 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016372 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018876 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.018876 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13910.005734 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016407 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016407 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018917 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15011.764280 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15011.764280 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47074.758065 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47074.758065 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13561.001945 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13561.001945 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14106.732348 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14106.732348 # average LoadLockedReq mshr miss latency
759,776c774,791
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25572.537038 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25572.537038 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23795.652756 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 23795.652756 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201721.546021 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.546021 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1698000 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.728664 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 113875998 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1698512 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 67.044565 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 25832791500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.728664 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997517 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997517 # Average percentage of cache occupancy
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28705.290614 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28705.290614 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26540.034208 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26540.034208 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201838.348642 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201838.348642 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.938938 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.938938 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1700003 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.693079 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 113858786 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1700515 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 66.955473 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.693079 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997447 # Average percentage of cache occupancy
778,781c793,796
< system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
783,821c798,836
< system.cpu.icache.tags.tag_accesses 117273034 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 117273034 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 113875998 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 113875998 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 113875998 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 113875998 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 113875998 # number of overall hits
< system.cpu.icache.overall_hits::total 113875998 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1698518 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1698518 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1698518 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1698518 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1698518 # number of overall misses
< system.cpu.icache.overall_misses::total 1698518 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23414403500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23414403500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23414403500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23414403500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23414403500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23414403500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 115574516 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 115574516 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 115574516 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 115574516 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 115574516 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 115574516 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014696 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.014696 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.014696 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13785.195977 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13785.195977 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 117259828 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 117259828 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 113858786 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 113858786 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 113858786 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 113858786 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 113858786 # number of overall hits
> system.cpu.icache.overall_hits::total 113858786 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1700521 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1700521 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1700521 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1700521 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1700521 # number of overall misses
> system.cpu.icache.overall_misses::total 1700521 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24021238000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24021238000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24021238000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24021238000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24021238000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24021238000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 115559307 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 115559307 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 115559307 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 115559307 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 115559307 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 115559307 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14125.810854 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14125.810854 # average overall miss latency
828,835c843,850
< system.cpu.icache.writebacks::writebacks 1698000 # number of writebacks
< system.cpu.icache.writebacks::total 1698000 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1698518 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1698518 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1698518 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1698518 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1698518 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1698518 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 1700003 # number of writebacks
> system.cpu.icache.writebacks::total 1700003 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700521 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1700521 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1700521 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1700521 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1700521 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1700521 # number of overall MSHR misses
840,877c855,892
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21715885500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 21715885500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21715885500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 21715885500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21715885500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 21715885500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 687287000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 687287000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 89464 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65017.694965 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4847707 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 154877 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 31.300367 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 144041988000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.877834 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.040783 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9524.120186 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 55489.656162 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22320717000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22320717000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22320717000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22320717000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22320717000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22320717000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014716 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.014716 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.014716 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13125.810854 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13125.810854 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 88035 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65011.446283 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4854285 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 153426 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 31.639259 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 146352515000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050747 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041160 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9651.725117 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 55356.629260 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy
879,919c894,934
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145327 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.846705 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992091 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65407 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4600 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60798 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998032 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 40230644 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 40230644 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5114 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2743 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 7857 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 683946 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 683946 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1666952 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1666952 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 2730 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 2730 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 166687 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 166687 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1680478 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1680478 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 512210 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 512210 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 5114 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 2743 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1680478 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 678897 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2367232 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 5114 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 2743 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1680478 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 678897 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2367232 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 8 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147274 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.844675 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.991996 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4355 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60952 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 40277345 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 40277345 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 4991 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2669 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 7660 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 685561 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 685561 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1667726 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1667726 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 2795 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 2795 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 168131 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 168131 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682557 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1682557 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513829 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 513829 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 4991 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2669 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1682557 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 681960 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2372177 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 4991 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2669 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1682557 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 681960 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2372177 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
921,923c936,938
< system.cpu.l2cache.ReadReq_misses::total 10 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses
926,932c941,947
< system.cpu.l2cache.ReadExReq_misses::cpu.data 129315 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 129315 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18016 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 18016 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12099 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 12099 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 8 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 127792 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 127792 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17948 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 17948 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12137 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 12137 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
934,937c949,952
< system.cpu.l2cache.demand_misses::cpu.inst 18016 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 141414 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 159440 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 8 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 17948 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 139929 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 157886 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
939,946c954,961
< system.cpu.l2cache.overall_misses::cpu.inst 18016 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 141414 # number of overall misses
< system.cpu.l2cache.overall_misses::total 159440 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 829500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 168000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 997500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 581000 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.inst 17948 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 139929 # number of overall misses
> system.cpu.l2cache.overall_misses::total 157886 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1334500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 555500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 555500 # number of UpgradeReq miss cycles
949,973c964,988
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10066469000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10066469000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1464060500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1464060500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1012302000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1012302000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 829500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 168000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1464060500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11078771000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12543829000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 829500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 168000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1464060500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11078771000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12543829000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5122 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2745 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7867 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 683946 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 683946 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1666952 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1666952 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2750 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2750 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11816022500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 11816022500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2043061500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2043061500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1517166500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1517166500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2043061500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13333189000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 15377585000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2043061500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13333189000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 15377585000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 4998 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2671 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7669 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 685561 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 685561 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1667726 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1667726 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2814 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2814 # number of UpgradeReq accesses(hits+misses)
976,996c991,1011
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296002 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296002 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1698494 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1698494 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 524309 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 524309 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5122 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 2745 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1698494 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 820311 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2526672 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5122 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 2745 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1698494 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 820311 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2526672 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001562 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000729 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.001271 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.007273 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.007273 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 295923 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 295923 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700505 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1700505 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525966 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 525966 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 4998 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2671 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1700505 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530063 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 4998 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2671 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1700505 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530063 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001401 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000749 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001174 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006752 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006752 # miss rate for UpgradeReq accesses
999,1002c1014,1017
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436872 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.436872 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010607 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.431842 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.431842 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010555 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010555 # miss rate for ReadCleanReq accesses
1005,1019c1020,1034
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001562 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000729 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.172391 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.063103 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001562 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000729 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.172391 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.063103 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103687.500000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 99750 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29050 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29050 # average UpgradeReq miss latency
---
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001401 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000749 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010555 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.170253 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.062404 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001401 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000749 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010555 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.170253 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.062404 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164928.571429 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 148277.777778 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29236.842105 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29236.842105 # average UpgradeReq miss latency
1022,1037c1037,1052
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77844.557863 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77844.557863 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81264.459369 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81264.459369 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83668.237044 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83668.237044 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78674.291269 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78674.291269 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92462.928039 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92462.928039 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 113832.265433 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 113832.265433 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125003.419296 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125003.419296 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 97396.760954 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 97396.760954 # average overall miss latency
1044,1046c1059,1061
< system.cpu.l2cache.writebacks::writebacks 82853 # number of writebacks
< system.cpu.l2cache.writebacks::total 82853 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 8 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 81484 # number of writebacks
> system.cpu.l2cache.writebacks::total 81484 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
1048,1050c1063,1065
< system.cpu.l2cache.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses
1053,1059c1068,1074
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129315 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 129315 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 18016 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 18016 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12099 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12099 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 8 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127792 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 127792 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17948 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17948 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12137 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12137 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
1061,1064c1076,1079
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 18016 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 141414 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 159440 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 8 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 17948 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 139929 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 157886 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
1066,1068c1081,1083
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 18016 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 141414 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 159440 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 17948 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 139929 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 157886 # number of overall MSHR misses
1077,1081c1092,1096
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 749500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 148000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 897500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 381000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 381000 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 365500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 365500 # number of UpgradeReq MSHR miss cycles
1084,1110c1099,1125
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8773319000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8773319000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1283900500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1283900500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 891312000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 891312000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 749500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 148000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1283900500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9664631000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10949429000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 749500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 148000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1283900500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9664631000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10949429000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 574512000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5891860500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6466372500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 574512000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5891860500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6466372500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001271 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.007273 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.007273 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10538102500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10538102500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1863581500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1863581500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1395796500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1395796500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1863581500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11933899000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 13798725000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1863581500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11933899000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 13798725000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895497500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527925500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895497500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527925500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001174 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006752 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006752 # mshr miss rate for UpgradeReq accesses
1113,1116c1128,1131
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436872 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436872 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010607 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.431842 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.431842 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010555 # mshr miss rate for ReadCleanReq accesses
1119,1133c1134,1148
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.063103 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.063103 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 89750 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19050 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19050 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.062404 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.062404 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105 # average UpgradeReq mshr miss latency
1136,1162c1151,1177
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 5058492 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539687 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38280 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 5065968 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543576 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 219 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 219 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1164,1166c1179,1181
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 67163 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2290209 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 67217 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2293895 # Transaction distribution
1169,1172c1184,1187
< system.cpu.toL2Bus.trans_dist::WritebackDirty 766799 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1698000 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 142435 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2750 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 767045 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1700003 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 142341 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2814 # Transaction distribution
1174,1194c1189,1209
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2752 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296002 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296002 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1698518 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 524530 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 4455 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5113056 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2583569 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11960 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22910 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7731495 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217411704 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96469597 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10980 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20488 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 313912769 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 113519 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 5394688 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 2710473 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.021286 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.144336 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 295923 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 295923 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700521 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 526163 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119073 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2588406 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11887 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22839 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7742205 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217668600 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96672157 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10684 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 19992 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 314371433 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 112178 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 5305776 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 2712615 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.021718 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.145761 # Request fanout histogram
1196,1197c1211,1212
< system.cpu.toL2Bus.snoop_fanout::0 2652778 97.87% 97.87% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 57695 2.13% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2653703 97.83% 97.83% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 58912 2.17% 100.00% # Request fanout histogram
1202,1203c1217,1218
< system.cpu.toL2Bus.snoop_fanout::total 2710473 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4962792000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2712615 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4970051500 # Layer occupancy (ticks)
1205c1220
< system.cpu.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 347876 # Layer occupancy (ticks)
1207c1222
< system.cpu.toL2Bus.respLayer0.occupancy 2556799000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2559803500 # Layer occupancy (ticks)
1209c1224
< system.cpu.toL2Bus.respLayer1.occupancy 1276777495 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1279174000 # Layer occupancy (ticks)
1211c1226
< system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
1213c1228
< system.cpu.toL2Bus.respLayer3.occupancy 17788000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 17841000 # Layer occupancy (ticks)
1215,1217c1230,1232
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 30159 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30159 # Transaction distribution
1240,1242c1255,1257
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes)
1263,1266c1278,1281
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks)
1270c1285
< system.iobus.reqLayer2.occupancy 338500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
1276c1291
< system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
1278c1293
< system.iobus.reqLayer8.occupancy 642000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks)
1300c1315
< system.iobus.reqLayer23.occupancy 6273000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6292000 # Layer occupancy (ticks)
1304c1319
< system.iobus.reqLayer25.occupancy 187671849 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187581870 # Layer occupancy (ticks)
1308c1323
< system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks)
1310,1312c1325,1327
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 36424 # number of replacements
< system.iocache.tags.tagsinuse 1.078594 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 36400 # number of replacements
> system.iocache.tags.tagsinuse 1.079755 # Cycle average of tags in use
1314c1329
< system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks.
1316,1319c1331,1334
< system.iocache.tags.warmup_cycle 309373303000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.078594 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.067412 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.067412 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 310620847000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.079755 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.067485 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.067485 # Average percentage of cache occupancy
1323,1327c1338,1342
< system.iocache.tags.tag_accesses 328122 # Number of tag accesses
< system.iocache.tags.data_accesses 328122 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 327906 # Number of tag accesses
> system.iocache.tags.data_accesses 327906 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 210 # number of ReadReq misses
1330,1343c1345,1358
< system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
< system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 36458 # number of overall misses
< system.iocache.overall_misses::total 36458 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4278807472 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4278807472 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4307704849 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4307704849 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4307704849 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4307704849 # number of overall miss cycles
< system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36434 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36434 # number of overall misses
> system.iocache.overall_misses::total 36434 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4367688494 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4367688494 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4401754870 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4401754870 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4401754870 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4401754870 # number of overall miss cycles
> system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses)
1346,1349c1361,1364
< system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses
1358,1365c1373,1380
< system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 118155.270421 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 118155.270421 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 120814.482901 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 120814.482901 # average overall miss latency
1374,1375c1389,1390
< system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses
1378,1389c1393,1404
< system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465502723 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2465502723 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2482700100 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2482700100 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2482700100 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2482700100 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2554457612 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2554457612 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2578023988 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2578023988 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2578023988 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2578023988 # number of overall MSHR miss cycles
1398,1408c1413,1423
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 321817 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 130498 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 318841 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 128997 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1412c1427
< system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
1414c1429
< system.membus.trans_dist::ReadResp 70519 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 70464 # Transaction distribution
1417,1418c1432,1433
< system.membus.trans_dist::WritebackDirty 119043 # Transaction distribution
< system.membus.trans_dist::CleanEvict 6845 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 117674 # Transaction distribution
> system.membus.trans_dist::CleanEvict 6761 # Transaction distribution
1422,1424c1437,1439
< system.membus.trans_dist::ReadExReq 129207 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129207 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 30359 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 127683 # Transaction distribution
> system.membus.trans_dist::ReadExResp 127683 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 30304 # Transaction distribution
1429,1433c1444,1448
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 435887 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543479 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 616376 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431348 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 538940 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 611789 # Packet count per connected master and slave (bytes)
1437,1438c1452,1453
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15537980 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15701333 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15350844 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15514197 # Cumulative packet size per connected master and slave (bytes)
1441,1446c1456,1461
< system.membus.pkt_size::total 18018453 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 498 # Total snoops (count)
< system.membus.snoopTraffic 31744 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 263669 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.018793 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.135792 # Request fanout histogram
---
> system.membus.pkt_size::total 17831317 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 474 # Total snoops (count)
> system.membus.snoopTraffic 30208 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 262090 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.018417 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.134455 # Request fanout histogram
1448,1449c1463,1464
< system.membus.snoop_fanout::0 258714 98.12% 98.12% # Request fanout histogram
< system.membus.snoop_fanout::1 4955 1.88% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 257263 98.16% 98.16% # Request fanout histogram
> system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram
1454,1455c1469,1470
< system.membus.snoop_fanout::total 263669 # Request fanout histogram
< system.membus.reqLayer0.occupancy 90449000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 262090 # Request fanout histogram
> system.membus.reqLayer0.occupancy 90471500 # Layer occupancy (ticks)
1459c1474
< system.membus.reqLayer2.occupancy 1734500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1726500 # Layer occupancy (ticks)
1461c1476
< system.membus.reqLayer5.occupancy 828323280 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 819732726 # Layer occupancy (ticks)
1463c1478
< system.membus.respLayer2.occupancy 954014500 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 945419750 # Layer occupancy (ticks)
1465c1480
< system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1085624 # Layer occupancy (ticks)
1467,1473c1482,1488
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
1480,1481c1495,1496
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
1513,1519c1528,1534
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
1524,1535c1539,1550
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states