7,13c7,13
< host_inst_rate 581636 # Simulator instruction rate (inst/s)
< host_op_rate 701272 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 15048595995 # Simulator tick rate (ticks/s)
< host_mem_usage 573724 # Number of bytes of host memory used
< host_seconds 193.35 # Real time elapsed on the host
< sim_insts 112457033 # Number of instructions simulated
< sim_ops 135588117 # Number of ops (including micro ops) simulated
---
> host_inst_rate 495886 # Simulator instruction rate (inst/s)
> host_op_rate 597884 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 12830006266 # Simulator tick rate (ticks/s)
> host_mem_usage 573732 # Number of bytes of host memory used
> host_seconds 226.78 # Real time elapsed on the host
> sim_insts 112457035 # Number of instructions simulated
> sim_ops 135588119 # Number of ops (including micro ops) simulated
264,265c264,265
< system.physmem.totQLat 1624802000 # Total ticks spent queuing
< system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 1624800000 # Total ticks spent queuing
> system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM
267c267
< system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst
269c269
< system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst
305,307c305,307
< system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ)
309c309
< system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states
312c312
< system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states
392c392
< system.cpu.dtb.read_hits 24520655 # DTB read hits
---
> system.cpu.dtb.read_hits 24520656 # DTB read hits
394c394
< system.cpu.dtb.write_hits 19606816 # DTB write hits
---
> system.cpu.dtb.write_hits 19606817 # DTB write hits
405,406c405,406
< system.cpu.dtb.read_accesses 24528779 # DTB read accesses
< system.cpu.dtb.write_accesses 19608238 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24528780 # DTB read accesses
> system.cpu.dtb.write_accesses 19608239 # DTB write accesses
408c408
< system.cpu.dtb.hits 44127471 # DTB hits
---
> system.cpu.dtb.hits 44127473 # DTB hits
410c410
< system.cpu.dtb.accesses 44137017 # DTB accesses
---
> system.cpu.dtb.accesses 44137019 # DTB accesses
494,495c494,495
< system.cpu.committedInsts 112457033 # Number of instructions committed
< system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed
---
> system.cpu.committedInsts 112457035 # Number of instructions committed
> system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed
502,503c502,503
< system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 218063466 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written
506c506
< system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read
---
> system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read
553c553
< system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks.
555c555
< system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks.
566,571c566,571
< system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits
578,581c578,581
< system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits
< system.cpu.dcache.overall_hits::total 42329995 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits
> system.cpu.dcache.overall_hits::total 42329997 # number of overall hits
608,611c608,611
< system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses)
618,621c618,621
< system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses
763,768c763,768
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles
781,786c781,786
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency
805,810c805,810
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles
821,826c821,826
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency
917,918c917,918
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles
923c923
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles
925c925
< system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles
928c928
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles
930c930
< system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles
990,991c990,991
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency
996c996
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency
998c998
< system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency
1001c1001
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency
1003c1003
< system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency
1052,1053c1052,1053
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171512500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171512500 # number of ReadCleanReq MSHR miss cycles
1058c1058
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles
1060c1060
< system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles
1063c1063
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles
1065c1065
< system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles
1104,1105c1104,1105
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency
1110c1110
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency
1112c1112
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency
1115c1115
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency
1117c1117
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency
< host_inst_rate 581636 # Simulator instruction rate (inst/s)
< host_op_rate 701272 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 15048595995 # Simulator tick rate (ticks/s)
< host_mem_usage 573724 # Number of bytes of host memory used
< host_seconds 193.35 # Real time elapsed on the host
< sim_insts 112457033 # Number of instructions simulated
< sim_ops 135588117 # Number of ops (including micro ops) simulated
---
> host_inst_rate 495886 # Simulator instruction rate (inst/s)
> host_op_rate 597884 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 12830006266 # Simulator tick rate (ticks/s)
> host_mem_usage 573732 # Number of bytes of host memory used
> host_seconds 226.78 # Real time elapsed on the host
> sim_insts 112457035 # Number of instructions simulated
> sim_ops 135588119 # Number of ops (including micro ops) simulated
264,265c264,265
< system.physmem.totQLat 1624802000 # Total ticks spent queuing
< system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 1624800000 # Total ticks spent queuing
> system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM
267c267
< system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst
269c269
< system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst
305,307c305,307
< system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ)
309c309
< system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states
312c312
< system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states
392c392
< system.cpu.dtb.read_hits 24520655 # DTB read hits
---
> system.cpu.dtb.read_hits 24520656 # DTB read hits
394c394
< system.cpu.dtb.write_hits 19606816 # DTB write hits
---
> system.cpu.dtb.write_hits 19606817 # DTB write hits
405,406c405,406
< system.cpu.dtb.read_accesses 24528779 # DTB read accesses
< system.cpu.dtb.write_accesses 19608238 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24528780 # DTB read accesses
> system.cpu.dtb.write_accesses 19608239 # DTB write accesses
408c408
< system.cpu.dtb.hits 44127471 # DTB hits
---
> system.cpu.dtb.hits 44127473 # DTB hits
410c410
< system.cpu.dtb.accesses 44137017 # DTB accesses
---
> system.cpu.dtb.accesses 44137019 # DTB accesses
494,495c494,495
< system.cpu.committedInsts 112457033 # Number of instructions committed
< system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed
---
> system.cpu.committedInsts 112457035 # Number of instructions committed
> system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed
502,503c502,503
< system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 218063466 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written
506c506
< system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read
---
> system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read
553c553
< system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks.
555c555
< system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks.
566,571c566,571
< system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits
578,581c578,581
< system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits
< system.cpu.dcache.overall_hits::total 42329995 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits
> system.cpu.dcache.overall_hits::total 42329997 # number of overall hits
608,611c608,611
< system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses)
618,621c618,621
< system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses
763,768c763,768
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles
781,786c781,786
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency
805,810c805,810
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles
821,826c821,826
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency
917,918c917,918
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles
923c923
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles
925c925
< system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles
928c928
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles
930c930
< system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles
990,991c990,991
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency
996c996
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency
998c998
< system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency
1001c1001
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency
1003c1003
< system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency
1052,1053c1052,1053
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171512500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171512500 # number of ReadCleanReq MSHR miss cycles
1058c1058
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles
1060c1060
< system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles
1063c1063
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles
1065c1065
< system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles
1104,1105c1104,1105
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency
1110c1110
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency
1112c1112
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency
1115c1115
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency
1117c1117
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency