7,11c7,11
< host_inst_rate 929184 # Simulator instruction rate (inst/s)
< host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 24040663881 # Simulator tick rate (ticks/s)
< host_mem_usage 581600 # Number of bytes of host memory used
< host_seconds 121.03 # Real time elapsed on the host
---
> host_inst_rate 812558 # Simulator instruction rate (inst/s)
> host_op_rate 979692 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 21023218607 # Simulator tick rate (ticks/s)
> host_mem_usage 578440 # Number of bytes of host memory used
> host_seconds 138.40 # Real time elapsed on the host
654,655d653
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
702,705c700,701
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278149500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278149500 # number of overall MSHR uncacheable cycles
736,740c732,733
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency
800,801d792
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
840d830
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1020,1021d1009
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1081,1082d1068
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles
1084,1085c1070,1071
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles
1135,1136d1120
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency
1138,1140c1122,1123
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency
1308,1311c1291,1294
< system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
< system.iocache.demand_misses::total 228 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 228 # number of overall misses
< system.iocache.overall_misses::total 228 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36452 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36452 # number of overall misses
> system.iocache.overall_misses::total 36452 # number of overall misses
1316,1319c1299,1302
< system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4577313527 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4577313527 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4577313527 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4577313527 # number of overall miss cycles
1324,1327c1307,1310
< system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses
1340,1343c1323,1326
< system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125570.984500 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125570.984500 # average overall miss latency
1350,1351d1332
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1358,1361c1339,1342
< system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses
1366,1369c1347,1350
< system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2753302003 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2753302003 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2753302003 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2753302003 # number of overall MSHR miss cycles
1382,1386c1363,1366
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency
< host_inst_rate 929184 # Simulator instruction rate (inst/s)
< host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 24040663881 # Simulator tick rate (ticks/s)
< host_mem_usage 581600 # Number of bytes of host memory used
< host_seconds 121.03 # Real time elapsed on the host
---
> host_inst_rate 812558 # Simulator instruction rate (inst/s)
> host_op_rate 979692 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 21023218607 # Simulator tick rate (ticks/s)
> host_mem_usage 578440 # Number of bytes of host memory used
> host_seconds 138.40 # Real time elapsed on the host
654,655d653
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
702,705c700,701
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278149500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278149500 # number of overall MSHR uncacheable cycles
736,740c732,733
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency
800,801d792
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
840d830
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1020,1021d1009
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1081,1082d1068
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles
1084,1085c1070,1071
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles
1135,1136d1120
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency
1138,1140c1122,1123
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency
1308,1311c1291,1294
< system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
< system.iocache.demand_misses::total 228 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 228 # number of overall misses
< system.iocache.overall_misses::total 228 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36452 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36452 # number of overall misses
> system.iocache.overall_misses::total 36452 # number of overall misses
1316,1319c1299,1302
< system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4577313527 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4577313527 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4577313527 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4577313527 # number of overall miss cycles
1324,1327c1307,1310
< system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses
1340,1343c1323,1326
< system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125570.984500 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125570.984500 # average overall miss latency
1350,1351d1332
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1358,1361c1339,1342
< system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses
1366,1369c1347,1350
< system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2753302003 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2753302003 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2753302003 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2753302003 # number of overall MSHR miss cycles
1382,1386c1363,1366
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency