3,5c3,5
< sim_seconds 2.909596 # Number of seconds simulated
< sim_ticks 2909596171500 # Number of ticks simulated
< final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.909587 # Number of seconds simulated
> sim_ticks 2909586837500 # Number of ticks simulated
> final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 322522 # Simulator instruction rate (inst/s)
< host_op_rate 388861 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 8344730622 # Simulator tick rate (ticks/s)
< host_mem_usage 560756 # Number of bytes of host memory used
< host_seconds 348.67 # Real time elapsed on the host
< sim_insts 112455206 # Number of instructions simulated
< sim_ops 135585876 # Number of ops (including micro ops) simulated
---
> host_inst_rate 929184 # Simulator instruction rate (inst/s)
> host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 24040663881 # Simulator tick rate (ticks/s)
> host_mem_usage 581600 # Number of bytes of host memory used
> host_seconds 121.03 # Real time elapsed on the host
> sim_insts 112457033 # Number of instructions simulated
> sim_ops 135588117 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 8901796 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory
29,30c29,30
< system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 139610 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 139611 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 166628 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory
38,39c38,39
< system.physmem.bw_read::cpu.inst 407756 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3059461 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 407801 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3059493 # Total read bandwidth from this memory (bytes/s)
41,44c41,44
< system.physmem.bw_read::total 3467744 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 407756 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 407756 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2581758 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3467822 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 407801 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 407801 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2581810 # Write bandwidth from this memory (bytes/s)
46,47c46,47
< system.physmem.bw_write::total 2587780 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2581758 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2587833 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2581810 # Total bandwidth to/from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_total::cpu.inst 407756 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3065484 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 407801 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3065516 # Total bandwidth to/from this memory (bytes/s)
53,63c53,63
< system.physmem.bw_total::total 6055525 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 166625 # Number of read requests accepted
< system.physmem.writeReqs 121754 # Number of write requests accepted
< system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7541952 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 6055654 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 166628 # Number of read requests accepted
> system.physmem.writeReqs 121756 # Number of write requests accepted
> system.physmem.readBursts 166628 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10657408 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7542016 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10089928 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue
65c65
< system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
69c69
< system.physmem.perBankRdBursts::3 10661 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 10660 # Per bank write bursts
71,73c71,73
< system.physmem.perBankRdBursts::5 9659 # Per bank write bursts
< system.physmem.perBankRdBursts::6 9663 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10485 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 9664 # Per bank write bursts
> system.physmem.perBankRdBursts::6 9666 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10487 # Per bank write bursts
78c78
< system.physmem.perBankRdBursts::12 9817 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 9822 # Per bank write bursts
80c80
< system.physmem.perBankRdBursts::14 9722 # Per bank write bursts
---
> system.physmem.perBankRdBursts::14 9723 # Per bank write bursts
89c89
< system.physmem.perBankWrBursts::7 7659 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 7661 # Per bank write bursts
94c94
< system.physmem.perBankWrBursts::12 7534 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 7533 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
< system.physmem.totGap 2909595814500 # Total gap between requests
---
> system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
> system.physmem.totGap 2909586480500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 157053 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 157056 # Read request sizes (log2)
114,117c114,117
< system.physmem.writePktSize::6 117373 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 165628 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 117375 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 165639 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 2125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2431 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5974 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5923 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6296 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6381 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7297 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7756 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7889 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 7774 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9310 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6775 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6274 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5950 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 54 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 58778 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 309.611351 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 182.749688 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 329.493771 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21450 36.49% 36.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14701 25.01% 61.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6086 10.35% 71.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3214 5.47% 77.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2550 4.34% 81.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1476 2.51% 84.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1054 1.79% 85.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1089 1.85% 87.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7158 12.18% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 58778 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5758 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.915596 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 590.311059 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 5757 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1976 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6995 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5904 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6826 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6035 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5867 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6713 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6456 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6988 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7862 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6789 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8357 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6865 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6620 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6747 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1220 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 295 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 76 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 58742 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 309.818528 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 182.858167 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.750191 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21399 36.43% 36.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14737 25.09% 61.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6061 10.32% 71.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3228 5.50% 77.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2535 4.32% 81.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1458 2.48% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1057 1.80% 85.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1079 1.84% 87.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7188 12.24% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 58742 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5615 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 29.654497 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 597.763680 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5614 99.98% 99.98% # Reads before turning the bus around for writes
230,270c230,267
< system.physmem.rdPerTurnAround::total 5758 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5758 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.465960 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.711564 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 13.116644 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4961 86.16% 86.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 87 1.51% 87.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 33 0.57% 88.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 172 2.99% 91.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 23 0.40% 91.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 160 2.78% 94.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 50 0.87% 95.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 6 0.10% 95.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 7 0.12% 95.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 22 0.38% 95.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 2 0.03% 95.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 6 0.10% 96.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 163 2.83% 98.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.05% 98.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 10 0.17% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 20 0.35% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.02% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.02% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.03% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 16 0.28% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5758 # Writes before turning the bus around for reads
< system.physmem.totQLat 1616458000 # Total ticks spent queuing
< system.physmem.totMemAccLat 4738464250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9708.05 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5615 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5615 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.987355 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.791633 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 15.100649 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4949 88.14% 88.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 78 1.39% 89.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 32 0.57% 90.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 46 0.82% 90.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 24 0.43% 91.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 20 0.36% 91.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 46 0.82% 92.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 4 0.07% 92.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 153 2.72% 95.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 11 0.20% 95.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 7 0.12% 95.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 13 0.23% 95.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 63 1.12% 96.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 5 0.09% 97.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 5 0.09% 97.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 26 0.46% 97.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 103 1.83% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.04% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 1 0.02% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 7 0.12% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads
> system.physmem.totQLat 1624802000 # Total ticks spent queuing
> system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst
272c269
< system.physmem.avgMemAccLat 28458.05 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst
283,299c280,296
< system.physmem.readRowHits 136072 # Number of row buffer hits during reads
< system.physmem.writeRowHits 89499 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes
< system.physmem.avgGap 10089485.76 # Average gap between requests
< system.physmem.pageHitRate 79.32 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 230958000 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 126018750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 702124800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 90366604425 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1666484751750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1948343566605 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.628332 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2772164122000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 97157580000 # Time in different power states
---
> system.physmem.readRowHits 136095 # Number of row buffer hits during reads
> system.physmem.writeRowHits 89528 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 81.73 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes
> system.physmem.avgGap 10089278.46 # Average gap between requests
> system.physmem.pageHitRate 79.34 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 230829480 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 125948625 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 702195000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 90325761075 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1666515907500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1948333254960 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.626580 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2772215900000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 97157320000 # Time in different power states
301c298
< system.physmem_0.memoryStateTime::ACT 40267816750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 40208512500 # Time in different power states
303,313c300,310
< system.physmem_1.actEnergy 213403680 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 116440500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 596622000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 370740240 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 88072375230 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1668497233500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1947907041630 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.478302 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2775541834250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 97157580000 # Time in different power states
---
> system.physmem_1.actEnergy 213260040 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 116362125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.477277 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states
315c312
< system.physmem_1.memoryStateTime::ACT 36896609250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states
373,375c370,372
< system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 8540.848722 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::mean 13159.035492 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 10920.963738 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 8541.710442 # Table walker service (enqueue to completion) latency
395c392
< system.cpu.dtb.read_hits 24520178 # DTB read hits
---
> system.cpu.dtb.read_hits 24520655 # DTB read hits
397c394
< system.cpu.dtb.write_hits 19606457 # DTB write hits
---
> system.cpu.dtb.write_hits 19606816 # DTB write hits
408,409c405,406
< system.cpu.dtb.read_accesses 24528302 # DTB read accesses
< system.cpu.dtb.write_accesses 19607879 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24528779 # DTB read accesses
> system.cpu.dtb.write_accesses 19608238 # DTB write accesses
411c408
< system.cpu.dtb.hits 44126635 # DTB hits
---
> system.cpu.dtb.hits 44127471 # DTB hits
413c410
< system.cpu.dtb.accesses 44136181 # DTB accesses
---
> system.cpu.dtb.accesses 44137017 # DTB accesses
471c468
< system.cpu.itb.inst_hits 115552414 # ITB inst hits
---
> system.cpu.itb.inst_hits 115554258 # ITB inst hits
488,489c485,486
< system.cpu.itb.inst_accesses 115557177 # ITB inst accesses
< system.cpu.itb.hits 115552414 # DTB hits
---
> system.cpu.itb.inst_accesses 115559021 # ITB inst accesses
> system.cpu.itb.hits 115554258 # DTB hits
491,492c488,489
< system.cpu.itb.accesses 115557177 # DTB accesses
< system.cpu.numCycles 5819192343 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 115559021 # DTB accesses
> system.cpu.numCycles 5819173675 # number of cpu cycles simulated
497,499c494,496
< system.cpu.committedInsts 112455206 # Number of instructions committed
< system.cpu.committedOps 135585876 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119891340 # Number of integer alu accesses
---
> system.cpu.committedInsts 112457033 # Number of instructions committed
> system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses
501,503c498,500
< system.cpu.num_func_calls 9892021 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 15230391 # number of instructions that are conditional controls
< system.cpu.num_int_insts 119891340 # number of integer instructions
---
> system.cpu.num_func_calls 9892146 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls
> system.cpu.num_int_insts 119893391 # number of integer instructions
505,506c502,503
< system.cpu.num_int_register_reads 218059811 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82644916 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written
509,518c506,515
< system.cpu.num_cc_register_reads 489735153 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51893214 # number of times the CC registers were written
< system.cpu.num_mem_refs 45407055 # number of memory refs
< system.cpu.num_load_insts 24842618 # Number of load instructions
< system.cpu.num_store_insts 20564437 # Number of store instructions
< system.cpu.num_idle_cycles 5379072985.844151 # Number of idle cycles
< system.cpu.num_busy_cycles 440119357.155849 # Number of busy cycles
< system.cpu.not_idle_fraction 0.075632 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.924368 # Percentage of idle cycles
< system.cpu.Branches 25916470 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written
> system.cpu.num_mem_refs 45407924 # number of memory refs
> system.cpu.num_load_insts 24843119 # Number of load instructions
> system.cpu.num_store_insts 20564805 # Number of store instructions
> system.cpu.num_idle_cycles 5379054575.844151 # Number of idle cycles
> system.cpu.num_busy_cycles 440119099.155849 # Number of busy cycles
> system.cpu.not_idle_fraction 0.075633 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.924367 # Percentage of idle cycles
> system.cpu.Branches 25916787 # Number of branches fetched
520,521c517,518
< system.cpu.op_class::IntAlu 93173703 67.17% 67.18% # Class of executed instruction
< system.cpu.op_class::IntMult 114388 0.08% 67.26% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93175095 67.17% 67.18% # Class of executed instruction
> system.cpu.op_class::IntMult 114406 0.08% 67.26% # Class of executed instruction
549,550c546,547
< system.cpu.op_class::MemRead 24842618 17.91% 85.17% # Class of executed instruction
< system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction
> system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction
553,558c550,555
< system.cpu.op_class::total 138705936 # Class of executed instruction
< system.cpu.dcache.tags.replacements 819217 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 43235406 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819729 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 52.743536 # Average number of references to valid blocks.
---
> system.cpu.op_class::total 138708215 # Class of executed instruction
> system.cpu.dcache.tags.replacements 819223 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks.
560c557
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor
569,592c566,589
< system.cpu.dcache.tags.tag_accesses 177109321 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177109321 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23112521 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23112521 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18823879 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18823879 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 392783 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 392783 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443242 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443242 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460216 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460216 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41936400 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41936400 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42329183 # number of overall hits
< system.cpu.dcache.overall_hits::total 42329183 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 399911 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 399911 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 298704 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 298704 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 118377 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 118377 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits
> system.cpu.dcache.overall_hits::total 42329995 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 298709 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 118381 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 118381 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22756 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses
595,604c592,601
< system.cpu.dcache.demand_misses::cpu.data 698615 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 698615 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 816992 # number of overall misses
< system.cpu.dcache.overall_misses::total 816992 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6486417000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6486417000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 19109109000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 19109109000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294489000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 294489000 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 698621 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 698621 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 817002 # number of overall misses
> system.cpu.dcache.overall_misses::total 817002 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6488404500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6488404500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100944000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 19100944000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293896000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 293896000 # number of LoadLockedReq miss cycles
607,624c604,621
< system.cpu.dcache.demand_miss_latency::cpu.data 25595526000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 25595526000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 25595526000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 25595526000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23512432 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23512432 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511160 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511160 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465999 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465999 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460218 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460218 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42635015 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42635015 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43146175 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43146175 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses
629,632c626,629
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231585 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.231585 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048835 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048835 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231590 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.231590 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048832 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048832 # miss rate for LoadLockedReq accesses
639,644c636,641
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709 # average LoadLockedReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16224.580658 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16224.580658 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63944.989940 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63944.989940 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12915.099314 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12915.099314 # average LoadLockedReq miss latency
647,651c644,648
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 36637.527107 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31328.979966 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 36628.370032 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 36628.370032 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31321.035322 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked
653c650
< system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked
655c652
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
659,674c656,671
< system.cpu.dcache.writebacks::writebacks 683842 # number of writebacks
< system.cpu.dcache.writebacks::total 683842 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 930 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 930 # number of ReadReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14247 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14247 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 930 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 930 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 930 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 930 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398981 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 398981 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298704 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298704 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116321 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 116321 # number of SoftPFReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks
> system.cpu.dcache.writebacks::total 683846 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14246 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14246 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 929 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 929 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398983 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 398983 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298709 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298709 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116322 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 116322 # number of SoftPFReq MSHR misses
679,682c676,679
< system.cpu.dcache.demand_mshr_misses::cpu.data 697685 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 697685 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 814006 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 814006 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 697692 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 697692 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 814014 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 814014 # number of overall MSHR misses
689,694c686,691
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058107000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058107000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18810405000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 18810405000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1614233500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1614233500 # number of SoftPFReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058749500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058749500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18802235000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 18802235000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1616519000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1616519000 # number of SoftPFReq MSHR miss cycles
699,708c696,705
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24868512000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 24868512000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26482745500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26482745500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278172000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278172000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089977500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089977500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368149500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368149500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24860984500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 24860984500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles
713,714c710,711
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227563 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227563 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227562 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227562 # mshr miss rate for SoftPFReq accesses
723,728c720,725
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908 # average SoftPFReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15185.482840 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15185.482840 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62944.989940 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62944.989940 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13896.932652 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13896.932652 # average SoftPFReq mshr miss latency
733,742c730,739
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency
744,748c741,745
< system.cpu.icache.tags.replacements 1695565 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.436866 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 113856331 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1696077 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 67.129223 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 1695721 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks.
750c747
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.436866 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor
759,796c756,793
< system.cpu.icache.tags.tag_accesses 117248497 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 117248497 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 113856331 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 113856331 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 113856331 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 113856331 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 113856331 # number of overall hits
< system.cpu.icache.overall_hits::total 113856331 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1696083 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1696083 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1696083 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1696083 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1696083 # number of overall misses
< system.cpu.icache.overall_misses::total 1696083 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 24267960000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 24267960000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 24267960000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 24267960000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 24267960000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 24267960000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 115552414 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 115552414 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 115552414 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 115552414 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 115552414 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 115552414 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14308.238453 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14308.238453 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 117250497 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 117250497 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 113858019 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 113858019 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 113858019 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 113858019 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits
> system.cpu.icache.overall_hits::total 113858019 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1696239 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses
> system.cpu.icache.overall_misses::total 1696239 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 115554258 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 115554258 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 115554258 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014679 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency
805,812c802,809
< system.cpu.icache.writebacks::writebacks 1695565 # number of writebacks
< system.cpu.icache.writebacks::total 1695565 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696083 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1696083 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1696083 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1696083 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1696083 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1696083 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks
> system.cpu.icache.writebacks::total 1695721 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses
817,822c814,819
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22571877000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22571877000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22571877000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22571877000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22571877000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22571877000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles
827,838c824,835
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13308.238453 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13308.238453 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency
844,848c841,845
< system.cpu.l2cache.tags.replacements 87562 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64865.195753 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4544223 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 152797 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 29.740263 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 87565 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks.
850c847
< system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor
852,855c849,852
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012652 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.731977 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.980293 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.765940 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012649 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.721355 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.976923 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.765941 # Average percentage of cache occupancy
860c857
< system.cpu.l2cache.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy
867,868c864,865
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56201 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6851 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id
871,873c868,870
< system.cpu.l2cache.tags.tag_accesses 40509810 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 40509810 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7810 # number of ReadReq hits
---
> system.cpu.l2cache.tags.tag_accesses 40512344 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 40512344 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits
875,879c872,876
< system.cpu.l2cache.ReadReq_hits::total 11849 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 683842 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 683842 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1664795 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1664795 # number of WritebackClean hits
---
> system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 683846 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 683846 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1664945 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1664945 # number of WritebackClean hits
882,888c879,885
< system.cpu.l2cache.ReadExReq_hits::cpu.data 167026 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 167026 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678074 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1678074 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511640 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 511640 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 7810 # number of demand (read+write) hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 167031 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 167031 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678228 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1678228 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511642 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 511642 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 7807 # number of demand (read+write) hits
890,893c887,890
< system.cpu.l2cache.demand_hits::cpu.inst 1678074 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 678666 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2368589 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 7810 # number of overall hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1678228 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 678673 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2368747 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 7807 # number of overall hits
895,897c892,894
< system.cpu.l2cache.overall_hits::cpu.inst 1678074 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 678666 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2368589 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1678228 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 678673 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2368747 # number of overall hits
901,902c898,899
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2740 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2740 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2742 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2742 # number of UpgradeReq misses
905,910c902,907
< system.cpu.l2cache.ReadExReq_misses::cpu.data 128915 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 128915 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17976 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 17976 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 128913 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 128913 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12173 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 12173 # number of ReadSharedReq misses
913,915c910,912
< system.cpu.l2cache.demand_misses::cpu.inst 17976 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 141087 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 159072 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 141086 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 159073 # number of demand (read+write) misses
918,920c915,917
< system.cpu.l2cache.overall_misses::cpu.inst 17976 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 141087 # number of overall misses
< system.cpu.l2cache.overall_misses::total 159072 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 141086 # number of overall misses
> system.cpu.l2cache.overall_misses::total 159073 # number of overall misses
924,925c921,922
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1857500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles
928,933c925,930
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16383348000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 16383348000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2349142000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2349142000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1612524000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1612524000 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles
936,938c933,935
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2349142000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 17995872000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 20346237500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles
941,944c938,941
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2349142000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 17995872000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 20346237500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7817 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses)
946,952c943,949
< system.cpu.l2cache.ReadReq_accesses::total 11858 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 683842 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 683842 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1664795 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1664795 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2763 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 683846 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 683846 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1664945 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1664945 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses)
955,961c952,958
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 295941 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 295941 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696050 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1696050 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523812 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 523812 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7817 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 295944 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 295944 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696206 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1696206 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523815 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 523815 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7814 # number of demand (read+write) accesses
963,966c960,963
< system.cpu.l2cache.demand_accesses::cpu.inst 1696050 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819753 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2527661 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7817 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1696206 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819759 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2527820 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7814 # number of overall (read+write) accesses
968,971c965,968
< system.cpu.l2cache.overall_accesses::cpu.inst 1696050 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819753 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2527661 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000895 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1696206 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819759 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2527820 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses
974,975c971,972
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991676 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991682 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses
978,979c975,976
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435610 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.435610 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435599 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.435599 # miss rate for ReadExReq accesses
982,984c979,981
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023237 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023237 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000895 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023239 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023239 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses
987,989c984,986
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.172109 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.062932 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000895 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.172107 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.062929 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses
992,993c989,990
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.172109 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.062932 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.172107 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.062929 # miss rate for overall accesses
997,998c994,995
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 677.919708 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 677.919708 # average UpgradeReq miss latency
---
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency
1001,1006c998,1003
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127086.436799 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127086.436799 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130682.131731 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132478.146566 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency
1009,1011c1006,1008
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 127905.838237 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency
1014,1016c1011,1013
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency
1025,1026c1022,1023
< system.cpu.l2cache.writebacks::writebacks 81183 # number of writebacks
< system.cpu.l2cache.writebacks::total 81183 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks
> system.cpu.l2cache.writebacks::total 81185 # number of writebacks
1030,1031c1027,1028
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2740 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses
1034,1039c1031,1036
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128915 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 128915 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17976 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17976 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128913 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 128913 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12173 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12173 # number of ReadSharedReq MSHR misses
1042,1044c1039,1041
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 17976 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 141087 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 159072 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 141086 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 159073 # number of demand (read+write) MSHR misses
1047,1049c1044,1046
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 17976 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 141087 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 159072 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 141086 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 159073 # number of overall MSHR misses
1061,1062c1058,1059
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003500 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186544500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186544500 # number of UpgradeReq MSHR miss cycles
1065,1070c1062,1067
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15094198000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15094198000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2169382000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2169382000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1490804000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1490804000 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles
1073,1075c1070,1072
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2169382000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16585002000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 18755517500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16587120500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles
1078,1080c1075,1077
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2169382000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16585002000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 18755517500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles
1082,1085c1079,1082
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888826500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918592500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles
1087,1089c1084,1086
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661400500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691166500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses
1092,1093c1089,1090
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses
1096,1097c1093,1094
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435610 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435610 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435599 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435599 # mshr miss rate for ReadExReq accesses
1100,1102c1097,1099
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023237 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023237 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023239 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses
1105,1107c1102,1104
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses
1110,1111c1107,1108
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses
1115,1116c1112,1113
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711 # average UpgradeReq mshr miss latency
1119,1124c1116,1121
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency
1127,1129c1124,1126
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
1132,1134c1129,1131
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency
1136,1139c1133,1136
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435 # average WriteReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency
1141,1142c1138,1139
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency
1144,1146c1141,1143
< system.cpu.toL2Bus.snoop_filter.tot_requests 5052537 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536723 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1151c1148
< system.cpu.toL2Bus.trans_dist::ReadResp 2287321 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution
1154,1157c1151,1154
< system.cpu.toL2Bus.trans_dist::WritebackDirty 801217 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1664795 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 134627 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 801231 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1695721 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 141985 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution
1159,1163c1156,1160
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696083 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 524040 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 295944 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 295944 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696239 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 524043 # Transaction distribution
1165,1166c1162,1163
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074972 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574565 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5106210 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581942 # Packet count per connected master and slave (bytes)
1168,1171c1165,1168
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25654 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7688448 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215130168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96426845 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25651 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7727060 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217119416 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96427485 # Cumulative packet size per connected master and slave (bytes)
1173,1178c1170,1175
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31268 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 311604445 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 175875 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 2773837 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.020867 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.142939 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31256 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 313594321 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 175889 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 2774012 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.020868 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.142944 # Request fanout histogram
1180,1181c1177,1178
< system.cpu.toL2Bus.snoop_fanout::0 2715955 97.91% 97.91% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 57882 2.09% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2716123 97.91% 97.91% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 57889 2.09% 100.00% # Request fanout histogram
1186,1187c1183,1184
< system.cpu.toL2Bus.snoop_fanout::total 2773837 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4957294000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2774012 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4957617000 # Layer occupancy (ticks)
1189c1186
< system.cpu.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks)
1191c1188
< system.cpu.toL2Bus.respLayer0.occupancy 2553146500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2553380500 # Layer occupancy (ticks)
1193c1190
< system.cpu.toL2Bus.respLayer1.occupancy 1275944500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1275954500 # Layer occupancy (ticks)
1249c1246
< system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks)
1283c1280
< system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks)
1287c1284
< system.iobus.reqLayer25.occupancy 186221548 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187058527 # Layer occupancy (ticks)
1294c1291
< system.iocache.tags.tagsinuse 1.084130 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use
1298,1301c1295,1298
< system.iocache.tags.warmup_cycle 313812613000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.084130 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 313812610000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.084082 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.067755 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.067755 # Average percentage of cache occupancy
1315,1322c1312,1319
< system.iocache.ReadReq_miss_latency::realview.ide 28228376 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 28228376 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4717653172 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4717653172 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 28228376 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 28228376 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 28228376 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 28228376 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles
1339,1347c1336,1344
< system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 123808.666667 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 123808.666667 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 123808.666667 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 910 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1349c1346
< system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1351c1348
< system.iocache.avg_blocked_cycles::no_mshrs 11.234568 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1365,1372c1362,1369
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 16828376 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 16828376 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906453172 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2906453172 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 16828376 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 16828376 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 16828376 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 16828376 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles
1381,1388c1378,1385
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
1391c1388
< system.membus.trans_dist::ReadResp 70545 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 70548 # Transaction distribution
1394,1395c1391,1392
< system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution
< system.membus.trans_dist::CleanEvict 6392 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution
> system.membus.trans_dist::CleanEvict 6608 # Transaction distribution
1398c1395
< system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1401c1398
< system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution
---
> system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution
1403d1399
< system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
1407,1411c1403,1407
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438817 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546409 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 655303 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 434329 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 541921 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 614806 # Packet count per connected master and slave (bytes)
1415,1416c1411,1412
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302332 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465685 # Cumulative packet size per connected master and slave (bytes)
1419c1415
< system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 17782805 # Cumulative packet size per connected master and slave (bytes)
1421c1417
< system.membus.snoop_fanout::samples 389997 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 390011 # Request fanout histogram
1426c1422
< system.membus.snoop_fanout::1 389997 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 390011 100.00% 100.00% # Request fanout histogram
1431,1432c1427,1428
< system.membus.snoop_fanout::total 389997 # Request fanout histogram
< system.membus.reqLayer0.occupancy 90470000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 390011 # Request fanout histogram
> system.membus.reqLayer0.occupancy 90460500 # Layer occupancy (ticks)
1436c1432
< system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks)
1438c1434
< system.membus.reqLayer5.occupancy 823068661 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 823136860 # Layer occupancy (ticks)
1440c1436
< system.membus.respLayer2.occupancy 952238748 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 943248500 # Layer occupancy (ticks)
1442c1438
< system.membus.respLayer3.occupancy 64113741 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks)