3,5c3,5
< sim_seconds 2.902862 # Number of seconds simulated
< sim_ticks 2902861767000 # Number of ticks simulated
< final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.903548 # Number of seconds simulated
> sim_ticks 2903547931500 # Number of ticks simulated
> final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 747193 # Simulator instruction rate (inst/s)
< host_op_rate 900893 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 19275657141 # Simulator tick rate (ticks/s)
< host_mem_usage 615228 # Number of bytes of host memory used
< host_seconds 150.60 # Real time elapsed on the host
< sim_insts 112525269 # Number of instructions simulated
< sim_ops 135672104 # Number of ops (including micro ops) simulated
---
> host_inst_rate 732027 # Simulator instruction rate (inst/s)
> host_op_rate 882601 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 18897780106 # Simulator tick rate (ticks/s)
> host_mem_usage 614620 # Number of bytes of host memory used
> host_seconds 153.65 # Real time elapsed on the host
> sim_insts 112472279 # Number of instructions simulated
> sim_ops 135607130 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory
29,30c29,30
< system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory
38,39c38,39
< system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s)
41,47c41,47
< system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s)
53,97c53,97
< system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 168015 # Number of read requests accepted
< system.physmem.writeReqs 158980 # Number of write requests accepted
< system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 9689 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9230 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10198 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10267 # Per bank write bursts
< system.physmem.perBankRdBursts::4 18984 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10226 # Per bank write bursts
< system.physmem.perBankRdBursts::6 10551 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10350 # Per bank write bursts
< system.physmem.perBankRdBursts::8 9702 # Per bank write bursts
< system.physmem.perBankRdBursts::9 9930 # Per bank write bursts
< system.physmem.perBankRdBursts::10 9908 # Per bank write bursts
< system.physmem.perBankRdBursts::11 8848 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9929 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10408 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9925 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9750 # Per bank write bursts
< system.physmem.perBankWrBursts::0 9389 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8975 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10251 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9953 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9418 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9499 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9770 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9764 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9682 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9836 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9791 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9091 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9681 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9852 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9372 # Per bank write bursts
< system.physmem.perBankWrBursts::15 9026 # Per bank write bursts
---
> system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 168876 # Number of read requests accepted
> system.physmem.writeReqs 160010 # Number of write requests accepted
> system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10030 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9665 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10302 # Per bank write bursts
> system.physmem.perBankRdBursts::3 9920 # Per bank write bursts
> system.physmem.perBankRdBursts::4 18863 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
> system.physmem.perBankRdBursts::6 10296 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10601 # Per bank write bursts
> system.physmem.perBankRdBursts::8 9928 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10198 # Per bank write bursts
> system.physmem.perBankRdBursts::10 9956 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9036 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9857 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10481 # Per bank write bursts
> system.physmem.perBankRdBursts::14 9974 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9528 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8313 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8253 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9067 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8494 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8419 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8394 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8676 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8975 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8824 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8984 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8586 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8136 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8548 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8715 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8203 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7843 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
< system.physmem.totGap 2902861390500 # Total gap between requests
---
> system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
> system.physmem.totGap 2903547607000 # Total gap between requests
107c107
< system.physmem.readPktSize::6 158443 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 159304 # Read request sizes (log2)
114,117c114,117
< system.physmem.writePktSize::6 154599 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 155629 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5390 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5752 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5724 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5981 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7843 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6318 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8094 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6968 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6571 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6360 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1258 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2331 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1806 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1887 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2576 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1933 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1944 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1580 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1707 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1310 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 998 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 760 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 309 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 274 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 60277 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 324.004977 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 188.393020 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 342.651376 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21725 36.04% 36.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14933 24.77% 60.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5631 9.34% 70.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2561 4.25% 79.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1497 2.48% 82.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1055 1.75% 84.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5494 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 577.316613 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5492 99.96% 99.96% # Reads before turning the bus around for writes
231,288c231,273
< system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads
< system.physmem.totQLat 1487834250 # Total ticks spent queuing
< system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5494 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5494 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 24.832545 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.556239 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 46.623010 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 5170 94.10% 94.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 87 1.58% 95.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 17 0.31% 96.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 12 0.22% 96.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 19 0.35% 96.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 28 0.51% 97.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 22 0.40% 97.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 14 0.25% 97.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 9 0.16% 97.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 4 0.07% 97.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 29 0.53% 98.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 12 0.22% 98.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 6 0.11% 98.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 2 0.04% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 2 0.04% 98.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 1 0.02% 98.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 2 0.04% 98.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 7 0.13% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 8 0.15% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 4 0.07% 99.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 4 0.07% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 10 0.18% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 2 0.04% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 3 0.05% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::400-415 1 0.02% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads
> system.physmem.totQLat 1499821694 # Total ticks spent queuing
> system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst
290,294c275,279
< system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s
296c281
< system.physmem.busUtil 0.06 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.05 # Data bus utilization in percentage
298c283
< system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
---
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
300,317c285,302
< system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing
< system.physmem.readRowHits 138089 # Number of row buffer hits during reads
< system.physmem.writeRowHits 122193 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes
< system.physmem.avgGap 8877387.70 # Average gap between requests
< system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.522458 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states
---
> system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing
> system.physmem.readRowHits 138826 # Number of row buffer hits during reads
> system.physmem.writeRowHits 106054 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes
> system.physmem.avgGap 8828431.76 # Average gap between requests
> system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.525264 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states
> system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states
319c304
< system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states
321,331c306,316
< system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.435479 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states
---
> system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.425095 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states
> system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states
333c318
< system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states
383,406c368,391
< system.cpu.dtb.walker.walks 9552 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walks 9545 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst
408,409c393,394
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst
411,412c396,397
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst
415,418c400,403
< system.cpu.dtb.read_hits 24537663 # DTB read hits
< system.cpu.dtb.read_misses 8142 # DTB read misses
< system.cpu.dtb.write_hits 19618927 # DTB write hits
< system.cpu.dtb.write_misses 1410 # DTB write misses
---
> system.cpu.dtb.read_hits 24524755 # DTB read hits
> system.cpu.dtb.read_misses 8132 # DTB read misses
> system.cpu.dtb.write_hits 19610055 # DTB write hits
> system.cpu.dtb.write_misses 1413 # DTB write misses
423c408
< system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB
425c410
< system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch
428,429c413,414
< system.cpu.dtb.read_accesses 24545805 # DTB read accesses
< system.cpu.dtb.write_accesses 19620337 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24532887 # DTB read accesses
> system.cpu.dtb.write_accesses 19611468 # DTB write accesses
431,433c416,418
< system.cpu.dtb.hits 44156590 # DTB hits
< system.cpu.dtb.misses 9552 # DTB misses
< system.cpu.dtb.accesses 44166142 # DTB accesses
---
> system.cpu.dtb.hits 44134810 # DTB hits
> system.cpu.dtb.misses 9545 # DTB misses
> system.cpu.dtb.accesses 44144355 # DTB accesses
471,478c456,463
< system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
480,482c465,467
< system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution
---
> system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution
493c478
< system.cpu.itb.inst_hits 115624412 # ITB inst hits
---
> system.cpu.itb.inst_hits 115569545 # ITB inst hits
510,511c495,496
< system.cpu.itb.inst_accesses 115629174 # ITB inst accesses
< system.cpu.itb.hits 115624412 # DTB hits
---
> system.cpu.itb.inst_accesses 115574307 # ITB inst accesses
> system.cpu.itb.hits 115569545 # DTB hits
513,514c498,499
< system.cpu.itb.accesses 115629174 # DTB accesses
< system.cpu.numCycles 5805723534 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 115574307 # DTB accesses
> system.cpu.numCycles 5807095863 # number of cpu cycles simulated
517,527c502,512
< system.cpu.committedInsts 112525269 # Number of instructions committed
< system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses
< system.cpu.num_func_calls 9899985 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls
< system.cpu.num_int_insts 119969678 # number of integer instructions
< system.cpu.num_fp_insts 11290 # number of float instructions
< system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read
---
> system.cpu.committedInsts 112472279 # Number of instructions committed
> system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
> system.cpu.num_func_calls 9892504 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls
> system.cpu.num_int_insts 119910547 # number of integer instructions
> system.cpu.num_fp_insts 11161 # number of float instructions
> system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
529,538c514,523
< system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written
< system.cpu.num_mem_refs 45438019 # number of memory refs
< system.cpu.num_load_insts 24860597 # Number of load instructions
< system.cpu.num_store_insts 20577422 # Number of store instructions
< system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles
< system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles
< system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.927847 # Percentage of idle cycles
< system.cpu.Branches 25932360 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written
> system.cpu.num_mem_refs 45415290 # number of memory refs
> system.cpu.num_load_insts 24846976 # Number of load instructions
> system.cpu.num_store_insts 20568314 # Number of store instructions
> system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles
> system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles
> system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.927424 # Percentage of idle cycles
> system.cpu.Branches 25918910 # Number of branches fetched
540,541c525,526
< system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction
< system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction
> system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction
565c550
< system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction
---
> system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction
569,570c554,555
< system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction
< system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction
> system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction
573c558
< system.cpu.op_class::total 138794587 # Class of executed instruction
---
> system.cpu.op_class::total 138727463 # Class of executed instruction
575,584c560,569
< system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
< system.cpu.dcache.tags.replacements 823321 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy
---
> system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
> system.cpu.dcache.tags.replacements 820494 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy
586,589c571,574
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
591,614c576,599
< system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18835651 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits
< system.cpu.dcache.overall_hits::total 42354457 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 402703 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 299019 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 299019 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 177143306 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177143306 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23115915 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23115915 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18827300 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18827300 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 392830 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 392830 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443506 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443506 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460403 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460403 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41943215 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41943215 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42336045 # number of overall hits
> system.cpu.dcache.overall_hits::total 42336045 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 400875 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 400875 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 298693 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 298693 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 118357 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 118357 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses
617,654c602,639
< system.cpu.dcache.demand_misses::cpu.data 701722 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 820894 # number of overall misses
< system.cpu.dcache.overall_misses::total 820894 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916458250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5916458250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11650381750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280295250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 280295250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17566840000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17566840000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17566840000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17566840000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23529387 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23529387 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19134670 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19134670 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511294 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511294 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466379 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466379 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460572 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460572 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42664057 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42664057 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43175351 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43175351 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017115 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015627 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015627 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233079 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.233079 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048765 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048765 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.data 699568 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 699568 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 817925 # number of overall misses
> system.cpu.dcache.overall_misses::total 817925 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5965444702 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5965444702 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639649008 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 12639649008 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280760500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 280760500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 18605093710 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 18605093710 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 18605093710 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 18605093710 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23516790 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23516790 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19125993 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19125993 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511187 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511187 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466191 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 466191 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460405 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460405 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42642783 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42642783 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43153970 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43153970 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017046 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.017046 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231534 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.231534 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048660 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048660 # miss rate for LoadLockedReq accesses
657,673c642,658
< system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.019013 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.019013 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38962.011611 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12324.462472 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12324.462472 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25033.902315 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 25033.902315 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21399.644778 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21399.644778 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.016405 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.016405 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.018954 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.018954 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14881.059437 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14881.059437 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42316.522342 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 42316.522342 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12376.482257 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12376.482257 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26595.118287 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 22746.698915 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked
675c660
< system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
677c662
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
681,698c666,683
< system.cpu.dcache.writebacks::writebacks 686487 # number of writebacks
< system.cpu.dcache.writebacks::total 686487 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 629 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14254 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14254 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 629 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 629 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 629 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 402074 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 402074 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299019 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 299019 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8489 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8489 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 683915 # number of writebacks
> system.cpu.dcache.writebacks::total 683915 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 674 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14143 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14143 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 674 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 674 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400201 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 400201 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298693 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298693 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116343 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 116343 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses
701,732c686,717
< system.cpu.dcache.demand_mshr_misses::cpu.data 701093 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 701093 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 818114 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 818114 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5098164750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5098164750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994871250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994871250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411142000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411142000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 100012000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 100012000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16093036000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 16093036000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17504178000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17504178000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791398250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791398250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429682000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429682000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080250 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483461242 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 17483461242 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18953838790 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 18953838790 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833129500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833129500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4513032000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4513032000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346161500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346161500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017018 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017018 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227594 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227594 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018323 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018323 # mshr miss rate for LoadLockedReq accesses
735,752c720,737
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016390 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018891 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.018891 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13367.614649 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13367.614649 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40622.741383 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40622.741383 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12638.298376 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12638.298376 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency
760,768c745,753
< system.cpu.icache.tags.replacements 1701491 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1698619 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997528 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997528 # Average percentage of cache occupancy
775,812c760,797
< system.cpu.icache.tags.tag_accesses 117326421 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 117326421 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 113922403 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 113922403 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 113922403 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 113922403 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 113922403 # number of overall hits
< system.cpu.icache.overall_hits::total 113922403 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1702009 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1702009 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1702009 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1702009 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1702009 # number of overall misses
< system.cpu.icache.overall_misses::total 1702009 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23268250500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23268250500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23268250500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23268250500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23268250500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23268250500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 115624412 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 115624412 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 115624412 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 115624412 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 115624412 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 115624412 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014720 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.014720 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.014720 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.014720 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.014720 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.014720 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13671.050212 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13671.050212 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13671.050212 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13671.050212 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 117268682 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 117268682 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 113870408 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 113870408 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 113870408 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 113870408 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 113870408 # number of overall hits
> system.cpu.icache.overall_hits::total 113870408 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699137 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699137 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699137 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699137 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699137 # number of overall misses
> system.cpu.icache.overall_misses::total 1699137 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23363194999 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23363194999 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23363194999 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23363194999 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23363194999 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23363194999 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 115569545 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 115569545 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 115569545 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 115569545 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 115569545 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 115569545 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13750.036047 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13750.036047 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13750.036047 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13750.036047 # average overall miss latency
821,848c806,833
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1702009 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1702009 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1702009 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1702009 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1702009 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1702009 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19857660500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19857660500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19857660500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19857660500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19857660500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19857660500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014720 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.014720 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.014720 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11667.188893 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11667.188893 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 677067750 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
854,858c839,843
< system.cpu.l2cache.tags.replacements 88884 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64931.599128 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2763158 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 154151 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 17.925009 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 89783 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks.
860,865c845,850
< system.cpu.l2cache.tags.occ_blocks::writebacks 50668.289778 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809348 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012227 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9584.205539 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4675.282236 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.773137 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807659 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012269 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9560.730853 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4902.381289 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.769944 # Average percentage of cache occupancy
868,870c853,855
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146243 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.071339 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.990778 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145885 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.074804 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.990692 # Average percentage of cache occupancy
872c857
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65262 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65228 # Occupied blocks per task id
874,878c859,863
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6961 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56128 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id
880,889c865,874
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995819 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 26260695 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26260695 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6986 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3658 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1683931 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 515395 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2209970 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 686487 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 686487 # number of Writeback hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 26192754 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26192754 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6798 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1681053 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 512833 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2204235 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 683915 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 683915 # number of Writeback hits
892,903c877,888
< system.cpu.l2cache.ReadExReq_hits::cpu.data 166042 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 166042 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6986 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 3658 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1683931 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 681437 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2376012 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6986 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 3658 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1683931 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 681437 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2376012 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 164921 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 164921 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6798 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1681053 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 677754 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2369156 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6798 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1681053 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 677754 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2369156 # number of overall hits
906,910c891,895
< system.cpu.l2cache.ReadReq_misses::cpu.inst 18053 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 12189 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 30251 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2710 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2710 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 18063 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 12253 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 30325 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2714 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2714 # number of UpgradeReq misses
913,914c898,899
< system.cpu.l2cache.ReadExReq_misses::cpu.data 130244 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 130244 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 131035 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 131035 # number of ReadExReq misses
917,919c902,904
< system.cpu.l2cache.demand_misses::cpu.inst 18053 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 142433 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 160495 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 18063 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143288 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 161360 # number of demand (read+write) misses
922,954c907,939
< system.cpu.l2cache.overall_misses::cpu.inst 18053 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 142433 # number of overall misses
< system.cpu.l2cache.overall_misses::total 160495 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 495250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1316295500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 927332750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2244273000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 444481 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 444481 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8974834460 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8974834460 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 495250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1316295500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9902167210 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11219107460 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 495250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1316295500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9902167210 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11219107460 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6993 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3660 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1701984 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 527584 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2240221 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 686487 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 686487 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2733 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2733 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.inst 18063 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143288 # number of overall misses
> system.cpu.l2cache.overall_misses::total 161360 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 722250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 165500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1457697500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1014855798 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2473441048 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 528483 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 528483 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10018114706 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10018114706 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 722250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 165500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1457697500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11032970504 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12491555754 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 722250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 165500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1457697500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11032970504 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12491555754 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6805 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699116 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 525086 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2234560 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 683915 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 683915 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2737 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2737 # number of UpgradeReq accesses(hits+misses)
957,975c942,960
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296286 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296286 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6993 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 3660 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1701984 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 823870 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2536507 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6993 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 3660 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1701984 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 823870 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2536507 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001001 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000546 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023103 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.013504 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991584 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991584 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 295956 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 295956 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6805 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1699116 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 821042 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530516 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6805 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1699116 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 821042 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530516 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001029 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010631 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023335 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.013571 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991597 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991597 # miss rate for UpgradeReq accesses
978,1010c963,995
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439589 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.439589 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001001 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000546 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.063274 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001001 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000546 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.063274 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70750 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72912.839971 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76079.477398 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74188.390466 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 164.015129 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 164.015129 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68907.853414 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68907.853414 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69903.158728 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69903.158728 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442752 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.442752 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001029 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010631 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.174520 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.063766 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001029 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010631 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.174520 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.063766 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103178.571429 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82750 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80700.741848 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82825.087570 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 81564.420379 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 194.724761 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 194.724761 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76453.731492 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76453.731492 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77414.202739 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77414.202739 # average overall miss latency
1019,1020c1004,1005
< system.cpu.l2cache.writebacks::writebacks 82185 # number of writebacks
< system.cpu.l2cache.writebacks::total 82185 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 83215 # number of writebacks
> system.cpu.l2cache.writebacks::total 83215 # number of writebacks
1023,1027c1008,1012
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18053 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12189 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 30251 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2710 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2710 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18063 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12253 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 30325 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2714 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2714 # number of UpgradeReq MSHR misses
1030,1031c1015,1016
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130244 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 130244 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131035 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 131035 # number of ReadExReq MSHR misses
1034,1036c1019,1021
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 18053 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 142433 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 160495 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses
1039,1077c1024,1062
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 18053 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 142433 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 160495 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 408750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1090271000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 775288750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1866093500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27282710 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27282710 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7345006540 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7345006540 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1090271000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8120295290 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9211100040 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 408750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1090271000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8120295290 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9211100040 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098165500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8377798294 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8377798294 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 635250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 140500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1231366500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9239411996 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10471554246 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 635250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 140500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1231366500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9239411996 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10471554246 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 546237750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5396778750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5943016500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4154268500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4154268500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 546237750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551047250 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10097285000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023335 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013571 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991597 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991597 # mshr miss rate for UpgradeReq accesses
1080,1112c1065,1097
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442752 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442752 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.063766 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.063766 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70250 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
1122,1128c1107,1113
< system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution
1130,1146c1115,1131
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 53107 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 53413 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram
1151,1154c1136,1137
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram
1156,1159c1139,1142
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks)
1163c1146
< system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks)
1165c1148
< system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks)
1169c1152
< system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks)
1171,1174c1154,1157
< system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
< system.iobus.trans_dist::WriteResp 22814 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
> system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
1176c1159
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1197c1180
< system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1200,1201c1183,1184
< system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1222c1205
< system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1225,1226c1208,1209
< system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
1266c1249
< system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks)
1270c1253
< system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1272c1255
< system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks)
1275c1258
< system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use
1279,1282c1262,1265
< system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy
1296,1303c1279,1286
< system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles
1320,1328c1303,1311
< system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked
1330c1313
< system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked
1332c1315
< system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked
1346,1353c1329,1336
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles
1362,1369c1345,1352
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency
1371,1375c1354,1358
< system.membus.trans_dist::ReadReq 70661 # Transaction distribution
< system.membus.trans_dist::ReadResp 70661 # Transaction distribution
< system.membus.trans_dist::WriteReq 27618 # Transaction distribution
< system.membus.trans_dist::WriteResp 27618 # Transaction distribution
< system.membus.trans_dist::Writeback 118375 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 70719 # Transaction distribution
> system.membus.trans_dist::ReadResp 70719 # Transaction distribution
> system.membus.trans_dist::WriteReq 27589 # Transaction distribution
> system.membus.trans_dist::WriteResp 27589 # Transaction distribution
> system.membus.trans_dist::Writeback 119405 # Transaction distribution
1378c1361
< system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution
1380,1383c1363,1366
< system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution
< system.membus.trans_dist::ReadExReq 128454 # Transaction distribution
< system.membus.trans_dist::ReadExResp 128454 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution
> system.membus.trans_dist::ReadExReq 129241 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129241 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1385,1387c1368,1370
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes)
1390,1391c1373,1374
< system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1393,1395c1376,1378
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes)
1398c1381
< system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes)
1400c1383
< system.membus.snoop_fanout::samples 318040 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 319985 # Request fanout histogram
1405c1388
< system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram
1410,1411c1393,1394
< system.membus.snoop_fanout::total 318040 # Request fanout histogram
< system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 319985 # Request fanout histogram
> system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks)
1413c1396
< system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1415c1398
< system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks)
1417,1421c1400,1404
< system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks)
< system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks)
> system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks)