7,13c7,13
< host_inst_rate 756630 # Simulator instruction rate (inst/s)
< host_op_rate 912268 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 19520630002 # Simulator tick rate (ticks/s)
< host_mem_usage 553652 # Number of bytes of host memory used
< host_seconds 148.70 # Real time elapsed on the host
< sim_insts 112506995 # Number of instructions simulated
< sim_ops 135649572 # Number of ops (including micro ops) simulated
---
> host_inst_rate 783857 # Simulator instruction rate (inst/s)
> host_op_rate 945096 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 20223090080 # Simulator tick rate (ticks/s)
> host_mem_usage 560080 # Number of bytes of host memory used
> host_seconds 143.53 # Real time elapsed on the host
> sim_insts 112507011 # Number of instructions simulated
> sim_ops 135649580 # Number of ops (including micro ops) simulated
16d15
< system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
20a20
> system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
25d24
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
26a26
> system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
28d27
< system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32a32
> system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
35d34
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
36a36
> system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
38d37
< system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
42a42
> system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
47d46
< system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s)
48a48
> system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s)
51d50
< system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s)
55a55
> system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s)
214,222c214,222
< system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 183.640199 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 334.584074 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21469 36.67% 36.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14640 25.00% 61.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5516 9.42% 71.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3473 5.93% 77.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2278 3.89% 80.91% # Bytes accessed per row activation
224,227c224,227
< system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 999 1.71% 85.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7539 12.88% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation
271,272c271,272
< system.physmem.totQLat 1492072500 # Total ticks spent queuing
< system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 1491102500 # Total ticks spent queuing
> system.physmem.totMemAccLat 4642883750 # Total ticks spent from burst creation until serviced by the DRAM
274c274
< system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8870.59 # Average queueing delay per DRAM burst
276c276
< system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 27620.59 # Average memory access latency per DRAM burst
287,288c287,288
< system.physmem.readRowHits 138435 # Number of row buffer hits during reads
< system.physmem.writeRowHits 90000 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 138436 # Number of row buffer hits during reads
> system.physmem.writeRowHits 90002 # Number of row buffer hits during writes
293c293
< system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states
---
> system.physmem.memoryStateTime::IDLE 2755210874500 # Time in different power states
296c296
< system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 50483546000 # Time in different power states
298,301c298,301
< system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ)
---
> system.physmem.actEnergy::0 226731960 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 215936280 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 123712875 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 117822375 # Energy for precharge commands per rank (pJ)
308,315c308,315
< system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.480439 # Core power per rank (mW)
< system.physmem.averagePower::1 669.392466 # Core power per rank (mW)
---
> system.physmem.actBackEnergy::0 86730297120 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 85558991580 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1665488607000 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1666516068000 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1943242491315 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1942986381555 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.480387 # Core power per rank (mW)
> system.physmem.averagePower::1 669.392153 # Core power per rank (mW)
328,410d327
< system.membus.trans_dist::ReadReq 70649 # Transaction distribution
< system.membus.trans_dist::ReadResp 70649 # Transaction distribution
< system.membus.trans_dist::WriteReq 27618 # Transaction distribution
< system.membus.trans_dist::WriteResp 27618 # Transaction distribution
< system.membus.trans_dist::Writeback 82180 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution
< system.membus.trans_dist::ReadExReq 128451 # Transaction distribution
< system.membus.trans_dist::ReadExResp 128451 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 219 # Total snoops (count)
< system.membus.snoop_fanout::samples 281834 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 281834 # Request fanout histogram
< system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
< system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks)
< system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks)
< system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks)
< system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
< system.realview.ethernet.droppedPackets 0 # number of packets dropped
417,518d333
< system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
< system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
< system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
< system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
< system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
< system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
< system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
< system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
< system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
< system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
< system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
< system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
< system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
< system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
< system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
< system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
< system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks)
< system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
543c358
< system.cpu.dtb.read_hits 24532668 # DTB read hits
---
> system.cpu.dtb.read_hits 24532671 # DTB read hits
545c360
< system.cpu.dtb.write_hits 19614514 # DTB write hits
---
> system.cpu.dtb.write_hits 19614515 # DTB write hits
556,557c371,372
< system.cpu.dtb.read_accesses 24540816 # DTB read accesses
< system.cpu.dtb.write_accesses 19615924 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24540819 # DTB read accesses
> system.cpu.dtb.write_accesses 19615925 # DTB write accesses
559c374
< system.cpu.dtb.hits 44147182 # DTB hits
---
> system.cpu.dtb.hits 44147186 # DTB hits
561c376
< system.cpu.dtb.accesses 44156740 # DTB accesses
---
> system.cpu.dtb.accesses 44156744 # DTB accesses
583c398
< system.cpu.itb.inst_hits 115605897 # ITB inst hits
---
> system.cpu.itb.inst_hits 115605918 # ITB inst hits
600,601c415,416
< system.cpu.itb.inst_accesses 115610659 # ITB inst accesses
< system.cpu.itb.hits 115605897 # DTB hits
---
> system.cpu.itb.inst_accesses 115610680 # ITB inst accesses
> system.cpu.itb.hits 115605918 # DTB hits
603c418
< system.cpu.itb.accesses 115610659 # DTB accesses
---
> system.cpu.itb.accesses 115610680 # DTB accesses
607,609c422,424
< system.cpu.committedInsts 112506995 # Number of instructions committed
< system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses
---
> system.cpu.committedInsts 112507011 # Number of instructions committed
> system.cpu.committedOps 135649580 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119948946 # Number of integer alu accesses
612,613c427,428
< system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls
< system.cpu.num_int_insts 119948923 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 15236406 # number of instructions that are conditional controls
> system.cpu.num_int_insts 119948946 # number of integer instructions
615,616c430,431
< system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 218165471 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82686622 # number of times the integer registers were written
619,628c434,443
< system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written
< system.cpu.num_mem_refs 45428231 # number of memory refs
< system.cpu.num_load_insts 24855392 # Number of load instructions
< system.cpu.num_store_insts 20572839 # Number of store instructions
< system.cpu.num_idle_cycles 5386456122.024144 # Number of idle cycles
< system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles
< system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.927861 # Percentage of idle cycles
< system.cpu.Branches 25929456 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 489970666 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51914345 # number of times the CC registers were written
> system.cpu.num_mem_refs 45428250 # number of memory refs
> system.cpu.num_load_insts 24855398 # Number of load instructions
> system.cpu.num_store_insts 20572852 # Number of store instructions
> system.cpu.num_idle_cycles 5386458042.024144 # Number of idle cycles
> system.cpu.num_busy_cycles 418780219.975856 # Number of busy cycles
> system.cpu.not_idle_fraction 0.072138 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.927862 # Percentage of idle cycles
> system.cpu.Branches 25929462 # Number of branches fetched
630,631c445,446
< system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction
< system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93218062 67.17% 67.18% # Class of executed instruction
> system.cpu.op_class::IntMult 114523 0.08% 67.26% # Class of executed instruction
659,660c474,475
< system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction
< system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 24855398 17.91% 85.18% # Class of executed instruction
> system.cpu.op_class::MemWrite 20572852 14.82% 100.00% # Class of executed instruction
663c478
< system.cpu.op_class::total 138771625 # Class of executed instruction
---
> system.cpu.op_class::total 138771647 # Class of executed instruction
665a481,664
> system.cpu.dcache.tags.replacements 822746 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 43252602 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 823258 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 52.538332 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 177194888 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 177194888 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23122389 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23122389 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18831358 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18831358 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41953747 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41953747 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 42345868 # number of overall hits
> system.cpu.dcache.overall_hits::total 42345868 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 402166 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 402166 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 701192 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 701192 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 820347 # number of overall misses
> system.cpu.dcache.overall_misses::total 820347 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900442000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5900442000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658351003 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11658351003 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 17558793003 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17558793003 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17558793003 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17558793003 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23524555 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23524555 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19130384 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19130384 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42654939 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42654939 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43166215 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43166215 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14671.657972 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14671.657972 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.750239 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.750239 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.348166 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25041.348166 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.104608 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21404.104608 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 686230 # number of writebacks
> system.cpu.dcache.writebacks::total 686230 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401539 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 401539 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 700565 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 700565 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 817569 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 817569 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083326500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083326500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002800997 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002800997 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086127497 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 16086127497 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497317497 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 17497317497 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12659.608407 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12659.608407 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.465936 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.465936 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22961.648808 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22961.648808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21401.640103 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21401.640103 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
668c667
< system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 113905582 # Total number of references to valid blocks.
670c669
< system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 66.990280 # Average number of references to valid blocks.
681,688c680,687
< system.cpu.icache.tags.tag_accesses 117306233 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 117306233 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 113905561 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 113905561 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 113905561 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 113905561 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 113905561 # number of overall hits
< system.cpu.icache.overall_hits::total 113905561 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 117306254 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 117306254 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 113905582 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 113905582 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 113905582 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 113905582 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 113905582 # number of overall hits
> system.cpu.icache.overall_hits::total 113905582 # number of overall hits
695,706c694,705
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23243215000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23243215000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23243215000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23243215000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23243215000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23243215000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 115605897 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 115605897 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 115605897 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 115605897 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 115605897 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 115605897 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23242723500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23242723500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23242723500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23242723500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23242723500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23242723500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 115605918 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 115605918 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 115605918 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 115605918 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 115605918 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 115605918 # number of overall (read+write) accesses
713,718c712,717
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.777620 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13669.777620 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13669.777620 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13669.777620 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.488560 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13669.488560 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13669.488560 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13669.488560 # average overall miss latency
733,738c732,737
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835992000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19835992000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835501500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19835501500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835501500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19835501500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835501500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19835501500 # number of overall MSHR miss cycles
749,754c748,753
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.636380 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.636380 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency
761,762c760,761
< system.cpu.l2cache.tags.tagsinuse 64932.369340 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2760846 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 64932.369335 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2760844 # Total number of references to valid blocks.
764c763
< system.cpu.l2cache.tags.avg_refs 17.911869 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 17.911856 # Average number of references to valid blocks.
766c765
< system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822165 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822123 # Average occupied blocks per requestor
769,770c768,769
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724019 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001590 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724050 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001596 # Average occupied blocks per requestor
787,788c786,787
< system.cpu.l2cache.tags.tag_accesses 26241966 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26241966 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 26241950 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26241950 # Number of data accesses
792,795c791,794
< system.cpu.l2cache.ReadReq_hits::cpu.data 514822 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2207892 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 686231 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 686231 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 514821 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2207891 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 686230 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 686230 # number of Writeback hits
803,804c802,803
< system.cpu.l2cache.demand_hits::cpu.data 680871 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2373941 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 680870 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2373940 # number of demand (read+write) hits
808,809c807,808
< system.cpu.l2cache.overall_hits::cpu.data 680871 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2373941 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 680870 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2373940 # number of overall hits
833,835c832,834
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312883000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918689000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2232289250 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312392500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918323250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2231433000 # number of ReadReq miss cycles
840,841c839,840
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982643216 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8982643216 # number of ReadExReq miss cycles
844,846c843,845
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1312392500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9900966466 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11214076216 # number of demand (read+write) miss cycles
849,851c848,850
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1312392500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9900966466 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11214076216 # number of overall miss cycles
855,858c854,857
< system.cpu.l2cache.ReadReq_accesses::cpu.data 527013 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2238131 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 686231 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 686231 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.data 527012 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2238130 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 686230 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 686230 # number of Writeback accesses(hits+misses)
868,869c867,868
< system.cpu.l2cache.demand_accesses::cpu.data 823297 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2534415 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 823296 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2534414 # number of demand (read+write) accesses
873,874c872,873
< system.cpu.l2cache.overall_accesses::cpu.data 823297 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2534415 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 823296 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2534414 # number of overall (read+write) accesses
898,900c897,899
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72753.062808 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75327.967353 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73793.214061 # average ReadReq miss latency
905,906c904,905
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.574316 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.574316 # average ReadExReq miss latency
909,911c908,910
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69880.954024 # average overall miss latency
914,916c913,915
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69880.954024 # average overall miss latency
950,952c949,951
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087047500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766535000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1854188250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1086559000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766168250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1853333000 # number of ReadReq MSHR miss cycles
957,958c956,957
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352907784 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352907784 # number of ReadExReq MSHR miss cycles
961,963c960,962
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1086559000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119076034 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9206240784 # number of demand (read+write) MSHR miss cycles
966,968c965,967
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1086559000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119076034 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9206240784 # number of overall MSHR miss cycles
1000,1002c999,1001
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60233.882144 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62847.038799 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61289.493700 # average ReadReq mshr miss latency
1007,1008c1006,1007
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56458.769025 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56458.769025 # average ReadExReq mshr miss latency
1011,1013c1010,1012
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency
1016,1018c1015,1017
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency
1028,1213c1027,1028
< system.cpu.dcache.tags.replacements 822747 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 43252597 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 823259 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 52.538262 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 177194873 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 177194873 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23122385 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23122385 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18831357 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18831357 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41953742 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41953742 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 42345863 # number of overall hits
< system.cpu.dcache.overall_hits::total 42345863 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 402167 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 402167 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses
< system.cpu.dcache.overall_misses::total 820348 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42654935 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42654935 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43166211 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43166211 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 686231 # number of writebacks
< system.cpu.dcache.writebacks::total 686231 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401540 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 401540 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2294825 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2294810 # Transaction distribution
1216c1031
< system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 686230 # Transaction distribution
1224c1039
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456073 # Packet count per connected master and slave (bytes)
1227c1042
< system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 5912638 # Packet count per connected master and slave (bytes)
1229c1044
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96806921 # Cumulative packet size per connected master and slave (bytes)
1232c1047
< system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205706201 # Cumulative packet size per connected master and slave (bytes)
1234c1049
< system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3276132 # Request fanout histogram
1243c1058
< system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 3239673 98.89% 98.89% # Request fanout histogram
1248,1249c1063,1064
< system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3276132 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2353772500 # Layer occupancy (ticks)
1253c1068
< system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2564911000 # Layer occupancy (ticks)
1255c1070
< system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1311851755 # Layer occupancy (ticks)
1260a1076,1177
> system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
> system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
> system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
> system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
> system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
> system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
> system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
> system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
> system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
> system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
> system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
> system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
> system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
> system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
> system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
> system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
> system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks)
> system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1345a1263,1345
> system.membus.trans_dist::ReadReq 70649 # Transaction distribution
> system.membus.trans_dist::ReadResp 70649 # Transaction distribution
> system.membus.trans_dist::WriteReq 27618 # Transaction distribution
> system.membus.trans_dist::WriteResp 27618 # Transaction distribution
> system.membus.trans_dist::Writeback 82180 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution
> system.membus.trans_dist::ReadExReq 128451 # Transaction distribution
> system.membus.trans_dist::ReadExResp 128451 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 219 # Total snoops (count)
> system.membus.snoop_fanout::samples 281834 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 281834 # Request fanout histogram
> system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
> system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks)
> system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer5.occupancy 1264017500 # Layer occupancy (ticks)
> system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer2.occupancy 1594856995 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks)
> system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
> system.realview.ethernet.droppedPackets 0 # number of packets dropped