7,13c7,13
< host_inst_rate 744858 # Simulator instruction rate (inst/s)
< host_op_rate 898074 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 19216925045 # Simulator tick rate (ticks/s)
< host_mem_usage 553548 # Number of bytes of host memory used
< host_seconds 151.05 # Real time elapsed on the host
< sim_insts 112506996 # Number of instructions simulated
< sim_ops 135649573 # Number of ops (including micro ops) simulated
---
> host_inst_rate 756630 # Simulator instruction rate (inst/s)
> host_op_rate 912268 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 19520630002 # Simulator tick rate (ticks/s)
> host_mem_usage 553652 # Number of bytes of host memory used
> host_seconds 148.70 # Real time elapsed on the host
> sim_insts 112506995 # Number of instructions simulated
> sim_ops 135649572 # Number of ops (including micro ops) simulated
103c103
< system.physmem.totGap 2902618699500 # Total gap between requests
---
> system.physmem.totGap 2902618754500 # Total gap between requests
214,220c214,220
< system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation
222c222
< system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation
224,227c224,227
< system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation
271,272c271,272
< system.physmem.totQLat 1491787750 # Total ticks spent queuing
< system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 1492072500 # Total ticks spent queuing
> system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM
274c274
< system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst
276c276
< system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst
287c287
< system.physmem.readRowHits 138438 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 138435 # Number of row buffer hits during reads
291c291
< system.physmem.avgGap 9972509.98 # Average gap between requests
---
> system.physmem.avgGap 9972510.17 # Average gap between requests
293c293
< system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states
---
> system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states
296c296
< system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states
298,301c298,301
< system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ)
---
> system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ)
308,329c308,329
< system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.480430 # Core power per rank (mW)
< system.physmem.averagePower::1 669.392372 # Core power per rank (mW)
< system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 70650 # Transaction distribution
< system.membus.trans_dist::ReadResp 70650 # Transaction distribution
---
> system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.480439 # Core power per rank (mW)
> system.physmem.averagePower::1 669.392466 # Core power per rank (mW)
> system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 70649 # Transaction distribution
> system.membus.trans_dist::ReadResp 70649 # Transaction distribution
341c341
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
344c344
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes)
347c347
< system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes)
349c349
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
352c352
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes)
355c355
< system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes)
370c370
< system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
376c376
< system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks)
607,609c607,609
< system.cpu.committedInsts 112506996 # Number of instructions committed
< system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses
---
> system.cpu.committedInsts 112506995 # Number of instructions committed
> system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses
613c613
< system.cpu.num_int_insts 119948924 # number of integer instructions
---
> system.cpu.num_int_insts 119948923 # number of integer instructions
615,616c615,616
< system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written
619,620c619,620
< system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written
---
> system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written
630c630
< system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction
663c663
< system.cpu.op_class::total 138771626 # Class of executed instruction
---
> system.cpu.op_class::total 138771625 # Class of executed instruction
739,742c739,742
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles
---
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
840,841c840,841
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles
845,846c845,846
< system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles
850,851c850,851
< system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles
905,906c905,906
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency
910,911c910,911
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency
915,916c915,916
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency
957,958c957,958
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles
962,963c962,963
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles
967,971c967,971
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles
974,976c974,976
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles
1007,1008c1007,1008
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency
1012,1013c1012,1013
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
1017,1018c1017,1018
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
1075,1076c1075,1076
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles
1081,1084c1081,1084
< system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles
1115,1116c1115,1116
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency
1121,1124c1121,1124
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency
1159,1160c1159,1160
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles
1167,1172c1167,1172
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles
1175,1176c1175,1176
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles
1193,1194c1193,1194
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency
1201,1204c1201,1204
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency
1212,1213c1212,1213
< system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution
1223c1223
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes)
1227,1228c1227,1228
< system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes)
1232c1232
< system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes)
1249c1249
< system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks)
1253c1253
< system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks)
1255c1255
< system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks)
< host_inst_rate 744858 # Simulator instruction rate (inst/s)
< host_op_rate 898074 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 19216925045 # Simulator tick rate (ticks/s)
< host_mem_usage 553548 # Number of bytes of host memory used
< host_seconds 151.05 # Real time elapsed on the host
< sim_insts 112506996 # Number of instructions simulated
< sim_ops 135649573 # Number of ops (including micro ops) simulated
---
> host_inst_rate 756630 # Simulator instruction rate (inst/s)
> host_op_rate 912268 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 19520630002 # Simulator tick rate (ticks/s)
> host_mem_usage 553652 # Number of bytes of host memory used
> host_seconds 148.70 # Real time elapsed on the host
> sim_insts 112506995 # Number of instructions simulated
> sim_ops 135649572 # Number of ops (including micro ops) simulated
103c103
< system.physmem.totGap 2902618699500 # Total gap between requests
---
> system.physmem.totGap 2902618754500 # Total gap between requests
214,220c214,220
< system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation
222c222
< system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation
224,227c224,227
< system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation
271,272c271,272
< system.physmem.totQLat 1491787750 # Total ticks spent queuing
< system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 1492072500 # Total ticks spent queuing
> system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM
274c274
< system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst
276c276
< system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst
287c287
< system.physmem.readRowHits 138438 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 138435 # Number of row buffer hits during reads
291c291
< system.physmem.avgGap 9972509.98 # Average gap between requests
---
> system.physmem.avgGap 9972510.17 # Average gap between requests
293c293
< system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states
---
> system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states
296c296
< system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states
298,301c298,301
< system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ)
---
> system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ)
308,329c308,329
< system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.480430 # Core power per rank (mW)
< system.physmem.averagePower::1 669.392372 # Core power per rank (mW)
< system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 70650 # Transaction distribution
< system.membus.trans_dist::ReadResp 70650 # Transaction distribution
---
> system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.480439 # Core power per rank (mW)
> system.physmem.averagePower::1 669.392466 # Core power per rank (mW)
> system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 70649 # Transaction distribution
> system.membus.trans_dist::ReadResp 70649 # Transaction distribution
341c341
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
344c344
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes)
347c347
< system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes)
349c349
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
352c352
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes)
355c355
< system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes)
370c370
< system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
376c376
< system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks)
607,609c607,609
< system.cpu.committedInsts 112506996 # Number of instructions committed
< system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses
---
> system.cpu.committedInsts 112506995 # Number of instructions committed
> system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses
613c613
< system.cpu.num_int_insts 119948924 # number of integer instructions
---
> system.cpu.num_int_insts 119948923 # number of integer instructions
615,616c615,616
< system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read
< system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read
> system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written
619,620c619,620
< system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written
---
> system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written
630c630
< system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction
663c663
< system.cpu.op_class::total 138771626 # Class of executed instruction
---
> system.cpu.op_class::total 138771625 # Class of executed instruction
739,742c739,742
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles
---
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
840,841c840,841
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles
845,846c845,846
< system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles
850,851c850,851
< system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles
905,906c905,906
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency
910,911c910,911
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency
915,916c915,916
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency
957,958c957,958
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles
962,963c962,963
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles
967,971c967,971
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles
974,976c974,976
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles
1007,1008c1007,1008
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency
1012,1013c1012,1013
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
1017,1018c1017,1018
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
1075,1076c1075,1076
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles
1081,1084c1081,1084
< system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles
1115,1116c1115,1116
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency
1121,1124c1121,1124
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency
1159,1160c1159,1160
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles
1167,1172c1167,1172
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles
1175,1176c1175,1176
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles
1193,1194c1193,1194
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency
1201,1204c1201,1204
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency
1212,1213c1212,1213
< system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution
1223c1223
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes)
1227,1228c1227,1228
< system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes)
1232c1232
< system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes)
1249c1249
< system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks)
1253c1253
< system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks)
1255c1255
< system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks)