3,5c3,5
< sim_seconds 2.616536 # Number of seconds simulated
< sim_ticks 2616536215000 # Number of ticks simulated
< final_tick 2616536215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.616230 # Number of seconds simulated
> sim_ticks 2616229847000 # Number of ticks simulated
> final_tick 2616229847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 594955 # Simulator instruction rate (inst/s)
< host_op_rate 757104 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 25859148121 # Simulator tick rate (ticks/s)
< host_mem_usage 420956 # Number of bytes of host memory used
< host_seconds 101.18 # Real time elapsed on the host
< sim_insts 60200059 # Number of instructions simulated
< sim_ops 76606878 # Number of ops (including micro ops) simulated
---
> host_inst_rate 375445 # Simulator instruction rate (inst/s)
> host_op_rate 477768 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16316419265 # Simulator tick rate (ticks/s)
> host_mem_usage 464828 # Number of bytes of host memory used
> host_seconds 160.34 # Real time elapsed on the host
> sim_insts 60200042 # Number of instructions simulated
> sim_ops 76606857 # Number of ops (including micro ops) simulated
15a16,27
> system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
19,24c31,36
< system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9089816 # Number of bytes read from this memory
< system.physmem.bytes_read::total 132477600 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 3706240 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.inst 703560 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9089944 # Number of bytes read from this memory
> system.physmem.bytes_read::total 132477344 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 703560 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 703560 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory
26c38
< system.physmem.bytes_written::total 6722312 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory
30,33c42,45
< system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 142064 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15494706 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 57910 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 17205 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 142066 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15494702 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory
35,36c47,48
< system.physmem.num_writes::total 811928 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 46887710 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 46893201 # Total read bandwidth from this memory (bytes/s)
39,48c51,60
< system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3473988 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 50630906 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1416468 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2569165 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1416468 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 46887710 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 268921 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3474444 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 50636737 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 268921 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 268921 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1416658 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1152831 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2569490 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1416658 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 46893201 # Total bandwidth to/from this memory (bytes/s)
51,66c63,78
< system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4626685 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53200071 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15494706 # Number of read requests accepted
< system.physmem.writeReqs 811928 # Number of write requests accepted
< system.physmem.readBursts 15494706 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 811928 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 991531648 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 129536 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6740736 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 132477600 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6722312 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 2024 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 706583 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 967775 # Per bank write bursts
---
> system.physmem.bw_total::cpu.inst 268921 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 4627275 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53206227 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15494702 # Number of read requests accepted
> system.physmem.writeReqs 811929 # Number of write requests accepted
> system.physmem.readBursts 15494702 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 991533248 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 127680 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6729728 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 132477344 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 1995 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 706751 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 967982 # Per bank write bursts
68,74c80,86
< system.physmem.perBankRdBursts::2 967672 # Per bank write bursts
< system.physmem.perBankRdBursts::3 967748 # Per bank write bursts
< system.physmem.perBankRdBursts::4 974561 # Per bank write bursts
< system.physmem.perBankRdBursts::5 968173 # Per bank write bursts
< system.physmem.perBankRdBursts::6 967769 # Per bank write bursts
< system.physmem.perBankRdBursts::7 967703 # Per bank write bursts
< system.physmem.perBankRdBursts::8 968545 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 967669 # Per bank write bursts
> system.physmem.perBankRdBursts::3 967754 # Per bank write bursts
> system.physmem.perBankRdBursts::4 974564 # Per bank write bursts
> system.physmem.perBankRdBursts::5 968184 # Per bank write bursts
> system.physmem.perBankRdBursts::6 967779 # Per bank write bursts
> system.physmem.perBankRdBursts::7 967692 # Per bank write bursts
> system.physmem.perBankRdBursts::8 968544 # Per bank write bursts
81,97c93,109
< system.physmem.perBankRdBursts::15 967797 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6510 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6313 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6323 # Per bank write bursts
< system.physmem.perBankWrBursts::3 6241 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6804 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6995 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6800 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6791 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7084 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6747 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6568 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6457 # Per bank write bursts
< system.physmem.perBankWrBursts::12 6495 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6295 # Per bank write bursts
< system.physmem.perBankWrBursts::14 6428 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6473 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 967600 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6503 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6305 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6309 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6231 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6800 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6982 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6786 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6777 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7080 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6733 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6548 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6441 # Per bank write bursts
> system.physmem.perBankWrBursts::12 6486 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6281 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6425 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6465 # Per bank write bursts
100c112
< system.physmem.totGap 2616531854000 # Total gap between requests
---
> system.physmem.totGap 2616225486000 # Total gap between requests
107c119
< system.physmem.readPktSize::6 152618 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 152614 # Read request sizes (log2)
114,131c126,143
< system.physmem.writePktSize::6 57910 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1116573 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 960474 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 961347 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 975907 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 963056 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 965451 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2812276 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2805674 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3709925 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 42008 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 34639 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 36264 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 33338 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 31474 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 22310 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 21858 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 57911 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1126567 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 970563 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 976518 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1090618 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 986596 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1051326 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2724005 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2632042 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3421723 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 136210 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 113171 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 104737 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 101252 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 19730 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 18895 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 18668 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 86 # What read queue length does an incoming req see
162,200c174,212
< system.physmem.wrQLenPdf::15 2478 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2541 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 3152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4807 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4792 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4786 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4793 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4827 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4839 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4834 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5981 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4975 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5804 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 4869 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 4878 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 4878 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 4793 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1099 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1078 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1070 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1076 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1063 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1059 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1059 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1059 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1059 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 1058 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 1058 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 3804 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3835 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6081 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6100 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6099 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6098 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 6095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6094 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6094 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
211,256c223,258
< system.physmem.bytesPerActivate::samples 977394 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 1014.625651 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 1002.644045 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 87.222028 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 3543 0.36% 0.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 3286 0.34% 0.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 1787 0.18% 0.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1165 0.12% 1.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 902 0.09% 1.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 711 0.07% 1.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 580 0.06% 1.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 432 0.04% 1.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 964988 98.73% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 977394 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 4784 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 3238.435619 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 134294.504205 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-524287 4779 99.90% 99.90% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.06% 99.96% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 4784 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 4784 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.015886 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 20.524536 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 9.242033 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 2224 46.49% 46.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 36 0.75% 47.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 227 4.74% 51.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1224 25.59% 77.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 8 0.17% 77.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 4 0.08% 77.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 1 0.02% 77.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::33 1 0.02% 77.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34 1 0.02% 77.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::39 945 19.75% 97.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40 67 1.40% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::41 15 0.31% 99.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::42 31 0.65% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 4784 # Writes before turning the bus around for reads
< system.physmem.totQLat 588095657500 # Total ticks spent queuing
< system.physmem.totMemAccLat 694960871250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 77463410000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 29401803750 # Total ticks spent accessing banks
< system.physmem.avgQLat 37959.58 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 1897.79 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1027354 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 971.683544 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 905.447521 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 204.224200 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22943 2.23% 2.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 22460 2.19% 4.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8461 0.82% 5.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2563 0.25% 5.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2504 0.24% 5.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1783 0.17% 5.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8706 0.85% 6.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 969 0.09% 6.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 956965 93.15% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1027354 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6094 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 2542.286675 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 118884.715097 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-524287 6090 99.93% 99.93% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6094 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6094 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.255005 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.227328 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.967528 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 2261 37.10% 37.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 29 0.48% 37.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 3794 62.26% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 9 0.15% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6094 # Writes before turning the bus around for reads
> system.physmem.totQLat 400062590250 # Total ticks spent queuing
> system.physmem.totMemAccLat 690550846500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 77463535000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25822.64 # Average queueing delay per DRAM burst
258,261c260,263
< system.physmem.avgMemAccLat 44857.36 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 44572.64 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 378.99 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 50.64 # Average system read bandwidth in MiByte/s
267,290c269,284
< system.physmem.avgRdQLen 7.03 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 29.46 # Average write queue length when enqueuing
< system.physmem.readRowHits 14490606 # Number of row buffer hits during reads
< system.physmem.writeRowHits 90101 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 85.53 # Row buffer hit rate for writes
< system.physmem.avgGap 160458.12 # Average gap between requests
< system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined
< system.physmem.prechargeAllPercent 3.85 # Percentage of time for which DRAM has all the banks in precharge state
< system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
< system.membus.throughput 54116651 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 16546597 # Transaction distribution
< system.membus.trans_dist::ReadResp 16546597 # Transaction distribution
---
> system.physmem.avgRdQLen 6.59 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing
> system.physmem.readRowHits 14482119 # Number of row buffer hits during reads
> system.physmem.writeRowHits 88386 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 84.03 # Row buffer hit rate for writes
> system.physmem.avgGap 160439.36 # Average gap between requests
> system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2245273695250 # Time in different power states
> system.physmem.memoryStateTime::REF 87361560000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 283591722250 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 54122917 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 16546592 # Transaction distribution
> system.membus.trans_dist::ReadResp 16546592 # Transaction distribution
293,298c287,292
< system.membus.trans_dist::Writeback 57910 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution
< system.membus.trans_dist::ReadExReq 132217 # Transaction distribution
< system.membus.trans_dist::ReadExResp 132217 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::Writeback 57911 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
> system.membus.trans_dist::ReadExReq 132219 # Transaction distribution
> system.membus.trans_dist::ReadExResp 132219 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383090 # Packet count per connected master and slave (bytes)
302,303c296,297
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893540 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280490 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893535 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280487 # Packet count per connected master and slave (bytes)
306,307c300,301
< system.membus.pkt_count::total 34951338 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 34951335 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390546 # Cumulative packet size per connected master and slave (bytes)
311,312c305,306
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516520 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914786 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516328 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914598 # Cumulative packet size per connected master and slave (bytes)
315,316c309,310
< system.membus.tot_pkt_size::total 141598178 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 141598178 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 141597990 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 141597990 # Total data (bytes)
318c312
< system.membus.reqLayer0.occupancy 1206225000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1206224000 # Layer occupancy (ticks)
322c316
< system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3616500 # Layer occupancy (ticks)
326c320
< system.membus.reqLayer6.occupancy 17911294000 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 17911182500 # Layer occupancy (ticks)
328c322
< system.membus.respLayer1.occupancy 4951349139 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4951111812 # Layer occupancy (ticks)
330,331c324,325
< system.membus.respLayer2.occupancy 38238689000 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
---
> system.membus.respLayer2.occupancy 37928474750 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
338,340c332,334
< system.iobus.throughput 47801339 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution
< system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution
---
> system.iobus.throughput 47806938 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 16518786 # Transaction distribution
> system.iobus.trans_dist::ReadResp 16518786 # Transaction distribution
344c338
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
366c360
< system.iobus.pkt_count_system.bridge.master::total 2383088 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 2383090 # Packet count per connected master and slave (bytes)
369c363
< system.iobus.pkt_count::total 33053936 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 33053938 # Packet count per connected master and slave (bytes)
371c365
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
393c387
< system.iobus.tot_pkt_size_system.bridge.master::total 2390542 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 2390546 # Cumulative packet size per connected master and slave (bytes)
396,397c390,391
< system.iobus.tot_pkt_size::total 125073934 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 125073934 # Total data (bytes)
---
> system.iobus.tot_pkt_size::total 125073938 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 125073938 # Total data (bytes)
400c394
< system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
446c440
< system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 2374907000 # Layer occupancy (ticks)
448c442
< system.iobus.respLayer1.occupancy 38265059000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 38686102250 # Layer occupancy (ticks)
474,477c468,471
< system.cpu.dtb.read_hits 14996179 # DTB read hits
< system.cpu.dtb.read_misses 7337 # DTB read misses
< system.cpu.dtb.write_hits 11230334 # DTB write hits
< system.cpu.dtb.write_misses 2213 # DTB write misses
---
> system.cpu.dtb.read_hits 14996190 # DTB read hits
> system.cpu.dtb.read_misses 7339 # DTB read misses
> system.cpu.dtb.write_hits 11230344 # DTB write hits
> system.cpu.dtb.write_misses 2214 # DTB write misses
482c476
< system.cpu.dtb.flush_entries 3411 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB
484c478
< system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch
487,488c481,482
< system.cpu.dtb.read_accesses 15003516 # DTB read accesses
< system.cpu.dtb.write_accesses 11232547 # DTB write accesses
---
> system.cpu.dtb.read_accesses 15003529 # DTB read accesses
> system.cpu.dtb.write_accesses 11232558 # DTB write accesses
490,492c484,486
< system.cpu.dtb.hits 26226513 # DTB hits
< system.cpu.dtb.misses 9550 # DTB misses
< system.cpu.dtb.accesses 26236063 # DTB accesses
---
> system.cpu.dtb.hits 26226534 # DTB hits
> system.cpu.dtb.misses 9553 # DTB misses
> system.cpu.dtb.accesses 26236087 # DTB accesses
514c508
< system.cpu.itb.inst_hits 61493932 # ITB inst hits
---
> system.cpu.itb.inst_hits 61493913 # ITB inst hits
531,532c525,526
< system.cpu.itb.inst_accesses 61498403 # ITB inst accesses
< system.cpu.itb.hits 61493932 # DTB hits
---
> system.cpu.itb.inst_accesses 61498384 # ITB inst accesses
> system.cpu.itb.hits 61493913 # DTB hits
534,535c528,529
< system.cpu.itb.accesses 61498403 # DTB accesses
< system.cpu.numCycles 5233072430 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 61498384 # DTB accesses
> system.cpu.numCycles 5232459694 # number of cpu cycles simulated
538,540c532,534
< system.cpu.committedInsts 60200059 # Number of instructions committed
< system.cpu.committedOps 76606878 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 69208659 # Number of integer alu accesses
---
> system.cpu.committedInsts 60200042 # Number of instructions committed
> system.cpu.committedOps 76606857 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 69208585 # Number of integer alu accesses
543,544c537,538
< system.cpu.num_conditional_control_insts 7948676 # number of instructions that are conditional controls
< system.cpu.num_int_insts 69208659 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 7948679 # number of instructions that are conditional controls
> system.cpu.num_int_insts 69208585 # number of integer instructions
546,547c540,541
< system.cpu.num_int_register_reads 401368432 # number of times the integer registers were read
< system.cpu.num_int_register_writes 74518953 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 401368270 # number of times the integer registers were read
> system.cpu.num_int_register_writes 74518872 # number of times the integer registers were written
550,557c544,586
< system.cpu.num_mem_refs 27394027 # number of memory refs
< system.cpu.num_load_insts 15660244 # Number of load instructions
< system.cpu.num_store_insts 11733783 # Number of store instructions
< system.cpu.num_idle_cycles 4581664281.608249 # Number of idle cycles
< system.cpu.num_busy_cycles 651408148.391751 # Number of busy cycles
< system.cpu.not_idle_fraction 0.124479 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.875521 # Percentage of idle cycles
< system.cpu.Branches 10308791 # Number of branches fetched
---
> system.cpu.num_mem_refs 27394017 # number of memory refs
> system.cpu.num_load_insts 15660224 # Number of load instructions
> system.cpu.num_store_insts 11733793 # Number of store instructions
> system.cpu.num_idle_cycles 4581582300.610249 # Number of idle cycles
> system.cpu.num_busy_cycles 650877393.389751 # Number of busy cycles
> system.cpu.not_idle_fraction 0.124392 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.875608 # Percentage of idle cycles
> system.cpu.Branches 10308802 # Number of branches fetched
> system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
> system.cpu.op_class::IntAlu 50389316 64.68% 64.72% # Class of executed instruction
> system.cpu.op_class::IntMult 87585 0.11% 64.83% # Class of executed instruction
> system.cpu.op_class::IntDiv 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::FloatAdd 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::FloatCmp 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::FloatCvt 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::FloatMult 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::FloatDiv 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction
> system.cpu.op_class::SimdFloatMisc 2109 0.00% 64.84% # Class of executed instruction
> system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction
> system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction
> system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction
> system.cpu.op_class::MemRead 15660224 20.10% 84.94% # Class of executed instruction
> system.cpu.op_class::MemWrite 11733793 15.06% 100.00% # Class of executed instruction
> system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
> system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
> system.cpu.op_class::total 77901545 # Class of executed instruction
559,568c588,597
< system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed
< system.cpu.icache.tags.replacements 856277 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.865256 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 60637143 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 856789 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 70.772551 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 20019652250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.865256 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997784 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997784 # Average percentage of cache occupancy
---
> system.cpu.kern.inst.quiesce 83017 # number of quiesce instructions executed
> system.cpu.icache.tags.replacements 856351 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.866135 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 60637050 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 856863 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 70.766330 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 20005377250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.866135 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997785 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997785 # Average percentage of cache occupancy
571,572c600,601
< system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id
575,612c604,641
< system.cpu.icache.tags.tag_accesses 62350721 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 62350721 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 60637143 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 60637143 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 60637143 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 60637143 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 60637143 # number of overall hits
< system.cpu.icache.overall_hits::total 60637143 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 856789 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 856789 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 856789 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 856789 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 856789 # number of overall misses
< system.cpu.icache.overall_misses::total 856789 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768796500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11768796500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11768796500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11768796500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11768796500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11768796500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 61493932 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 61493932 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 61493932 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 61493932 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 61493932 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 61493932 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.933234 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13735.933234 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13735.933234 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 62350776 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 62350776 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 60637050 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 60637050 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 60637050 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 60637050 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 60637050 # number of overall hits
> system.cpu.icache.overall_hits::total 60637050 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 856863 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 856863 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 856863 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 856863 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 856863 # number of overall misses
> system.cpu.icache.overall_misses::total 856863 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766560750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11766560750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11766560750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11766560750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11766560750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11766560750 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 61493913 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 61493913 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 61493913 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 61493913 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 61493913 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 61493913 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13732.137751 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13732.137751 # average overall miss latency
621,648c650,677
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856789 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 856789 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 856789 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 856789 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 856789 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 856789 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051259500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 10051259500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051259500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 10051259500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051259500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 10051259500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 442799750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 442799750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 442799750 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 442799750 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.312494 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.312494 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856863 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 856863 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 856863 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 856863 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 856863 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 856863 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10048829250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 10048829250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10048829250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 10048829250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10048829250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 10048829250 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 441046000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 441046000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 441046000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 441046000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013934 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.013934 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.013934 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11727.463142 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11727.463142 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency
654,661c683,690
< system.cpu.l2cache.tags.replacements 62510 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 50754.341814 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1682268 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 127892 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 13.153817 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2565667436000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 37718.224228 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884316 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.replacements 62506 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 50753.322403 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1682121 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 127886 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 13.153285 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2565374310000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 37717.253716 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884318 # Average occupied blocks per requestor
663,665c692,694
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.295627 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.936941 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.575534 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.225103 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.958564 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.575520 # Average percentage of cache occupancy
668c697
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106709 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106708 # Average percentage of cache occupancy
670c699
< system.cpu.l2cache.tags.occ_percent::total 0.774450 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.774434 # Average percentage of cache occupancy
672c701
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65376 # Occupied blocks per task id
674c703
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
676,678c705,707
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2162 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6903 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56263 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2163 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6647 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56517 # Occupied blocks per task id
680,689c709,718
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 17138143 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 17138143 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8709 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 844568 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 369661 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1226471 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 595273 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 595273 # number of Writeback hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997559 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 17140869 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 17140869 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8713 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3537 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 844650 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 369794 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1226694 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 595396 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 595396 # number of Writeback hits
692,703c721,732
< system.cpu.l2cache.ReadExReq_hits::cpu.data 113398 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 113398 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 8709 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 844568 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 483059 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1339869 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 8709 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 844568 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 483059 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1339869 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 113396 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 113396 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 8713 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 3537 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 844650 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 483190 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1340090 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 8713 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 3537 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 844650 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 483190 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1340090 # number of overall hits
706c735
< system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 10579 # number of ReadReq misses
708,712c737,741
< system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2905 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133827 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133827 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 20395 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2902 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2902 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133833 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133833 # number of ReadExReq misses
715,716c744,745
< system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 143636 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 10579 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143642 # number of demand (read+write) misses
720,721c749,750
< system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 143636 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 10579 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143642 # number of overall misses
723c752
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 397250 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles
725,727c754,756
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747154500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 739313250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1487015000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 743832250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 729584000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1473871500 # number of ReadReq miss cycles
730,732c759,761
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9526600640 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9526600640 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 397250 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9271605886 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9271605886 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles
734,737c763,766
< system.cpu.l2cache.demand_miss_latency::cpu.inst 747154500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10265913890 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11013615640 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 397250 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 743832250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10001189886 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10745477386 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles
739,762c768,791
< system.cpu.l2cache.overall_miss_latency::cpu.inst 747154500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10265913890 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11013615640 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8714 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 855153 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 379470 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1246872 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 595273 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 595273 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2931 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2931 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 247225 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 247225 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8714 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 855153 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 626695 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1494097 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8714 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 855153 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 626695 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1494097 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 743832250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10001189886 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10745477386 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8718 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3539 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 855229 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 379603 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1247089 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 595396 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 595396 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2928 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2928 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 247229 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 247229 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8718 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 3539 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 855229 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 626832 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1494318 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8718 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 3539 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 855229 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 626832 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1494318 # number of overall (read+write) accesses
764,771c793,800
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025849 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991129 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991129 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541317 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.541317 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012370 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025840 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.016354 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991120 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991120 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541332 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.541332 # miss rate for ReadExReq accesses
773,776c802,805
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.229196 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.103225 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012370 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.229155 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.103210 # miss rate for demand accesses
778,782c807,811
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.229196 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.103225 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79450 # average ReadReq miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012370 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.229155 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.103210 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency
784,791c813,820
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70586.159660 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75370.909369 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72889.319151 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.783133 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.783133 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71185.938861 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71185.938861 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70312.151432 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74379.039657 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72266.315273 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.950379 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.950379 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69277.426987 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69277.426987 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
793,796c822,825
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71411.258915 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69672.675429 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
798,800c827,829
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71411.258915 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69672.675429 # average overall miss latency
809,810c838,839
< system.cpu.l2cache.writebacks::writebacks 57910 # number of writebacks
< system.cpu.l2cache.writebacks::total 57910 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 57911 # number of writebacks
> system.cpu.l2cache.writebacks::total 57911 # number of writebacks
813c842
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10579 # number of ReadReq MSHR misses
815,819c844,848
< system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2905 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133827 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133827 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 20395 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2902 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2902 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133833 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133833 # number of ReadExReq MSHR misses
822,823c851,852
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 143636 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 10579 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143642 # number of demand (read+write) MSHR misses
827,828c856,857
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 143636 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 10579 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143642 # number of overall MSHR misses
830c859
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 335750 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles
832,839c861,868
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 614626500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 616437250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1231524500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29056905 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29056905 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7852026860 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7852026860 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 335750 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 611350250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 606711500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1218429500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29025902 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29025902 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7597036114 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7597036114 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles
841,844c870,873
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 614626500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8468464110 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9083551360 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 335750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611350250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8203747614 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 8815465614 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles
846,856c875,885
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 614626500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8468464110 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9083551360 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 351469750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664489250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167015959000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706272596 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706272596 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 351469750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370761846 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183722231596 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611350250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8203747614 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 8815465614 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 349718500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664427750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014146250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706100672 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706100672 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349718500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370528422 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720246922 # number of overall MSHR uncacheable cycles
858,865c887,894
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025849 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991129 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991129 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541317 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541317 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025840 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016354 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991120 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991120 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541332 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541332 # mshr miss rate for ReadExReq accesses
867,870c896,899
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.103225 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.103210 # mshr miss rate for demand accesses
872,876c901,905
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.103225 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.103210 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency
878,885c907,914
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58065.800661 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62844.046284 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60365.888927 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.376936 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.376936 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.964798 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.964798 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57789.039607 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61852.533388 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59741.578818 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.033770 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.033770 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56765.043853 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56765.043853 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
887,890c916,919
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
892,894c921,923
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency
904,912c933,941
< system.cpu.dcache.tags.replacements 626183 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.875243 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 23656065 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 626695 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 37.747333 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.875243 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999756 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999756 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.replacements 626320 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.875633 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 23655948 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 626832 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 37.738897 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.875633 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
914,916c943,945
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
919,966c948,995
< system.cpu.dcache.tags.tag_accesses 97757735 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 97757735 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 13196205 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13196205 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 9972754 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 9972754 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 236397 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 236397 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 23168959 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 23168959 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 23168959 # number of overall hits
< system.cpu.dcache.overall_hits::total 23168959 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 368088 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 368088 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 250156 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 250156 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 11382 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 11382 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 618244 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 618244 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 618244 # number of overall misses
< system.cpu.dcache.overall_misses::total 618244 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5418733500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5418733500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11526229765 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11526229765 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157891250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 157891250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 16944963265 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16944963265 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16944963265 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16944963265 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13564293 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13564293 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10222910 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10222910 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 23787203 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 23787203 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 23787203 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 23787203 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027137 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.027137 # miss rate for ReadReq accesses
---
> system.cpu.dcache.tags.tag_accesses 97757952 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 97757952 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 13196101 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13196101 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 9972757 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 9972757 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 236378 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236378 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 247784 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 247784 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 23168858 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 23168858 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 23168858 # number of overall hits
> system.cpu.dcache.overall_hits::total 23168858 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 368196 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 368196 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 250157 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 250157 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 11407 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 11407 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 618353 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 618353 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 618353 # number of overall misses
> system.cpu.dcache.overall_misses::total 618353 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5410361250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5410361250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11271639016 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11271639016 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158326750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 158326750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 16682000266 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16682000266 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16682000266 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16682000266 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13564297 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13564297 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10222914 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10222914 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247785 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 247785 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 247784 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 247784 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 23787211 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 23787211 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 23787211 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 23787211 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027144 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.027144 # miss rate for ReadReq accesses
969,984c998,1013
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045936 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045936 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.025991 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.025991 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.025991 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.025991 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 27408.213044 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 27408.213044 # average overall miss latency
---
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046036 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046036 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.025995 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.025995 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.025995 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.025995 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14694.242333 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14694.242333 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45058.259477 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 45058.259477 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13879.788726 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13879.788726 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26978.118107 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26978.118107 # average overall miss latency
993,1022c1022,1051
< system.cpu.dcache.writebacks::writebacks 595273 # number of writebacks
< system.cpu.dcache.writebacks::total 595273 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368088 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 368088 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250156 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 250156 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 618244 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 618244 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 618244 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 618244 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4680319500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4680319500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976351235 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976351235 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135073750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135073750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15656670735 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 15656670735 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15656670735 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 15656670735 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058625250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058625250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242395404 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242395404 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301020654 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301020654 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027137 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027137 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.writebacks::writebacks 595396 # number of writebacks
> system.cpu.dcache.writebacks::total 595396 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368196 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 368196 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250157 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 250157 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11407 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 11407 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 618353 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 618353 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 618353 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 618353 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4671668750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4671668750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10721268984 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10721268984 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135458250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135458250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15392937734 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 15392937734 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15392937734 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 15392937734 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242925328 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242925328 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027144 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027144 # mshr miss rate for ReadReq accesses
1025,1040c1054,1069
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045936 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045936 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.025991 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.025991 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency
---
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046036 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046036 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025995 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025995 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency
1048,1050c1077,1079
< system.cpu.toL2Bus.throughput 52967752 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2454681 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2454681 # Transaction distribution
---
> system.cpu.toL2Bus.throughput 52982138 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 2454896 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2454896 # Transaction distribution
1053,1070c1082,1099
< system.cpu.toL2Bus.trans_dist::Writeback 595273 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2931 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2931 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 247225 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 247225 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725204 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749577 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12461 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27438 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7514680 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54756316 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83620422 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14140 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 138425734 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 138425734 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 166308 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3008713250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::Writeback 595396 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2928 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2928 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 247229 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 247229 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725354 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749970 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12465 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27449 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7515238 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54761180 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83637066 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14156 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34872 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 138447274 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 138447274 # Total data (bytes)
> system.cpu.toL2Bus.snoop_data_through_bus 166176 # Total snoop data (bytes)
> system.cpu.toL2Bus.reqLayer0.occupancy 3009006000 # Layer occupancy (ticks)
1072c1101
< system.cpu.toL2Bus.respLayer0.occupancy 1295332250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1295477750 # Layer occupancy (ticks)
1074c1103
< system.cpu.toL2Bus.respLayer1.occupancy 2533285861 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2533767938 # Layer occupancy (ticks)
1078c1107
< system.cpu.toL2Bus.respLayer3.occupancy 18724250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 18731500 # Layer occupancy (ticks)
1096,1099c1125,1128
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1763840630000 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1759698189250 # number of overall MSHR uncacheable cycles