Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.591442 # Number of seconds simulated
4sim_ticks 2591441692000 # Number of ticks simulated
5final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 879685 # Simulator instruction rate (inst/s)
8host_op_rate 1123921 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38588641896 # Simulator tick rate (ticks/s)
10host_mem_usage 377580 # Number of bytes of host memory used
11host_seconds 67.16 # Real time elapsed on the host

7host_inst_rate 302887 # Simulator instruction rate (inst/s)
8host_op_rate 386981 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 13286578938 # Simulator tick rate (ticks/s)
10host_mem_usage 384192 # Number of bytes of host memory used
11host_seconds 195.04 # Real time elapsed on the host

12sim_insts 59075703 # Number of instructions simulated
13sim_ops 75477535 # Number of ops (including micro ops) simulated

14system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
15system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
17system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory
18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
20system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s)
21system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s)
22system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s)

23system.physmem.bytes_read 133655408 # Number of bytes read from this memory
24system.physmem.bytes_inst_read 949920 # Number of instructions bytes read from this memory
25system.physmem.bytes_written 9634312 # Number of bytes written to this memory
26system.physmem.num_reads 15513098 # Number of read requests responded to by this memory
27system.physmem.num_writes 857428 # Number of write requests responded to by this memory
28system.physmem.num_other 0 # Number of other requests responded to by this memory
29system.physmem.bw_read 51575696 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read 366560 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s)

14system.physmem.bytes_read 133655408 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 949920 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 9634312 # Number of bytes written to this memory
17system.physmem.num_reads 15513098 # Number of read requests responded to by this memory
18system.physmem.num_writes 857428 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 51575696 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 366560 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s)

24system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s)

33system.l2c.replacements 117809 # number of replacements
34system.l2c.tagsinuse 24929.234619 # Cycle average of tags in use
35system.l2c.total_refs 1535239 # Total number of references to valid blocks.
36system.l2c.sampled_refs 146709 # Sample count of references to valid blocks.
37system.l2c.avg_refs 10.464518 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 14588.908290 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor
41system.l2c.occ_blocks::cpu.itb.walker 0.970411 # Average occupied blocks per requestor
42system.l2c.occ_blocks::cpu.inst 5159.303507 # Average occupied blocks per requestor
43system.l2c.occ_blocks::cpu.data 5173.088486 # Average occupied blocks per requestor
44system.l2c.occ_percent::writebacks 0.222609 # Average percentage of cache occupancy
45system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy
46system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
47system.l2c.occ_percent::cpu.inst 0.078725 # Average percentage of cache occupancy
48system.l2c.occ_percent::cpu.data 0.078935 # Average percentage of cache occupancy
49system.l2c.occ_percent::total 0.380390 # Average percentage of cache occupancy
50system.l2c.ReadReq_hits::cpu.dtb.walker 8825 # number of ReadReq hits
51system.l2c.ReadReq_hits::cpu.itb.walker 3670 # number of ReadReq hits
52system.l2c.ReadReq_hits::cpu.inst 837469 # number of ReadReq hits
53system.l2c.ReadReq_hits::cpu.data 360891 # number of ReadReq hits
54system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits
55system.l2c.Writeback_hits::writebacks 610049 # number of Writeback hits
56system.l2c.Writeback_hits::total 610049 # number of Writeback hits
57system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
58system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
59system.l2c.ReadExReq_hits::cpu.data 106473 # number of ReadExReq hits
60system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits
61system.l2c.demand_hits::cpu.dtb.walker 8825 # number of demand (read+write) hits
62system.l2c.demand_hits::cpu.itb.walker 3670 # number of demand (read+write) hits
63system.l2c.demand_hits::cpu.inst 837469 # number of demand (read+write) hits
64system.l2c.demand_hits::cpu.data 467364 # number of demand (read+write) hits
65system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits
66system.l2c.overall_hits::cpu.dtb.walker 8825 # number of overall hits
67system.l2c.overall_hits::cpu.itb.walker 3670 # number of overall hits
68system.l2c.overall_hits::cpu.inst 837469 # number of overall hits
69system.l2c.overall_hits::cpu.data 467364 # number of overall hits
70system.l2c.overall_hits::total 1317328 # number of overall hits
71system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses
72system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses
73system.l2c.ReadReq_misses::cpu.inst 14429 # number of ReadReq misses
74system.l2c.ReadReq_misses::cpu.data 17256 # number of ReadReq misses
75system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses
76system.l2c.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses
77system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
78system.l2c.ReadExReq_misses::cpu.data 140928 # number of ReadExReq misses
79system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses
80system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses
81system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses
82system.l2c.demand_misses::cpu.inst 14429 # number of demand (read+write) misses
83system.l2c.demand_misses::cpu.data 158184 # number of demand (read+write) misses
84system.l2c.demand_misses::total 172650 # number of demand (read+write) misses
85system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses
86system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses
87system.l2c.overall_misses::cpu.inst 14429 # number of overall misses
88system.l2c.overall_misses::cpu.data 158184 # number of overall misses
89system.l2c.overall_misses::total 172650 # number of overall misses
90system.l2c.ReadReq_miss_latency::cpu.dtb.walker 1250000 # number of ReadReq miss cycles
91system.l2c.ReadReq_miss_latency::cpu.itb.walker 676000 # number of ReadReq miss cycles
92system.l2c.ReadReq_miss_latency::cpu.inst 753120500 # number of ReadReq miss cycles
93system.l2c.ReadReq_miss_latency::cpu.data 899469500 # number of ReadReq miss cycles
94system.l2c.ReadReq_miss_latency::total 1654516000 # number of ReadReq miss cycles
95system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
96system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
97system.l2c.ReadExReq_miss_latency::cpu.data 7338006500 # number of ReadExReq miss cycles
98system.l2c.ReadExReq_miss_latency::total 7338006500 # number of ReadExReq miss cycles
99system.l2c.demand_miss_latency::cpu.dtb.walker 1250000 # number of demand (read+write) miss cycles
100system.l2c.demand_miss_latency::cpu.itb.walker 676000 # number of demand (read+write) miss cycles
101system.l2c.demand_miss_latency::cpu.inst 753120500 # number of demand (read+write) miss cycles
102system.l2c.demand_miss_latency::cpu.data 8237476000 # number of demand (read+write) miss cycles
103system.l2c.demand_miss_latency::total 8992522500 # number of demand (read+write) miss cycles
104system.l2c.overall_miss_latency::cpu.dtb.walker 1250000 # number of overall miss cycles
105system.l2c.overall_miss_latency::cpu.itb.walker 676000 # number of overall miss cycles
106system.l2c.overall_miss_latency::cpu.inst 753120500 # number of overall miss cycles
107system.l2c.overall_miss_latency::cpu.data 8237476000 # number of overall miss cycles
108system.l2c.overall_miss_latency::total 8992522500 # number of overall miss cycles
109system.l2c.ReadReq_accesses::cpu.dtb.walker 8849 # number of ReadReq accesses(hits+misses)
110system.l2c.ReadReq_accesses::cpu.itb.walker 3683 # number of ReadReq accesses(hits+misses)
111system.l2c.ReadReq_accesses::cpu.inst 851898 # number of ReadReq accesses(hits+misses)
112system.l2c.ReadReq_accesses::cpu.data 378147 # number of ReadReq accesses(hits+misses)
113system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses)
114system.l2c.Writeback_accesses::writebacks 610049 # number of Writeback accesses(hits+misses)
115system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses)
116system.l2c.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses)
117system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
118system.l2c.ReadExReq_accesses::cpu.data 247401 # number of ReadExReq accesses(hits+misses)
119system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses)
120system.l2c.demand_accesses::cpu.dtb.walker 8849 # number of demand (read+write) accesses
121system.l2c.demand_accesses::cpu.itb.walker 3683 # number of demand (read+write) accesses
122system.l2c.demand_accesses::cpu.inst 851898 # number of demand (read+write) accesses
123system.l2c.demand_accesses::cpu.data 625548 # number of demand (read+write) accesses
124system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses
125system.l2c.overall_accesses::cpu.dtb.walker 8849 # number of overall (read+write) accesses
126system.l2c.overall_accesses::cpu.itb.walker 3683 # number of overall (read+write) accesses
127system.l2c.overall_accesses::cpu.inst 851898 # number of overall (read+write) accesses
128system.l2c.overall_accesses::cpu.data 625548 # number of overall (read+write) accesses
129system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses
130system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002712 # miss rate for ReadReq accesses
131system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003530 # miss rate for ReadReq accesses
132system.l2c.ReadReq_miss_rate::cpu.inst 0.016937 # miss rate for ReadReq accesses
133system.l2c.ReadReq_miss_rate::cpu.data 0.045633 # miss rate for ReadReq accesses
134system.l2c.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses
135system.l2c.ReadExReq_miss_rate::cpu.data 0.569634 # miss rate for ReadExReq accesses
136system.l2c.demand_miss_rate::cpu.dtb.walker 0.002712 # miss rate for demand accesses
137system.l2c.demand_miss_rate::cpu.itb.walker 0.003530 # miss rate for demand accesses
138system.l2c.demand_miss_rate::cpu.inst 0.016937 # miss rate for demand accesses
139system.l2c.demand_miss_rate::cpu.data 0.252873 # miss rate for demand accesses
140system.l2c.overall_miss_rate::cpu.dtb.walker 0.002712 # miss rate for overall accesses
141system.l2c.overall_miss_rate::cpu.itb.walker 0.003530 # miss rate for overall accesses
142system.l2c.overall_miss_rate::cpu.inst 0.016937 # miss rate for overall accesses
143system.l2c.overall_miss_rate::cpu.data 0.252873 # miss rate for overall accesses
144system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52083.333333 # average ReadReq miss latency
145system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
146system.l2c.ReadReq_avg_miss_latency::cpu.inst 52194.919953 # average ReadReq miss latency
147system.l2c.ReadReq_avg_miss_latency::cpu.data 52125.028975 # average ReadReq miss latency
148system.l2c.UpgradeReq_avg_miss_latency::cpu.data 361.739130 # average UpgradeReq miss latency
149system.l2c.ReadExReq_avg_miss_latency::cpu.data 52069.187812 # average ReadExReq miss latency
150system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency
151system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
152system.l2c.demand_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency
153system.l2c.demand_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency
154system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency
155system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
156system.l2c.overall_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency
157system.l2c.overall_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency
158system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
159system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
160system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
161system.l2c.blocked::no_targets 0 # number of cycles access was blocked

162system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
163system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

162system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
163system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

164system.l2c.fast_writes 0 # number of fast writes performed
165system.l2c.cache_copies 0 # number of cache copies performed
166system.l2c.writebacks::writebacks 103410 # number of writebacks
167system.l2c.writebacks::total 103410 # number of writebacks
168system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 24 # number of ReadReq MSHR misses
169system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses
170system.l2c.ReadReq_mshr_misses::cpu.inst 14429 # number of ReadReq MSHR misses
171system.l2c.ReadReq_mshr_misses::cpu.data 17256 # number of ReadReq MSHR misses
172system.l2c.ReadReq_mshr_misses::total 31722 # number of ReadReq MSHR misses
173system.l2c.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses
174system.l2c.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses
175system.l2c.ReadExReq_mshr_misses::cpu.data 140928 # number of ReadExReq MSHR misses
176system.l2c.ReadExReq_mshr_misses::total 140928 # number of ReadExReq MSHR misses
177system.l2c.demand_mshr_misses::cpu.dtb.walker 24 # number of demand (read+write) MSHR misses
178system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses
179system.l2c.demand_mshr_misses::cpu.inst 14429 # number of demand (read+write) MSHR misses
180system.l2c.demand_mshr_misses::cpu.data 158184 # number of demand (read+write) MSHR misses
181system.l2c.demand_mshr_misses::total 172650 # number of demand (read+write) MSHR misses
182system.l2c.overall_mshr_misses::cpu.dtb.walker 24 # number of overall MSHR misses
183system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses
184system.l2c.overall_mshr_misses::cpu.inst 14429 # number of overall MSHR misses
185system.l2c.overall_mshr_misses::cpu.data 158184 # number of overall MSHR misses
186system.l2c.overall_mshr_misses::total 172650 # number of overall MSHR misses
187system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 962000 # number of ReadReq MSHR miss cycles
188system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 520000 # number of ReadReq MSHR miss cycles
189system.l2c.ReadReq_mshr_miss_latency::cpu.inst 579966000 # number of ReadReq MSHR miss cycles
190system.l2c.ReadReq_mshr_miss_latency::cpu.data 692396000 # number of ReadReq MSHR miss cycles
191system.l2c.ReadReq_mshr_miss_latency::total 1273844000 # number of ReadReq MSHR miss cycles
192system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 115156000 # number of UpgradeReq MSHR miss cycles
193system.l2c.UpgradeReq_mshr_miss_latency::total 115156000 # number of UpgradeReq MSHR miss cycles
194system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5646870000 # number of ReadExReq MSHR miss cycles
195system.l2c.ReadExReq_mshr_miss_latency::total 5646870000 # number of ReadExReq MSHR miss cycles
196system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 962000 # number of demand (read+write) MSHR miss cycles
197system.l2c.demand_mshr_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) MSHR miss cycles
198system.l2c.demand_mshr_miss_latency::cpu.inst 579966000 # number of demand (read+write) MSHR miss cycles
199system.l2c.demand_mshr_miss_latency::cpu.data 6339266000 # number of demand (read+write) MSHR miss cycles
200system.l2c.demand_mshr_miss_latency::total 6920714000 # number of demand (read+write) MSHR miss cycles
201system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 962000 # number of overall MSHR miss cycles
202system.l2c.overall_mshr_miss_latency::cpu.itb.walker 520000 # number of overall MSHR miss cycles
203system.l2c.overall_mshr_miss_latency::cpu.inst 579966000 # number of overall MSHR miss cycles
204system.l2c.overall_mshr_miss_latency::cpu.data 6339266000 # number of overall MSHR miss cycles
205system.l2c.overall_mshr_miss_latency::total 6920714000 # number of overall MSHR miss cycles
206system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
207system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131552673000 # number of ReadReq MSHR uncacheable cycles
208system.l2c.ReadReq_mshr_uncacheable_latency::total 131817513000 # number of ReadReq MSHR uncacheable cycles
209system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31206766500 # number of WriteReq MSHR uncacheable cycles
210system.l2c.WriteReq_mshr_uncacheable_latency::total 31206766500 # number of WriteReq MSHR uncacheable cycles
211system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
212system.l2c.overall_mshr_uncacheable_latency::cpu.data 162759439500 # number of overall MSHR uncacheable cycles
213system.l2c.overall_mshr_uncacheable_latency::total 163024279500 # number of overall MSHR uncacheable cycles
214system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for ReadReq accesses
215system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for ReadReq accesses
216system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for ReadReq accesses
217system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.045633 # mshr miss rate for ReadReq accesses
218system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses
219system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569634 # mshr miss rate for ReadExReq accesses
220system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for demand accesses
221system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for demand accesses
222system.l2c.demand_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for demand accesses
223system.l2c.demand_mshr_miss_rate::cpu.data 0.252873 # mshr miss rate for demand accesses
224system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for overall accesses
225system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for overall accesses
226system.l2c.overall_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for overall accesses
227system.l2c.overall_mshr_miss_rate::cpu.data 0.252873 # mshr miss rate for overall accesses
228system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average ReadReq mshr miss latency
229system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
230system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40194.469471 # average ReadReq mshr miss latency
231system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40124.942049 # average ReadReq mshr miss latency
232system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.260870 # average UpgradeReq mshr miss latency
233system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.184264 # average ReadExReq mshr miss latency
234system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average overall mshr miss latency
235system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
236system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40194.469471 # average overall mshr miss latency
237system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.266778 # average overall mshr miss latency
238system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average overall mshr miss latency
239system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
240system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40194.469471 # average overall mshr miss latency
241system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.266778 # average overall mshr miss latency
242system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
243system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
244system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
245system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
246system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
247system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
248system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
249system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
250system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
251system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
252system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
253system.cf0.dma_write_txs 0 # Number of DMA write transactions.
254system.cpu.dtb.inst_hits 0 # ITB inst hits
255system.cpu.dtb.inst_misses 0 # ITB inst misses
256system.cpu.dtb.read_hits 14970649 # DTB read hits
257system.cpu.dtb.read_misses 7343 # DTB read misses
258system.cpu.dtb.write_hits 11215606 # DTB write hits
259system.cpu.dtb.write_misses 2208 # DTB write misses
260system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
261system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
262system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
263system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
264system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
265system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
266system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch
267system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
268system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
269system.cpu.dtb.read_accesses 14977992 # DTB read accesses
270system.cpu.dtb.write_accesses 11217814 # DTB write accesses
271system.cpu.dtb.inst_accesses 0 # ITB inst accesses
272system.cpu.dtb.hits 26186255 # DTB hits
273system.cpu.dtb.misses 9551 # DTB misses
274system.cpu.dtb.accesses 26195806 # DTB accesses
275system.cpu.itb.inst_hits 60357742 # ITB inst hits
276system.cpu.itb.inst_misses 4471 # ITB inst misses
277system.cpu.itb.read_hits 0 # DTB read hits
278system.cpu.itb.read_misses 0 # DTB read misses
279system.cpu.itb.write_hits 0 # DTB write hits
280system.cpu.itb.write_misses 0 # DTB write misses
281system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
282system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
283system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
284system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
285system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
286system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
287system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
288system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
289system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
290system.cpu.itb.read_accesses 0 # DTB read accesses
291system.cpu.itb.write_accesses 0 # DTB write accesses
292system.cpu.itb.inst_accesses 60362213 # ITB inst accesses
293system.cpu.itb.hits 60357742 # DTB hits
294system.cpu.itb.misses 4471 # DTB misses
295system.cpu.itb.accesses 60362213 # DTB accesses
296system.cpu.numCycles 5182883384 # number of cpu cycles simulated
297system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
298system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
299system.cpu.committedInsts 59075703 # Number of instructions committed
300system.cpu.committedOps 75477535 # Number of ops (including micro ops) committed
301system.cpu.num_int_alu_accesses 68255288 # Number of integer alu accesses
302system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
303system.cpu.num_func_calls 1975579 # number of times a function call or return occured
304system.cpu.num_conditional_control_insts 7643992 # number of instructions that are conditional controls
305system.cpu.num_int_insts 68255288 # number of integer instructions
306system.cpu.num_fp_insts 10269 # number of float instructions
307system.cpu.num_int_register_reads 390835490 # number of times the integer registers were read
308system.cpu.num_int_register_writes 72984180 # number of times the integer registers were written
309system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
310system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
311system.cpu.num_mem_refs 27351737 # number of memory refs
312system.cpu.num_load_insts 15632523 # Number of load instructions
313system.cpu.num_store_insts 11719214 # Number of store instructions
314system.cpu.num_idle_cycles 4574345726.482235 # Number of idle cycles
315system.cpu.num_busy_cycles 608537657.517765 # Number of busy cycles
316system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles
317system.cpu.idle_fraction 0.882587 # Percentage of idle cycles
318system.cpu.kern.inst.arm 0 # number of arm instructions executed
319system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed
320system.cpu.icache.replacements 852971 # number of replacements
321system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use
322system.cpu.icache.total_refs 59504259 # Total number of references to valid blocks.
323system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks.
324system.cpu.icache.avg_refs 69.719325 # Average number of references to valid blocks.
325system.cpu.icache.warmup_cycle 18513021000 # Cycle when the warmup percentage was hit.
326system.cpu.icache.occ_blocks::cpu.inst 510.943281 # Average occupied blocks per requestor
327system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy
328system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy
329system.cpu.icache.ReadReq_hits::cpu.inst 59504259 # number of ReadReq hits
330system.cpu.icache.ReadReq_hits::total 59504259 # number of ReadReq hits
331system.cpu.icache.demand_hits::cpu.inst 59504259 # number of demand (read+write) hits
332system.cpu.icache.demand_hits::total 59504259 # number of demand (read+write) hits
333system.cpu.icache.overall_hits::cpu.inst 59504259 # number of overall hits
334system.cpu.icache.overall_hits::total 59504259 # number of overall hits
335system.cpu.icache.ReadReq_misses::cpu.inst 853483 # number of ReadReq misses
336system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses
337system.cpu.icache.demand_misses::cpu.inst 853483 # number of demand (read+write) misses
338system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses
339system.cpu.icache.overall_misses::cpu.inst 853483 # number of overall misses
340system.cpu.icache.overall_misses::total 853483 # number of overall misses
341system.cpu.icache.ReadReq_miss_latency::cpu.inst 12547128000 # number of ReadReq miss cycles
342system.cpu.icache.ReadReq_miss_latency::total 12547128000 # number of ReadReq miss cycles
343system.cpu.icache.demand_miss_latency::cpu.inst 12547128000 # number of demand (read+write) miss cycles
344system.cpu.icache.demand_miss_latency::total 12547128000 # number of demand (read+write) miss cycles
345system.cpu.icache.overall_miss_latency::cpu.inst 12547128000 # number of overall miss cycles
346system.cpu.icache.overall_miss_latency::total 12547128000 # number of overall miss cycles
347system.cpu.icache.ReadReq_accesses::cpu.inst 60357742 # number of ReadReq accesses(hits+misses)
348system.cpu.icache.ReadReq_accesses::total 60357742 # number of ReadReq accesses(hits+misses)
349system.cpu.icache.demand_accesses::cpu.inst 60357742 # number of demand (read+write) accesses
350system.cpu.icache.demand_accesses::total 60357742 # number of demand (read+write) accesses
351system.cpu.icache.overall_accesses::cpu.inst 60357742 # number of overall (read+write) accesses
352system.cpu.icache.overall_accesses::total 60357742 # number of overall (read+write) accesses
353system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014140 # miss rate for ReadReq accesses
354system.cpu.icache.demand_miss_rate::cpu.inst 0.014140 # miss rate for demand accesses
355system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses
356system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14701.087192 # average ReadReq miss latency
357system.cpu.icache.demand_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency
358system.cpu.icache.overall_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency
359system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
360system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
361system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
362system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

363system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
364system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

363system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
364system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

365system.cpu.icache.fast_writes 0 # number of fast writes performed
366system.cpu.icache.cache_copies 0 # number of cache copies performed
367system.cpu.icache.writebacks::writebacks 45661 # number of writebacks
368system.cpu.icache.writebacks::total 45661 # number of writebacks
369system.cpu.icache.ReadReq_mshr_misses::cpu.inst 853483 # number of ReadReq MSHR misses
370system.cpu.icache.ReadReq_mshr_misses::total 853483 # number of ReadReq MSHR misses
371system.cpu.icache.demand_mshr_misses::cpu.inst 853483 # number of demand (read+write) MSHR misses
372system.cpu.icache.demand_mshr_misses::total 853483 # number of demand (read+write) MSHR misses
373system.cpu.icache.overall_mshr_misses::cpu.inst 853483 # number of overall MSHR misses
374system.cpu.icache.overall_mshr_misses::total 853483 # number of overall MSHR misses
375system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9984295500 # number of ReadReq MSHR miss cycles
376system.cpu.icache.ReadReq_mshr_miss_latency::total 9984295500 # number of ReadReq MSHR miss cycles
377system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9984295500 # number of demand (read+write) MSHR miss cycles
378system.cpu.icache.demand_mshr_miss_latency::total 9984295500 # number of demand (read+write) MSHR miss cycles
379system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9984295500 # number of overall MSHR miss cycles
380system.cpu.icache.overall_mshr_miss_latency::total 9984295500 # number of overall MSHR miss cycles
381system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
382system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
383system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
384system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
385system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for ReadReq accesses
386system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for demand accesses
387system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for overall accesses
388system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.294518 # average ReadReq mshr miss latency
389system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency
390system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency
391system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
392system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
393system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.dcache.replacements 626903 # number of replacements
395system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use
396system.cpu.dcache.total_refs 23615099 # Total number of references to valid blocks.
397system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks.
398system.cpu.dcache.avg_refs 37.638722 # Average number of references to valid blocks.
399system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
400system.cpu.dcache.occ_blocks::cpu.data 511.875592 # Average occupied blocks per requestor
401system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
402system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy
403system.cpu.dcache.ReadReq_hits::cpu.data 13170369 # number of ReadReq hits
404system.cpu.dcache.ReadReq_hits::total 13170369 # number of ReadReq hits
405system.cpu.dcache.WriteReq_hits::cpu.data 9958095 # number of WriteReq hits
406system.cpu.dcache.WriteReq_hits::total 9958095 # number of WriteReq hits
407system.cpu.dcache.LoadLockedReq_hits::cpu.data 236142 # number of LoadLockedReq hits
408system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits
409system.cpu.dcache.StoreCondReq_hits::cpu.data 247592 # number of StoreCondReq hits
410system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits
411system.cpu.dcache.demand_hits::cpu.data 23128464 # number of demand (read+write) hits
412system.cpu.dcache.demand_hits::total 23128464 # number of demand (read+write) hits
413system.cpu.dcache.overall_hits::cpu.data 23128464 # number of overall hits
414system.cpu.dcache.overall_hits::total 23128464 # number of overall hits
415system.cpu.dcache.ReadReq_misses::cpu.data 368563 # number of ReadReq misses
416system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses
417system.cpu.dcache.WriteReq_misses::cpu.data 250302 # number of WriteReq misses
418system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses
419system.cpu.dcache.LoadLockedReq_misses::cpu.data 11451 # number of LoadLockedReq misses
420system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses
421system.cpu.dcache.demand_misses::cpu.data 618865 # number of demand (read+write) misses
422system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses
423system.cpu.dcache.overall_misses::cpu.data 618865 # number of overall misses
424system.cpu.dcache.overall_misses::total 618865 # number of overall misses
425system.cpu.dcache.ReadReq_miss_latency::cpu.data 5846897000 # number of ReadReq miss cycles
426system.cpu.dcache.ReadReq_miss_latency::total 5846897000 # number of ReadReq miss cycles
427system.cpu.dcache.WriteReq_miss_latency::cpu.data 9551170500 # number of WriteReq miss cycles
428system.cpu.dcache.WriteReq_miss_latency::total 9551170500 # number of WriteReq miss cycles
429system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186076500 # number of LoadLockedReq miss cycles
430system.cpu.dcache.LoadLockedReq_miss_latency::total 186076500 # number of LoadLockedReq miss cycles
431system.cpu.dcache.demand_miss_latency::cpu.data 15398067500 # number of demand (read+write) miss cycles
432system.cpu.dcache.demand_miss_latency::total 15398067500 # number of demand (read+write) miss cycles
433system.cpu.dcache.overall_miss_latency::cpu.data 15398067500 # number of overall miss cycles
434system.cpu.dcache.overall_miss_latency::total 15398067500 # number of overall miss cycles
435system.cpu.dcache.ReadReq_accesses::cpu.data 13538932 # number of ReadReq accesses(hits+misses)
436system.cpu.dcache.ReadReq_accesses::total 13538932 # number of ReadReq accesses(hits+misses)
437system.cpu.dcache.WriteReq_accesses::cpu.data 10208397 # number of WriteReq accesses(hits+misses)
438system.cpu.dcache.WriteReq_accesses::total 10208397 # number of WriteReq accesses(hits+misses)
439system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247593 # number of LoadLockedReq accesses(hits+misses)
440system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses)
441system.cpu.dcache.StoreCondReq_accesses::cpu.data 247592 # number of StoreCondReq accesses(hits+misses)
442system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses)
443system.cpu.dcache.demand_accesses::cpu.data 23747329 # number of demand (read+write) accesses
444system.cpu.dcache.demand_accesses::total 23747329 # number of demand (read+write) accesses
445system.cpu.dcache.overall_accesses::cpu.data 23747329 # number of overall (read+write) accesses
446system.cpu.dcache.overall_accesses::total 23747329 # number of overall (read+write) accesses
447system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027222 # miss rate for ReadReq accesses
448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024519 # miss rate for WriteReq accesses
449system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046249 # miss rate for LoadLockedReq accesses
450system.cpu.dcache.demand_miss_rate::cpu.data 0.026060 # miss rate for demand accesses
451system.cpu.dcache.overall_miss_rate::cpu.data 0.026060 # miss rate for overall accesses
452system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15864.036813 # average ReadReq miss latency
453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428 # average WriteReq miss latency
454system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511 # average LoadLockedReq miss latency
455system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency
456system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency
457system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
458system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
459system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
460system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

461system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
462system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

461system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
462system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

463system.cpu.dcache.fast_writes 0 # number of fast writes performed
464system.cpu.dcache.cache_copies 0 # number of cache copies performed
465system.cpu.dcache.writebacks::writebacks 564388 # number of writebacks
466system.cpu.dcache.writebacks::total 564388 # number of writebacks
467system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368563 # number of ReadReq MSHR misses
468system.cpu.dcache.ReadReq_mshr_misses::total 368563 # number of ReadReq MSHR misses
469system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250302 # number of WriteReq MSHR misses
470system.cpu.dcache.WriteReq_mshr_misses::total 250302 # number of WriteReq MSHR misses
471system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11451 # number of LoadLockedReq MSHR misses
472system.cpu.dcache.LoadLockedReq_mshr_misses::total 11451 # number of LoadLockedReq MSHR misses
473system.cpu.dcache.demand_mshr_misses::cpu.data 618865 # number of demand (read+write) MSHR misses
474system.cpu.dcache.demand_mshr_misses::total 618865 # number of demand (read+write) MSHR misses
475system.cpu.dcache.overall_mshr_misses::cpu.data 618865 # number of overall MSHR misses
476system.cpu.dcache.overall_mshr_misses::total 618865 # number of overall MSHR misses
477system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741074500 # number of ReadReq MSHR miss cycles
478system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741074500 # number of ReadReq MSHR miss cycles
479system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800219500 # number of WriteReq MSHR miss cycles
480system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800219500 # number of WriteReq MSHR miss cycles
481system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151723500 # number of LoadLockedReq MSHR miss cycles
482system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151723500 # number of LoadLockedReq MSHR miss cycles
483system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13541294000 # number of demand (read+write) MSHR miss cycles
484system.cpu.dcache.demand_mshr_miss_latency::total 13541294000 # number of demand (read+write) MSHR miss cycles
485system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13541294000 # number of overall MSHR miss cycles
486system.cpu.dcache.overall_mshr_miss_latency::total 13541294000 # number of overall MSHR miss cycles
487system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146946835000 # number of ReadReq MSHR uncacheable cycles
488system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146946835000 # number of ReadReq MSHR uncacheable cycles
489system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367455500 # number of WriteReq MSHR uncacheable cycles
490system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367455500 # number of WriteReq MSHR uncacheable cycles
491system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187314290500 # number of overall MSHR uncacheable cycles
492system.cpu.dcache.overall_mshr_uncacheable_latency::total 187314290500 # number of overall MSHR uncacheable cycles
493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027222 # mshr miss rate for ReadReq accesses
494system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024519 # mshr miss rate for WriteReq accesses
495system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046249 # mshr miss rate for LoadLockedReq accesses
496system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for demand accesses
497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for overall accesses
498system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12863.674596 # average ReadReq mshr miss latency
499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35158.406645 # average WriteReq mshr miss latency
500system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13249.803511 # average LoadLockedReq mshr miss latency
501system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency
502system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency
503system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
504system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
505system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
506system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
507system.iocache.replacements 0 # number of replacements
508system.iocache.tagsinuse 0 # Cycle average of tags in use
509system.iocache.total_refs 0 # Total number of references to valid blocks.
510system.iocache.sampled_refs 0 # Sample count of references to valid blocks.

511system.iocache.avg_refs no_value # Average number of references to valid blocks.

511system.iocache.avg_refs nan # Average number of references to valid blocks.

512system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
513system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
514system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
515system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
516system.iocache.blocked::no_targets 0 # number of cycles access was blocked

517system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
518system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

517system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
518system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked