1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.615716 # Number of seconds simulated
4sim_ticks 2615716222000 # Number of ticks simulated
5final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 250038 # Simulator instruction rate (inst/s)
8host_op_rate 318184 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 10864403710 # Simulator tick rate (ticks/s)
10host_mem_usage 394540 # Number of bytes of host memory used
11host_seconds 240.76 # Real time elapsed on the host
12sim_insts 60199078 # Number of instructions simulated
13sim_ops 76605946 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory
19system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory
23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory
25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory
32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller
53system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller
54system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
55system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
56system.physmem.bytesRead 991665344 # Total number of bytes read from memory
57system.physmem.bytesWritten 51967296 # Total number of bytes written to memory
58system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize()
59system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize()
60system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q
61system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed
62system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis
75system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis
76system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis
77system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis
78system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis
91system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis
92system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis
93system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis
94system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
95system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
96system.physmem.totGap 2615711849000 # Total gap between requests
97system.physmem.readPktSize::0 0 # Categorize read packet sizes
98system.physmem.readPktSize::1 0 # Categorize read packet sizes
99system.physmem.readPktSize::2 6652 # Categorize read packet sizes
100system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
101system.physmem.readPktSize::4 0 # Categorize read packet sizes
102system.physmem.readPktSize::5 0 # Categorize read packet sizes
103system.physmem.readPktSize::6 152695 # Categorize read packet sizes
104system.physmem.writePktSize::0 0 # Categorize write packet sizes
105system.physmem.writePktSize::1 0 # Categorize write packet sizes
106system.physmem.writePktSize::2 754018 # Categorize write packet sizes
107system.physmem.writePktSize::3 0 # Categorize write packet sizes
108system.physmem.writePktSize::4 0 # Categorize write packet sizes
109system.physmem.writePktSize::5 0 # Categorize write packet sizes
110system.physmem.writePktSize::6 57971 # Categorize write packet sizes
111system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
143system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::2 4662 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::3 4662 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::4 4662 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::5 4662 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::6 4662 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::7 4662 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::8 4662 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::9 4662 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::10 4662 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::11 4662 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::12 4662 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::13 4662 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::14 4662 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::15 4662 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::16 4662 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::17 4662 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::18 4662 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::19 4662 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::20 4662 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::21 4662 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::22 4662 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
175system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation
176system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation
177system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation
178system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation
179system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::3328-3391 16 0.04% 57.74% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.75% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::3520-3583 6 0.02% 57.80% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::3584-3647 5 0.01% 57.81% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::3648-3711 5 0.01% 57.82% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::3776-3839 6 0.02% 57.86% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::3840-3903 6 0.02% 57.87% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.89% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::3968-4031 9 0.02% 57.91% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.94% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4096-4159 42 0.11% 58.05% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4160-4223 2 0.01% 58.05% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.06% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4288-4351 4 0.01% 58.07% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::4352-4415 8 0.02% 58.09% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.11% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::4480-4543 4 0.01% 58.12% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.13% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::4608-4671 5 0.01% 58.15% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::4672-4735 6 0.02% 58.16% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::4736-4799 2 0.01% 58.17% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::4800-4863 1 0.00% 58.17% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::4864-4927 6 0.02% 58.19% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::4928-4991 1 0.00% 58.19% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.20% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.20% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5120-5183 10 0.03% 58.23% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5248-5311 2 0.01% 58.24% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::5312-5375 5 0.01% 58.25% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::5440-5503 2 0.01% 58.27% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::5504-5567 3 0.01% 58.27% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::5568-5631 3 0.01% 58.28% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.29% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::5760-5823 3 0.01% 58.30% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::5888-5951 1 0.00% 58.30% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::5952-6015 2 0.01% 58.30% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.31% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::6144-6207 2 0.01% 58.31% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::6272-6335 2 0.01% 58.32% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::6336-6399 1 0.00% 58.32% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::6464-6527 4 0.01% 58.33% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::6528-6591 1 0.00% 58.34% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.34% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::6656-6719 1 0.00% 58.34% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::6720-6783 6 0.02% 58.36% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::6784-6847 16 0.04% 58.40% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::6848-6911 4 0.01% 58.41% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::6976-7039 4 0.01% 58.42% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::7040-7103 4 0.01% 58.43% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.43% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.44% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::7232-7295 2 0.01% 58.45% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::7360-7423 2 0.01% 58.45% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.46% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.47% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.47% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.48% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::7680-7743 5 0.01% 58.50% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::7744-7807 2 0.01% 58.50% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.51% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.52% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::7936-7999 7 0.02% 58.54% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::8000-8063 6 0.02% 58.56% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::8064-8127 8 0.02% 58.58% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::8128-8191 8 0.02% 58.60% # Bytes accessed per row activation
299system.physmem.bytesPerActivate::8192-8255 328 0.86% 59.46% # Bytes accessed per row activation
300system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.46% # Bytes accessed per row activation
301system.physmem.bytesPerActivate::8448-8511 24 0.06% 59.53% # Bytes accessed per row activation
302system.physmem.bytesPerActivate::8512-8575 141 0.37% 59.90% # Bytes accessed per row activation
303system.physmem.bytesPerActivate::8576-8639 169 0.44% 60.34% # Bytes accessed per row activation
304system.physmem.bytesPerActivate::8704-8767 1 0.00% 60.34% # Bytes accessed per row activation
305system.physmem.bytesPerActivate::8768-8831 1 0.00% 60.34% # Bytes accessed per row activation
306system.physmem.bytesPerActivate::8832-8895 2 0.01% 60.35% # Bytes accessed per row activation
307system.physmem.bytesPerActivate::8960-9023 3 0.01% 60.36% # Bytes accessed per row activation
308system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation
309system.physmem.bytesPerActivate::9472-9535 1 0.00% 60.37% # Bytes accessed per row activation
310system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation
311system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation
312system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation
313system.physmem.bytesPerActivate::12032-12095 2 0.01% 60.39% # Bytes accessed per row activation
314system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation
315system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation
316system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation
317system.physmem.bytesPerActivate::13312-13375 1 0.00% 60.41% # Bytes accessed per row activation
318system.physmem.bytesPerActivate::13824-13887 1 0.00% 60.41% # Bytes accessed per row activation
319system.physmem.bytesPerActivate::13952-14015 1 0.00% 60.41% # Bytes accessed per row activation
320system.physmem.bytesPerActivate::14336-14399 4 0.01% 60.42% # Bytes accessed per row activation
321system.physmem.bytesPerActivate::14592-14655 1 0.00% 60.43% # Bytes accessed per row activation
322system.physmem.bytesPerActivate::14976-15039 1 0.00% 60.43% # Bytes accessed per row activation
323system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.43% # Bytes accessed per row activation
324system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.44% # Bytes accessed per row activation
325system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.44% # Bytes accessed per row activation
326system.physmem.bytesPerActivate::16640-16703 1 0.00% 60.44% # Bytes accessed per row activation
327system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.44% # Bytes accessed per row activation
328system.physmem.bytesPerActivate::17408-17471 3 0.01% 60.45% # Bytes accessed per row activation
329system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.45% # Bytes accessed per row activation
330system.physmem.bytesPerActivate::18176-18239 2 0.01% 60.46% # Bytes accessed per row activation
331system.physmem.bytesPerActivate::18432-18495 5 0.01% 60.47% # Bytes accessed per row activation
332system.physmem.bytesPerActivate::18624-18687 1 0.00% 60.48% # Bytes accessed per row activation
333system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.48% # Bytes accessed per row activation
334system.physmem.bytesPerActivate::19328-19391 1 0.00% 60.48% # Bytes accessed per row activation
335system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.49% # Bytes accessed per row activation
336system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.49% # Bytes accessed per row activation
337system.physmem.bytesPerActivate::20352-20415 1 0.00% 60.49% # Bytes accessed per row activation
338system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.50% # Bytes accessed per row activation
339system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.50% # Bytes accessed per row activation
340system.physmem.bytesPerActivate::22016-22079 2 0.01% 60.50% # Bytes accessed per row activation
341system.physmem.bytesPerActivate::22144-22207 1 0.00% 60.51% # Bytes accessed per row activation
342system.physmem.bytesPerActivate::22272-22335 1 0.00% 60.51% # Bytes accessed per row activation
343system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.51% # Bytes accessed per row activation
344system.physmem.bytesPerActivate::23040-23103 1 0.00% 60.52% # Bytes accessed per row activation
345system.physmem.bytesPerActivate::23168-23231 1 0.00% 60.52% # Bytes accessed per row activation
346system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.52% # Bytes accessed per row activation
347system.physmem.bytesPerActivate::23552-23615 4 0.01% 60.53% # Bytes accessed per row activation
348system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.53% # Bytes accessed per row activation
349system.physmem.bytesPerActivate::24192-24255 1 0.00% 60.54% # Bytes accessed per row activation
350system.physmem.bytesPerActivate::24320-24383 3 0.01% 60.54% # Bytes accessed per row activation
351system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.55% # Bytes accessed per row activation
352system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.55% # Bytes accessed per row activation
353system.physmem.bytesPerActivate::25088-25151 1 0.00% 60.55% # Bytes accessed per row activation
354system.physmem.bytesPerActivate::25344-25407 1 0.00% 60.55% # Bytes accessed per row activation
355system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.56% # Bytes accessed per row activation
356system.physmem.bytesPerActivate::25728-25791 1 0.00% 60.56% # Bytes accessed per row activation
357system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation
358system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation
359system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation
360system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation
361system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation
362system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation
363system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation
364system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation
365system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation
366system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation
367system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation
368system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation
369system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation
370system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation
371system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation
372system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation
373system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation
374system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation
375system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation
376system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation
377system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation
378system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation
379system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation
380system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation
381system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation
382system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation
383system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation
384system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation
385system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation
386system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation
387system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation
388system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation
389system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation
390system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation
391system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation
392system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation
393system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation
394system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation
395system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation
396system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation
397system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation
398system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation
399system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation
400system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation
401system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation
402system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation
403system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation
404system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation
405system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation
406system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation
407system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation
408system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation
409system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation
410system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation
411system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation
412system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation
413system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation
414system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation
415system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation
416system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation
417system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation
418system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation
419system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation
420system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation
421system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation
422system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation
423system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation
424system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation
425system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation
426system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation
427system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
428system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation
429system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays
430system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests
431system.physmem.totBusLat 77465575000 # Total cycles spent in databus access
432system.physmem.totBankLat 16358058750 # Total cycles spent in bank access
433system.physmem.avgQLat 19154.87 # Average queueing delay per request
434system.physmem.avgBankLat 1055.83 # Average bank access latency per request
435system.physmem.avgBusLat 5000.00 # Average bus latency per request
436system.physmem.avgMemAccLat 25210.70 # Average memory access latency
437system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s
438system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s
439system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s
440system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
441system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
442system.physmem.busUtil 3.12 # Data bus utilization in percentage
443system.physmem.avgRdQLen 0.15 # Average read queue length over time
444system.physmem.avgWrQLen 13.76 # Average write queue length over time
445system.physmem.readRowHits 15468398 # Number of row buffer hits during reads
446system.physmem.writeRowHits 93875 # Number of row buffer hits during writes
447system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
448system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes
449system.physmem.avgGap 160406.60 # Average gap between requests
450system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
451system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
452system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
453system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
454system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
455system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
456system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
457system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
458system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
459system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
460system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
461system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
462system.membus.throughput 54136917 # Throughput (bytes/s)
463system.membus.trans_dist::ReadReq 16546596 # Transaction distribution
464system.membus.trans_dist::ReadResp 16546596 # Transaction distribution
465system.membus.trans_dist::WriteReq 763368 # Transaction distribution
466system.membus.trans_dist::WriteResp 763368 # Transaction distribution
467system.membus.trans_dist::Writeback 57971 # Transaction distribution
468system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution
469system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution
470system.membus.trans_dist::ReadExReq 132250 # Transaction distribution
471system.membus.trans_dist::ReadExResp 132250 # Transaction distribution
472system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
473system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
475system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
476system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes)
477system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes)
478system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
479system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
480system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes)
481system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
482system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
483system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
484system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
485system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes)
486system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes)
487system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
488system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
489system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes)
490system.membus.data_through_bus 141606813 # Total data (bytes)
491system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
492system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks)
493system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
494system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
495system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
496system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks)
497system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
498system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
499system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
500system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks)
501system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
502system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks)
503system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
504system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks)
505system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
506system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
507system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
508system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
509system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
510system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
511system.cf0.dma_write_txs 0 # Number of DMA write transactions.
512system.iobus.throughput 47816267 # Throughput (bytes/s)
513system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution
514system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution
515system.iobus.trans_dist::WriteReq 8166 # Transaction distribution
516system.iobus.trans_dist::WriteResp 8166 # Transaction distribution
517system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
518system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
519system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
520system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
521system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
522system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
523system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
524system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
525system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
526system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)

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532system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
533system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
534system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
535system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
536system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
537system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
538system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
539system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
540system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes)
541system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
542system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
543system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes)
544system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
545system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
546system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
547system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
548system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
549system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
550system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
551system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
552system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
553system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)

--- 5 unchanged lines hidden (view full) ---

559system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
560system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
561system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
562system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
563system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
564system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
565system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
566system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
567system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes)
568system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
569system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
570system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes)
571system.iobus.data_through_bus 125073785 # Total data (bytes)
572system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
573system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
574system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
575system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
576system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
577system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
578system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
579system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
580system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
581system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
582system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)

--- 29 unchanged lines hidden (view full) ---

612system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
613system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
614system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
615system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
616system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
617system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
618system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
619system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
620system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks)
621system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
622system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks)
623system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
624system.cpu.dtb.inst_hits 0 # ITB inst hits
625system.cpu.dtb.inst_misses 0 # ITB inst misses
626system.cpu.dtb.read_hits 14996146 # DTB read hits
627system.cpu.dtb.read_misses 7341 # DTB read misses
628system.cpu.dtb.write_hits 11230467 # DTB write hits
629system.cpu.dtb.write_misses 2217 # DTB write misses
630system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
631system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
632system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
633system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
634system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB
635system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
636system.cpu.dtb.prefetch_faults 197 # Number of TLB faults due to prefetch
637system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
638system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
639system.cpu.dtb.read_accesses 15003487 # DTB read accesses
640system.cpu.dtb.write_accesses 11232684 # DTB write accesses
641system.cpu.dtb.inst_accesses 0 # ITB inst accesses
642system.cpu.dtb.hits 26226613 # DTB hits
643system.cpu.dtb.misses 9558 # DTB misses
644system.cpu.dtb.accesses 26236171 # DTB accesses
645system.cpu.itb.inst_hits 61492923 # ITB inst hits
646system.cpu.itb.inst_misses 4471 # ITB inst misses
647system.cpu.itb.read_hits 0 # DTB read hits
648system.cpu.itb.read_misses 0 # DTB read misses
649system.cpu.itb.write_hits 0 # DTB write hits
650system.cpu.itb.write_misses 0 # DTB write misses
651system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
652system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
653system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
654system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
655system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
656system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
657system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
658system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
659system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
660system.cpu.itb.read_accesses 0 # DTB read accesses
661system.cpu.itb.write_accesses 0 # DTB write accesses
662system.cpu.itb.inst_accesses 61497394 # ITB inst accesses
663system.cpu.itb.hits 61492923 # DTB hits
664system.cpu.itb.misses 4471 # DTB misses
665system.cpu.itb.accesses 61497394 # DTB accesses
666system.cpu.numCycles 5231432444 # number of cpu cycles simulated
667system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
668system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
669system.cpu.committedInsts 60199078 # Number of instructions committed
670system.cpu.committedOps 76605946 # Number of ops (including micro ops) committed
671system.cpu.num_int_alu_accesses 68872726 # Number of integer alu accesses
672system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
673system.cpu.num_func_calls 2140465 # number of times a function call or return occured
674system.cpu.num_conditional_control_insts 7948429 # number of instructions that are conditional controls
675system.cpu.num_int_insts 68872726 # number of integer instructions
676system.cpu.num_fp_insts 10269 # number of float instructions
677system.cpu.num_int_register_reads 394779183 # number of times the integer registers were read
678system.cpu.num_int_register_writes 74182470 # number of times the integer registers were written
679system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
680system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
681system.cpu.num_mem_refs 27394080 # number of memory refs
682system.cpu.num_load_insts 15660200 # Number of load instructions
683system.cpu.num_store_insts 11733880 # Number of store instructions
684system.cpu.num_idle_cycles 4581975478.612248 # Number of idle cycles
685system.cpu.num_busy_cycles 649456965.387752 # Number of busy cycles
686system.cpu.not_idle_fraction 0.124145 # Percentage of non-idle cycles
687system.cpu.idle_fraction 0.875855 # Percentage of idle cycles
688system.cpu.kern.inst.arm 0 # number of arm instructions executed
689system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
690system.cpu.icache.tags.replacements 856273 # number of replacements
691system.cpu.icache.tags.tagsinuse 510.884220 # Cycle average of tags in use
692system.cpu.icache.tags.total_refs 60636138 # Total number of references to valid blocks.
693system.cpu.icache.tags.sampled_refs 856785 # Sample count of references to valid blocks.
694system.cpu.icache.tags.avg_refs 70.771708 # Average number of references to valid blocks.
695system.cpu.icache.tags.warmup_cycle 19799760250 # Cycle when the warmup percentage was hit.
696system.cpu.icache.tags.occ_blocks::cpu.inst 510.884220 # Average occupied blocks per requestor
697system.cpu.icache.tags.occ_percent::cpu.inst 0.997821 # Average percentage of cache occupancy
698system.cpu.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy
699system.cpu.icache.ReadReq_hits::cpu.inst 60636138 # number of ReadReq hits
700system.cpu.icache.ReadReq_hits::total 60636138 # number of ReadReq hits
701system.cpu.icache.demand_hits::cpu.inst 60636138 # number of demand (read+write) hits
702system.cpu.icache.demand_hits::total 60636138 # number of demand (read+write) hits
703system.cpu.icache.overall_hits::cpu.inst 60636138 # number of overall hits
704system.cpu.icache.overall_hits::total 60636138 # number of overall hits
705system.cpu.icache.ReadReq_misses::cpu.inst 856785 # number of ReadReq misses
706system.cpu.icache.ReadReq_misses::total 856785 # number of ReadReq misses
707system.cpu.icache.demand_misses::cpu.inst 856785 # number of demand (read+write) misses
708system.cpu.icache.demand_misses::total 856785 # number of demand (read+write) misses
709system.cpu.icache.overall_misses::cpu.inst 856785 # number of overall misses
710system.cpu.icache.overall_misses::total 856785 # number of overall misses
711system.cpu.icache.ReadReq_miss_latency::cpu.inst 11770019500 # number of ReadReq miss cycles
712system.cpu.icache.ReadReq_miss_latency::total 11770019500 # number of ReadReq miss cycles
713system.cpu.icache.demand_miss_latency::cpu.inst 11770019500 # number of demand (read+write) miss cycles
714system.cpu.icache.demand_miss_latency::total 11770019500 # number of demand (read+write) miss cycles
715system.cpu.icache.overall_miss_latency::cpu.inst 11770019500 # number of overall miss cycles
716system.cpu.icache.overall_miss_latency::total 11770019500 # number of overall miss cycles
717system.cpu.icache.ReadReq_accesses::cpu.inst 61492923 # number of ReadReq accesses(hits+misses)
718system.cpu.icache.ReadReq_accesses::total 61492923 # number of ReadReq accesses(hits+misses)
719system.cpu.icache.demand_accesses::cpu.inst 61492923 # number of demand (read+write) accesses
720system.cpu.icache.demand_accesses::total 61492923 # number of demand (read+write) accesses
721system.cpu.icache.overall_accesses::cpu.inst 61492923 # number of overall (read+write) accesses
722system.cpu.icache.overall_accesses::total 61492923 # number of overall (read+write) accesses
723system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses
724system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses
725system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses
726system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses
727system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses
728system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses
729system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13737.424792 # average ReadReq miss latency
730system.cpu.icache.ReadReq_avg_miss_latency::total 13737.424792 # average ReadReq miss latency
731system.cpu.icache.demand_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency
732system.cpu.icache.demand_avg_miss_latency::total 13737.424792 # average overall miss latency
733system.cpu.icache.overall_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency
734system.cpu.icache.overall_avg_miss_latency::total 13737.424792 # average overall miss latency
735system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
736system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
737system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
738system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
739system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
740system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
741system.cpu.icache.fast_writes 0 # number of fast writes performed
742system.cpu.icache.cache_copies 0 # number of cache copies performed
743system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856785 # number of ReadReq MSHR misses
744system.cpu.icache.ReadReq_mshr_misses::total 856785 # number of ReadReq MSHR misses
745system.cpu.icache.demand_mshr_misses::cpu.inst 856785 # number of demand (read+write) MSHR misses
746system.cpu.icache.demand_mshr_misses::total 856785 # number of demand (read+write) MSHR misses
747system.cpu.icache.overall_mshr_misses::cpu.inst 856785 # number of overall MSHR misses
748system.cpu.icache.overall_mshr_misses::total 856785 # number of overall MSHR misses
749system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051263500 # number of ReadReq MSHR miss cycles
750system.cpu.icache.ReadReq_mshr_miss_latency::total 10051263500 # number of ReadReq MSHR miss cycles
751system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051263500 # number of demand (read+write) MSHR miss cycles
752system.cpu.icache.demand_mshr_miss_latency::total 10051263500 # number of demand (read+write) MSHR miss cycles
753system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051263500 # number of overall MSHR miss cycles
754system.cpu.icache.overall_mshr_miss_latency::total 10051263500 # number of overall MSHR miss cycles
755system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 414413750 # number of ReadReq MSHR uncacheable cycles
756system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles
757system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 414413750 # number of overall MSHR uncacheable cycles
758system.cpu.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles
759system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses
760system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses
761system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses
762system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses
763system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses
764system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses
765system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.371931 # average ReadReq mshr miss latency
766system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.371931 # average ReadReq mshr miss latency
767system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency
768system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency
769system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency
770system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency
771system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
772system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
773system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
774system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
775system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
776system.cpu.l2cache.tags.replacements 62587 # number of replacements
777system.cpu.l2cache.tags.tagsinuse 50733.810806 # Cycle average of tags in use
778system.cpu.l2cache.tags.total_refs 1683077 # Total number of references to valid blocks.
779system.cpu.l2cache.tags.sampled_refs 127973 # Sample count of references to valid blocks.
780system.cpu.l2cache.tags.avg_refs 13.151813 # Average number of references to valid blocks.
781system.cpu.l2cache.tags.warmup_cycle 2564904211000 # Cycle when the warmup percentage was hit.
782system.cpu.l2cache.tags.occ_blocks::writebacks 37696.862224 # Average occupied blocks per requestor
783system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884576 # Average occupied blocks per requestor
784system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor
785system.cpu.l2cache.tags.occ_blocks::cpu.inst 6998.396772 # Average occupied blocks per requestor
786system.cpu.l2cache.tags.occ_blocks::cpu.data 6034.666541 # Average occupied blocks per requestor
787system.cpu.l2cache.tags.occ_percent::writebacks 0.575208 # Average percentage of cache occupancy
788system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
789system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
790system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106787 # Average percentage of cache occupancy
791system.cpu.l2cache.tags.occ_percent::cpu.data 0.092082 # Average percentage of cache occupancy
792system.cpu.l2cache.tags.occ_percent::total 0.774137 # Average percentage of cache occupancy
793system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits
794system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits
795system.cpu.l2cache.ReadReq_hits::cpu.inst 844543 # number of ReadReq hits
796system.cpu.l2cache.ReadReq_hits::cpu.data 370162 # number of ReadReq hits
797system.cpu.l2cache.ReadReq_hits::total 1226960 # number of ReadReq hits
798system.cpu.l2cache.Writeback_hits::writebacks 595785 # number of Writeback hits
799system.cpu.l2cache.Writeback_hits::total 595785 # number of Writeback hits
800system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
801system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
802system.cpu.l2cache.ReadExReq_hits::cpu.data 113425 # number of ReadExReq hits
803system.cpu.l2cache.ReadExReq_hits::total 113425 # number of ReadExReq hits
804system.cpu.l2cache.demand_hits::cpu.dtb.walker 8720 # number of demand (read+write) hits
805system.cpu.l2cache.demand_hits::cpu.itb.walker 3535 # number of demand (read+write) hits
806system.cpu.l2cache.demand_hits::cpu.inst 844543 # number of demand (read+write) hits
807system.cpu.l2cache.demand_hits::cpu.data 483587 # number of demand (read+write) hits
808system.cpu.l2cache.demand_hits::total 1340385 # number of demand (read+write) hits
809system.cpu.l2cache.overall_hits::cpu.dtb.walker 8720 # number of overall hits
810system.cpu.l2cache.overall_hits::cpu.itb.walker 3535 # number of overall hits
811system.cpu.l2cache.overall_hits::cpu.inst 844543 # number of overall hits
812system.cpu.l2cache.overall_hits::cpu.data 483587 # number of overall hits
813system.cpu.l2cache.overall_hits::total 1340385 # number of overall hits
814system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
815system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
816system.cpu.l2cache.ReadReq_misses::cpu.inst 10601 # number of ReadReq misses
817system.cpu.l2cache.ReadReq_misses::cpu.data 9837 # number of ReadReq misses
818system.cpu.l2cache.ReadReq_misses::total 20445 # number of ReadReq misses
819system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses
820system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses
821system.cpu.l2cache.ReadExReq_misses::cpu.data 133893 # number of ReadExReq misses
822system.cpu.l2cache.ReadExReq_misses::total 133893 # number of ReadExReq misses
823system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
824system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
825system.cpu.l2cache.demand_misses::cpu.inst 10601 # number of demand (read+write) misses
826system.cpu.l2cache.demand_misses::cpu.data 143730 # number of demand (read+write) misses
827system.cpu.l2cache.demand_misses::total 154338 # number of demand (read+write) misses
828system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
829system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
830system.cpu.l2cache.overall_misses::cpu.inst 10601 # number of overall misses
831system.cpu.l2cache.overall_misses::cpu.data 143730 # number of overall misses
832system.cpu.l2cache.overall_misses::total 154338 # number of overall misses
833system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 390500 # number of ReadReq miss cycles
834system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122500 # number of ReadReq miss cycles
835system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747407000 # number of ReadReq miss cycles
836system.cpu.l2cache.ReadReq_miss_latency::cpu.data 696870750 # number of ReadReq miss cycles
837system.cpu.l2cache.ReadReq_miss_latency::total 1444790750 # number of ReadReq miss cycles
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893system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61250 # average ReadReq miss latency
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898system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.990251 # average UpgradeReq miss latency
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900system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64298.119446 # average ReadExReq miss latency
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902system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency
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907system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency
908system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency
909system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency
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916system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
917system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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961system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166980137500 # number of ReadReq MSHR uncacheable cycles
962system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702542535 # number of WriteReq MSHR uncacheable cycles
963system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702542535 # number of WriteReq MSHR uncacheable cycles
964system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 322980250 # number of overall MSHR uncacheable cycles
965system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359699785 # number of overall MSHR uncacheable cycles
966system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183682680035 # number of overall MSHR uncacheable cycles
967system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses
968system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses
969system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses
970system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025887 # mshr miss rate for ReadReq accesses
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972system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses
973system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses
974system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541380 # mshr miss rate for ReadExReq accesses
975system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541380 # mshr miss rate for ReadExReq accesses
976system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses
977system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses
978system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for demand accesses
979system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses
980system.cpu.l2cache.demand_mshr_miss_rate::total 0.103255 # mshr miss rate for demand accesses
981system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses
982system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses
983system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for overall accesses
984system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for overall accesses
985system.cpu.l2cache.overall_mshr_miss_rate::total 0.103255 # mshr miss rate for overall accesses
986system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average ReadReq mshr miss latency
987system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency
988system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57913.923215 # average ReadReq mshr miss latency
989system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58212.285250 # average ReadReq mshr miss latency
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991system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.044568 # average UpgradeReq mshr miss latency
992system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.044568 # average UpgradeReq mshr miss latency
993system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51782.777240 # average ReadExReq mshr miss latency
994system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51782.777240 # average ReadExReq mshr miss latency
995system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency
996system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency
997system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency
998system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency
999system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency
1000system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency
1001system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency
1002system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency
1003system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency
1004system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency
1005system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1006system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1007system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1008system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1009system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1010system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1011system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1012system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1013system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1014system.cpu.dcache.tags.replacements 626805 # number of replacements
1015system.cpu.dcache.tags.tagsinuse 511.881003 # Cycle average of tags in use
1016system.cpu.dcache.tags.total_refs 23655596 # Total number of references to valid blocks.
1017system.cpu.dcache.tags.sampled_refs 627317 # Sample count of references to valid blocks.
1018system.cpu.dcache.tags.avg_refs 37.709158 # Average number of references to valid blocks.
1019system.cpu.dcache.tags.warmup_cycle 640871250 # Cycle when the warmup percentage was hit.
1020system.cpu.dcache.tags.occ_blocks::cpu.data 511.881003 # Average occupied blocks per requestor
1021system.cpu.dcache.tags.occ_percent::cpu.data 0.999768 # Average percentage of cache occupancy
1022system.cpu.dcache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy
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1024system.cpu.dcache.ReadReq_hits::total 13195774 # number of ReadReq hits
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1026system.cpu.dcache.WriteReq_hits::total 9972821 # number of WriteReq hits
1027system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits
1028system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits
1029system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits
1030system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits
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1032system.cpu.dcache.demand_hits::total 23168595 # number of demand (read+write) hits
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1034system.cpu.dcache.overall_hits::total 23168595 # number of overall hits
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1036system.cpu.dcache.ReadReq_misses::total 368499 # number of ReadReq misses
1037system.cpu.dcache.WriteReq_misses::cpu.data 250216 # number of WriteReq misses
1038system.cpu.dcache.WriteReq_misses::total 250216 # number of WriteReq misses
1039system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses
1040system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses
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1042system.cpu.dcache.demand_misses::total 618715 # number of demand (read+write) misses
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1044system.cpu.dcache.overall_misses::total 618715 # number of overall misses
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1046system.cpu.dcache.ReadReq_miss_latency::total 5384538000 # number of ReadReq miss cycles
1047system.cpu.dcache.WriteReq_miss_latency::cpu.data 10623511265 # number of WriteReq miss cycles
1048system.cpu.dcache.WriteReq_miss_latency::total 10623511265 # number of WriteReq miss cycles
1049system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158750500 # number of LoadLockedReq miss cycles
1050system.cpu.dcache.LoadLockedReq_miss_latency::total 158750500 # number of LoadLockedReq miss cycles
1051system.cpu.dcache.demand_miss_latency::cpu.data 16008049265 # number of demand (read+write) miss cycles
1052system.cpu.dcache.demand_miss_latency::total 16008049265 # number of demand (read+write) miss cycles
1053system.cpu.dcache.overall_miss_latency::cpu.data 16008049265 # number of overall miss cycles
1054system.cpu.dcache.overall_miss_latency::total 16008049265 # number of overall miss cycles
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1056system.cpu.dcache.ReadReq_accesses::total 13564273 # number of ReadReq accesses(hits+misses)
1057system.cpu.dcache.WriteReq_accesses::cpu.data 10223037 # number of WriteReq accesses(hits+misses)
1058system.cpu.dcache.WriteReq_accesses::total 10223037 # number of WriteReq accesses(hits+misses)
1059system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses)
1060system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses)
1061system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses)
1062system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses)
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1064system.cpu.dcache.demand_accesses::total 23787310 # number of demand (read+write) accesses
1065system.cpu.dcache.overall_accesses::cpu.data 23787310 # number of overall (read+write) accesses
1066system.cpu.dcache.overall_accesses::total 23787310 # number of overall (read+write) accesses
1067system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027167 # miss rate for ReadReq accesses
1068system.cpu.dcache.ReadReq_miss_rate::total 0.027167 # miss rate for ReadReq accesses
1069system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024476 # miss rate for WriteReq accesses
1070system.cpu.dcache.WriteReq_miss_rate::total 0.024476 # miss rate for WriteReq accesses
1071system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses
1072system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses
1073system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses
1074system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses
1075system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses
1076system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses
1077system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14612.083072 # average ReadReq miss latency
1078system.cpu.dcache.ReadReq_avg_miss_latency::total 14612.083072 # average ReadReq miss latency
1079system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42457.361899 # average WriteReq miss latency
1080system.cpu.dcache.WriteReq_avg_miss_latency::total 42457.361899 # average WriteReq miss latency
1081system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13804.391304 # average LoadLockedReq miss latency
1082system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304 # average LoadLockedReq miss latency
1083system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency
1084system.cpu.dcache.demand_avg_miss_latency::total 25873.058298 # average overall miss latency
1085system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency
1086system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency
1087system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1088system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1089system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1090system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1091system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1092system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1093system.cpu.dcache.fast_writes 0 # number of fast writes performed
1094system.cpu.dcache.cache_copies 0 # number of cache copies performed
1095system.cpu.dcache.writebacks::writebacks 595785 # number of writebacks
1096system.cpu.dcache.writebacks::total 595785 # number of writebacks
1097system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368499 # number of ReadReq MSHR misses
1098system.cpu.dcache.ReadReq_mshr_misses::total 368499 # number of ReadReq MSHR misses
1099system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250216 # number of WriteReq MSHR misses
1100system.cpu.dcache.WriteReq_mshr_misses::total 250216 # number of WriteReq MSHR misses
1101system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses
1102system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses
1103system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses
1104system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses
1105system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses
1106system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses
1107system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles
1108system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles
1109system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # number of WriteReq MSHR miss cycles
1110system.cpu.dcache.WriteReq_mshr_miss_latency::total 10058410735 # number of WriteReq MSHR miss cycles
1111system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135673500 # number of LoadLockedReq MSHR miss cycles
1112system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135673500 # number of LoadLockedReq MSHR miss cycles
1113system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14701227235 # number of demand (read+write) MSHR miss cycles
1114system.cpu.dcache.demand_mshr_miss_latency::total 14701227235 # number of demand (read+write) MSHR miss cycles
1115system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles
1116system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles
1117system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles
1118system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles
1119system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles
1120system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles
1121system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles
1122system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles
1123system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses
1124system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses
1125system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses
1126system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses
1127system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses
1128system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses
1129system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses
1130system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses
1131system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses
1132system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses
1133system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency
1134system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency
1135system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency
1136system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency
1137system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency
1138system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency
1139system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency
1140system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency
1141system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency
1142system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency
1143system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1144system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1145system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1146system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1147system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1148system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1149system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1150system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s)
1151system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution
1152system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution
1153system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution
1154system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution
1155system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution
1156system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution
1159system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution
1160system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes)
1161system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes)
1162system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes)
1163system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes)
1164system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes)
1165system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes)
1166system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes)
1167system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes)
1168system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes)
1169system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes)
1170system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes)
1171system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes)
1172system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks)
1173system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1174system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks)
1175system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1176system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks)
1177system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1178system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks)
1179system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1180system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks)
1181system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1182system.iocache.tags.replacements 0 # number of replacements
1183system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
1184system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1185system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
1186system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
1187system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1188system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1189system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1190system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1191system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1192system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1193system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1194system.iocache.fast_writes 0 # number of fast writes performed
1195system.iocache.cache_copies 0 # number of cache copies performed
1196system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles
1197system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles
1198system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles
1199system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles
1200system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1201system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1202system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1203system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1204system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1205
1206---------- End Simulation Statistics ----------