1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.591419 # Number of seconds simulated
4sim_ticks 2591419000000 # Number of ticks simulated
5final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 632591 # Simulator instruction rate (inst/s)
8host_op_rate 807921 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 27699122939 # Simulator tick rate (ticks/s)
10host_mem_usage 380048 # Number of bytes of host memory used
11host_seconds 93.56 # Real time elapsed on the host
12sim_insts 59182652 # Number of instructions simulated
13sim_ops 75585847 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 133632176 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 955744 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 9600072 # Number of bytes written to this memory
17system.physmem.num_reads 15512735 # Number of read requests responded to by this memory
18system.physmem.num_writes 856893 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 51567182 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 368811 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 3704562 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 55271744 # Total bandwidth to/from this memory (bytes/s)
24system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s)
33system.l2c.replacements 117210 # number of replacements
34system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use
35system.l2c.total_refs 1536782 # Total number of references to valid blocks.
36system.l2c.sampled_refs 146347 # Sample count of references to valid blocks.
37system.l2c.avg_refs 10.500946 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor
--- 85 unchanged lines hidden (view full) ---
126system.l2c.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses
127system.l2c.overall_accesses::cpu.inst 854305 # number of overall (read+write) accesses
128system.l2c.overall_accesses::cpu.data 625721 # number of overall (read+write) accesses
129system.l2c.overall_accesses::total 1492315 # number of overall (read+write) accesses
130system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 # miss rate for ReadReq accesses
131system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses
132system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses
133system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses
134system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses
135system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses
136system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses
137system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses
138system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses
139system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses
140system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses
141system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses
142system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses
143system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses
144system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
145system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
146system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency
147system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency
148system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency
149system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency
150system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
151system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
152system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
153system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
154system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
155system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
156system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
157system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
158system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
159system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
160system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
161system.l2c.blocked::no_targets 0 # number of cycles access was blocked
162system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
163system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
164system.l2c.fast_writes 0 # number of fast writes performed
165system.l2c.cache_copies 0 # number of cache copies performed
--- 44 unchanged lines hidden (view full) ---
210system.l2c.WriteReq_mshr_uncacheable_latency::total 31207839500 # number of WriteReq MSHR uncacheable cycles
211system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
212system.l2c.overall_mshr_uncacheable_latency::cpu.data 162752588500 # number of overall MSHR uncacheable cycles
213system.l2c.overall_mshr_uncacheable_latency::total 163017428500 # number of overall MSHR uncacheable cycles
214system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for ReadReq accesses
215system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses
216system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses
217system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses
218system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses
219system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses
220system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses
221system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses
222system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses
223system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses
224system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses
225system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses
226system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses
227system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses
228system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
229system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
230system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency
231system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency
232system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency
233system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency
234system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
235system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
236system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
237system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
238system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
239system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
240system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
241system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
242system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
243system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
244system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
245system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
246system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
247system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
248system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
249system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
250system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
251system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
252system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
253system.cf0.dma_write_txs 0 # Number of DMA write transactions.
254system.cpu.dtb.inst_hits 0 # ITB inst hits
--- 91 unchanged lines hidden (view full) ---
346system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles
347system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses)
348system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses)
349system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses
350system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses
351system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses
352system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses
353system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses
354system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses
355system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses
356system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency
357system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
358system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
359system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
360system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
361system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
362system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
363system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
364system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
365system.cpu.icache.fast_writes 0 # number of fast writes performed
366system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
378system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles
379system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles
380system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles
381system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
382system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
383system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
384system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
385system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses
386system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses
387system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses
388system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency
389system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
390system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
391system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
392system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
393system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.dcache.replacements 627094 # number of replacements
395system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use
396system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks.
397system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks.
398system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks.
399system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
400system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
440system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses)
441system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses)
442system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses)
443system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses
444system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses
445system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses
446system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses
447system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses
448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses
449system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses
450system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses
451system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses
452system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency
453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency
454system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency
455system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
456system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
457system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
458system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
459system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
460system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
461system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
462system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
463system.cpu.dcache.fast_writes 0 # number of fast writes performed
464system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
486system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles
487system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles
488system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles
489system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles
490system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles
491system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles
492system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles
493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses
494system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses
495system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses
496system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses
497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses
498system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency
499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency
500system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency
501system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
502system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
503system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
504system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
505system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
506system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
507system.iocache.replacements 0 # number of replacements
508system.iocache.tagsinuse 0 # Cycle average of tags in use
509system.iocache.total_refs 0 # Total number of references to valid blocks.
510system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
511system.iocache.avg_refs nan # Average number of references to valid blocks.
512system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
513system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
--- 4 unchanged lines hidden (view full) ---
518system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
519system.iocache.fast_writes 0 # number of fast writes performed
520system.iocache.cache_copies 0 # number of cache copies performed
521system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles
522system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles
523system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles
524system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles
525system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
526system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
527system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
528
529---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.591419 # Number of seconds simulated
4sim_ticks 2591419000000 # Number of ticks simulated
5final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 632591 # Simulator instruction rate (inst/s)
8host_op_rate 807921 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 27699122939 # Simulator tick rate (ticks/s)
10host_mem_usage 380048 # Number of bytes of host memory used
11host_seconds 93.56 # Real time elapsed on the host
12sim_insts 59182652 # Number of instructions simulated
13sim_ops 75585847 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 133632176 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 955744 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 9600072 # Number of bytes written to this memory
17system.physmem.num_reads 15512735 # Number of read requests responded to by this memory
18system.physmem.num_writes 856893 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 51567182 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 368811 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 3704562 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 55271744 # Total bandwidth to/from this memory (bytes/s)
24system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s)
33system.l2c.replacements 117210 # number of replacements
34system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use
35system.l2c.total_refs 1536782 # Total number of references to valid blocks.
36system.l2c.sampled_refs 146347 # Sample count of references to valid blocks.
37system.l2c.avg_refs 10.500946 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor
--- 85 unchanged lines hidden (view full) ---
126system.l2c.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses
127system.l2c.overall_accesses::cpu.inst 854305 # number of overall (read+write) accesses
128system.l2c.overall_accesses::cpu.data 625721 # number of overall (read+write) accesses
129system.l2c.overall_accesses::total 1492315 # number of overall (read+write) accesses
130system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 # miss rate for ReadReq accesses
131system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses
132system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses
133system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses
134system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses
135system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses
136system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses
137system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses
138system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses
139system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses
140system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses
141system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses
142system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses
143system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses
144system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
145system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
146system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency
147system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency
148system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency
149system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency
150system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
151system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
152system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
153system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
154system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
155system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
156system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency
157system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency
158system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
159system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
160system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
161system.l2c.blocked::no_targets 0 # number of cycles access was blocked
162system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
163system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
164system.l2c.fast_writes 0 # number of fast writes performed
165system.l2c.cache_copies 0 # number of cache copies performed
--- 44 unchanged lines hidden (view full) ---
210system.l2c.WriteReq_mshr_uncacheable_latency::total 31207839500 # number of WriteReq MSHR uncacheable cycles
211system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
212system.l2c.overall_mshr_uncacheable_latency::cpu.data 162752588500 # number of overall MSHR uncacheable cycles
213system.l2c.overall_mshr_uncacheable_latency::total 163017428500 # number of overall MSHR uncacheable cycles
214system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for ReadReq accesses
215system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses
216system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses
217system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses
218system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses
219system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses
220system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses
221system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses
222system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses
223system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses
224system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses
225system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses
226system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses
227system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses
228system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
229system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
230system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency
231system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency
232system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency
233system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency
234system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
235system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
236system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
237system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
238system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
239system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
240system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency
241system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency
242system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
243system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
244system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
245system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
246system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
247system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
248system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
249system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
250system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
251system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
252system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
253system.cf0.dma_write_txs 0 # Number of DMA write transactions.
254system.cpu.dtb.inst_hits 0 # ITB inst hits
--- 91 unchanged lines hidden (view full) ---
346system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles
347system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses)
348system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses)
349system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses
350system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses
351system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses
352system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses
353system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses
354system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses
355system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses
356system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency
357system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
358system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency
359system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
360system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
361system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
362system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
363system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
364system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
365system.cpu.icache.fast_writes 0 # number of fast writes performed
366system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
378system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles
379system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles
380system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles
381system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
382system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
383system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
384system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
385system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses
386system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses
387system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses
388system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency
389system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
390system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency
391system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
392system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
393system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.dcache.replacements 627094 # number of replacements
395system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use
396system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks.
397system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks.
398system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks.
399system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
400system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
440system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses)
441system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses)
442system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses)
443system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses
444system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses
445system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses
446system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses
447system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses
448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses
449system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses
450system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses
451system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses
452system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency
453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency
454system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency
455system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
456system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency
457system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
458system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
459system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
460system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
461system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
462system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
463system.cpu.dcache.fast_writes 0 # number of fast writes performed
464system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
486system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles
487system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles
488system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles
489system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles
490system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles
491system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles
492system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles
493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses
494system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses
495system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses
496system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses
497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses
498system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency
499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency
500system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency
501system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
502system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
503system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
504system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
505system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
506system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
507system.iocache.replacements 0 # number of replacements
508system.iocache.tagsinuse 0 # Cycle average of tags in use
509system.iocache.total_refs 0 # Total number of references to valid blocks.
510system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
511system.iocache.avg_refs nan # Average number of references to valid blocks.
512system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
513system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
--- 4 unchanged lines hidden (view full) ---
518system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
519system.iocache.fast_writes 0 # number of fast writes performed
520system.iocache.cache_copies 0 # number of cache copies performed
521system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles
522system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles
523system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles
524system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles
525system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
526system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
527system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
528
529---------- End Simulation Statistics ----------