1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.905317 # Number of seconds simulated
4sim_ticks 2905316914500 # Number of ticks simulated
5final_tick 2905316914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1074625 # Simulator instruction rate (inst/s)
8host_op_rate 1295669 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 27762631762 # Simulator tick rate (ticks/s)
10host_mem_usage 582724 # Number of bytes of host memory used
11host_seconds 104.65 # Real time elapsed on the host
12sim_insts 112457861 # Number of instructions simulated
13sim_ops 135589764 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 8969572 # Number of bytes read from this memory
21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
22system.physmem.bytes_read::total 10157640 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7562240 # Number of bytes written to this memory
26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7579764 # Number of bytes written to this memory
28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 140669 # Number of read requests responded to by this memory
32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 167686 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 118160 # Number of write requests responded to by this memory
35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
36system.physmem.num_writes::total 122541 # Number of write requests responded to by this memory
37system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 408400 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 3087296 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::total 3496224 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu.inst 408400 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 408400 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 2602897 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_write::total 2608928 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_total::writebacks 2602897 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 408400 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 3093327 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::total 6105153 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.readReqs 167686 # Number of read requests accepted
56system.physmem.writeReqs 122541 # Number of write requests accepted
57system.physmem.readBursts 167686 # Number of DRAM read bursts, including those serviced by the write queue
58system.physmem.writeBursts 122541 # Number of DRAM write bursts, including those merged in the write queue
59system.physmem.bytesReadDRAM 10724160 # Total number of bytes read from DRAM
60system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue
61system.physmem.bytesWritten 7592640 # Total number of bytes written to DRAM
62system.physmem.bytesReadSys 10157640 # Total read bytes from the system interface side
63system.physmem.bytesWrittenSys 7579764 # Total written bytes from the system interface side
64system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue
65system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
67system.physmem.perBankRdBursts::0 9873 # Per bank write bursts
68system.physmem.perBankRdBursts::1 9614 # Per bank write bursts
69system.physmem.perBankRdBursts::2 9963 # Per bank write bursts
70system.physmem.perBankRdBursts::3 9595 # Per bank write bursts
71system.physmem.perBankRdBursts::4 18744 # Per bank write bursts
72system.physmem.perBankRdBursts::5 9936 # Per bank write bursts
73system.physmem.perBankRdBursts::6 10635 # Per bank write bursts
74system.physmem.perBankRdBursts::7 11205 # Per bank write bursts
75system.physmem.perBankRdBursts::8 9589 # Per bank write bursts
76system.physmem.perBankRdBursts::9 10033 # Per bank write bursts
77system.physmem.perBankRdBursts::10 9283 # Per bank write bursts
78system.physmem.perBankRdBursts::11 8863 # Per bank write bursts
79system.physmem.perBankRdBursts::12 10202 # Per bank write bursts
80system.physmem.perBankRdBursts::13 10190 # Per bank write bursts
81system.physmem.perBankRdBursts::14 10325 # Per bank write bursts
82system.physmem.perBankRdBursts::15 9515 # Per bank write bursts
83system.physmem.perBankWrBursts::0 7137 # Per bank write bursts
84system.physmem.perBankWrBursts::1 7022 # Per bank write bursts
85system.physmem.perBankWrBursts::2 7742 # Per bank write bursts
86system.physmem.perBankWrBursts::3 7365 # Per bank write bursts
87system.physmem.perBankWrBursts::4 7465 # Per bank write bursts
88system.physmem.perBankWrBursts::5 7289 # Per bank write bursts
89system.physmem.perBankWrBursts::6 7716 # Per bank write bursts
90system.physmem.perBankWrBursts::7 8300 # Per bank write bursts
91system.physmem.perBankWrBursts::8 7184 # Per bank write bursts
92system.physmem.perBankWrBursts::9 7439 # Per bank write bursts
93system.physmem.perBankWrBursts::10 6836 # Per bank write bursts
94system.physmem.perBankWrBursts::11 6804 # Per bank write bursts
95system.physmem.perBankWrBursts::12 7947 # Per bank write bursts
96system.physmem.perBankWrBursts::13 7681 # Per bank write bursts
97system.physmem.perBankWrBursts::14 7752 # Per bank write bursts
98system.physmem.perBankWrBursts::15 6956 # Per bank write bursts
99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
100system.physmem.numWrRetry 62 # Number of times write queue was full causing retry
101system.physmem.totGap 2905316552500 # Total gap between requests
102system.physmem.readPktSize::0 0 # Read request sizes (log2)
103system.physmem.readPktSize::1 0 # Read request sizes (log2)
104system.physmem.readPktSize::2 9558 # Read request sizes (log2)
105system.physmem.readPktSize::3 14 # Read request sizes (log2)
106system.physmem.readPktSize::4 0 # Read request sizes (log2)
107system.physmem.readPktSize::5 0 # Read request sizes (log2)
108system.physmem.readPktSize::6 158114 # Read request sizes (log2)
109system.physmem.writePktSize::0 0 # Write request sizes (log2)
110system.physmem.writePktSize::1 0 # Write request sizes (log2)
111system.physmem.writePktSize::2 4381 # Write request sizes (log2)
112system.physmem.writePktSize::3 0 # Write request sizes (log2)
113system.physmem.writePktSize::4 0 # Write request sizes (log2)
114system.physmem.writePktSize::5 0 # Write request sizes (log2)
115system.physmem.writePktSize::6 118160 # Write request sizes (log2)
116system.physmem.rdQLenPdf::0 166731 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::1 559 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::2 263 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::16 2821 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::17 5995 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::18 5894 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::19 6231 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::20 5852 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::21 6236 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::22 6586 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::24 7121 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::25 8226 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::26 8867 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::28 6554 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::29 6505 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::31 6131 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::33 449 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::35 379 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::38 287 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::40 223 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::41 280 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::42 242 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::43 243 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::44 233 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::45 174 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::46 175 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::48 164 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::50 171 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::56 247 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::59 206 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::60 194 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::61 187 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see
212system.physmem.bytesPerActivate::samples 57707 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::mean 317.409257 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::gmean 186.502400 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::stdev 335.930049 # Bytes accessed per row activation
216system.physmem.bytesPerActivate::0-127 20577 35.66% 35.66% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::128-255 14716 25.50% 61.16% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::256-383 5644 9.78% 70.94% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::384-511 3157 5.47% 76.41% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::512-639 2419 4.19% 80.60% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::640-767 1386 2.40% 83.00% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::768-895 1272 2.20% 85.21% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::896-1023 912 1.58% 86.79% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::1024-1151 7624 13.21% 100.00% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::total 57707 # Bytes accessed per row activation
226system.physmem.rdPerTurnAround::samples 5794 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::mean 28.920090 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::stdev 588.859251 # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::0-2047 5793 99.98% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 5794 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 5794 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 20.475492 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.528054 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 14.935092 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-19 5069 87.49% 87.49% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-27 41 0.71% 88.94% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::28-31 52 0.90% 89.83% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::32-35 288 4.97% 94.80% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::36-39 23 0.40% 95.20% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::40-43 16 0.28% 95.48% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::48-51 5 0.09% 95.69% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::136-139 6 0.10% 99.71% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::140-143 5 0.09% 99.79% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::total 5794 # Writes before turning the bus around for reads
272system.physmem.totQLat 4572629500 # Total ticks spent queuing
273system.physmem.totMemAccLat 7714473250 # Total ticks spent from burst creation until serviced by the DRAM
274system.physmem.totBusLat 837825000 # Total ticks spent in databus transfers
275system.physmem.avgQLat 27288.69 # Average queueing delay per DRAM burst
276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
277system.physmem.avgMemAccLat 46038.69 # Average memory access latency per DRAM burst
278system.physmem.avgRdBW 3.69 # Average DRAM read bandwidth in MiByte/s
279system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s
280system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s
281system.physmem.avgWrBWSys 2.61 # Average system write bandwidth in MiByte/s
282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
283system.physmem.busUtil 0.05 # Data bus utilization in percentage
284system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
285system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
286system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
287system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing
288system.physmem.readRowHits 138575 # Number of row buffer hits during reads
289system.physmem.writeRowHits 89917 # Number of row buffer hits during writes
290system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads
291system.physmem.writeRowHitRate 75.78 # Row buffer hit rate for writes
292system.physmem.avgGap 10010497.14 # Average gap between requests
293system.physmem.pageHitRate 79.83 # Row buffer hit rate, read and write combined
294system.physmem_0.actEnergy 209944560 # Energy for activate commands per rank (pJ)
295system.physmem_0.preEnergy 111588180 # Energy for precharge commands per rank (pJ)
296system.physmem_0.readEnergy 639494100 # Energy for read commands per rank (pJ)
297system.physmem_0.writeEnergy 313387920 # Energy for write commands per rank (pJ)
298system.physmem_0.refreshEnergy 6674375760.000002 # Energy for refresh commands per rank (pJ)
299system.physmem_0.actBackEnergy 4793281050 # Energy for active background per rank (pJ)
300system.physmem_0.preBackEnergy 418187520 # Energy for precharge background per rank (pJ)
301system.physmem_0.actPowerDownEnergy 13958691240 # Energy for active power-down per rank (pJ)
302system.physmem_0.prePowerDownEnergy 9415844160 # Energy for precharge power-down per rank (pJ)
303system.physmem_0.selfRefreshEnergy 682618118940 # Energy for self refresh per rank (pJ)
304system.physmem_0.totalEnergy 719155193400 # Total energy per rank (pJ)
305system.physmem_0.averagePower 247.530722 # Core power per rank (mW)
306system.physmem_0.totalIdleTime 2893187924000 # Total Idle time Per DRAM Rank
307system.physmem_0.memoryStateTime::IDLE 788400750 # Time in different power states
308system.physmem_0.memoryStateTime::REF 2838298000 # Time in different power states
309system.physmem_0.memoryStateTime::SREF 2838579624000 # Time in different power states
310system.physmem_0.memoryStateTime::PRE_PDN 24520427750 # Time in different power states
311system.physmem_0.memoryStateTime::ACT 7978656750 # Time in different power states
312system.physmem_0.memoryStateTime::ACT_PDN 30611507250 # Time in different power states
313system.physmem_1.actEnergy 202090560 # Energy for activate commands per rank (pJ)
314system.physmem_1.preEnergy 107409885 # Energy for precharge commands per rank (pJ)
315system.physmem_1.readEnergy 556920000 # Energy for read commands per rank (pJ)
316system.physmem_1.writeEnergy 305886780 # Energy for write commands per rank (pJ)
317system.physmem_1.refreshEnergy 6670687920.000002 # Energy for refresh commands per rank (pJ)
318system.physmem_1.actBackEnergy 4519112190 # Energy for active background per rank (pJ)
319system.physmem_1.preBackEnergy 410472000 # Energy for precharge background per rank (pJ)
320system.physmem_1.actPowerDownEnergy 13651117530 # Energy for active power-down per rank (pJ)
321system.physmem_1.prePowerDownEnergy 9526323840 # Energy for precharge power-down per rank (pJ)
322system.physmem_1.selfRefreshEnergy 682932964665 # Energy for self refresh per rank (pJ)
323system.physmem_1.totalEnergy 718884016170 # Total energy per rank (pJ)
324system.physmem_1.averagePower 247.437384 # Core power per rank (mW)
325system.physmem_1.totalIdleTime 2894335317000 # Total Idle time Per DRAM Rank
326system.physmem_1.memoryStateTime::IDLE 777922000 # Time in different power states
327system.physmem_1.memoryStateTime::REF 2837434000 # Time in different power states
328system.physmem_1.memoryStateTime::SREF 2839590532250 # Time in different power states
329system.physmem_1.memoryStateTime::PRE_PDN 24808008250 # Time in different power states
330system.physmem_1.memoryStateTime::ACT 7366175500 # Time in different power states
331system.physmem_1.memoryStateTime::ACT_PDN 29936842500 # Time in different power states
332system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
333system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
334system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
335system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
336system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
337system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
338system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
339system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
340system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
341system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
342system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
343system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
344system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
345system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
346system.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
347system.bridge.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
348system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
349system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
350system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
351system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
352system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
353system.cf0.dma_write_txs 631 # Number of DMA write transactions.
354system.cpu_clk_domain.clock 500 # Clock period in ticks
355system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
356system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
364system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
365system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
366system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
367system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
368system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
369system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
370system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
371system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
372system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
373system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
374system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
375system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
376system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
377system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
378system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
379system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
380system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
381system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
382system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
383system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
384system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
385system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
386system.cpu.dtb.walker.walks 9553 # Table walker walks requested
387system.cpu.dtb.walker.walksShort 9553 # Table walker walks initiated with short descriptors
388system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256 # Level at which table walker walks with short descriptors terminate
389system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8297 # Level at which table walker walks with short descriptors terminate
390system.cpu.dtb.walker.walkWaitTime::samples 9553 # Table walker wait (enqueue to first request) latency
391system.cpu.dtb.walker.walkWaitTime::0 9553 100.00% 100.00% # Table walker wait (enqueue to first request) latency
392system.cpu.dtb.walker.walkWaitTime::total 9553 # Table walker wait (enqueue to first request) latency
393system.cpu.dtb.walker.walkCompletionTime::samples 7389 # Table walker service (enqueue to completion) latency
394system.cpu.dtb.walker.walkCompletionTime::mean 10013.601299 # Table walker service (enqueue to completion) latency
395system.cpu.dtb.walker.walkCompletionTime::gmean 8464.254766 # Table walker service (enqueue to completion) latency
396system.cpu.dtb.walker.walkCompletionTime::stdev 6610.467359 # Table walker service (enqueue to completion) latency
397system.cpu.dtb.walker.walkCompletionTime::0-16383 6588 89.16% 89.16% # Table walker service (enqueue to completion) latency
398system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93% # Table walker service (enqueue to completion) latency
399system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
400system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
401system.cpu.dtb.walker.walkCompletionTime::total 7389 # Table walker service (enqueue to completion) latency
402system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution
403system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution
404system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution
405system.cpu.dtb.walker.walkPageSizes::4K 6180 83.64% 83.64% # Table walker page sizes translated
406system.cpu.dtb.walker.walkPageSizes::1M 1209 16.36% 100.00% # Table walker page sizes translated
407system.cpu.dtb.walker.walkPageSizes::total 7389 # Table walker page sizes translated
408system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9553 # Table walker requests started/completed, data/inst
409system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
410system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9553 # Table walker requests started/completed, data/inst
411system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7389 # Table walker requests started/completed, data/inst
412system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
413system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7389 # Table walker requests started/completed, data/inst
414system.cpu.dtb.walker.walkRequestOrigin::total 16942 # Table walker requests started/completed, data/inst
415system.cpu.dtb.inst_hits 0 # ITB inst hits
416system.cpu.dtb.inst_misses 0 # ITB inst misses
417system.cpu.dtb.read_hits 24519746 # DTB read hits
418system.cpu.dtb.read_misses 8140 # DTB read misses
419system.cpu.dtb.write_hits 19605246 # DTB write hits
420system.cpu.dtb.write_misses 1413 # DTB write misses
421system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
422system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
423system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
424system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
425system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB
426system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
427system.cpu.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
428system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
429system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
430system.cpu.dtb.read_accesses 24527886 # DTB read accesses
431system.cpu.dtb.write_accesses 19606659 # DTB write accesses
432system.cpu.dtb.inst_accesses 0 # ITB inst accesses
433system.cpu.dtb.hits 44124992 # DTB hits
434system.cpu.dtb.misses 9553 # DTB misses
435system.cpu.dtb.accesses 44134545 # DTB accesses
436system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
437system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
438system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
445system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
446system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
447system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
448system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
449system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
450system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
451system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
452system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
453system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
454system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
455system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
456system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
457system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
458system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
459system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
460system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
461system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
462system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
463system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
464system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
465system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
466system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
467system.cpu.itb.walker.walks 4763 # Table walker walks requested
468system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
469system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
470system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
471system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
472system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
473system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
474system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
475system.cpu.itb.walker.walkCompletionTime::mean 10180.341055 # Table walker service (enqueue to completion) latency
476system.cpu.itb.walker.walkCompletionTime::gmean 8232.055098 # Table walker service (enqueue to completion) latency
477system.cpu.itb.walker.walkCompletionTime::stdev 7311.468363 # Table walker service (enqueue to completion) latency
478system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency
479system.cpu.itb.walker.walkCompletionTime::8192-16383 761 24.49% 83.08% # Table walker service (enqueue to completion) latency
480system.cpu.itb.walker.walkCompletionTime::16384-24575 524 16.86% 99.94% # Table walker service (enqueue to completion) latency
481system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
482system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
483system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
484system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution
485system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution
486system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution
487system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
488system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
489system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
490system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
491system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
492system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
493system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
494system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
495system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
496system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
497system.cpu.itb.inst_hits 115555708 # ITB inst hits
498system.cpu.itb.inst_misses 4763 # ITB inst misses
499system.cpu.itb.read_hits 0 # DTB read hits
500system.cpu.itb.read_misses 0 # DTB read misses
501system.cpu.itb.write_hits 0 # DTB write hits
502system.cpu.itb.write_misses 0 # DTB write misses
503system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
504system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
505system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
506system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
507system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
508system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
509system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
510system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
511system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
512system.cpu.itb.read_accesses 0 # DTB read accesses
513system.cpu.itb.write_accesses 0 # DTB write accesses
514system.cpu.itb.inst_accesses 115560471 # ITB inst accesses
515system.cpu.itb.hits 115555708 # DTB hits
516system.cpu.itb.misses 4763 # DTB misses
517system.cpu.itb.accesses 115560471 # DTB accesses
518system.cpu.numPwrStateTransitions 6064 # Number of power state transitions
519system.cpu.pwrStateClkGateDist::samples 3032 # Distribution of time spent in the clock gated state
520system.cpu.pwrStateClkGateDist::mean 887473262.784960 # Distribution of time spent in the clock gated state
521system.cpu.pwrStateClkGateDist::stdev 17466686239.333317 # Distribution of time spent in the clock gated state
522system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89% # Distribution of time spent in the clock gated state
523system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state
524system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
525system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
526system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
527system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
528system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
529system.cpu.pwrStateClkGateDist::max_value 499963437276 # Distribution of time spent in the clock gated state
530system.cpu.pwrStateClkGateDist::total 3032 # Distribution of time spent in the clock gated state
531system.cpu.pwrStateResidencyTicks::ON 214497981736 # Cumulative time (in ticks) in various power states
532system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818932764 # Cumulative time (in ticks) in various power states
533system.cpu.numCycles 5810633829 # number of cpu cycles simulated
534system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
535system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
536system.cpu.kern.inst.arm 0 # number of arm instructions executed
537system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
538system.cpu.committedInsts 112457861 # Number of instructions committed
539system.cpu.committedOps 135589764 # Number of ops (including micro ops) committed
540system.cpu.num_int_alu_accesses 119894844 # Number of integer alu accesses
541system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses
542system.cpu.num_func_calls 9894754 # number of times a function call or return occured
543system.cpu.num_conditional_control_insts 15230835 # number of instructions that are conditional controls
544system.cpu.num_int_insts 119894844 # number of integer instructions
545system.cpu.num_fp_insts 11290 # number of float instructions
546system.cpu.num_int_register_reads 218056368 # number of times the integer registers were read
547system.cpu.num_int_register_writes 82647309 # number of times the integer registers were written
548system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read
549system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
550system.cpu.num_cc_register_reads 489747242 # number of times the CC registers were read
551system.cpu.num_cc_register_writes 51895082 # number of times the CC registers were written
552system.cpu.num_mem_refs 45405279 # number of memory refs
553system.cpu.num_load_insts 24842044 # Number of load instructions
554system.cpu.num_store_insts 20563235 # Number of store instructions
555system.cpu.num_idle_cycles 5381637865.526148 # Number of idle cycles
556system.cpu.num_busy_cycles 428995963.473852 # Number of busy cycles
557system.cpu.not_idle_fraction 0.073829 # Percentage of non-idle cycles
558system.cpu.idle_fraction 0.926171 # Percentage of idle cycles
559system.cpu.Branches 25919556 # Number of branches fetched
560system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
561system.cpu.op_class::IntAlu 93179861 67.18% 67.18% # Class of executed instruction
562system.cpu.op_class::IntMult 114520 0.08% 67.26% # Class of executed instruction
563system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
564system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
565system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
566system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
567system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
568system.cpu.op_class::FloatMultAcc 0 0.00% 67.26% # Class of executed instruction
569system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
570system.cpu.op_class::FloatMisc 0 0.00% 67.26% # Class of executed instruction
571system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
572system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
573system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
574system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
575system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
576system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
577system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
578system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
579system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
580system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
581system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
582system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
583system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
584system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
585system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
586system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
587system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
588system.cpu.op_class::SimdFloatMisc 8439 0.01% 67.27% # Class of executed instruction
589system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction
590system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction
591system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction
592system.cpu.op_class::MemRead 24839336 17.91% 85.17% # Class of executed instruction
593system.cpu.op_class::MemWrite 20554657 14.82% 99.99% # Class of executed instruction
594system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% # Class of executed instruction
595system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00% # Class of executed instruction
596system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
597system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
598system.cpu.op_class::total 138710436 # Class of executed instruction
599system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
600system.cpu.dcache.tags.replacements 821157 # number of replacements
601system.cpu.dcache.tags.tagsinuse 511.816175 # Cycle average of tags in use
602system.cpu.dcache.tags.total_refs 43232042 # Total number of references to valid blocks.
603system.cpu.dcache.tags.sampled_refs 821669 # Sample count of references to valid blocks.
604system.cpu.dcache.tags.avg_refs 52.614912 # Average number of references to valid blocks.
605system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit.
606system.cpu.dcache.tags.occ_blocks::cpu.data 511.816175 # Average occupied blocks per requestor
607system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy
608system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy
609system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
610system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
611system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
612system.cpu.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
613system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
614system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
615system.cpu.dcache.tags.tag_accesses 177104694 # Number of tag accesses
616system.cpu.dcache.tags.data_accesses 177104694 # Number of data accesses
617system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
618system.cpu.dcache.ReadReq_hits::cpu.data 23110946 # number of ReadReq hits
619system.cpu.dcache.ReadReq_hits::total 23110946 # number of ReadReq hits
620system.cpu.dcache.WriteReq_hits::cpu.data 18822565 # number of WriteReq hits
621system.cpu.dcache.WriteReq_hits::total 18822565 # number of WriteReq hits
622system.cpu.dcache.SoftPFReq_hits::cpu.data 392473 # number of SoftPFReq hits
623system.cpu.dcache.SoftPFReq_hits::total 392473 # number of SoftPFReq hits
624system.cpu.dcache.LoadLockedReq_hits::cpu.data 443108 # number of LoadLockedReq hits
625system.cpu.dcache.LoadLockedReq_hits::total 443108 # number of LoadLockedReq hits
626system.cpu.dcache.StoreCondReq_hits::cpu.data 460141 # number of StoreCondReq hits
627system.cpu.dcache.StoreCondReq_hits::total 460141 # number of StoreCondReq hits
628system.cpu.dcache.demand_hits::cpu.data 41933511 # number of demand (read+write) hits
629system.cpu.dcache.demand_hits::total 41933511 # number of demand (read+write) hits
630system.cpu.dcache.overall_hits::cpu.data 42325984 # number of overall hits
631system.cpu.dcache.overall_hits::total 42325984 # number of overall hits
632system.cpu.dcache.ReadReq_misses::cpu.data 401142 # number of ReadReq misses
633system.cpu.dcache.ReadReq_misses::total 401142 # number of ReadReq misses
634system.cpu.dcache.WriteReq_misses::cpu.data 298882 # number of WriteReq misses
635system.cpu.dcache.WriteReq_misses::total 298882 # number of WriteReq misses
636system.cpu.dcache.SoftPFReq_misses::cpu.data 118684 # number of SoftPFReq misses
637system.cpu.dcache.SoftPFReq_misses::total 118684 # number of SoftPFReq misses
638system.cpu.dcache.LoadLockedReq_misses::cpu.data 22806 # number of LoadLockedReq misses
639system.cpu.dcache.LoadLockedReq_misses::total 22806 # number of LoadLockedReq misses
640system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
641system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
642system.cpu.dcache.demand_misses::cpu.data 700024 # number of demand (read+write) misses
643system.cpu.dcache.demand_misses::total 700024 # number of demand (read+write) misses
644system.cpu.dcache.overall_misses::cpu.data 818708 # number of overall misses
645system.cpu.dcache.overall_misses::total 818708 # number of overall misses
646system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437831500 # number of ReadReq miss cycles
647system.cpu.dcache.ReadReq_miss_latency::total 6437831500 # number of ReadReq miss cycles
648system.cpu.dcache.WriteReq_miss_latency::cpu.data 14440805000 # number of WriteReq miss cycles
649system.cpu.dcache.WriteReq_miss_latency::total 14440805000 # number of WriteReq miss cycles
650system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297461000 # number of LoadLockedReq miss cycles
651system.cpu.dcache.LoadLockedReq_miss_latency::total 297461000 # number of LoadLockedReq miss cycles
652system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles
653system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
654system.cpu.dcache.demand_miss_latency::cpu.data 20878636500 # number of demand (read+write) miss cycles
655system.cpu.dcache.demand_miss_latency::total 20878636500 # number of demand (read+write) miss cycles
656system.cpu.dcache.overall_miss_latency::cpu.data 20878636500 # number of overall miss cycles
657system.cpu.dcache.overall_miss_latency::total 20878636500 # number of overall miss cycles
658system.cpu.dcache.ReadReq_accesses::cpu.data 23512088 # number of ReadReq accesses(hits+misses)
659system.cpu.dcache.ReadReq_accesses::total 23512088 # number of ReadReq accesses(hits+misses)
660system.cpu.dcache.WriteReq_accesses::cpu.data 19121447 # number of WriteReq accesses(hits+misses)
661system.cpu.dcache.WriteReq_accesses::total 19121447 # number of WriteReq accesses(hits+misses)
662system.cpu.dcache.SoftPFReq_accesses::cpu.data 511157 # number of SoftPFReq accesses(hits+misses)
663system.cpu.dcache.SoftPFReq_accesses::total 511157 # number of SoftPFReq accesses(hits+misses)
664system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465914 # number of LoadLockedReq accesses(hits+misses)
665system.cpu.dcache.LoadLockedReq_accesses::total 465914 # number of LoadLockedReq accesses(hits+misses)
666system.cpu.dcache.StoreCondReq_accesses::cpu.data 460143 # number of StoreCondReq accesses(hits+misses)
667system.cpu.dcache.StoreCondReq_accesses::total 460143 # number of StoreCondReq accesses(hits+misses)
668system.cpu.dcache.demand_accesses::cpu.data 42633535 # number of demand (read+write) accesses
669system.cpu.dcache.demand_accesses::total 42633535 # number of demand (read+write) accesses
670system.cpu.dcache.overall_accesses::cpu.data 43144692 # number of overall (read+write) accesses
671system.cpu.dcache.overall_accesses::total 43144692 # number of overall (read+write) accesses
672system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses
673system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses
674system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses
675system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses
676system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232187 # miss rate for SoftPFReq accesses
677system.cpu.dcache.SoftPFReq_miss_rate::total 0.232187 # miss rate for SoftPFReq accesses
678system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048949 # miss rate for LoadLockedReq accesses
679system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048949 # miss rate for LoadLockedReq accesses
680system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
681system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
682system.cpu.dcache.demand_miss_rate::cpu.data 0.016420 # miss rate for demand accesses
683system.cpu.dcache.demand_miss_rate::total 0.016420 # miss rate for demand accesses
684system.cpu.dcache.overall_miss_rate::cpu.data 0.018976 # miss rate for overall accesses
685system.cpu.dcache.overall_miss_rate::total 0.018976 # miss rate for overall accesses
686system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.759542 # average ReadReq miss latency
687system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.759542 # average ReadReq miss latency
688system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48316.074571 # average WriteReq miss latency
689system.cpu.dcache.WriteReq_avg_miss_latency::total 48316.074571 # average WriteReq miss latency
690system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.102692 # average LoadLockedReq miss latency
691system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.102692 # average LoadLockedReq miss latency
692system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency
693system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency
694system.cpu.dcache.demand_avg_miss_latency::cpu.data 29825.600979 # average overall miss latency
695system.cpu.dcache.demand_avg_miss_latency::total 29825.600979 # average overall miss latency
696system.cpu.dcache.overall_avg_miss_latency::cpu.data 25501.932924 # average overall miss latency
697system.cpu.dcache.overall_avg_miss_latency::total 25501.932924 # average overall miss latency
698system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
699system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
700system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
701system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
702system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
703system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
704system.cpu.dcache.writebacks::writebacks 685616 # number of writebacks
705system.cpu.dcache.writebacks::total 685616 # number of writebacks
706system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708 # number of ReadReq MSHR hits
707system.cpu.dcache.ReadReq_mshr_hits::total 708 # number of ReadReq MSHR hits
708system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits
709system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits
710system.cpu.dcache.demand_mshr_hits::cpu.data 708 # number of demand (read+write) MSHR hits
711system.cpu.dcache.demand_mshr_hits::total 708 # number of demand (read+write) MSHR hits
712system.cpu.dcache.overall_mshr_hits::cpu.data 708 # number of overall MSHR hits
713system.cpu.dcache.overall_mshr_hits::total 708 # number of overall MSHR hits
714system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400434 # number of ReadReq MSHR misses
715system.cpu.dcache.ReadReq_mshr_misses::total 400434 # number of ReadReq MSHR misses
716system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298882 # number of WriteReq MSHR misses
717system.cpu.dcache.WriteReq_mshr_misses::total 298882 # number of WriteReq MSHR misses
718system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661 # number of SoftPFReq MSHR misses
719system.cpu.dcache.SoftPFReq_mshr_misses::total 116661 # number of SoftPFReq MSHR misses
720system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8528 # number of LoadLockedReq MSHR misses
721system.cpu.dcache.LoadLockedReq_mshr_misses::total 8528 # number of LoadLockedReq MSHR misses
722system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
723system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
724system.cpu.dcache.demand_mshr_misses::cpu.data 699316 # number of demand (read+write) MSHR misses
725system.cpu.dcache.demand_mshr_misses::total 699316 # number of demand (read+write) MSHR misses
726system.cpu.dcache.overall_mshr_misses::cpu.data 815977 # number of overall MSHR misses
727system.cpu.dcache.overall_mshr_misses::total 815977 # number of overall MSHR misses
728system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
729system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
730system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
731system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
732system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
733system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
734system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6012304000 # number of ReadReq MSHR miss cycles
735system.cpu.dcache.ReadReq_mshr_miss_latency::total 6012304000 # number of ReadReq MSHR miss cycles
736system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14141923000 # number of WriteReq MSHR miss cycles
737system.cpu.dcache.WriteReq_mshr_miss_latency::total 14141923000 # number of WriteReq MSHR miss cycles
738system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1586831500 # number of SoftPFReq MSHR miss cycles
739system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1586831500 # number of SoftPFReq MSHR miss cycles
740system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118977500 # number of LoadLockedReq MSHR miss cycles
741system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118977500 # number of LoadLockedReq MSHR miss cycles
742system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles
743system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles
744system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154227000 # number of demand (read+write) MSHR miss cycles
745system.cpu.dcache.demand_mshr_miss_latency::total 20154227000 # number of demand (read+write) MSHR miss cycles
746system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741058500 # number of overall MSHR miss cycles
747system.cpu.dcache.overall_mshr_miss_latency::total 21741058500 # number of overall MSHR miss cycles
748system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284829000 # number of ReadReq MSHR uncacheable cycles
749system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284829000 # number of ReadReq MSHR uncacheable cycles
750system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284829000 # number of overall MSHR uncacheable cycles
751system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284829000 # number of overall MSHR uncacheable cycles
752system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017031 # mshr miss rate for ReadReq accesses
753system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017031 # mshr miss rate for ReadReq accesses
754system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
755system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
756system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228229 # mshr miss rate for SoftPFReq accesses
757system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228229 # mshr miss rate for SoftPFReq accesses
758system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018304 # mshr miss rate for LoadLockedReq accesses
759system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018304 # mshr miss rate for LoadLockedReq accesses
760system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
761system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
762system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403 # mshr miss rate for demand accesses
763system.cpu.dcache.demand_mshr_miss_rate::total 0.016403 # mshr miss rate for demand accesses
764system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913 # mshr miss rate for overall accesses
765system.cpu.dcache.overall_mshr_miss_rate::total 0.018913 # mshr miss rate for overall accesses
766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15014.469301 # average ReadReq mshr miss latency
767system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15014.469301 # average ReadReq mshr miss latency
768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47316.074571 # average WriteReq mshr miss latency
769system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47316.074571 # average WriteReq mshr miss latency
770system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13602.073529 # average SoftPFReq mshr miss latency
771system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13602.073529 # average SoftPFReq mshr miss latency
772system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.395403 # average LoadLockedReq mshr miss latency
773system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.395403 # average LoadLockedReq mshr miss latency
774system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
775system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
776system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28819.914030 # average overall mshr miss latency
777system.cpu.dcache.demand_avg_mshr_miss_latency::total 28819.914030 # average overall mshr miss latency
778system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26644.205045 # average overall mshr miss latency
779system.cpu.dcache.overall_avg_mshr_miss_latency::total 26644.205045 # average overall mshr miss latency
780system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201837.915088 # average ReadReq mshr uncacheable latency
781system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201837.915088 # average ReadReq mshr uncacheable latency
782system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.709061 # average overall mshr uncacheable latency
783system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.709061 # average overall mshr uncacheable latency
784system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
785system.cpu.icache.tags.replacements 1700062 # number of replacements
786system.cpu.icache.tags.tagsinuse 510.693087 # Cycle average of tags in use
787system.cpu.icache.tags.total_refs 113855128 # Total number of references to valid blocks.
788system.cpu.icache.tags.sampled_refs 1700574 # Sample count of references to valid blocks.
789system.cpu.icache.tags.avg_refs 66.950999 # Average number of references to valid blocks.
790system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit.
791system.cpu.icache.tags.occ_blocks::cpu.inst 510.693087 # Average occupied blocks per requestor
792system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy
793system.cpu.icache.tags.occ_percent::total 0.997447 # Average percentage of cache occupancy
794system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
795system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
796system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
797system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
798system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
799system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
800system.cpu.icache.tags.tag_accesses 117256288 # Number of tag accesses
801system.cpu.icache.tags.data_accesses 117256288 # Number of data accesses
802system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
803system.cpu.icache.ReadReq_hits::cpu.inst 113855128 # number of ReadReq hits
804system.cpu.icache.ReadReq_hits::total 113855128 # number of ReadReq hits
805system.cpu.icache.demand_hits::cpu.inst 113855128 # number of demand (read+write) hits
806system.cpu.icache.demand_hits::total 113855128 # number of demand (read+write) hits
807system.cpu.icache.overall_hits::cpu.inst 113855128 # number of overall hits
808system.cpu.icache.overall_hits::total 113855128 # number of overall hits
809system.cpu.icache.ReadReq_misses::cpu.inst 1700580 # number of ReadReq misses
810system.cpu.icache.ReadReq_misses::total 1700580 # number of ReadReq misses
811system.cpu.icache.demand_misses::cpu.inst 1700580 # number of demand (read+write) misses
812system.cpu.icache.demand_misses::total 1700580 # number of demand (read+write) misses
813system.cpu.icache.overall_misses::cpu.inst 1700580 # number of overall misses
814system.cpu.icache.overall_misses::total 1700580 # number of overall misses
815system.cpu.icache.ReadReq_miss_latency::cpu.inst 24044969500 # number of ReadReq miss cycles
816system.cpu.icache.ReadReq_miss_latency::total 24044969500 # number of ReadReq miss cycles
817system.cpu.icache.demand_miss_latency::cpu.inst 24044969500 # number of demand (read+write) miss cycles
818system.cpu.icache.demand_miss_latency::total 24044969500 # number of demand (read+write) miss cycles
819system.cpu.icache.overall_miss_latency::cpu.inst 24044969500 # number of overall miss cycles
820system.cpu.icache.overall_miss_latency::total 24044969500 # number of overall miss cycles
821system.cpu.icache.ReadReq_accesses::cpu.inst 115555708 # number of ReadReq accesses(hits+misses)
822system.cpu.icache.ReadReq_accesses::total 115555708 # number of ReadReq accesses(hits+misses)
823system.cpu.icache.demand_accesses::cpu.inst 115555708 # number of demand (read+write) accesses
824system.cpu.icache.demand_accesses::total 115555708 # number of demand (read+write) accesses
825system.cpu.icache.overall_accesses::cpu.inst 115555708 # number of overall (read+write) accesses
826system.cpu.icache.overall_accesses::total 115555708 # number of overall (read+write) accesses
827system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014717 # miss rate for ReadReq accesses
828system.cpu.icache.ReadReq_miss_rate::total 0.014717 # miss rate for ReadReq accesses
829system.cpu.icache.demand_miss_rate::cpu.inst 0.014717 # miss rate for demand accesses
830system.cpu.icache.demand_miss_rate::total 0.014717 # miss rate for demand accesses
831system.cpu.icache.overall_miss_rate::cpu.inst 0.014717 # miss rate for overall accesses
832system.cpu.icache.overall_miss_rate::total 0.014717 # miss rate for overall accesses
833system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.275718 # average ReadReq miss latency
834system.cpu.icache.ReadReq_avg_miss_latency::total 14139.275718 # average ReadReq miss latency
835system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency
836system.cpu.icache.demand_avg_miss_latency::total 14139.275718 # average overall miss latency
837system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency
838system.cpu.icache.overall_avg_miss_latency::total 14139.275718 # average overall miss latency
839system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
840system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
841system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
842system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
843system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
844system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
845system.cpu.icache.writebacks::writebacks 1700062 # number of writebacks
846system.cpu.icache.writebacks::total 1700062 # number of writebacks
847system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700580 # number of ReadReq MSHR misses
848system.cpu.icache.ReadReq_mshr_misses::total 1700580 # number of ReadReq MSHR misses
849system.cpu.icache.demand_mshr_misses::cpu.inst 1700580 # number of demand (read+write) MSHR misses
850system.cpu.icache.demand_mshr_misses::total 1700580 # number of demand (read+write) MSHR misses
851system.cpu.icache.overall_mshr_misses::cpu.inst 1700580 # number of overall MSHR misses
852system.cpu.icache.overall_mshr_misses::total 1700580 # number of overall MSHR misses
853system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
854system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
855system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
856system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
857system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344389500 # number of ReadReq MSHR miss cycles
858system.cpu.icache.ReadReq_mshr_miss_latency::total 22344389500 # number of ReadReq MSHR miss cycles
859system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344389500 # number of demand (read+write) MSHR miss cycles
860system.cpu.icache.demand_mshr_miss_latency::total 22344389500 # number of demand (read+write) MSHR miss cycles
861system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344389500 # number of overall MSHR miss cycles
862system.cpu.icache.overall_mshr_miss_latency::total 22344389500 # number of overall MSHR miss cycles
863system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles
864system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles
865system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles
866system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 # number of overall MSHR uncacheable cycles
867system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for ReadReq accesses
868system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014717 # mshr miss rate for ReadReq accesses
869system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for demand accesses
870system.cpu.icache.demand_mshr_miss_rate::total 0.014717 # mshr miss rate for demand accesses
871system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for overall accesses
872system.cpu.icache.overall_mshr_miss_rate::total 0.014717 # mshr miss rate for overall accesses
873system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.275718 # average ReadReq mshr miss latency
874system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.275718 # average ReadReq mshr miss latency
875system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency
876system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency
877system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency
878system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency
879system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency
880system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency
881system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency
882system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency
883system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
884system.cpu.l2cache.tags.replacements 88598 # number of replacements
885system.cpu.l2cache.tags.tagsinuse 65011.992508 # Cycle average of tags in use
886system.cpu.l2cache.tags.total_refs 4854149 # Total number of references to valid blocks.
887system.cpu.l2cache.tags.sampled_refs 154025 # Sample count of references to valid blocks.
888system.cpu.l2cache.tags.avg_refs 31.515332 # Average number of references to valid blocks.
889system.cpu.l2cache.tags.warmup_cycle 147534324000 # Cycle when the warmup percentage was hit.
890system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681 # Average occupied blocks per requestor
891system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041157 # Average occupied blocks per requestor
892system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.969504 # Average occupied blocks per requestor
893system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.931167 # Average occupied blocks per requestor
894system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy
895system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
896system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147018 # Average percentage of cache occupancy
897system.cpu.l2cache.tags.occ_percent::cpu.data 0.844939 # Average percentage of cache occupancy
898system.cpu.l2cache.tags.occ_percent::total 0.992004 # Average percentage of cache occupancy
899system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
900system.cpu.l2cache.tags.occ_task_id_blocks::1024 65422 # Occupied blocks per task id
901system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
902system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
903system.cpu.l2cache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id
904system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4349 # Occupied blocks per task id
905system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60996 # Occupied blocks per task id
906system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
907system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260 # Percentage of cache occupancy per task id
908system.cpu.l2cache.tags.tag_accesses 40276408 # Number of tag accesses
909system.cpu.l2cache.tags.data_accesses 40276408 # Number of data accesses
910system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
911system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5063 # number of ReadReq hits
912system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684 # number of ReadReq hits
913system.cpu.l2cache.ReadReq_hits::total 7747 # number of ReadReq hits
914system.cpu.l2cache.WritebackDirty_hits::writebacks 685616 # number of WritebackDirty hits
915system.cpu.l2cache.WritebackDirty_hits::total 685616 # number of WritebackDirty hits
916system.cpu.l2cache.WritebackClean_hits::writebacks 1667781 # number of WritebackClean hits
917system.cpu.l2cache.WritebackClean_hits::total 1667781 # number of WritebackClean hits
918system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789 # number of UpgradeReq hits
919system.cpu.l2cache.UpgradeReq_hits::total 2789 # number of UpgradeReq hits
920system.cpu.l2cache.ReadExReq_hits::cpu.data 167648 # number of ReadExReq hits
921system.cpu.l2cache.ReadExReq_hits::total 167648 # number of ReadExReq hits
922system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682586 # number of ReadCleanReq hits
923system.cpu.l2cache.ReadCleanReq_hits::total 1682586 # number of ReadCleanReq hits
924system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513551 # number of ReadSharedReq hits
925system.cpu.l2cache.ReadSharedReq_hits::total 513551 # number of ReadSharedReq hits
926system.cpu.l2cache.demand_hits::cpu.dtb.walker 5063 # number of demand (read+write) hits
927system.cpu.l2cache.demand_hits::cpu.itb.walker 2684 # number of demand (read+write) hits
928system.cpu.l2cache.demand_hits::cpu.inst 1682586 # number of demand (read+write) hits
929system.cpu.l2cache.demand_hits::cpu.data 681199 # number of demand (read+write) hits
930system.cpu.l2cache.demand_hits::total 2371532 # number of demand (read+write) hits
931system.cpu.l2cache.overall_hits::cpu.dtb.walker 5063 # number of overall hits
932system.cpu.l2cache.overall_hits::cpu.itb.walker 2684 # number of overall hits
933system.cpu.l2cache.overall_hits::cpu.inst 1682586 # number of overall hits
934system.cpu.l2cache.overall_hits::cpu.data 681199 # number of overall hits
935system.cpu.l2cache.overall_hits::total 2371532 # number of overall hits
936system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
937system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
938system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
939system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses
940system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses
941system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
942system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
943system.cpu.l2cache.ReadExReq_misses::cpu.data 128427 # number of ReadExReq misses
944system.cpu.l2cache.ReadExReq_misses::total 128427 # number of ReadExReq misses
945system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses
946system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses
947system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072 # number of ReadSharedReq misses
948system.cpu.l2cache.ReadSharedReq_misses::total 12072 # number of ReadSharedReq misses
949system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
950system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
951system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses
952system.cpu.l2cache.demand_misses::cpu.data 140499 # number of demand (read+write) misses
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954system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
955system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
956system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses
957system.cpu.l2cache.overall_misses::cpu.data 140499 # number of overall misses
958system.cpu.l2cache.overall_misses::total 158486 # number of overall misses
959system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000 # number of ReadReq miss cycles
960system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles
961system.cpu.l2cache.ReadReq_miss_latency::total 1334000 # number of ReadReq miss cycles
962system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 525000 # number of UpgradeReq miss cycles
963system.cpu.l2cache.UpgradeReq_miss_latency::total 525000 # number of UpgradeReq miss cycles
964system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles
965system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles
966system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11899913500 # number of ReadExReq miss cycles
967system.cpu.l2cache.ReadExReq_miss_latency::total 11899913500 # number of ReadExReq miss cycles
968system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066366000 # number of ReadCleanReq miss cycles
969system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066366000 # number of ReadCleanReq miss cycles
970system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1520063000 # number of ReadSharedReq miss cycles
971system.cpu.l2cache.ReadSharedReq_miss_latency::total 1520063000 # number of ReadSharedReq miss cycles
972system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000 # number of demand (read+write) miss cycles
973system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles
974system.cpu.l2cache.demand_miss_latency::cpu.inst 2066366000 # number of demand (read+write) miss cycles
975system.cpu.l2cache.demand_miss_latency::cpu.data 13419976500 # number of demand (read+write) miss cycles
976system.cpu.l2cache.demand_miss_latency::total 15487676500 # number of demand (read+write) miss cycles
977system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000 # number of overall miss cycles
978system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles
979system.cpu.l2cache.overall_miss_latency::cpu.inst 2066366000 # number of overall miss cycles
980system.cpu.l2cache.overall_miss_latency::cpu.data 13419976500 # number of overall miss cycles
981system.cpu.l2cache.overall_miss_latency::total 15487676500 # number of overall miss cycles
982system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5070 # number of ReadReq accesses(hits+misses)
983system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686 # number of ReadReq accesses(hits+misses)
984system.cpu.l2cache.ReadReq_accesses::total 7756 # number of ReadReq accesses(hits+misses)
985system.cpu.l2cache.WritebackDirty_accesses::writebacks 685616 # number of WritebackDirty accesses(hits+misses)
986system.cpu.l2cache.WritebackDirty_accesses::total 685616 # number of WritebackDirty accesses(hits+misses)
987system.cpu.l2cache.WritebackClean_accesses::writebacks 1667781 # number of WritebackClean accesses(hits+misses)
988system.cpu.l2cache.WritebackClean_accesses::total 1667781 # number of WritebackClean accesses(hits+misses)
989system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2807 # number of UpgradeReq accesses(hits+misses)
990system.cpu.l2cache.UpgradeReq_accesses::total 2807 # number of UpgradeReq accesses(hits+misses)
991system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
992system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
993system.cpu.l2cache.ReadExReq_accesses::cpu.data 296075 # number of ReadExReq accesses(hits+misses)
994system.cpu.l2cache.ReadExReq_accesses::total 296075 # number of ReadExReq accesses(hits+misses)
995system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700564 # number of ReadCleanReq accesses(hits+misses)
996system.cpu.l2cache.ReadCleanReq_accesses::total 1700564 # number of ReadCleanReq accesses(hits+misses)
997system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525623 # number of ReadSharedReq accesses(hits+misses)
998system.cpu.l2cache.ReadSharedReq_accesses::total 525623 # number of ReadSharedReq accesses(hits+misses)
999system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5070 # number of demand (read+write) accesses
1000system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686 # number of demand (read+write) accesses
1001system.cpu.l2cache.demand_accesses::cpu.inst 1700564 # number of demand (read+write) accesses
1002system.cpu.l2cache.demand_accesses::cpu.data 821698 # number of demand (read+write) accesses
1003system.cpu.l2cache.demand_accesses::total 2530018 # number of demand (read+write) accesses
1004system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5070 # number of overall (read+write) accesses
1005system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686 # number of overall (read+write) accesses
1006system.cpu.l2cache.overall_accesses::cpu.inst 1700564 # number of overall (read+write) accesses
1007system.cpu.l2cache.overall_accesses::cpu.data 821698 # number of overall (read+write) accesses
1008system.cpu.l2cache.overall_accesses::total 2530018 # number of overall (read+write) accesses
1009system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381 # miss rate for ReadReq accesses
1010system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745 # miss rate for ReadReq accesses
1011system.cpu.l2cache.ReadReq_miss_rate::total 0.001160 # miss rate for ReadReq accesses
1012system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006413 # miss rate for UpgradeReq accesses
1013system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006413 # miss rate for UpgradeReq accesses
1014system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
1015system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1016system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433765 # miss rate for ReadExReq accesses
1017system.cpu.l2cache.ReadExReq_miss_rate::total 0.433765 # miss rate for ReadExReq accesses
1018system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010572 # miss rate for ReadCleanReq accesses
1019system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010572 # miss rate for ReadCleanReq accesses
1020system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022967 # miss rate for ReadSharedReq accesses
1021system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022967 # miss rate for ReadSharedReq accesses
1022system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381 # miss rate for demand accesses
1023system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745 # miss rate for demand accesses
1024system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010572 # miss rate for demand accesses
1025system.cpu.l2cache.demand_miss_rate::cpu.data 0.170986 # miss rate for demand accesses
1026system.cpu.l2cache.demand_miss_rate::total 0.062642 # miss rate for demand accesses
1027system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381 # miss rate for overall accesses
1028system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745 # miss rate for overall accesses
1029system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010572 # miss rate for overall accesses
1030system.cpu.l2cache.overall_miss_rate::cpu.data 0.170986 # miss rate for overall accesses
1031system.cpu.l2cache.overall_miss_rate::total 0.062642 # miss rate for overall accesses
1032system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857 # average ReadReq miss latency
1033system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency
1034system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222 # average ReadReq miss latency
1035system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29166.666667 # average UpgradeReq miss latency
1036system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29166.666667 # average UpgradeReq miss latency
1037system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency
1038system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency
1039system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92658.969687 # average ReadExReq miss latency
1040system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92658.969687 # average ReadExReq miss latency
1041system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114938.591612 # average ReadCleanReq miss latency
1042system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114938.591612 # average ReadCleanReq miss latency
1043system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125916.418158 # average ReadSharedReq miss latency
1044system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125916.418158 # average ReadSharedReq miss latency
1045system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency
1046system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
1047system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency
1048system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency
1049system.cpu.l2cache.demand_avg_miss_latency::total 97722.678975 # average overall miss latency
1050system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency
1051system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
1052system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency
1053system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency
1054system.cpu.l2cache.overall_avg_miss_latency::total 97722.678975 # average overall miss latency
1055system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1056system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1057system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1058system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1059system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1060system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1061system.cpu.l2cache.writebacks::writebacks 81970 # number of writebacks
1062system.cpu.l2cache.writebacks::total 81970 # number of writebacks
1063system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
1064system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
1065system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
1066system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses
1067system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
1068system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1069system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1070system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128427 # number of ReadExReq MSHR misses
1071system.cpu.l2cache.ReadExReq_mshr_misses::total 128427 # number of ReadExReq MSHR misses
1072system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses
1073system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses
1074system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072 # number of ReadSharedReq MSHR misses
1075system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072 # number of ReadSharedReq MSHR misses
1076system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
1077system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
1078system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses
1079system.cpu.l2cache.demand_mshr_misses::cpu.data 140499 # number of demand (read+write) MSHR misses
1080system.cpu.l2cache.demand_mshr_misses::total 158486 # number of demand (read+write) MSHR misses
1081system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
1082system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
1083system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses
1084system.cpu.l2cache.overall_mshr_misses::cpu.data 140499 # number of overall MSHR misses
1085system.cpu.l2cache.overall_mshr_misses::total 158486 # number of overall MSHR misses
1086system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
1087system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
1088system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
1089system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
1090system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
1091system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
1092system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
1093system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
1094system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084000 # number of ReadReq MSHR miss cycles
1095system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 # number of ReadReq MSHR miss cycles
1096system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244000 # number of ReadReq MSHR miss cycles
1097system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345000 # number of UpgradeReq MSHR miss cycles
1098system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345000 # number of UpgradeReq MSHR miss cycles
1099system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles
1100system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles
1101system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10615643500 # number of ReadExReq MSHR miss cycles
1102system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10615643500 # number of ReadExReq MSHR miss cycles
1103system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886586000 # number of ReadCleanReq MSHR miss cycles
1104system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886586000 # number of ReadCleanReq MSHR miss cycles
1105system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399343000 # number of ReadSharedReq MSHR miss cycles
1106system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399343000 # number of ReadSharedReq MSHR miss cycles
1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000 # number of demand (read+write) MSHR miss cycles
1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886586000 # number of demand (read+write) MSHR miss cycles
1110system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12014986500 # number of demand (read+write) MSHR miss cycles
1111system.cpu.l2cache.demand_mshr_miss_latency::total 13902816500 # number of demand (read+write) MSHR miss cycles
1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000 # number of overall MSHR miss cycles
1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles
1114system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886586000 # number of overall MSHR miss cycles
1115system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12014986500 # number of overall MSHR miss cycles
1116system.cpu.l2cache.overall_mshr_miss_latency::total 13902816500 # number of overall MSHR miss cycles
1117system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles
1118system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895484000 # number of ReadReq MSHR uncacheable cycles
1119system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527912000 # number of ReadReq MSHR uncacheable cycles
1120system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 # number of overall MSHR uncacheable cycles
1121system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895484000 # number of overall MSHR uncacheable cycles
1122system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527912000 # number of overall MSHR uncacheable cycles
1123system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for ReadReq accesses
1124system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for ReadReq accesses
1125system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001160 # mshr miss rate for ReadReq accesses
1126system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006413 # mshr miss rate for UpgradeReq accesses
1127system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006413 # mshr miss rate for UpgradeReq accesses
1128system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1129system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1130system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433765 # mshr miss rate for ReadExReq accesses
1131system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433765 # mshr miss rate for ReadExReq accesses
1132system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for ReadCleanReq accesses
1133system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010572 # mshr miss rate for ReadCleanReq accesses
1134system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022967 # mshr miss rate for ReadSharedReq accesses
1135system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022967 # mshr miss rate for ReadSharedReq accesses
1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for demand accesses
1137system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for demand accesses
1138system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for demand accesses
1139system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for demand accesses
1140system.cpu.l2cache.demand_mshr_miss_rate::total 0.062642 # mshr miss rate for demand accesses
1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for overall accesses
1142system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for overall accesses
1143system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for overall accesses
1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for overall accesses
1145system.cpu.l2cache.overall_mshr_miss_rate::total 0.062642 # mshr miss rate for overall accesses
1146system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average ReadReq mshr miss latency
1147system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency
1148system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222 # average ReadReq mshr miss latency
1149system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19166.666667 # average UpgradeReq mshr miss latency
1150system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency
1151system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
1152system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
1153system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82658.969687 # average ReadExReq mshr miss latency
1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82658.969687 # average ReadExReq mshr miss latency
1155system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104938.591612 # average ReadCleanReq mshr miss latency
1156system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104938.591612 # average ReadCleanReq mshr miss latency
1157system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115916.418158 # average ReadSharedReq mshr miss latency
1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115916.418158 # average ReadSharedReq mshr miss latency
1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency
1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency
1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency
1163system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency
1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency
1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency
1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency
1168system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency
1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency
1170system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.061276 # average ReadReq mshr uncacheable latency
1171system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.609562 # average ReadReq mshr uncacheable latency
1172system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency
1173system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100387.964650 # average overall mshr uncacheable latency
1174system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.366854 # average overall mshr uncacheable latency
1175system.cpu.toL2Bus.snoop_filter.tot_requests 5065624 # Total number of requests made to the snoop filter.
1176system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543358 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1177system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1178system.cpu.toL2Bus.snoop_filter.tot_snoops 227 # Total number of snoops made to the snoop filter.
1179system.cpu.toL2Bus.snoop_filter.hit_single_snoops 227 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1180system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1181system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1182system.cpu.toL2Bus.trans_dist::ReadReq 67226 # Transaction distribution
1183system.cpu.toL2Bus.trans_dist::ReadResp 2293620 # Transaction distribution
1184system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
1185system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
1186system.cpu.toL2Bus.trans_dist::WritebackDirty 767586 # Transaction distribution
1187system.cpu.toL2Bus.trans_dist::WritebackClean 1700062 # Transaction distribution
1188system.cpu.toL2Bus.trans_dist::CleanEvict 142169 # Transaction distribution
1189system.cpu.toL2Bus.trans_dist::UpgradeReq 2807 # Transaction distribution
1190system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1191system.cpu.toL2Bus.trans_dist::UpgradeResp 2809 # Transaction distribution
1192system.cpu.toL2Bus.trans_dist::ReadExReq 296075 # Transaction distribution
1193system.cpu.toL2Bus.trans_dist::ReadExResp 296075 # Transaction distribution
1194system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700580 # Transaction distribution
1195system.cpu.toL2Bus.trans_dist::ReadSharedReq 525822 # Transaction distribution
1196system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution
1197system.cpu.toL2Bus.trans_dist::InvalidateResp 14 # Transaction distribution
1198system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119250 # Packet count per connected master and slave (bytes)
1199system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587830 # Packet count per connected master and slave (bytes)
1200system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes)
1201system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22920 # Packet count per connected master and slave (bytes)
1202system.cpu.toL2Bus.pkt_count::total 7741902 # Packet count per connected master and slave (bytes)
1203system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676152 # Cumulative packet size per connected master and slave (bytes)
1204system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663453 # Cumulative packet size per connected master and slave (bytes)
1205system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744 # Cumulative packet size per connected master and slave (bytes)
1206system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20280 # Cumulative packet size per connected master and slave (bytes)
1207system.cpu.toL2Bus.pkt_size::total 314370629 # Cumulative packet size per connected master and slave (bytes)
1208system.cpu.toL2Bus.snoops 112679 # Total snoops (count)
1209system.cpu.toL2Bus.snoopTraffic 5336568 # Total snoop traffic (bytes)
1210system.cpu.toL2Bus.snoop_fanout::samples 2713050 # Request fanout histogram
1211system.cpu.toL2Bus.snoop_fanout::mean 0.021694 # Request fanout histogram
1212system.cpu.toL2Bus.snoop_fanout::stdev 0.145681 # Request fanout histogram
1213system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1214system.cpu.toL2Bus.snoop_fanout::0 2654194 97.83% 97.83% # Request fanout histogram
1215system.cpu.toL2Bus.snoop_fanout::1 58856 2.17% 100.00% # Request fanout histogram
1216system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1217system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1218system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1219system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1220system.cpu.toL2Bus.snoop_fanout::total 2713050 # Request fanout histogram
1221system.cpu.toL2Bus.reqLayer0.occupancy 4970033000 # Layer occupancy (ticks)
1222system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1223system.cpu.toL2Bus.snoopLayer0.occupancy 354876 # Layer occupancy (ticks)
1224system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1225system.cpu.toL2Bus.respLayer0.occupancy 2559892000 # Layer occupancy (ticks)
1226system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1227system.cpu.toL2Bus.respLayer1.occupancy 1278884000 # Layer occupancy (ticks)
1228system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1229system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
1230system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1231system.cpu.toL2Bus.respLayer3.occupancy 17850000 # Layer occupancy (ticks)
1232system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1233system.iobus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1234system.iobus.trans_dist::ReadReq 30159 # Transaction distribution
1235system.iobus.trans_dist::ReadResp 30159 # Transaction distribution
1236system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1237system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1238system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1239system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1240system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1241system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1242system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1243system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1244system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
1245system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1246system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1247system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1248system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1249system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
1250system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1251system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1252system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
1253system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1254system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1255system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1256system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1257system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1258system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes)
1259system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes)
1260system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes)
1261system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1262system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1263system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
1264system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1265system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1266system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1267system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1268system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1269system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1270system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1271system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1272system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
1273system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1274system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1275system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
1276system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1277system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1278system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1279system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1280system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1281system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes)
1282system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes)
1283system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes)
1284system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks)
1285system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1286system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
1287system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1288system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
1289system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1290system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks)
1291system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1292system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks)
1293system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1294system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
1295system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1296system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks)
1297system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1298system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
1299system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1300system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
1301system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1302system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
1303system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1304system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
1305system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1306system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks)
1307system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1308system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
1309system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1310system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
1311system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1312system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
1313system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1314system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
1315system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1316system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
1317system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1318system.iobus.reqLayer23.occupancy 6289000 # Layer occupancy (ticks)
1319system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1320system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks)
1321system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1322system.iobus.reqLayer25.occupancy 187507137 # Layer occupancy (ticks)
1323system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1324system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1325system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1326system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks)
1327system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1328system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1329system.iocache.tags.replacements 36400 # number of replacements
1330system.iocache.tags.tagsinuse 1.079862 # Cycle average of tags in use
1331system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1332system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks.
1333system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1334system.iocache.tags.warmup_cycle 310617748000 # Cycle when the warmup percentage was hit.
1335system.iocache.tags.occ_blocks::realview.ide 1.079862 # Average occupied blocks per requestor
1336system.iocache.tags.occ_percent::realview.ide 0.067491 # Average percentage of cache occupancy
1337system.iocache.tags.occ_percent::total 0.067491 # Average percentage of cache occupancy
1338system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1339system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1340system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1341system.iocache.tags.tag_accesses 327906 # Number of tag accesses
1342system.iocache.tags.data_accesses 327906 # Number of data accesses
1343system.iocache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1344system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses
1345system.iocache.ReadReq_misses::total 210 # number of ReadReq misses
1346system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1347system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1348system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses
1349system.iocache.demand_misses::total 36434 # number of demand (read+write) misses
1350system.iocache.overall_misses::realview.ide 36434 # number of overall misses
1351system.iocache.overall_misses::total 36434 # number of overall misses
1352system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles
1353system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles
1354system.iocache.WriteLineReq_miss_latency::realview.ide 4377262761 # number of WriteLineReq miss cycles
1355system.iocache.WriteLineReq_miss_latency::total 4377262761 # number of WriteLineReq miss cycles
1356system.iocache.demand_miss_latency::realview.ide 4411329137 # number of demand (read+write) miss cycles
1357system.iocache.demand_miss_latency::total 4411329137 # number of demand (read+write) miss cycles
1358system.iocache.overall_miss_latency::realview.ide 4411329137 # number of overall miss cycles
1359system.iocache.overall_miss_latency::total 4411329137 # number of overall miss cycles
1360system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses)
1361system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses)
1362system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1363system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1364system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses
1365system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses
1366system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses
1367system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses
1368system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1369system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1370system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1371system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1372system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1373system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1374system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1375system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1376system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency
1377system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency
1378system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120838.746715 # average WriteLineReq miss latency
1379system.iocache.WriteLineReq_avg_miss_latency::total 120838.746715 # average WriteLineReq miss latency
1380system.iocache.demand_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency
1381system.iocache.demand_avg_miss_latency::total 121077.266756 # average overall miss latency
1382system.iocache.overall_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency
1383system.iocache.overall_avg_miss_latency::total 121077.266756 # average overall miss latency
1384system.iocache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked
1385system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1386system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
1387system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1388system.iocache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked
1389system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1390system.iocache.writebacks::writebacks 36190 # number of writebacks
1391system.iocache.writebacks::total 36190 # number of writebacks
1392system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses
1393system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses
1394system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1395system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1396system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses
1397system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses
1398system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses
1399system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses
1400system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles
1401system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles
1402system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564294505 # number of WriteLineReq MSHR miss cycles
1403system.iocache.WriteLineReq_mshr_miss_latency::total 2564294505 # number of WriteLineReq MSHR miss cycles
1404system.iocache.demand_mshr_miss_latency::realview.ide 2587860881 # number of demand (read+write) MSHR miss cycles
1405system.iocache.demand_mshr_miss_latency::total 2587860881 # number of demand (read+write) MSHR miss cycles
1406system.iocache.overall_mshr_miss_latency::realview.ide 2587860881 # number of overall MSHR miss cycles
1407system.iocache.overall_mshr_miss_latency::total 2587860881 # number of overall MSHR miss cycles
1408system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1409system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1410system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1411system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1412system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1413system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1414system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1415system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1416system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency
1417system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency
1418system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70789.932227 # average WriteLineReq mshr miss latency
1419system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70789.932227 # average WriteLineReq mshr miss latency
1420system.iocache.demand_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency
1421system.iocache.demand_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency
1422system.iocache.overall_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency
1423system.iocache.overall_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency
1424system.membus.snoop_filter.tot_requests 320000 # Total number of requests made to the snoop filter.
1425system.membus.snoop_filter.hit_single_requests 129537 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1426system.membus.snoop_filter.hit_multi_requests 496 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1427system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1428system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1429system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1430system.membus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1431system.membus.trans_dist::ReadReq 40160 # Transaction distribution
1432system.membus.trans_dist::ReadResp 70429 # Transaction distribution
1433system.membus.trans_dist::WriteReq 27589 # Transaction distribution
1434system.membus.trans_dist::WriteResp 27589 # Transaction distribution
1435system.membus.trans_dist::WritebackDirty 118160 # Transaction distribution
1436system.membus.trans_dist::CleanEvict 6838 # Transaction distribution
1437system.membus.trans_dist::UpgradeReq 128 # Transaction distribution
1438system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1439system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1440system.membus.trans_dist::ReadExReq 128317 # Transaction distribution
1441system.membus.trans_dist::ReadExResp 128317 # Transaction distribution
1442system.membus.trans_dist::ReadSharedReq 30269 # Transaction distribution
1443system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
1444system.membus.trans_dist::InvalidateResp 4315 # Transaction distribution
1445system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1446system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
1447system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
1448system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433109 # Packet count per connected master and slave (bytes)
1449system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540701 # Packet count per connected master and slave (bytes)
1450system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes)
1451system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes)
1452system.membus.pkt_count::total 613550 # Packet count per connected master and slave (bytes)
1453system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1454system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
1455system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
1456system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420284 # Cumulative packet size per connected master and slave (bytes)
1457system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583637 # Cumulative packet size per connected master and slave (bytes)
1458system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1459system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
1460system.membus.pkt_size::total 17900757 # Cumulative packet size per connected master and slave (bytes)
1461system.membus.snoops 4789 # Total snoops (count)
1462system.membus.snoopTraffic 30208 # Total snoop traffic (bytes)
1463system.membus.snoop_fanout::samples 262689 # Request fanout histogram
1464system.membus.snoop_fanout::mean 0.018383 # Request fanout histogram
1465system.membus.snoop_fanout::stdev 0.134332 # Request fanout histogram
1466system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1467system.membus.snoop_fanout::0 257860 98.16% 98.16% # Request fanout histogram
1468system.membus.snoop_fanout::1 4829 1.84% 100.00% # Request fanout histogram
1469system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1470system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1471system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1472system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1473system.membus.snoop_fanout::total 262689 # Request fanout histogram
1474system.membus.reqLayer0.occupancy 90467000 # Layer occupancy (ticks)
1475system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1476system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1477system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1478system.membus.reqLayer2.occupancy 1724500 # Layer occupancy (ticks)
1479system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1480system.membus.reqLayer5.occupancy 822822299 # Layer occupancy (ticks)
1481system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1482system.membus.respLayer2.occupancy 948652750 # Layer occupancy (ticks)
1483system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1484system.membus.respLayer3.occupancy 5614930 # Layer occupancy (ticks)
1485system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1486system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1487system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1488system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1489system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1490system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1491system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1492system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1493system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1494system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1495system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1496system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1497system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1498system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1499system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1500system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1501system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1502system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1503system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1504system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1505system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1506system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1507system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1508system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1509system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1510system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1511system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1512system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1513system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1514system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1515system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1516system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1517system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1518system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1519system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1520system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1521system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1522system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1523system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1524system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1525system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1526system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1527system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1528system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1529system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1530system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1531system.realview.ethernet.droppedPackets 0 # number of packets dropped
1532system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1533system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1534system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1535system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1536system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1537system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1538system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1539system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1540system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1541system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1542system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1543system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1544system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1545system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1546system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1547system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1548system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1549system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1550system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1551system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1552system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1553system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1554system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states
1555
1556---------- End Simulation Statistics ----------