1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.909343 # Number of seconds simulated
4sim_ticks 2909343316500 # Number of ticks simulated
5final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 666869 # Simulator instruction rate (inst/s)
8host_op_rate 804035 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 17251437084 # Simulator tick rate (ticks/s)
10host_mem_usage 624248 # Number of bytes of host memory used
11host_seconds 168.64 # Real time elapsed on the host
12sim_insts 112463069 # Number of instructions simulated
13sim_ops 135595282 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 166592 # Number of read requests accepted
55system.physmem.writeReqs 121840 # Number of write requests accepted
56system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
60system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 10226 # Per bank write bursts
67system.physmem.perBankRdBursts::1 9700 # Per bank write bursts
68system.physmem.perBankRdBursts::2 10356 # Per bank write bursts
69system.physmem.perBankRdBursts::3 10496 # Per bank write bursts
70system.physmem.perBankRdBursts::4 18505 # Per bank write bursts
71system.physmem.perBankRdBursts::5 10022 # Per bank write bursts
72system.physmem.perBankRdBursts::6 10179 # Per bank write bursts
73system.physmem.perBankRdBursts::7 10614 # Per bank write bursts
74system.physmem.perBankRdBursts::8 9478 # Per bank write bursts
75system.physmem.perBankRdBursts::9 10041 # Per bank write bursts
76system.physmem.perBankRdBursts::10 9320 # Per bank write bursts
77system.physmem.perBankRdBursts::11 9342 # Per bank write bursts
78system.physmem.perBankRdBursts::12 9424 # Per bank write bursts
79system.physmem.perBankRdBursts::13 10229 # Per bank write bursts
80system.physmem.perBankRdBursts::14 9340 # Per bank write bursts
81system.physmem.perBankRdBursts::15 9201 # Per bank write bursts
82system.physmem.perBankWrBursts::0 7577 # Per bank write bursts
83system.physmem.perBankWrBursts::1 7036 # Per bank write bursts
84system.physmem.perBankWrBursts::2 7887 # Per bank write bursts
85system.physmem.perBankWrBursts::3 8049 # Per bank write bursts
86system.physmem.perBankWrBursts::4 7151 # Per bank write bursts
87system.physmem.perBankWrBursts::5 7579 # Per bank write bursts
88system.physmem.perBankWrBursts::6 7566 # Per bank write bursts
89system.physmem.perBankWrBursts::7 7770 # Per bank write bursts
90system.physmem.perBankWrBursts::8 7275 # Per bank write bursts
91system.physmem.perBankWrBursts::9 7619 # Per bank write bursts
92system.physmem.perBankWrBursts::10 6810 # Per bank write bursts
93system.physmem.perBankWrBursts::11 7097 # Per bank write bursts
94system.physmem.perBankWrBursts::12 7200 # Per bank write bursts
95system.physmem.perBankWrBursts::13 7753 # Per bank write bursts
96system.physmem.perBankWrBursts::14 6925 # Per bank write bursts
97system.physmem.perBankWrBursts::15 6640 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
100system.physmem.totGap 2909342872000 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 9558 # Read request sizes (log2)
104system.physmem.readPktSize::3 14 # Read request sizes (log2)
105system.physmem.readPktSize::4 0 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 157020 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 4381 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 117459 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see

--- 28 unchanged lines hidden (view full) ---

154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 89 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 170 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 111 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 104 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes
231system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads
259system.physmem.totQLat 1636363750 # Total ticks spent queuing
260system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM
261system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers
262system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst
263system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
264system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst
265system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
266system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
267system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
268system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s
269system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
270system.physmem.busUtil 0.05 # Data bus utilization in percentage
271system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
272system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
273system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
274system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing
275system.physmem.readRowHits 136200 # Number of row buffer hits during reads
276system.physmem.writeRowHits 89619 # Number of row buffer hits during writes
277system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads
278system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes
279system.physmem.avgGap 10086754.84 # Average gap between requests
280system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined
281system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ)
282system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ)
283system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ)
284system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ)
285system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ)
286system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ)
287system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ)
288system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ)
289system.physmem_0.averagePower 669.621597 # Core power per rank (mW)
290system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states
291system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states
292system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
293system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states
294system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
295system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ)
296system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ)
297system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ)
298system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ)
299system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ)
300system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ)
301system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ)
302system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ)
303system.physmem_1.averagePower 669.478544 # Core power per rank (mW)
304system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states
305system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states
306system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
307system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states
308system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
309system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
310system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
311system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
312system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
313system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
314system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
315system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)

--- 33 unchanged lines hidden (view full) ---

349system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
350system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
351system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
352system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
353system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
354system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
355system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
356system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
357system.cpu.dtb.walker.walks 9555 # Table walker walks requested
358system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors
359system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate
360system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate
361system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency
362system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency
363system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency
364system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency
365system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency
366system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency
367system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency
368system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency
369system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
370system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
371system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency
372system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution
373system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution
374system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution
375system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated
376system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated
377system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated
378system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst
379system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
380system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst
381system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst
382system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
383system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst
384system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst
385system.cpu.dtb.inst_hits 0 # ITB inst hits
386system.cpu.dtb.inst_misses 0 # ITB inst misses
387system.cpu.dtb.read_hits 24521784 # DTB read hits
388system.cpu.dtb.read_misses 8135 # DTB read misses
389system.cpu.dtb.write_hits 19607400 # DTB write hits
390system.cpu.dtb.write_misses 1420 # DTB write misses
391system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
392system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
393system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
394system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
395system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
396system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
397system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch
398system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
399system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
400system.cpu.dtb.read_accesses 24529919 # DTB read accesses
401system.cpu.dtb.write_accesses 19608820 # DTB write accesses
402system.cpu.dtb.inst_accesses 0 # ITB inst accesses
403system.cpu.dtb.hits 44129184 # DTB hits
404system.cpu.dtb.misses 9555 # DTB misses
405system.cpu.dtb.accesses 44138739 # DTB accesses
406system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
407system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
408system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
409system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
410system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
411system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
412system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
413system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

427system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
428system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
429system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
430system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
431system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
432system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
433system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
434system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
435system.cpu.itb.walker.walks 4763 # Table walker walks requested
436system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
437system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
438system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
439system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
440system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
441system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
442system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
443system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency
444system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency
445system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency
446system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency
447system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency
448system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
449system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
450system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution
451system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution
452system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution
453system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
454system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
455system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
456system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
457system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
458system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
459system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
460system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
461system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
462system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
463system.cpu.itb.inst_hits 115560644 # ITB inst hits
464system.cpu.itb.inst_misses 4763 # ITB inst misses
465system.cpu.itb.read_hits 0 # DTB read hits
466system.cpu.itb.read_misses 0 # DTB read misses
467system.cpu.itb.write_hits 0 # DTB write hits
468system.cpu.itb.write_misses 0 # DTB write misses
469system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
470system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
471system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
472system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
473system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
474system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
475system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
476system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
477system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
478system.cpu.itb.read_accesses 0 # DTB read accesses
479system.cpu.itb.write_accesses 0 # DTB write accesses
480system.cpu.itb.inst_accesses 115565407 # ITB inst accesses
481system.cpu.itb.hits 115560644 # DTB hits
482system.cpu.itb.misses 4763 # DTB misses
483system.cpu.itb.accesses 115565407 # DTB accesses
484system.cpu.numCycles 5818686633 # number of cpu cycles simulated
485system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
486system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
487system.cpu.committedInsts 112463069 # Number of instructions committed
488system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed
489system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses
490system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
491system.cpu.num_func_calls 9893453 # number of times a function call or return occured
492system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls
493system.cpu.num_int_insts 119900050 # number of integer instructions
494system.cpu.num_fp_insts 11161 # number of float instructions
495system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read
496system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written
497system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
498system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
499system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read
500system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written
501system.cpu.num_mem_refs 45409486 # number of memory refs
502system.cpu.num_load_insts 24844046 # Number of load instructions
503system.cpu.num_store_insts 20565440 # Number of store instructions
504system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles
505system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles
506system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles
507system.cpu.idle_fraction 0.924573 # Percentage of idle cycles
508system.cpu.Branches 25918657 # Number of branches fetched
509system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
510system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction
511system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction
512system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
513system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
514system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
515system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
516system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
517system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
518system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
519system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction

--- 11 unchanged lines hidden (view full) ---

531system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
532system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
533system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
534system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
535system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Class of executed instruction
536system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
537system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
538system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
539system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction
540system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction
541system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
542system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
543system.cpu.op_class::total 138715716 # Class of executed instruction
544system.cpu.kern.inst.arm 0 # number of arm instructions executed
545system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
546system.cpu.dcache.tags.replacements 821347 # number of replacements
547system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use
548system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks.
549system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks.
550system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks.
551system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit.
552system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor
553system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy
554system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy
555system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
556system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
557system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
558system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
559system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
560system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
561system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses
562system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses
563system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits
564system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits
565system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits
566system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits
567system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits
568system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits
569system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits
570system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits
571system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits
572system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits
573system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits
574system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits
575system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits
576system.cpu.dcache.overall_hits::total 42329639 # number of overall hits
577system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses
578system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses
579system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses
580system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses
581system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses
582system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses
583system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses
584system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses
585system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
586system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
587system.cpu.dcache.demand_misses::cpu.data 700790 # number of demand (read+write) misses
588system.cpu.dcache.demand_misses::total 700790 # number of demand (read+write) misses
589system.cpu.dcache.overall_misses::cpu.data 819113 # number of overall misses
590system.cpu.dcache.overall_misses::total 819113 # number of overall misses
591system.cpu.dcache.ReadReq_miss_latency::cpu.data 6512815000 # number of ReadReq miss cycles
592system.cpu.dcache.ReadReq_miss_latency::total 6512815000 # number of ReadReq miss cycles
593system.cpu.dcache.WriteReq_miss_latency::cpu.data 19103648000 # number of WriteReq miss cycles
594system.cpu.dcache.WriteReq_miss_latency::total 19103648000 # number of WriteReq miss cycles
595system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294606000 # number of LoadLockedReq miss cycles
596system.cpu.dcache.LoadLockedReq_miss_latency::total 294606000 # number of LoadLockedReq miss cycles
597system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
598system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
599system.cpu.dcache.demand_miss_latency::cpu.data 25616463000 # number of demand (read+write) miss cycles
600system.cpu.dcache.demand_miss_latency::total 25616463000 # number of demand (read+write) miss cycles
601system.cpu.dcache.overall_miss_latency::cpu.data 25616463000 # number of overall miss cycles
602system.cpu.dcache.overall_miss_latency::total 25616463000 # number of overall miss cycles
603system.cpu.dcache.ReadReq_accesses::cpu.data 23514081 # number of ReadReq accesses(hits+misses)
604system.cpu.dcache.ReadReq_accesses::total 23514081 # number of ReadReq accesses(hits+misses)
605system.cpu.dcache.WriteReq_accesses::cpu.data 19123541 # number of WriteReq accesses(hits+misses)
606system.cpu.dcache.WriteReq_accesses::total 19123541 # number of WriteReq accesses(hits+misses)
607system.cpu.dcache.SoftPFReq_accesses::cpu.data 511130 # number of SoftPFReq accesses(hits+misses)
608system.cpu.dcache.SoftPFReq_accesses::total 511130 # number of SoftPFReq accesses(hits+misses)
609system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses)
610system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses)
611system.cpu.dcache.StoreCondReq_accesses::cpu.data 460202 # number of StoreCondReq accesses(hits+misses)
612system.cpu.dcache.StoreCondReq_accesses::total 460202 # number of StoreCondReq accesses(hits+misses)
613system.cpu.dcache.demand_accesses::cpu.data 42637622 # number of demand (read+write) accesses
614system.cpu.dcache.demand_accesses::total 42637622 # number of demand (read+write) accesses
615system.cpu.dcache.overall_accesses::cpu.data 43148752 # number of overall (read+write) accesses
616system.cpu.dcache.overall_accesses::total 43148752 # number of overall (read+write) accesses
617system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017088 # miss rate for ReadReq accesses
618system.cpu.dcache.ReadReq_miss_rate::total 0.017088 # miss rate for ReadReq accesses
619system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015634 # miss rate for WriteReq accesses
620system.cpu.dcache.WriteReq_miss_rate::total 0.015634 # miss rate for WriteReq accesses
621system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231493 # miss rate for SoftPFReq accesses
622system.cpu.dcache.SoftPFReq_miss_rate::total 0.231493 # miss rate for SoftPFReq accesses
623system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048836 # miss rate for LoadLockedReq accesses
624system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses
625system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
626system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
627system.cpu.dcache.demand_miss_rate::cpu.data 0.016436 # miss rate for demand accesses
628system.cpu.dcache.demand_miss_rate::total 0.016436 # miss rate for demand accesses
629system.cpu.dcache.overall_miss_rate::cpu.data 0.018983 # miss rate for overall accesses
630system.cpu.dcache.overall_miss_rate::total 0.018983 # miss rate for overall accesses
631system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16208.370456 # average ReadReq miss latency
632system.cpu.dcache.ReadReq_avg_miss_latency::total 16208.370456 # average ReadReq miss latency
633system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63897.783070 # average WriteReq miss latency
634system.cpu.dcache.WriteReq_avg_miss_latency::total 63897.783070 # average WriteReq miss latency
635system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12945.730984 # average LoadLockedReq miss latency
636system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12945.730984 # average LoadLockedReq miss latency
637system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
638system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
639system.cpu.dcache.demand_avg_miss_latency::cpu.data 36553.693689 # average overall miss latency
640system.cpu.dcache.demand_avg_miss_latency::total 36553.693689 # average overall miss latency
641system.cpu.dcache.overall_avg_miss_latency::cpu.data 31273.417709 # average overall miss latency
642system.cpu.dcache.overall_avg_miss_latency::total 31273.417709 # average overall miss latency
643system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
644system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
645system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
646system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
647system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
648system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
649system.cpu.dcache.fast_writes 0 # number of fast writes performed
650system.cpu.dcache.cache_copies 0 # number of cache copies performed
651system.cpu.dcache.writebacks::writebacks 685107 # number of writebacks
652system.cpu.dcache.writebacks::total 685107 # number of writebacks
653system.cpu.dcache.ReadReq_mshr_hits::cpu.data 939 # number of ReadReq MSHR hits
654system.cpu.dcache.ReadReq_mshr_hits::total 939 # number of ReadReq MSHR hits
655system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14240 # number of LoadLockedReq MSHR hits
656system.cpu.dcache.LoadLockedReq_mshr_hits::total 14240 # number of LoadLockedReq MSHR hits
657system.cpu.dcache.demand_mshr_hits::cpu.data 939 # number of demand (read+write) MSHR hits
658system.cpu.dcache.demand_mshr_hits::total 939 # number of demand (read+write) MSHR hits
659system.cpu.dcache.overall_mshr_hits::cpu.data 939 # number of overall MSHR hits
660system.cpu.dcache.overall_mshr_hits::total 939 # number of overall MSHR hits
661system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400879 # number of ReadReq MSHR misses
662system.cpu.dcache.ReadReq_mshr_misses::total 400879 # number of ReadReq MSHR misses
663system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298972 # number of WriteReq MSHR misses
664system.cpu.dcache.WriteReq_mshr_misses::total 298972 # number of WriteReq MSHR misses
665system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116280 # number of SoftPFReq MSHR misses
666system.cpu.dcache.SoftPFReq_mshr_misses::total 116280 # number of SoftPFReq MSHR misses
667system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8517 # number of LoadLockedReq MSHR misses
668system.cpu.dcache.LoadLockedReq_mshr_misses::total 8517 # number of LoadLockedReq MSHR misses
669system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
670system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
671system.cpu.dcache.demand_mshr_misses::cpu.data 699851 # number of demand (read+write) MSHR misses
672system.cpu.dcache.demand_mshr_misses::total 699851 # number of demand (read+write) MSHR misses
673system.cpu.dcache.overall_mshr_misses::cpu.data 816131 # number of overall MSHR misses
674system.cpu.dcache.overall_mshr_misses::total 816131 # number of overall MSHR misses
675system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
676system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
677system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
678system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
679system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
680system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
681system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080968000 # number of ReadReq MSHR miss cycles
682system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080968000 # number of ReadReq MSHR miss cycles
683system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18804676000 # number of WriteReq MSHR miss cycles
684system.cpu.dcache.WriteReq_mshr_miss_latency::total 18804676000 # number of WriteReq MSHR miss cycles
685system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617499500 # number of SoftPFReq MSHR miss cycles
686system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617499500 # number of SoftPFReq MSHR miss cycles
687system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115437000 # number of LoadLockedReq MSHR miss cycles
688system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115437000 # number of LoadLockedReq MSHR miss cycles
689system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles
690system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles
691system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24885644000 # number of demand (read+write) MSHR miss cycles
692system.cpu.dcache.demand_mshr_miss_latency::total 24885644000 # number of demand (read+write) MSHR miss cycles
693system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26503143500 # number of overall MSHR miss cycles
694system.cpu.dcache.overall_mshr_miss_latency::total 26503143500 # number of overall MSHR miss cycles
695system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5936758500 # number of ReadReq MSHR uncacheable cycles
696system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5936758500 # number of ReadReq MSHR uncacheable cycles
697system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4791465500 # number of WriteReq MSHR uncacheable cycles
698system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4791465500 # number of WriteReq MSHR uncacheable cycles
699system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10728224000 # number of overall MSHR uncacheable cycles
700system.cpu.dcache.overall_mshr_uncacheable_latency::total 10728224000 # number of overall MSHR uncacheable cycles
701system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017048 # mshr miss rate for ReadReq accesses
702system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017048 # mshr miss rate for ReadReq accesses
703system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015634 # mshr miss rate for WriteReq accesses
704system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015634 # mshr miss rate for WriteReq accesses
705system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227496 # mshr miss rate for SoftPFReq accesses
706system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227496 # mshr miss rate for SoftPFReq accesses
707system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018277 # mshr miss rate for LoadLockedReq accesses
708system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018277 # mshr miss rate for LoadLockedReq accesses
709system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
710system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
711system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses
712system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses
713system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses
714system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses
715system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency
716system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency
717system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency
718system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency
719system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency
720system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency
721system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency
722system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency
723system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
724system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
725system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35558.488878 # average overall mshr miss latency
726system.cpu.dcache.demand_avg_mshr_miss_latency::total 35558.488878 # average overall mshr miss latency
727system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32474.129153 # average overall mshr miss latency
728system.cpu.dcache.overall_avg_mshr_miss_latency::total 32474.129153 # average overall mshr miss latency
729system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190659.595992 # average ReadReq mshr uncacheable latency
730system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.595992 # average ReadReq mshr uncacheable latency
731system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173673.039980 # average WriteReq mshr uncacheable latency
732system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173673.039980 # average WriteReq mshr uncacheable latency
733system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.585199 # average overall mshr uncacheable latency
734system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.585199 # average overall mshr uncacheable latency
735system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
736system.cpu.icache.tags.replacements 1696276 # number of replacements
737system.cpu.icache.tags.tagsinuse 510.440576 # Cycle average of tags in use
738system.cpu.icache.tags.total_refs 113863850 # Total number of references to valid blocks.
739system.cpu.icache.tags.sampled_refs 1696788 # Sample count of references to valid blocks.
740system.cpu.icache.tags.avg_refs 67.105525 # Average number of references to valid blocks.
741system.cpu.icache.tags.warmup_cycle 28967481500 # Cycle when the warmup percentage was hit.
742system.cpu.icache.tags.occ_blocks::cpu.inst 510.440576 # Average occupied blocks per requestor
743system.cpu.icache.tags.occ_percent::cpu.inst 0.996954 # Average percentage of cache occupancy
744system.cpu.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
745system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
746system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
747system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
748system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
749system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
750system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
751system.cpu.icache.tags.tag_accesses 117257438 # Number of tag accesses
752system.cpu.icache.tags.data_accesses 117257438 # Number of data accesses
753system.cpu.icache.ReadReq_hits::cpu.inst 113863850 # number of ReadReq hits
754system.cpu.icache.ReadReq_hits::total 113863850 # number of ReadReq hits
755system.cpu.icache.demand_hits::cpu.inst 113863850 # number of demand (read+write) hits
756system.cpu.icache.demand_hits::total 113863850 # number of demand (read+write) hits
757system.cpu.icache.overall_hits::cpu.inst 113863850 # number of overall hits
758system.cpu.icache.overall_hits::total 113863850 # number of overall hits
759system.cpu.icache.ReadReq_misses::cpu.inst 1696794 # number of ReadReq misses
760system.cpu.icache.ReadReq_misses::total 1696794 # number of ReadReq misses
761system.cpu.icache.demand_misses::cpu.inst 1696794 # number of demand (read+write) misses
762system.cpu.icache.demand_misses::total 1696794 # number of demand (read+write) misses
763system.cpu.icache.overall_misses::cpu.inst 1696794 # number of overall misses
764system.cpu.icache.overall_misses::total 1696794 # number of overall misses
765system.cpu.icache.ReadReq_miss_latency::cpu.inst 24262817500 # number of ReadReq miss cycles
766system.cpu.icache.ReadReq_miss_latency::total 24262817500 # number of ReadReq miss cycles
767system.cpu.icache.demand_miss_latency::cpu.inst 24262817500 # number of demand (read+write) miss cycles
768system.cpu.icache.demand_miss_latency::total 24262817500 # number of demand (read+write) miss cycles
769system.cpu.icache.overall_miss_latency::cpu.inst 24262817500 # number of overall miss cycles
770system.cpu.icache.overall_miss_latency::total 24262817500 # number of overall miss cycles
771system.cpu.icache.ReadReq_accesses::cpu.inst 115560644 # number of ReadReq accesses(hits+misses)
772system.cpu.icache.ReadReq_accesses::total 115560644 # number of ReadReq accesses(hits+misses)
773system.cpu.icache.demand_accesses::cpu.inst 115560644 # number of demand (read+write) accesses
774system.cpu.icache.demand_accesses::total 115560644 # number of demand (read+write) accesses
775system.cpu.icache.overall_accesses::cpu.inst 115560644 # number of overall (read+write) accesses
776system.cpu.icache.overall_accesses::total 115560644 # number of overall (read+write) accesses
777system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014683 # miss rate for ReadReq accesses
778system.cpu.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses
779system.cpu.icache.demand_miss_rate::cpu.inst 0.014683 # miss rate for demand accesses
780system.cpu.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses
781system.cpu.icache.overall_miss_rate::cpu.inst 0.014683 # miss rate for overall accesses
782system.cpu.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses
783system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14299.212220 # average ReadReq miss latency
784system.cpu.icache.ReadReq_avg_miss_latency::total 14299.212220 # average ReadReq miss latency
785system.cpu.icache.demand_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency
786system.cpu.icache.demand_avg_miss_latency::total 14299.212220 # average overall miss latency
787system.cpu.icache.overall_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency
788system.cpu.icache.overall_avg_miss_latency::total 14299.212220 # average overall miss latency
789system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
790system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
791system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
792system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
793system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
794system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
795system.cpu.icache.fast_writes 0 # number of fast writes performed
796system.cpu.icache.cache_copies 0 # number of cache copies performed
797system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696794 # number of ReadReq MSHR misses
798system.cpu.icache.ReadReq_mshr_misses::total 1696794 # number of ReadReq MSHR misses
799system.cpu.icache.demand_mshr_misses::cpu.inst 1696794 # number of demand (read+write) MSHR misses
800system.cpu.icache.demand_mshr_misses::total 1696794 # number of demand (read+write) MSHR misses
801system.cpu.icache.overall_mshr_misses::cpu.inst 1696794 # number of overall MSHR misses
802system.cpu.icache.overall_mshr_misses::total 1696794 # number of overall MSHR misses
803system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
804system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
805system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
806system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
807system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles
808system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles
809system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles
810system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles
811system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles
812system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles
813system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles
814system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles
815system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles
816system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles
817system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for ReadReq accesses
818system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses
819system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for demand accesses
820system.cpu.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses
821system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for overall accesses
822system.cpu.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses
823system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13299.212220 # average ReadReq mshr miss latency
824system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13299.212220 # average ReadReq mshr miss latency
825system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency
826system.cpu.icache.demand_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency
827system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency
828system.cpu.icache.overall_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency
829system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency
830system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
831system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
832system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
833system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
834system.cpu.l2cache.tags.replacements 87598 # number of replacements
835system.cpu.l2cache.tags.tagsinuse 64865.821065 # Cycle average of tags in use
836system.cpu.l2cache.tags.total_refs 4548879 # Total number of references to valid blocks.
837system.cpu.l2cache.tags.sampled_refs 152768 # Sample count of references to valid blocks.
838system.cpu.l2cache.tags.avg_refs 29.776386 # Average number of references to valid blocks.
839system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
840system.cpu.l2cache.tags.occ_blocks::writebacks 50190.412542 # Average occupied blocks per requestor
841system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.801705 # Average occupied blocks per requestor
842system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012642 # Average occupied blocks per requestor
843system.cpu.l2cache.tags.occ_blocks::cpu.inst 9659.374197 # Average occupied blocks per requestor
844system.cpu.l2cache.tags.occ_blocks::cpu.data 5012.219980 # Average occupied blocks per requestor
845system.cpu.l2cache.tags.occ_percent::writebacks 0.765845 # Average percentage of cache occupancy
846system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
847system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
848system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147390 # Average percentage of cache occupancy
849system.cpu.l2cache.tags.occ_percent::cpu.data 0.076480 # Average percentage of cache occupancy
850system.cpu.l2cache.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy
851system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
852system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id
853system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
854system.cpu.l2cache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
855system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
856system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id
857system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id
858system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id
859system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
860system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id
861system.cpu.l2cache.tags.tag_accesses 40555786 # Number of tag accesses
862system.cpu.l2cache.tags.data_accesses 40555786 # Number of data accesses
863system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7774 # number of ReadReq hits
864system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4032 # number of ReadReq hits
865system.cpu.l2cache.ReadReq_hits::total 11806 # number of ReadReq hits
866system.cpu.l2cache.Writeback_hits::writebacks 685107 # number of Writeback hits
867system.cpu.l2cache.Writeback_hits::total 685107 # number of Writeback hits
868system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits
869system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits
870system.cpu.l2cache.ReadExReq_hits::cpu.data 167410 # number of ReadExReq hits
871system.cpu.l2cache.ReadExReq_hits::total 167410 # number of ReadExReq hits
872system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678817 # number of ReadCleanReq hits
873system.cpu.l2cache.ReadCleanReq_hits::total 1678817 # number of ReadCleanReq hits
874system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513395 # number of ReadSharedReq hits
875system.cpu.l2cache.ReadSharedReq_hits::total 513395 # number of ReadSharedReq hits
876system.cpu.l2cache.demand_hits::cpu.dtb.walker 7774 # number of demand (read+write) hits
877system.cpu.l2cache.demand_hits::cpu.itb.walker 4032 # number of demand (read+write) hits
878system.cpu.l2cache.demand_hits::cpu.inst 1678817 # number of demand (read+write) hits
879system.cpu.l2cache.demand_hits::cpu.data 680805 # number of demand (read+write) hits
880system.cpu.l2cache.demand_hits::total 2371428 # number of demand (read+write) hits
881system.cpu.l2cache.overall_hits::cpu.dtb.walker 7774 # number of overall hits
882system.cpu.l2cache.overall_hits::cpu.itb.walker 4032 # number of overall hits
883system.cpu.l2cache.overall_hits::cpu.inst 1678817 # number of overall hits
884system.cpu.l2cache.overall_hits::cpu.data 680805 # number of overall hits
885system.cpu.l2cache.overall_hits::total 2371428 # number of overall hits
886system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
887system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
888system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
889system.cpu.l2cache.UpgradeReq_misses::cpu.data 2735 # number of UpgradeReq misses
890system.cpu.l2cache.UpgradeReq_misses::total 2735 # number of UpgradeReq misses
891system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
892system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
893system.cpu.l2cache.ReadExReq_misses::cpu.data 128803 # number of ReadExReq misses
894system.cpu.l2cache.ReadExReq_misses::total 128803 # number of ReadExReq misses
895system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17954 # number of ReadCleanReq misses
896system.cpu.l2cache.ReadCleanReq_misses::total 17954 # number of ReadCleanReq misses
897system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12281 # number of ReadSharedReq misses
898system.cpu.l2cache.ReadSharedReq_misses::total 12281 # number of ReadSharedReq misses
899system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
900system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
901system.cpu.l2cache.demand_misses::cpu.inst 17954 # number of demand (read+write) misses
902system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses
903system.cpu.l2cache.demand_misses::total 159047 # number of demand (read+write) misses
904system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
905system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
906system.cpu.l2cache.overall_misses::cpu.inst 17954 # number of overall misses
907system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses
908system.cpu.l2cache.overall_misses::total 159047 # number of overall misses
909system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 929000 # number of ReadReq miss cycles
910system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles
911system.cpu.l2cache.ReadReq_miss_latency::total 1195000 # number of ReadReq miss cycles
912system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1856500 # number of UpgradeReq miss cycles
913system.cpu.l2cache.UpgradeReq_miss_latency::total 1856500 # number of UpgradeReq miss cycles
914system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
915system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
916system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16377126500 # number of ReadExReq miss cycles
917system.cpu.l2cache.ReadExReq_miss_latency::total 16377126500 # number of ReadExReq miss cycles
918system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2358568000 # number of ReadCleanReq miss cycles
919system.cpu.l2cache.ReadCleanReq_miss_latency::total 2358568000 # number of ReadCleanReq miss cycles
920system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1624402500 # number of ReadSharedReq miss cycles
921system.cpu.l2cache.ReadSharedReq_miss_latency::total 1624402500 # number of ReadSharedReq miss cycles
922system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 929000 # number of demand (read+write) miss cycles
923system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles
924system.cpu.l2cache.demand_miss_latency::cpu.inst 2358568000 # number of demand (read+write) miss cycles
925system.cpu.l2cache.demand_miss_latency::cpu.data 18001529000 # number of demand (read+write) miss cycles
926system.cpu.l2cache.demand_miss_latency::total 20361292000 # number of demand (read+write) miss cycles
927system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 929000 # number of overall miss cycles
928system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles
929system.cpu.l2cache.overall_miss_latency::cpu.inst 2358568000 # number of overall miss cycles
930system.cpu.l2cache.overall_miss_latency::cpu.data 18001529000 # number of overall miss cycles
931system.cpu.l2cache.overall_miss_latency::total 20361292000 # number of overall miss cycles
932system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7781 # number of ReadReq accesses(hits+misses)
933system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4034 # number of ReadReq accesses(hits+misses)
934system.cpu.l2cache.ReadReq_accesses::total 11815 # number of ReadReq accesses(hits+misses)
935system.cpu.l2cache.Writeback_accesses::writebacks 685107 # number of Writeback accesses(hits+misses)
936system.cpu.l2cache.Writeback_accesses::total 685107 # number of Writeback accesses(hits+misses)
937system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2759 # number of UpgradeReq accesses(hits+misses)
938system.cpu.l2cache.UpgradeReq_accesses::total 2759 # number of UpgradeReq accesses(hits+misses)
939system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
940system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
941system.cpu.l2cache.ReadExReq_accesses::cpu.data 296213 # number of ReadExReq accesses(hits+misses)
942system.cpu.l2cache.ReadExReq_accesses::total 296213 # number of ReadExReq accesses(hits+misses)
943system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696771 # number of ReadCleanReq accesses(hits+misses)
944system.cpu.l2cache.ReadCleanReq_accesses::total 1696771 # number of ReadCleanReq accesses(hits+misses)
945system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525676 # number of ReadSharedReq accesses(hits+misses)
946system.cpu.l2cache.ReadSharedReq_accesses::total 525676 # number of ReadSharedReq accesses(hits+misses)
947system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7781 # number of demand (read+write) accesses
948system.cpu.l2cache.demand_accesses::cpu.itb.walker 4034 # number of demand (read+write) accesses
949system.cpu.l2cache.demand_accesses::cpu.inst 1696771 # number of demand (read+write) accesses
950system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses
951system.cpu.l2cache.demand_accesses::total 2530475 # number of demand (read+write) accesses
952system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7781 # number of overall (read+write) accesses
953system.cpu.l2cache.overall_accesses::cpu.itb.walker 4034 # number of overall (read+write) accesses
954system.cpu.l2cache.overall_accesses::cpu.inst 1696771 # number of overall (read+write) accesses
955system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses
956system.cpu.l2cache.overall_accesses::total 2530475 # number of overall (read+write) accesses
957system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000900 # miss rate for ReadReq accesses
958system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000496 # miss rate for ReadReq accesses
959system.cpu.l2cache.ReadReq_miss_rate::total 0.000762 # miss rate for ReadReq accesses
960system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991301 # miss rate for UpgradeReq accesses
961system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991301 # miss rate for UpgradeReq accesses
962system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
963system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
964system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.434832 # miss rate for ReadExReq accesses
965system.cpu.l2cache.ReadExReq_miss_rate::total 0.434832 # miss rate for ReadExReq accesses
966system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010581 # miss rate for ReadCleanReq accesses
967system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010581 # miss rate for ReadCleanReq accesses
968system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023362 # miss rate for ReadSharedReq accesses
969system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023362 # miss rate for ReadSharedReq accesses
970system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000900 # miss rate for demand accesses
971system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000496 # miss rate for demand accesses
972system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010581 # miss rate for demand accesses
973system.cpu.l2cache.demand_miss_rate::cpu.data 0.171658 # miss rate for demand accesses
974system.cpu.l2cache.demand_miss_rate::total 0.062853 # miss rate for demand accesses
975system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000900 # miss rate for overall accesses
976system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000496 # miss rate for overall accesses
977system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010581 # miss rate for overall accesses
978system.cpu.l2cache.overall_miss_rate::cpu.data 0.171658 # miss rate for overall accesses
979system.cpu.l2cache.overall_miss_rate::total 0.062853 # miss rate for overall accesses
980system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132714.285714 # average ReadReq miss latency
981system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency
982system.cpu.l2cache.ReadReq_avg_miss_latency::total 132777.777778 # average ReadReq miss latency
983system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 678.793419 # average UpgradeReq miss latency
984system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 678.793419 # average UpgradeReq miss latency
985system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
986system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
987system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127148.641724 # average ReadExReq miss latency
988system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127148.641724 # average ReadExReq miss latency
989system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131367.271917 # average ReadCleanReq miss latency
990system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131367.271917 # average ReadCleanReq miss latency
991system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132269.562739 # average ReadSharedReq miss latency
992system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132269.562739 # average ReadSharedReq miss latency
993system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132714.285714 # average overall miss latency
994system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
995system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131367.271917 # average overall miss latency
996system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127594.404752 # average overall miss latency
997system.cpu.l2cache.demand_avg_miss_latency::total 128020.597685 # average overall miss latency
998system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132714.285714 # average overall miss latency
999system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
1000system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131367.271917 # average overall miss latency
1001system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127594.404752 # average overall miss latency
1002system.cpu.l2cache.overall_avg_miss_latency::total 128020.597685 # average overall miss latency
1003system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1004system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1005system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1006system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1007system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1008system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1009system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1010system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1011system.cpu.l2cache.writebacks::writebacks 81269 # number of writebacks
1012system.cpu.l2cache.writebacks::total 81269 # number of writebacks
1013system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
1014system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
1015system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
1016system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2735 # number of UpgradeReq MSHR misses
1017system.cpu.l2cache.UpgradeReq_mshr_misses::total 2735 # number of UpgradeReq MSHR misses
1018system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1019system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1020system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128803 # number of ReadExReq MSHR misses
1021system.cpu.l2cache.ReadExReq_mshr_misses::total 128803 # number of ReadExReq MSHR misses
1022system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17954 # number of ReadCleanReq MSHR misses
1023system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17954 # number of ReadCleanReq MSHR misses
1024system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12281 # number of ReadSharedReq MSHR misses
1025system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12281 # number of ReadSharedReq MSHR misses
1026system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
1027system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
1028system.cpu.l2cache.demand_mshr_misses::cpu.inst 17954 # number of demand (read+write) MSHR misses
1029system.cpu.l2cache.demand_mshr_misses::cpu.data 141084 # number of demand (read+write) MSHR misses
1030system.cpu.l2cache.demand_mshr_misses::total 159047 # number of demand (read+write) MSHR misses
1031system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
1032system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
1033system.cpu.l2cache.overall_mshr_misses::cpu.inst 17954 # number of overall MSHR misses
1034system.cpu.l2cache.overall_mshr_misses::cpu.data 141084 # number of overall MSHR misses
1035system.cpu.l2cache.overall_mshr_misses::total 159047 # number of overall MSHR misses
1036system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
1037system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
1038system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
1039system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
1040system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
1041system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
1042system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
1043system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
1044system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 859000 # number of ReadReq MSHR miss cycles
1045system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles
1046system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1105000 # number of ReadReq MSHR miss cycles
1047system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 193639500 # number of UpgradeReq MSHR miss cycles
1048system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 193639500 # number of UpgradeReq MSHR miss cycles
1049system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles
1050system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles
1051system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15089096500 # number of ReadExReq MSHR miss cycles
1052system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15089096500 # number of ReadExReq MSHR miss cycles
1053system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2179028000 # number of ReadCleanReq MSHR miss cycles
1054system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2179028000 # number of ReadCleanReq MSHR miss cycles
1055system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1501592500 # number of ReadSharedReq MSHR miss cycles
1056system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1501592500 # number of ReadSharedReq MSHR miss cycles
1057system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 859000 # number of demand (read+write) MSHR miss cycles
1058system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles
1059system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2179028000 # number of demand (read+write) MSHR miss cycles
1060system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16590689000 # number of demand (read+write) MSHR miss cycles
1061system.cpu.l2cache.demand_mshr_miss_latency::total 18770822000 # number of demand (read+write) MSHR miss cycles
1062system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 859000 # number of overall MSHR miss cycles
1063system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles
1064system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2179028000 # number of overall MSHR miss cycles
1065system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16590689000 # number of overall MSHR miss cycles
1066system.cpu.l2cache.overall_mshr_miss_latency::total 18770822000 # number of overall MSHR miss cycles
1067system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles
1068system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5547532500 # number of ReadReq MSHR uncacheable cycles
1069system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6577298500 # number of ReadReq MSHR uncacheable cycles
1070system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4474192000 # number of WriteReq MSHR uncacheable cycles
1071system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4474192000 # number of WriteReq MSHR uncacheable cycles
1072system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles
1073system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10021724500 # number of overall MSHR uncacheable cycles
1074system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11051490500 # number of overall MSHR uncacheable cycles
1075system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for ReadReq accesses
1076system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadReq accesses
1077system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000762 # mshr miss rate for ReadReq accesses
1078system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991301 # mshr miss rate for UpgradeReq accesses
1079system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses
1080system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1081system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1082system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses
1083system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses
1084system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses
1085system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses
1086system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses
1087system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses
1088system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses
1089system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses
1090system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses
1091system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses
1092system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses
1093system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses
1094system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses
1095system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses
1096system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses
1097system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses
1098system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency
1099system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency
1100system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency
1101system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency
1102system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency
1103system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
1104system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
1105system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency
1106system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency
1107system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency
1108system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency
1109system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency
1110system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency
1111system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency
1112system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
1113system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency
1114system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency
1115system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency
1116system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency
1117system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
1118system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency
1119system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency
1120system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency
1121system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency
1122system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency
1123system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency
1124system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency
1125system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency
1126system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency
1127system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency
1128system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency
1129system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1130system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter.
1131system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1132system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1133system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter.
1134system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1135system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1136system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution
1137system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution
1138system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
1139system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
1140system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution
1141system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution
1142system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution
1143system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1144system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
1145system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution
1146system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution
1147system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution
1148system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution
1149system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1150system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes)
1151system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes)
1152system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes)
1153system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes)
1154system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes)
1155system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes)
1156system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes)
1157system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes)
1158system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes)
1159system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes)
1160system.cpu.toL2Bus.snoops 175948 # Total snoops (count)
1161system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram
1162system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram
1163system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram
1164system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1165system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram
1166system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram
1167system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1168system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1169system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1170system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1171system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram
1172system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks)
1173system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1174system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks)
1175system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1176system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks)
1177system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1178system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks)
1179system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1180system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
1181system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1182system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks)
1183system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1184system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
1185system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
1186system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1187system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1188system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1189system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1190system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1191system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1192system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1193system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)

--- 8 unchanged lines hidden (view full) ---

1202system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1203system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1204system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1205system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1206system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1207system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1208system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1209system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1210system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes)
1211system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes)
1212system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
1213system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1214system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1215system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1216system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1217system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1218system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1219system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1220system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)

--- 6 unchanged lines hidden (view full) ---

1227system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1228system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1229system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1230system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
1231system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1232system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
1233system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1234system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1235system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes)
1236system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes)
1237system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes)
1238system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
1239system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1240system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
1241system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1242system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
1243system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1244system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
1245system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)

--- 24 unchanged lines hidden (view full) ---

1270system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
1271system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1272system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
1273system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1274system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
1275system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1276system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
1277system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1278system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks)
1279system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1280system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1281system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1282system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1283system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1284system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
1285system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1286system.iocache.tags.replacements 36418 # number of replacements
1287system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use
1288system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1289system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks.
1290system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1291system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit.
1292system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor
1293system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy
1294system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy
1295system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1296system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1297system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1298system.iocache.tags.tag_accesses 328068 # Number of tag accesses
1299system.iocache.tags.data_accesses 328068 # Number of data accesses
1300system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
1301system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
1302system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1303system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1304system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
1305system.iocache.demand_misses::total 228 # number of demand (read+write) misses
1306system.iocache.overall_misses::realview.ide 228 # number of overall misses
1307system.iocache.overall_misses::total 228 # number of overall misses
1308system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles
1309system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles
1310system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles
1311system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles
1312system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles
1313system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles
1314system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles
1315system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles
1316system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
1317system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
1318system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1319system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1320system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
1321system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
1322system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
1323system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
1324system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1325system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1326system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1327system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1328system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1329system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1330system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1331system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1332system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency
1333system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency
1334system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency
1335system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency
1336system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency
1337system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency
1338system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency
1339system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency
1340system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1341system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1342system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1343system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1344system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1345system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1346system.iocache.fast_writes 0 # number of fast writes performed
1347system.iocache.cache_copies 0 # number of cache copies performed
1348system.iocache.writebacks::writebacks 36190 # number of writebacks
1349system.iocache.writebacks::total 36190 # number of writebacks
1350system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
1351system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
1352system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1353system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1354system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
1355system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
1356system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
1357system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
1358system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles
1359system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles
1360system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles
1361system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles
1362system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles
1363system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles
1364system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles
1365system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles
1366system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1367system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1368system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1369system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1370system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1371system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1372system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1373system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1374system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency
1375system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency
1376system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency
1377system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency
1378system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency
1379system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency
1380system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency
1381system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency
1382system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1383system.membus.trans_dist::ReadReq 40160 # Transaction distribution
1384system.membus.trans_dist::ReadResp 70632 # Transaction distribution
1385system.membus.trans_dist::WriteReq 27589 # Transaction distribution
1386system.membus.trans_dist::WriteResp 27589 # Transaction distribution
1387system.membus.trans_dist::Writeback 117459 # Transaction distribution
1388system.membus.trans_dist::CleanEvict 6342 # Transaction distribution
1389system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution
1390system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1391system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution
1392system.membus.trans_dist::ReadExReq 127038 # Transaction distribution
1393system.membus.trans_dist::ReadExResp 127038 # Transaction distribution
1394system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution
1395system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
1396system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
1397system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1398system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
1399system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
1400system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes)
1401system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes)
1402system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes)
1403system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes)
1404system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes)
1405system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1406system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
1407system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
1408system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes)
1409system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes)
1410system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1411system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
1412system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes)
1413system.membus.snoops 492 # Total snoops (count)
1414system.membus.snoop_fanout::samples 390004 # Request fanout histogram
1415system.membus.snoop_fanout::mean 1 # Request fanout histogram
1416system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1417system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1418system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1419system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram
1420system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1421system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1422system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1423system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1424system.membus.snoop_fanout::total 390004 # Request fanout histogram
1425system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks)
1426system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1427system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1428system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1429system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks)
1430system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1431system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks)
1432system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1433system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks)
1434system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1435system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks)
1436system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1437system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1438system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1439system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1440system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1441system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1442system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1443system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

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1460system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1461system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1462system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1463system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1464system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1465system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1466system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1467system.realview.ethernet.droppedPackets 0 # number of packets dropped
1468system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
1469system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
1470system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
1471system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
1472system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
1473system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
1474system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
1475system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
1476system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
1477system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
1478
1479---------- End Simulation Statistics ----------