| config.ini (10636:9ac724889705) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 24 unchanged lines hidden (view full) --- 33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=timing 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 24 unchanged lines hidden (view full) --- 33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=timing 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram |
| 41mmap_using_noreserve=false |
|
| 41multi_proc=true 42num_work_ids=16 43panic_on_oops=true 44panic_on_panic=true 45phys_addr_range_64=40 46readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 47reset_addr_64=0 48symbolfile= --- 119 unchanged lines hidden (view full) --- 168sequential_access=false 169size=32768 170 171[system.cpu.dstage2_mmu] 172type=ArmStage2MMU 173children=stage2_tlb 174eventq_index=0 175stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb | 42multi_proc=true 43num_work_ids=16 44panic_on_oops=true 45panic_on_panic=true 46phys_addr_range_64=40 47readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 48reset_addr_64=0 49symbolfile= --- 119 unchanged lines hidden (view full) --- 169sequential_access=false 170size=32768 171 172[system.cpu.dstage2_mmu] 173type=ArmStage2MMU 174children=stage2_tlb 175eventq_index=0 176stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| 177sys=system |
|
| 176tlb=system.cpu.dtb 177 178[system.cpu.dstage2_mmu.stage2_tlb] 179type=ArmTLB 180children=walker 181eventq_index=0 182is_stage2=true 183size=32 184walker=system.cpu.dstage2_mmu.stage2_tlb.walker 185 186[system.cpu.dstage2_mmu.stage2_tlb.walker] 187type=ArmTableWalker 188clk_domain=system.cpu_clk_domain 189eventq_index=0 190is_stage2=true 191num_squash_per_cycle=2 192sys=system | 178tlb=system.cpu.dtb 179 180[system.cpu.dstage2_mmu.stage2_tlb] 181type=ArmTLB 182children=walker 183eventq_index=0 184is_stage2=true 185size=32 186walker=system.cpu.dstage2_mmu.stage2_tlb.walker 187 188[system.cpu.dstage2_mmu.stage2_tlb.walker] 189type=ArmTableWalker 190clk_domain=system.cpu_clk_domain 191eventq_index=0 192is_stage2=true 193num_squash_per_cycle=2 194sys=system |
| 193port=system.cpu.toL2Bus.slave[5] | |
| 194 195[system.cpu.dtb] 196type=ArmTLB 197children=walker 198eventq_index=0 199is_stage2=false 200size=64 201walker=system.cpu.dtb.walker --- 77 unchanged lines hidden (view full) --- 279pmu=Null 280system=system 281 282[system.cpu.istage2_mmu] 283type=ArmStage2MMU 284children=stage2_tlb 285eventq_index=0 286stage2_tlb=system.cpu.istage2_mmu.stage2_tlb | 195 196[system.cpu.dtb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=false 201size=64 202walker=system.cpu.dtb.walker --- 77 unchanged lines hidden (view full) --- 280pmu=Null 281system=system 282 283[system.cpu.istage2_mmu] 284type=ArmStage2MMU 285children=stage2_tlb 286eventq_index=0 287stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| 288sys=system |
|
| 287tlb=system.cpu.itb 288 289[system.cpu.istage2_mmu.stage2_tlb] 290type=ArmTLB 291children=walker 292eventq_index=0 293is_stage2=true 294size=32 295walker=system.cpu.istage2_mmu.stage2_tlb.walker 296 297[system.cpu.istage2_mmu.stage2_tlb.walker] 298type=ArmTableWalker 299clk_domain=system.cpu_clk_domain 300eventq_index=0 301is_stage2=true 302num_squash_per_cycle=2 303sys=system | 289tlb=system.cpu.itb 290 291[system.cpu.istage2_mmu.stage2_tlb] 292type=ArmTLB 293children=walker 294eventq_index=0 295is_stage2=true 296size=32 297walker=system.cpu.istage2_mmu.stage2_tlb.walker 298 299[system.cpu.istage2_mmu.stage2_tlb.walker] 300type=ArmTableWalker 301clk_domain=system.cpu_clk_domain 302eventq_index=0 303is_stage2=true 304num_squash_per_cycle=2 305sys=system |
| 304port=system.cpu.toL2Bus.slave[4] | |
| 305 306[system.cpu.itb] 307type=ArmTLB 308children=walker 309eventq_index=0 310is_stage2=false 311size=64 312walker=system.cpu.itb.walker --- 42 unchanged lines hidden (view full) --- 355hit_latency=20 356sequential_access=false 357size=4194304 358 359[system.cpu.toL2Bus] 360type=CoherentXBar 361clk_domain=system.cpu_clk_domain 362eventq_index=0 | 306 307[system.cpu.itb] 308type=ArmTLB 309children=walker 310eventq_index=0 311is_stage2=false 312size=64 313walker=system.cpu.itb.walker --- 42 unchanged lines hidden (view full) --- 356hit_latency=20 357sequential_access=false 358size=4194304 359 360[system.cpu.toL2Bus] 361type=CoherentXBar 362clk_domain=system.cpu_clk_domain 363eventq_index=0 |
| 363header_cycles=1 | 364forward_latency=0 365frontend_latency=1 366response_latency=1 |
| 364snoop_filter=Null | 367snoop_filter=Null |
| 368snoop_response_latency=1 |
|
| 365system=system 366use_default_range=false 367width=32 368master=system.cpu.l2cache.cpu_side | 369system=system 370use_default_range=false 371width=32 372master=system.cpu.l2cache.cpu_side |
| 369slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port | 373slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 370 371[system.cpu.tracer] 372type=ExeTracer 373eventq_index=0 374 375[system.cpu_clk_domain] 376type=SrcClockDomain 377clock=500 --- 14 unchanged lines hidden (view full) --- 392type=IntrControl 393eventq_index=0 394sys=system 395 396[system.iobus] 397type=NoncoherentXBar 398clk_domain=system.clk_domain 399eventq_index=0 | 374 375[system.cpu.tracer] 376type=ExeTracer 377eventq_index=0 378 379[system.cpu_clk_domain] 380type=SrcClockDomain 381clock=500 --- 14 unchanged lines hidden (view full) --- 396type=IntrControl 397eventq_index=0 398sys=system 399 400[system.iobus] 401type=NoncoherentXBar 402clk_domain=system.clk_domain 403eventq_index=0 |
| 400header_cycles=1 | 404forward_latency=1 405frontend_latency=2 406response_latency=2 |
| 401use_default_range=true | 407use_default_range=true |
| 402width=8 | 408width=16 |
| 403default=system.realview.pciconfig.pio 404master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 405slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 406 407[system.iocache] 408type=BaseCache 409children=tags 410addr_ranges=2147483648:2415919103 --- 29 unchanged lines hidden (view full) --- 440sequential_access=false 441size=1024 442 443[system.membus] 444type=CoherentXBar 445children=badaddr_responder 446clk_domain=system.clk_domain 447eventq_index=0 | 409default=system.realview.pciconfig.pio 410master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 411slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 412 413[system.iocache] 414type=BaseCache 415children=tags 416addr_ranges=2147483648:2415919103 --- 29 unchanged lines hidden (view full) --- 446sequential_access=false 447size=1024 448 449[system.membus] 450type=CoherentXBar 451children=badaddr_responder 452clk_domain=system.clk_domain 453eventq_index=0 |
| 448header_cycles=1 | 454forward_latency=4 455frontend_latency=3 456response_latency=2 |
| 449snoop_filter=Null | 457snoop_filter=Null |
| 458snoop_response_latency=4 |
|
| 450system=system 451use_default_range=false | 459system=system 460use_default_range=false |
| 452width=8 | 461width=16 |
| 453default=system.membus.badaddr_responder.pio 454master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port 455slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 456 457[system.membus.badaddr_responder] 458type=IsaFake 459clk_domain=system.clk_domain 460eventq_index=0 --- 33 unchanged lines hidden (view full) --- 494IDD4W2=0.000000 495IDD5=0.220000 496IDD52=0.000000 497IDD6=0.000000 498IDD62=0.000000 499VDD=1.500000 500VDD2=0.000000 501activation_limit=4 | 462default=system.membus.badaddr_responder.pio 463master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port 464slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 465 466[system.membus.badaddr_responder] 467type=IsaFake 468clk_domain=system.clk_domain 469eventq_index=0 --- 33 unchanged lines hidden (view full) --- 503IDD4W2=0.000000 504IDD5=0.220000 505IDD52=0.000000 506IDD6=0.000000 507IDD62=0.000000 508VDD=1.500000 509VDD2=0.000000 510activation_limit=4 |
| 502addr_mapping=RoRaBaChCo | 511addr_mapping=RoRaBaCoCh |
| 503bank_groups_per_rank=0 504banks_per_rank=8 505burst_length=8 506channels=1 507clk_domain=system.clk_domain 508conf_table_reported=true 509device_bus_width=8 510device_rowbuffer_size=1024 --- 710 unchanged lines hidden --- | 512bank_groups_per_rank=0 513banks_per_rank=8 514burst_length=8 515channels=1 516clk_domain=system.clk_domain 517conf_table_reported=true 518device_bus_width=8 519device_rowbuffer_size=1024 --- 710 unchanged lines hidden --- |