40a41
> mmap_using_noreserve=false
175a177
> sys=system
193d194
< port=system.cpu.toL2Bus.slave[5]
286a288
> sys=system
304d305
< port=system.cpu.toL2Bus.slave[4]
363c364,366
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
364a368
> snoop_response_latency=1
369c373
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
400c404,406
< header_cycles=1
---
> forward_latency=1
> frontend_latency=2
> response_latency=2
402c408
< width=8
---
> width=16
448c454,456
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
449a458
> snoop_response_latency=4
452c461
< width=8
---
> width=16
502c511
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh