| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.195756 # Number of seconds simulated 4sim_ticks 1195756323500 # Number of ticks simulated 5final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.195792 # Number of seconds simulated 4sim_ticks 1195791950500 # Number of ticks simulated 5final_tick 1195791950500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 469394 # Simulator instruction rate (inst/s) 8host_op_rate 598174 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9145402965 # Simulator tick rate (ticks/s) 10host_mem_usage 398732 # Number of bytes of host memory used 11host_seconds 130.75 # Real time elapsed on the host 12sim_insts 61373013 # Number of instructions simulated 13sim_ops 78210923 # Number of ops (including micro ops) simulated | 7host_inst_rate 418462 # Simulator instruction rate (inst/s) 8host_op_rate 533251 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8153682245 # Simulator tick rate (ticks/s) 10host_mem_usage 447424 # Number of bytes of host memory used 11host_seconds 146.66 # Real time elapsed on the host 12sim_insts 61370228 # Number of instructions simulated 13sim_ops 78204808 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 6626164 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory | 21system.physmem.bytes_read::cpu1.data 2903920 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62155172 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory |
| 24system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory | 24system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory |
| 25system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory | 25system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4136128 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 27system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory | 29system.physmem.bytes_written::total 7163472 # Number of bytes written to this memory |
| 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 103606 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory | 37system.physmem.num_reads::cpu1.data 45400 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654629 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64627 # Number of write requests responded to by this memory |
| 40system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 40system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 42system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s) | 42system.physmem.num_writes::total 821463 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43405972 # Total read bandwidth from this memory (bytes/s) |
| 44system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.inst 387790 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 5541235 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu1.inst 214429 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2428449 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51978249 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 387790 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 214429 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 602218 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3458903 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 2531631 # Write bandwidth from this memory (bytes/s) |
| 57system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) | 57system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s) | 58system.physmem.bw_write::total 5990567 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3458903 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43405972 # Total bandwidth to/from this memory (bytes/s) |
| 61system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) |
| 63system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::cpu0.inst 387790 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 8072866 # Total bandwidth to/from this memory (bytes/s) |
| 65system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) | 65system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654771 # Number of read requests accepted 70system.physmem.writeReqs 821574 # Number of write requests accepted 71system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue 72system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue 73system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM 74system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue 75system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM 76system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side 77system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side 78system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue 79system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one 80system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write 81system.physmem.perBankRdBursts::0 415729 # Per bank write bursts | 66system.physmem.bw_total::cpu1.inst 214429 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 2428483 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 57968816 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654629 # Number of read requests accepted 70system.physmem.writeReqs 821463 # Number of write requests accepted 71system.physmem.readBursts 6654629 # Number of DRAM read bursts, including those serviced by the write queue 72system.physmem.writeBursts 821463 # Number of DRAM write bursts, including those merged in the write queue 73system.physmem.bytesReadDRAM 425873472 # Total number of bytes read from DRAM 74system.physmem.bytesReadWrQ 22784 # Total number of bytes read from write queue 75system.physmem.bytesWritten 7293184 # Total number of bytes written to DRAM 76system.physmem.bytesReadSys 62155172 # Total read bytes from the system interface side 77system.physmem.bytesWrittenSys 7163472 # Total written bytes from the system interface side 78system.physmem.servicedByWrQ 356 # Number of DRAM read bursts serviced by the write queue 79system.physmem.mergedWrBursts 707504 # Number of DRAM write bursts merged with an existing one 80system.physmem.neitherReadNorWriteReqs 10661 # Number of requests that are neither read nor write 81system.physmem.perBankRdBursts::0 415730 # Per bank write bursts |
| 82system.physmem.perBankRdBursts::1 415559 # Per bank write bursts | 82system.physmem.perBankRdBursts::1 415559 # Per bank write bursts |
| 83system.physmem.perBankRdBursts::2 414962 # Per bank write bursts 84system.physmem.perBankRdBursts::3 415336 # Per bank write bursts 85system.physmem.perBankRdBursts::4 422370 # Per bank write bursts | 83system.physmem.perBankRdBursts::2 414961 # Per bank write bursts 84system.physmem.perBankRdBursts::3 415335 # Per bank write bursts 85system.physmem.perBankRdBursts::4 422368 # Per bank write bursts |
| 86system.physmem.perBankRdBursts::5 415375 # Per bank write bursts | 86system.physmem.perBankRdBursts::5 415375 # Per bank write bursts |
| 87system.physmem.perBankRdBursts::6 415451 # Per bank write bursts | 87system.physmem.perBankRdBursts::6 415446 # Per bank write bursts |
| 88system.physmem.perBankRdBursts::7 415289 # Per bank write bursts 89system.physmem.perBankRdBursts::8 415350 # Per bank write bursts 90system.physmem.perBankRdBursts::9 415631 # Per bank write bursts 91system.physmem.perBankRdBursts::10 415265 # Per bank write bursts 92system.physmem.perBankRdBursts::11 414898 # Per bank write bursts | 88system.physmem.perBankRdBursts::7 415289 # Per bank write bursts 89system.physmem.perBankRdBursts::8 415350 # Per bank write bursts 90system.physmem.perBankRdBursts::9 415631 # Per bank write bursts 91system.physmem.perBankRdBursts::10 415265 # Per bank write bursts 92system.physmem.perBankRdBursts::11 414898 # Per bank write bursts |
| 93system.physmem.perBankRdBursts::12 415464 # Per bank write bursts | 93system.physmem.perBankRdBursts::12 415491 # Per bank write bursts |
| 94system.physmem.perBankRdBursts::13 416088 # Per bank write bursts | 94system.physmem.perBankRdBursts::13 416088 # Per bank write bursts |
| 95system.physmem.perBankRdBursts::14 415829 # Per bank write bursts 96system.physmem.perBankRdBursts::15 415792 # Per bank write bursts 97system.physmem.perBankWrBursts::0 7314 # Per bank write bursts 98system.physmem.perBankWrBursts::1 7200 # Per bank write bursts 99system.physmem.perBankWrBursts::2 6696 # Per bank write bursts 100system.physmem.perBankWrBursts::3 6864 # Per bank write bursts 101system.physmem.perBankWrBursts::4 7395 # Per bank write bursts 102system.physmem.perBankWrBursts::5 6961 # Per bank write bursts 103system.physmem.perBankWrBursts::6 7170 # Per bank write bursts 104system.physmem.perBankWrBursts::7 6990 # Per bank write bursts 105system.physmem.perBankWrBursts::8 6985 # Per bank write bursts 106system.physmem.perBankWrBursts::9 7249 # Per bank write bursts | 95system.physmem.perBankRdBursts::14 415759 # Per bank write bursts 96system.physmem.perBankRdBursts::15 415728 # Per bank write bursts 97system.physmem.perBankWrBursts::0 7313 # Per bank write bursts 98system.physmem.perBankWrBursts::1 7201 # Per bank write bursts 99system.physmem.perBankWrBursts::2 6692 # Per bank write bursts 100system.physmem.perBankWrBursts::3 6866 # Per bank write bursts 101system.physmem.perBankWrBursts::4 7393 # Per bank write bursts 102system.physmem.perBankWrBursts::5 6958 # Per bank write bursts 103system.physmem.perBankWrBursts::6 7169 # Per bank write bursts 104system.physmem.perBankWrBursts::7 6986 # Per bank write bursts 105system.physmem.perBankWrBursts::8 6988 # Per bank write bursts 106system.physmem.perBankWrBursts::9 7250 # Per bank write bursts |
| 107system.physmem.perBankWrBursts::10 6972 # Per bank write bursts 108system.physmem.perBankWrBursts::11 6687 # Per bank write bursts | 107system.physmem.perBankWrBursts::10 6972 # Per bank write bursts 108system.physmem.perBankWrBursts::11 6687 # Per bank write bursts |
| 109system.physmem.perBankWrBursts::12 7224 # Per bank write bursts 110system.physmem.perBankWrBursts::13 7527 # Per bank write bursts 111system.physmem.perBankWrBursts::14 7429 # Per bank write bursts 112system.physmem.perBankWrBursts::15 7403 # Per bank write bursts | 109system.physmem.perBankWrBursts::12 7223 # Per bank write bursts 110system.physmem.perBankWrBursts::13 7529 # Per bank write bursts 111system.physmem.perBankWrBursts::14 7375 # Per bank write bursts 112system.physmem.perBankWrBursts::15 7354 # Per bank write bursts |
| 113system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 114system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 113system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 114system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 115system.physmem.totGap 1195751937000 # Total gap between requests | 115system.physmem.totGap 1195787534500 # Total gap between requests |
| 116system.physmem.readPktSize::0 0 # Read request sizes (log2) 117system.physmem.readPktSize::1 0 # Read request sizes (log2) 118system.physmem.readPktSize::2 6825 # Read request sizes (log2) 119system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 120system.physmem.readPktSize::4 0 # Read request sizes (log2) 121system.physmem.readPktSize::5 0 # Read request sizes (log2) | 116system.physmem.readPktSize::0 0 # Read request sizes (log2) 117system.physmem.readPktSize::1 0 # Read request sizes (log2) 118system.physmem.readPktSize::2 6825 # Read request sizes (log2) 119system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 120system.physmem.readPktSize::4 0 # Read request sizes (log2) 121system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 122system.physmem.readPktSize::6 159882 # Read request sizes (log2) | 122system.physmem.readPktSize::6 159740 # Read request sizes (log2) |
| 123system.physmem.writePktSize::0 0 # Write request sizes (log2) 124system.physmem.writePktSize::1 0 # Write request sizes (log2) 125system.physmem.writePktSize::2 756836 # Write request sizes (log2) 126system.physmem.writePktSize::3 0 # Write request sizes (log2) 127system.physmem.writePktSize::4 0 # Write request sizes (log2) 128system.physmem.writePktSize::5 0 # Write request sizes (log2) | 123system.physmem.writePktSize::0 0 # Write request sizes (log2) 124system.physmem.writePktSize::1 0 # Write request sizes (log2) 125system.physmem.writePktSize::2 756836 # Write request sizes (log2) 126system.physmem.writePktSize::3 0 # Write request sizes (log2) 127system.physmem.writePktSize::4 0 # Write request sizes (log2) 128system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 129system.physmem.writePktSize::6 64738 # Write request sizes (log2) 130system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see | 129system.physmem.writePktSize::6 64627 # Write request sizes (log2) 130system.physmem.rdQLenPdf::0 636769 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::1 483388 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::2 484627 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::3 1579502 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::4 1123930 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::5 1118197 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::6 1114450 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::7 25137 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::8 24391 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::9 9450 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::10 9387 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::11 9266 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::12 8971 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::13 8900 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::14 8855 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::15 8823 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::16 219 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see |
| 148system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 148system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::0 5178 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::1 5187 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::2 5182 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::3 5179 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::4 5180 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::5 5179 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::6 5179 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::7 5180 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::8 5177 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::9 5179 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::10 5177 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::11 5178 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::12 5178 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::13 5178 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::14 5179 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::15 5179 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::16 5178 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::19 5180 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::20 5184 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::21 5183 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 187system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 194system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11008-11015 75 0.10% 84.01% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11264-11271 96 0.13% 84.13% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11520-11527 79 0.11% 84.24% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11776-11783 29 0.04% 84.28% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.28% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::11968-11975 1 0.00% 84.28% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::12032-12039 17 0.02% 84.30% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.30% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::12288-12295 176 0.23% 84.54% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.54% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.54% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::12544-12551 83 0.11% 84.65% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.65% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::12800-12807 12 0.02% 84.67% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.67% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::13056-13063 24 0.03% 84.70% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.70% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::13312-13319 154 0.21% 84.91% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::13440-13447 2 0.00% 84.91% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::13568-13575 30 0.04% 84.95% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::13632-13639 1 0.00% 84.95% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::13824-13831 90 0.12% 85.07% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::13952-13959 1 0.00% 85.08% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::14080-14087 16 0.02% 85.10% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::14336-14343 91 0.12% 85.22% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.22% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::14592-14599 14 0.02% 85.24% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.24% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::14720-14727 2 0.00% 85.24% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::14848-14855 154 0.21% 85.45% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::15104-15111 12 0.02% 85.46% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::15360-15367 76 0.10% 85.56% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::15616-15623 82 0.11% 85.67% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::15872-15879 16 0.02% 85.69% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.70% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::16128-16135 19 0.03% 85.72% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::16256-16263 4 0.01% 85.73% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::16384-16391 270 0.36% 86.09% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.09% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.09% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.12% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::16768-16775 2 0.00% 86.12% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::16896-16903 17 0.02% 86.14% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::17152-17159 84 0.11% 86.25% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.25% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::17408-17415 77 0.10% 86.36% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::17664-17671 12 0.02% 86.37% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::17792-17799 2 0.00% 86.38% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::17920-17927 156 0.21% 86.58% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::18176-18183 14 0.02% 86.60% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.60% # Bytes accessed per row activation | 194system.physmem.bytesPerActivate::samples 74963 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 5778.397556 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 392.859970 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 13041.482454 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::64-71 26098 34.81% 34.81% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-135 15301 20.41% 55.23% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::192-199 3417 4.56% 59.78% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::256-263 2337 3.12% 62.90% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::320-327 1552 2.07% 64.97% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-391 1311 1.75% 66.72% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::448-455 1048 1.40% 68.12% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-519 1133 1.51% 69.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::576-583 708 0.94% 70.57% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::640-647 576 0.77% 71.34% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::704-711 588 0.78% 72.13% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-775 600 0.80% 72.93% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::832-839 313 0.42% 73.35% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-903 304 0.41% 73.75% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::960-967 211 0.28% 74.03% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1031 484 0.65% 74.68% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1088-1095 181 0.24% 74.92% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1152-1159 133 0.18% 75.10% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1216-1223 163 0.22% 75.31% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1280-1287 181 0.24% 75.56% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1344-1351 117 0.16% 75.71% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1408-1415 2275 3.03% 78.75% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1472-1479 133 0.18% 78.92% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1536-1543 94 0.13% 79.05% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1600-1607 64 0.09% 79.14% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1664-1671 60 0.08% 79.22% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1728-1735 43 0.06% 79.27% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1792-1799 123 0.16% 79.44% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.51% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1920-1927 29 0.04% 79.55% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.57% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2048-2055 191 0.25% 79.83% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2112-2119 19 0.03% 79.85% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2176-2183 18 0.02% 79.88% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2240-2247 24 0.03% 79.91% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2304-2311 41 0.05% 79.96% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.98% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2432-2439 25 0.03% 80.02% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2496-2503 28 0.04% 80.05% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2560-2567 24 0.03% 80.09% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2624-2631 25 0.03% 80.12% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2688-2695 17 0.02% 80.14% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2752-2759 20 0.03% 80.17% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2816-2823 20 0.03% 80.20% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.20% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2944-2951 20 0.03% 80.23% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3008-3015 6 0.01% 80.24% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3072-3079 190 0.25% 80.49% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3136-3143 23 0.03% 80.52% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3200-3207 8 0.01% 80.53% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3264-3271 10 0.01% 80.55% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3328-3335 98 0.13% 80.68% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.69% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3456-3463 7 0.01% 80.70% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3520-3527 16 0.02% 80.72% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3584-3591 20 0.03% 80.75% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3648-3655 6 0.01% 80.75% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.78% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3776-3783 37 0.05% 80.83% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3840-3847 47 0.06% 80.89% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3904-3911 17 0.02% 80.91% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3968-3975 8 0.01% 80.93% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4032-4039 6 0.01% 80.93% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4096-4103 197 0.26% 81.20% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4160-4167 7 0.01% 81.21% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4224-4231 10 0.01% 81.22% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4288-4295 14 0.02% 81.24% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4352-4359 80 0.11% 81.34% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4416-4423 4 0.01% 81.35% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4480-4487 14 0.02% 81.37% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.37% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4608-4615 33 0.04% 81.42% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4672-4679 14 0.02% 81.43% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.44% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.44% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4864-4871 23 0.03% 81.47% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4928-4935 5 0.01% 81.48% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::4992-4999 7 0.01% 81.49% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.51% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5120-5127 154 0.21% 81.72% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.72% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5248-5255 14 0.02% 81.74% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5312-5319 6 0.01% 81.75% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5376-5383 35 0.05% 81.79% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5440-5447 170 0.23% 82.02% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5504-5511 59 0.08% 82.10% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5632-5639 78 0.10% 82.20% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.20% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::5888-5895 9 0.01% 82.22% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6144-6151 89 0.12% 82.34% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6272-6279 2 0.00% 82.34% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6400-6407 70 0.09% 82.43% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6464-6471 1 0.00% 82.43% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.44% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.44% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6656-6663 108 0.14% 82.58% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6848-6855 1 0.00% 82.58% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.60% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.61% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7168-7175 32 0.04% 82.65% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7424-7431 132 0.18% 82.82% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7680-7687 28 0.04% 82.86% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7936-7943 74 0.10% 82.96% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.96% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.96% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8192-8199 29 0.04% 83.00% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.00% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8448-8455 75 0.10% 83.10% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8704-8711 29 0.04% 83.14% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8832-8839 2 0.00% 83.15% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8960-8967 130 0.17% 83.32% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.32% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::9216-9223 29 0.04% 83.36% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.36% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9472-9479 17 0.02% 83.38% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9728-9735 100 0.13% 83.52% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.52% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9984-9991 74 0.10% 83.62% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::10240-10247 86 0.11% 83.73% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::10496-10503 12 0.02% 83.75% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::10752-10759 80 0.11% 83.85% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::11008-11015 29 0.04% 83.89% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.89% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.90% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::11264-11271 147 0.20% 84.09% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.09% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::11520-11527 8 0.01% 84.10% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::11776-11783 25 0.03% 84.14% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::12032-12039 77 0.10% 84.24% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::12288-12295 181 0.24% 84.48% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.48% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::12544-12551 36 0.05% 84.53% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::12800-12807 17 0.02% 84.56% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.56% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::13056-13063 77 0.10% 84.66% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.66% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::13312-13319 164 0.22% 84.88% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::13568-13575 12 0.02% 84.90% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::13824-13831 12 0.02% 84.91% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::13952-13959 1 0.00% 84.91% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::14080-14087 27 0.04% 84.95% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::14144-14151 1 0.00% 84.95% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::14208-14215 3 0.00% 84.95% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::14336-14343 162 0.22% 85.17% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::14592-14599 88 0.12% 85.29% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.29% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::14848-14855 21 0.03% 85.32% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::15040-15047 2 0.00% 85.32% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::15104-15111 28 0.04% 85.36% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.36% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::15360-15367 218 0.29% 85.65% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::15616-15623 20 0.03% 85.68% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::15872-15879 17 0.02% 85.70% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.70% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::16128-16135 8 0.01% 85.71% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::16256-16263 2 0.00% 85.71% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::16384-16391 272 0.36% 86.08% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::16640-16647 7 0.01% 86.09% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.09% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::16896-16903 16 0.02% 86.11% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::17152-17159 23 0.03% 86.14% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.14% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::17408-17415 224 0.30% 86.44% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::17600-17607 2 0.00% 86.44% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::17664-17671 24 0.03% 86.47% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::17920-17927 18 0.02% 86.50% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.50% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::18176-18183 85 0.11% 86.61% # Bytes accessed per row activation |
| 378system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation | 367system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation |
| 379system.physmem.bytesPerActivate::18432-18439 92 0.12% 86.73% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::18496-18503 1 0.00% 86.73% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.73% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::18688-18695 12 0.02% 86.75% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::18944-18951 95 0.13% 86.87% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.87% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::19200-19207 30 0.04% 86.91% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::19264-19271 1 0.00% 86.92% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::19456-19463 153 0.20% 87.12% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::19712-19719 23 0.03% 87.15% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::19968-19975 10 0.01% 87.16% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.16% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::20224-20231 83 0.11% 87.28% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.28% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.28% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::20480-20487 180 0.24% 87.52% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::20544-20551 2 0.00% 87.52% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.52% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::20736-20743 18 0.02% 87.55% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.55% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.58% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::21184-21191 1 0.00% 87.58% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::21248-21255 75 0.10% 87.68% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.68% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::21504-21511 92 0.12% 87.81% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.90% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::21952-21959 1 0.00% 87.90% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::22016-22023 14 0.02% 87.92% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::22272-22279 35 0.05% 87.97% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.97% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::22528-22535 142 0.19% 88.16% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::22656-22663 1 0.00% 88.16% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::22784-22791 87 0.12% 88.28% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.28% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::22976-22983 1 0.00% 88.28% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.30% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::23296-23303 4 0.01% 88.30% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::23552-23559 166 0.22% 88.52% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.52% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::23808-23815 23 0.03% 88.55% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::24064-24071 66 0.09% 88.64% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.64% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::24320-24327 30 0.04% 88.68% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.69% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::24576-24583 147 0.20% 88.88% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::24832-24839 27 0.04% 88.92% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::25088-25095 68 0.09% 89.01% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::25344-25351 24 0.03% 89.04% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::25472-25479 1 0.00% 89.04% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::25600-25607 171 0.23% 89.27% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::25856-25863 5 0.01% 89.28% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::26112-26119 19 0.03% 89.30% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::26304-26311 1 0.00% 89.30% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::26368-26375 83 0.11% 89.41% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.41% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::26624-26631 139 0.19% 89.60% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::26880-26887 34 0.05% 89.64% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.66% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.66% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::27392-27399 75 0.10% 89.76% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.76% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.76% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::27584-27591 2 0.00% 89.77% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::27648-27655 88 0.12% 89.88% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::27776-27783 2 0.00% 89.89% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::27904-27911 75 0.10% 89.99% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::28096-28103 1 0.00% 89.99% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::28160-28167 24 0.03% 90.02% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::28352-28359 1 0.00% 90.02% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::28416-28423 21 0.03% 90.05% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::28672-28679 180 0.24% 90.29% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::28800-28807 2 0.00% 90.29% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::28928-28935 82 0.11% 90.40% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::29184-29191 10 0.01% 90.41% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::29440-29447 24 0.03% 90.45% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.45% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::29696-29703 153 0.20% 90.65% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.65% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::29952-29959 28 0.04% 90.69% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::30208-30215 92 0.12% 90.81% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::30336-30343 1 0.00% 90.81% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::30464-30471 14 0.02% 90.83% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::30720-30727 87 0.12% 90.95% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::30976-30983 12 0.02% 90.97% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::31104-31111 2 0.00% 90.97% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::31232-31239 151 0.20% 91.17% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::31488-31495 11 0.01% 91.19% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.19% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.19% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::31744-31751 72 0.10% 91.28% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.28% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::32000-32007 84 0.11% 91.40% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.40% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::32256-32263 15 0.02% 91.42% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.42% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.45% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::32768-32775 273 0.36% 91.82% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::33024-33031 27 0.04% 91.85% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::33152-33159 2 0.00% 91.85% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::33280-33287 28 0.04% 91.89% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::33536-33543 83 0.11% 92.00% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::33792-33799 70 0.09% 92.10% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.11% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::34304-34311 153 0.20% 92.32% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.32% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::34560-34567 13 0.02% 92.34% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::34816-34823 85 0.11% 92.45% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::35072-35079 13 0.02% 92.47% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::35328-35335 90 0.12% 92.59% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::35584-35591 32 0.04% 92.63% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::35840-35847 150 0.20% 92.83% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.83% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.86% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::36352-36359 9 0.01% 92.87% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.99% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::36736-36743 1 0.00% 92.99% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::36864-36871 172 0.23% 93.22% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::37120-37127 19 0.03% 93.24% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::37184-37191 1 0.00% 93.24% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::37248-37255 2 0.00% 93.25% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::37376-37383 23 0.03% 93.28% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.28% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.28% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::37632-37639 70 0.09% 93.37% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::37888-37895 89 0.12% 93.49% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::37952-37959 2 0.00% 93.49% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.49% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.50% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::38144-38151 74 0.10% 93.59% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.60% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.61% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::38656-38663 31 0.04% 93.65% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::38912-38919 140 0.19% 93.84% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::39168-39175 81 0.11% 93.95% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::39232-39239 1 0.00% 93.95% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::39424-39431 14 0.02% 93.97% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::39680-39687 5 0.01% 93.97% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::39936-39943 169 0.23% 94.20% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::40064-40071 1 0.00% 94.20% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::40192-40199 23 0.03% 94.23% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.32% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::40704-40711 29 0.04% 94.36% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::40960-40967 152 0.20% 94.56% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::41216-41223 26 0.03% 94.60% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::41472-41479 66 0.09% 94.68% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::41728-41735 22 0.03% 94.71% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::41920-41927 1 0.00% 94.72% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::41984-41991 165 0.22% 94.93% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::42240-42247 4 0.01% 94.94% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.94% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::42496-42503 13 0.02% 94.96% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::42560-42567 1 0.00% 94.96% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::42752-42759 87 0.12% 95.08% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::43008-43015 139 0.19% 95.26% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::43264-43271 32 0.04% 95.30% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.32% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::43584-43591 1 0.00% 95.32% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::43776-43783 72 0.10% 95.42% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.54% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.54% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::44288-44295 72 0.10% 95.64% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.64% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::44544-44551 22 0.03% 95.67% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::44736-44743 1 0.00% 95.67% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.69% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.69% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::44992-44999 1 0.00% 95.69% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::45056-45063 169 0.23% 95.92% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.92% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::45312-45319 83 0.11% 96.03% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.03% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::45568-45575 7 0.01% 96.04% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::45824-45831 22 0.03% 96.07% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::46080-46087 150 0.20% 96.27% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.27% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::46272-46279 1 0.00% 96.27% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.31% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::46592-46599 96 0.13% 96.44% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::46848-46855 12 0.02% 96.45% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::46976-46983 2 0.00% 96.46% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.46% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::47104-47111 92 0.12% 96.58% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.58% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::47232-47239 3 0.00% 96.59% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::47360-47367 18 0.02% 96.61% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::47488-47495 2 0.00% 96.61% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::47616-47623 154 0.21% 96.82% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.82% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::47808-47815 1 0.00% 96.82% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::47872-47879 17 0.02% 96.84% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.85% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.85% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::48128-48135 94 0.13% 96.97% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.98% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.98% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.98% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::48384-48391 97 0.13% 97.11% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::48640-48647 12 0.02% 97.13% # Bytes accessed per row activation | 368system.physmem.bytesPerActivate::18432-18439 154 0.21% 86.82% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::18688-18695 30 0.04% 86.86% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::18944-18951 16 0.02% 86.88% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::19200-19207 19 0.03% 86.91% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::19328-19335 1 0.00% 86.91% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::19456-19463 169 0.23% 87.13% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::19712-19719 71 0.09% 87.23% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::19968-19975 12 0.02% 87.24% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::20224-20231 44 0.06% 87.30% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.30% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.30% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::20480-20487 167 0.22% 87.53% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::20608-20615 3 0.00% 87.53% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::20736-20743 78 0.10% 87.64% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.64% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::20864-20871 1 0.00% 87.64% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.67% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::21184-21191 2 0.00% 87.67% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::21248-21255 12 0.02% 87.69% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::21376-21383 1 0.00% 87.69% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::21504-21511 139 0.19% 87.88% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.91% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::22016-22023 79 0.11% 88.01% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::22208-22215 1 0.00% 88.01% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::22272-22279 9 0.01% 88.03% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::22528-22535 89 0.12% 88.14% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::22592-22599 2 0.00% 88.15% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::22784-22791 71 0.09% 88.24% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::23040-23047 103 0.14% 88.38% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::23296-23303 16 0.02% 88.40% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.40% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::23552-23559 26 0.03% 88.44% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.44% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::23808-23815 131 0.17% 88.61% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::24064-24071 26 0.03% 88.65% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::24320-24327 72 0.10% 88.74% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::24384-24391 1 0.00% 88.75% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::24576-24583 23 0.03% 88.78% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::24832-24839 77 0.10% 88.88% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::25088-25095 26 0.03% 88.91% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::25216-25223 1 0.00% 88.91% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::25344-25351 132 0.18% 89.09% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::25600-25607 29 0.04% 89.13% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::25856-25863 15 0.02% 89.15% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::26112-26119 98 0.13% 89.28% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::26240-26247 1 0.00% 89.28% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.28% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::26368-26375 75 0.10% 89.38% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.39% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::26560-26567 1 0.00% 89.39% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::26624-26631 84 0.11% 89.50% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::26880-26887 13 0.02% 89.52% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::27136-27143 81 0.11% 89.62% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::27392-27399 23 0.03% 89.65% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.66% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::27648-27655 143 0.19% 89.85% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::27840-27847 1 0.00% 89.85% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::27904-27911 9 0.01% 89.86% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::28032-28039 1 0.00% 89.86% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::28160-28167 25 0.03% 89.90% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::28288-28295 1 0.00% 89.90% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::28416-28423 80 0.11% 90.00% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::28544-28551 3 0.00% 90.01% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.01% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::28672-28679 176 0.23% 90.24% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.24% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::28928-28935 40 0.05% 90.30% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::29184-29191 16 0.02% 90.32% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::29440-29447 72 0.10% 90.42% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::29632-29639 1 0.00% 90.42% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::29696-29703 167 0.22% 90.64% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::29760-29767 1 0.00% 90.64% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.66% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::30208-30215 6 0.01% 90.67% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.67% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::30464-30471 29 0.04% 90.71% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::30720-30727 150 0.20% 90.91% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::30848-30855 1 0.00% 90.91% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::30976-30983 84 0.11% 91.02% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::31232-31239 19 0.03% 91.05% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::31488-31495 30 0.04% 91.09% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.09% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::31744-31751 220 0.29% 91.38% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.39% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::32000-32007 20 0.03% 91.41% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::32256-32263 17 0.02% 91.43% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::32512-32519 10 0.01% 91.45% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.45% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::32768-32775 269 0.36% 91.81% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.83% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::33216-33223 1 0.00% 91.83% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::33280-33287 25 0.03% 91.86% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.86% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::33536-33543 22 0.03% 91.89% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.89% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.90% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::33728-33735 1 0.00% 91.90% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::33792-33799 216 0.29% 92.19% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.19% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::34048-34055 26 0.03% 92.22% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.22% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::34304-34311 19 0.03% 92.25% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::34560-34567 84 0.11% 92.36% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::34688-34695 2 0.00% 92.36% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::34816-34823 148 0.20% 92.56% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.56% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::35072-35079 27 0.04% 92.60% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::35328-35335 6 0.01% 92.61% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.62% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::35776-35783 1 0.00% 92.62% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::35840-35847 165 0.22% 92.84% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::35904-35911 1 0.00% 92.85% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::36096-36103 71 0.09% 92.94% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::36352-36359 14 0.02% 92.96% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::36480-36487 1 0.00% 92.96% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::36608-36615 37 0.05% 93.01% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.01% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::36864-36871 169 0.23% 93.24% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::36928-36935 1 0.00% 93.24% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::36992-36999 2 0.00% 93.24% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.35% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::37248-37255 1 0.00% 93.35% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::37376-37383 25 0.03% 93.38% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.38% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::37632-37639 9 0.01% 93.39% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::37888-37895 142 0.19% 93.58% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.58% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::38144-38151 22 0.03% 93.61% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::38400-38407 79 0.11% 93.72% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::38656-38663 11 0.01% 93.73% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::38912-38919 85 0.11% 93.85% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::38976-38983 1 0.00% 93.85% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.85% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::39168-39175 73 0.10% 93.95% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::39232-39239 2 0.00% 93.95% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::39424-39431 96 0.13% 94.08% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::39680-39687 14 0.02% 94.10% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::39936-39943 27 0.04% 94.13% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::40192-40199 131 0.17% 94.31% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::40320-40327 1 0.00% 94.31% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::40448-40455 24 0.03% 94.34% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::40512-40519 1 0.00% 94.34% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::40704-40711 75 0.10% 94.44% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::40768-40775 1 0.00% 94.44% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::40960-40967 23 0.03% 94.47% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::41152-41159 1 0.00% 94.48% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::41216-41223 72 0.10% 94.57% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::41344-41351 1 0.00% 94.57% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::41472-41479 24 0.03% 94.61% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::41728-41735 130 0.17% 94.78% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::41984-41991 25 0.03% 94.81% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::42240-42247 15 0.02% 94.83% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::42496-42503 101 0.13% 94.97% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::42752-42759 70 0.09% 95.06% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.06% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::43008-43015 85 0.11% 95.17% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::43264-43271 8 0.01% 95.19% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::43520-43527 78 0.10% 95.29% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.29% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::43776-43783 24 0.03% 95.32% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::44032-44039 140 0.19% 95.51% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.53% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.53% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::44416-44423 1 0.00% 95.53% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::44544-44551 23 0.03% 95.56% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::44800-44807 80 0.11% 95.67% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::44928-44935 2 0.00% 95.67% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::45056-45063 165 0.22% 95.89% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.89% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::45248-45255 1 0.00% 95.89% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::45312-45319 38 0.05% 95.94% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::45568-45575 12 0.02% 95.96% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::45824-45831 71 0.09% 96.05% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.05% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::46080-46087 165 0.22% 96.27% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.28% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::46336-46343 15 0.02% 96.30% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::46592-46599 12 0.02% 96.31% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::46720-46727 1 0.00% 96.31% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::46848-46855 31 0.04% 96.35% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::47104-47111 151 0.20% 96.56% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.56% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::47360-47367 87 0.12% 96.67% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.67% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::47616-47623 21 0.03% 96.70% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.70% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::47872-47879 24 0.03% 96.74% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.74% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.74% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::48128-48135 239 0.32% 97.06% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.06% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::48256-48263 1 0.00% 97.06% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::48384-48391 36 0.05% 97.11% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::48640-48647 14 0.02% 97.13% # Bytes accessed per row activation |
| 578system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation | 564system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation |
| 579system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation 586system.physmem.totQLat 159590177750 # Total ticks spent queuing 587system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM 588system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers 589system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks 590system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst 591system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst | 565system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.15% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.16% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.16% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::49152-49159 2125 2.83% 100.00% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::total 74963 # Bytes accessed per row activation 571system.physmem.totQLat 159518930750 # Total ticks spent queuing 572system.physmem.totMemAccLat 202571234500 # Total ticks spent from burst creation until serviced by the DRAM 573system.physmem.totBusLat 33271365000 # Total ticks spent in databus transfers 574system.physmem.totBankLat 9780938750 # Total ticks spent accessing banks 575system.physmem.avgQLat 23972.41 # Average queueing delay per DRAM burst 576system.physmem.avgBankLat 1469.87 # Average bank access latency per DRAM burst |
| 592system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 577system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 593system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst 594system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s 595system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s 596system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s 597system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s | 578system.physmem.avgMemAccLat 30442.28 # Average memory access latency per DRAM burst 579system.physmem.avgRdBW 356.14 # Average DRAM read bandwidth in MiByte/s 580system.physmem.avgWrBW 6.10 # Average achieved write bandwidth in MiByte/s 581system.physmem.avgRdBWSys 51.98 # Average system read bandwidth in MiByte/s 582system.physmem.avgWrBWSys 5.99 # Average system write bandwidth in MiByte/s |
| 598system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 599system.physmem.busUtil 2.83 # Data bus utilization in percentage 600system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 601system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 602system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing | 583system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 584system.physmem.busUtil 2.83 # Data bus utilization in percentage 585system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 586system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 587system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing |
| 603system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing 604system.physmem.readRowHits 6598517 # Number of row buffer hits during reads 605system.physmem.writeRowHits 94894 # Number of row buffer hits during writes | 588system.physmem.avgWrQLen 12.12 # Average write queue length when enqueuing 589system.physmem.readRowHits 6598430 # Number of row buffer hits during reads 590system.physmem.writeRowHits 94836 # Number of row buffer hits during writes |
| 606system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads | 591system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads |
| 607system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes 608system.physmem.avgGap 159938.04 # Average gap between requests | 592system.physmem.writeRowHitRate 83.22 # Row buffer hit rate for writes 593system.physmem.avgGap 159948.21 # Average gap between requests |
| 609system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined | 594system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined |
| 610system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state | 595system.physmem.prechargeAllPercent 4.87 # Percentage of time for which DRAM has all the banks in precharge state |
| 611system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 612system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 613system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 614system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 615system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 616system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 617system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 618system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 619system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 620system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 621system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 622system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 623system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 624system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 625system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 626system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 627system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 628system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) | 596system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 597system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 598system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 599system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 600system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 601system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 602system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 603system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 604system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 605system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 606system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 607system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 608system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 609system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 610system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 611system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 612system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 613system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) |
| 629system.membus.throughput 59999152 # Throughput (bytes/s) 630system.membus.trans_dist::ReadReq 7703168 # Transaction distribution 631system.membus.trans_dist::ReadResp 7703168 # Transaction distribution | 614system.membus.throughput 59983824 # Throughput (bytes/s) 615system.membus.trans_dist::ReadReq 7703157 # Transaction distribution 616system.membus.trans_dist::ReadResp 7703157 # Transaction distribution |
| 632system.membus.trans_dist::WriteReq 767205 # Transaction distribution 633system.membus.trans_dist::WriteResp 767205 # Transaction distribution | 617system.membus.trans_dist::WriteReq 767205 # Transaction distribution 618system.membus.trans_dist::WriteResp 767205 # Transaction distribution |
| 634system.membus.trans_dist::Writeback 64738 # Transaction distribution 635system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution 636system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution 637system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution 638system.membus.trans_dist::ReadExReq 137900 # Transaction distribution 639system.membus.trans_dist::ReadExResp 137428 # Transaction distribution | 619system.membus.trans_dist::Writeback 64627 # Transaction distribution 620system.membus.trans_dist::UpgradeReq 27746 # Transaction distribution 621system.membus.trans_dist::SCUpgradeReq 16446 # Transaction distribution 622system.membus.trans_dist::UpgradeResp 10661 # Transaction distribution 623system.membus.trans_dist::ReadExReq 137744 # Transaction distribution 624system.membus.trans_dist::ReadExResp 137297 # Transaction distribution |
| 640system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) 641system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 642system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) 643system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 644system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) | 625system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) 626system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 627system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) 628system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 629system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) |
| 645system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes) 646system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes) | 630system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966729 # Packet count per connected master and slave (bytes) 631system.membus.pkt_count_system.l2c.mem_side::total 4359117 # Packet count per connected master and slave (bytes) |
| 647system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 648system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) | 632system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 633system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) |
| 649system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes) | 634system.membus.pkt_count::total 17335245 # Packet count per connected master and slave (bytes) |
| 650system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) 651system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 652system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) 653system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 654system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) | 635system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) 636system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 637system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) 638system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 639system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) |
| 655system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes) 656system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes) | 640system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) 641system.membus.tot_pkt_size_system.l2c.mem_side::total 19823662 # Cumulative packet size per connected master and slave (bytes) |
| 657system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 658system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) | 642system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 643system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) |
| 659system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes) 660system.membus.data_through_bus 71744366 # Total data (bytes) | 644system.membus.tot_pkt_size::total 71728174 # Cumulative packet size per connected master and slave (bytes) 645system.membus.data_through_bus 71728174 # Total data (bytes) |
| 661system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 646system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 662system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks) | 647system.membus.reqLayer0.occupancy 1224786000 # Layer occupancy (ticks) |
| 663system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 664system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 665system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 648system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 649system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 650system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 666system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks) | 651system.membus.reqLayer2.occupancy 7986500 # Layer occupancy (ticks) |
| 667system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 668system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 669system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 652system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 653system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 654system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 670system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) | 655system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks) |
| 671system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 656system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 672system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks) | 657system.membus.reqLayer6.occupancy 9213145499 # Layer occupancy (ticks) |
| 673system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) | 658system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) |
| 674system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks) | 659system.membus.respLayer1.occupancy 5079077969 # Layer occupancy (ticks) |
| 675system.membus.respLayer1.utilization 0.4 # Layer utilization (%) | 660system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 676system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks) | 661system.membus.respLayer2.occupancy 14657796999 # Layer occupancy (ticks) |
| 677system.membus.respLayer2.utilization 1.2 # Layer utilization (%) | 662system.membus.respLayer2.utilization 1.2 # Layer utilization (%) |
| 678system.l2c.tags.replacements 69764 # number of replacements 679system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use 680system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks. 681system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks. 682system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks. | 663system.l2c.tags.replacements 69622 # number of replacements 664system.l2c.tags.tagsinuse 53154.714662 # Cycle average of tags in use 665system.l2c.tags.total_refs 1651251 # Total number of references to valid blocks. 666system.l2c.tags.sampled_refs 134786 # Sample count of references to valid blocks. 667system.l2c.tags.avg_refs 12.250909 # Average number of references to valid blocks. |
| 683system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 668system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 684system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor 685system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor | 669system.l2c.tags.occ_blocks::writebacks 40043.388352 # Average occupied blocks per requestor 670system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667642 # Average occupied blocks per requestor |
| 686system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor | 671system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor |
| 687system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor 688system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor | 672system.l2c.tags.occ_blocks::cpu0.inst 4637.694613 # Average occupied blocks per requestor 673system.l2c.tags.occ_blocks::cpu0.data 5787.547519 # Average occupied blocks per requestor |
| 689system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor | 674system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor |
| 690system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor 691system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor 692system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy | 675system.l2c.tags.occ_blocks::cpu1.inst 1927.667021 # Average occupied blocks per requestor 676system.l2c.tags.occ_blocks::cpu1.data 755.746308 # Average occupied blocks per requestor 677system.l2c.tags.occ_percent::writebacks 0.611014 # Average percentage of cache occupancy |
| 693system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy 694system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 695system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy | 678system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy 679system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 680system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy |
| 696system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy | 681system.l2c.tags.occ_percent::cpu0.data 0.088311 # Average percentage of cache occupancy |
| 697system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 698system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy | 682system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 683system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy |
| 699system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache occupancy 700system.l2c.tags.occ_percent::total 0.811096 # Average percentage of cache occupancy 701system.l2c.ReadReq_hits::cpu0.dtb.walker 4686 # number of ReadReq hits 702system.l2c.ReadReq_hits::cpu0.itb.walker 1510 # number of ReadReq hits 703system.l2c.ReadReq_hits::cpu0.inst 483170 # number of ReadReq hits 704system.l2c.ReadReq_hits::cpu0.data 242041 # number of ReadReq hits 705system.l2c.ReadReq_hits::cpu1.dtb.walker 3562 # number of ReadReq hits 706system.l2c.ReadReq_hits::cpu1.itb.walker 1809 # number of ReadReq hits 707system.l2c.ReadReq_hits::cpu1.inst 372569 # number of ReadReq hits 708system.l2c.ReadReq_hits::cpu1.data 110996 # number of ReadReq hits 709system.l2c.ReadReq_hits::total 1220343 # number of ReadReq hits 710system.l2c.Writeback_hits::writebacks 576824 # number of Writeback hits 711system.l2c.Writeback_hits::total 576824 # number of Writeback hits 712system.l2c.UpgradeReq_hits::cpu0.data 1289 # number of UpgradeReq hits 713system.l2c.UpgradeReq_hits::cpu1.data 452 # number of UpgradeReq hits 714system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits 715system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits 716system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits 717system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits 718system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits 719system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits 720system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits 721system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits 722system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits 723system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits 724system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits 725system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits 726system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits 727system.l2c.demand_hits::cpu1.inst 372569 # number of demand (read+write) hits 728system.l2c.demand_hits::cpu1.data 156291 # number of demand (read+write) hits 729system.l2c.demand_hits::total 1331260 # number of demand (read+write) hits 730system.l2c.overall_hits::cpu0.dtb.walker 4686 # number of overall hits 731system.l2c.overall_hits::cpu0.itb.walker 1510 # number of overall hits 732system.l2c.overall_hits::cpu0.inst 483170 # number of overall hits 733system.l2c.overall_hits::cpu0.data 307663 # number of overall hits 734system.l2c.overall_hits::cpu1.dtb.walker 3562 # number of overall hits 735system.l2c.overall_hits::cpu1.itb.walker 1809 # number of overall hits 736system.l2c.overall_hits::cpu1.inst 372569 # number of overall hits 737system.l2c.overall_hits::cpu1.data 156291 # number of overall hits 738system.l2c.overall_hits::total 1331260 # number of overall hits | 684system.l2c.tags.occ_percent::cpu1.data 0.011532 # Average percentage of cache occupancy 685system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy 686system.l2c.ReadReq_hits::cpu0.dtb.walker 4526 # number of ReadReq hits 687system.l2c.ReadReq_hits::cpu0.itb.walker 1443 # number of ReadReq hits 688system.l2c.ReadReq_hits::cpu0.inst 483144 # number of ReadReq hits 689system.l2c.ReadReq_hits::cpu0.data 241974 # number of ReadReq hits 690system.l2c.ReadReq_hits::cpu1.dtb.walker 3792 # number of ReadReq hits 691system.l2c.ReadReq_hits::cpu1.itb.walker 1866 # number of ReadReq hits 692system.l2c.ReadReq_hits::cpu1.inst 372505 # number of ReadReq hits 693system.l2c.ReadReq_hits::cpu1.data 110561 # number of ReadReq hits 694system.l2c.ReadReq_hits::total 1219811 # number of ReadReq hits 695system.l2c.Writeback_hits::writebacks 576138 # number of Writeback hits 696system.l2c.Writeback_hits::total 576138 # number of Writeback hits 697system.l2c.UpgradeReq_hits::cpu0.data 1247 # number of UpgradeReq hits 698system.l2c.UpgradeReq_hits::cpu1.data 445 # number of UpgradeReq hits 699system.l2c.UpgradeReq_hits::total 1692 # number of UpgradeReq hits 700system.l2c.SCUpgradeReq_hits::cpu0.data 260 # number of SCUpgradeReq hits 701system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits 702system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits 703system.l2c.ReadExReq_hits::cpu0.data 65526 # number of ReadExReq hits 704system.l2c.ReadExReq_hits::cpu1.data 45407 # number of ReadExReq hits 705system.l2c.ReadExReq_hits::total 110933 # number of ReadExReq hits 706system.l2c.demand_hits::cpu0.dtb.walker 4526 # number of demand (read+write) hits 707system.l2c.demand_hits::cpu0.itb.walker 1443 # number of demand (read+write) hits 708system.l2c.demand_hits::cpu0.inst 483144 # number of demand (read+write) hits 709system.l2c.demand_hits::cpu0.data 307500 # number of demand (read+write) hits 710system.l2c.demand_hits::cpu1.dtb.walker 3792 # number of demand (read+write) hits 711system.l2c.demand_hits::cpu1.itb.walker 1866 # number of demand (read+write) hits 712system.l2c.demand_hits::cpu1.inst 372505 # number of demand (read+write) hits 713system.l2c.demand_hits::cpu1.data 155968 # number of demand (read+write) hits 714system.l2c.demand_hits::total 1330744 # number of demand (read+write) hits 715system.l2c.overall_hits::cpu0.dtb.walker 4526 # number of overall hits 716system.l2c.overall_hits::cpu0.itb.walker 1443 # number of overall hits 717system.l2c.overall_hits::cpu0.inst 483144 # number of overall hits 718system.l2c.overall_hits::cpu0.data 307500 # number of overall hits 719system.l2c.overall_hits::cpu1.dtb.walker 3792 # number of overall hits 720system.l2c.overall_hits::cpu1.itb.walker 1866 # number of overall hits 721system.l2c.overall_hits::cpu1.inst 372505 # number of overall hits 722system.l2c.overall_hits::cpu1.data 155968 # number of overall hits 723system.l2c.overall_hits::total 1330744 # number of overall hits |
| 739system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 740system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 724system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 725system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 741system.l2c.ReadReq_misses::cpu0.inst 6835 # number of ReadReq misses 742system.l2c.ReadReq_misses::cpu0.data 9720 # number of ReadReq misses | 726system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses 727system.l2c.ReadReq_misses::cpu0.data 9714 # number of ReadReq misses |
| 743system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 744system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses | 728system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 729system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses |
| 745system.l2c.ReadReq_misses::cpu1.data 1892 # number of ReadReq misses 746system.l2c.ReadReq_misses::total 22455 # number of ReadReq misses 747system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses 748system.l2c.UpgradeReq_misses::cpu1.data 3383 # number of UpgradeReq misses 749system.l2c.UpgradeReq_misses::total 7371 # number of UpgradeReq misses 750system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses | 730system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses 731system.l2c.ReadReq_misses::total 22444 # number of ReadReq misses 732system.l2c.UpgradeReq_misses::cpu0.data 3977 # number of UpgradeReq misses 733system.l2c.UpgradeReq_misses::cpu1.data 3384 # number of UpgradeReq misses 734system.l2c.UpgradeReq_misses::total 7361 # number of UpgradeReq misses 735system.l2c.SCUpgradeReq_misses::cpu0.data 388 # number of SCUpgradeReq misses |
| 751system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses | 736system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses |
| 752system.l2c.SCUpgradeReq_misses::total 866 # number of SCUpgradeReq misses 753system.l2c.ReadExReq_misses::cpu0.data 95249 # number of ReadExReq misses 754system.l2c.ReadExReq_misses::cpu1.data 44598 # number of ReadExReq misses 755system.l2c.ReadExReq_misses::total 139847 # number of ReadExReq misses | 737system.l2c.SCUpgradeReq_misses::total 867 # number of SCUpgradeReq misses 738system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses 739system.l2c.ReadExReq_misses::cpu1.data 44594 # number of ReadExReq misses 740system.l2c.ReadExReq_misses::total 139730 # number of ReadExReq misses |
| 756system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 757system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 741system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 742system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 758system.l2c.demand_misses::cpu0.inst 6835 # number of demand (read+write) misses 759system.l2c.demand_misses::cpu0.data 104969 # number of demand (read+write) misses | 743system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses 744system.l2c.demand_misses::cpu0.data 104850 # number of demand (read+write) misses |
| 760system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 761system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses | 745system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 746system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses |
| 762system.l2c.demand_misses::cpu1.data 46490 # number of demand (read+write) misses 763system.l2c.demand_misses::total 162302 # number of demand (read+write) misses | 747system.l2c.demand_misses::cpu1.data 46484 # number of demand (read+write) misses 748system.l2c.demand_misses::total 162174 # number of demand (read+write) misses |
| 764system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 765system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 749system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 750system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 766system.l2c.overall_misses::cpu0.inst 6835 # number of overall misses 767system.l2c.overall_misses::cpu0.data 104969 # number of overall misses | 751system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses 752system.l2c.overall_misses::cpu0.data 104850 # number of overall misses |
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miss rate for overall accesses 855system.l2c.overall_miss_rate::cpu0.inst 0.013944 # miss rate for overall accesses 856system.l2c.overall_miss_rate::cpu0.data 0.254274 # miss rate for overall accesses 857system.l2c.overall_miss_rate::cpu1.itb.walker 0.000536 # miss rate for overall accesses 858system.l2c.overall_miss_rate::cpu1.inst 0.010627 # miss rate for overall accesses 859system.l2c.overall_miss_rate::cpu1.data 0.229605 # miss rate for overall accesses 860system.l2c.overall_miss_rate::total 0.108629 # miss rate for overall accesses 861system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75750 # average ReadReq miss latency 862system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 863system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72642.381440 # average ReadReq miss latency 864system.l2c.ReadReq_avg_miss_latency::cpu0.data 75216.002368 # average ReadReq miss latency 865system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 866system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72166.395901 # average ReadReq miss latency 867system.l2c.ReadReq_avg_miss_latency::cpu1.data 78460.185185 # average ReadReq miss latency 868system.l2c.ReadReq_avg_miss_latency::total 74162.159018 # average ReadReq miss latency 869system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2867.238622 # average UpgradeReq miss latency 870system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3642.870272 # average UpgradeReq miss latency 871system.l2c.UpgradeReq_avg_miss_latency::total 3223.812118 # average UpgradeReq miss latency 872system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5034.577320 # average SCUpgradeReq miss latency 873system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2334.972860 # average SCUpgradeReq miss latency 874system.l2c.SCUpgradeReq_avg_miss_latency::total 3543.100346 # average SCUpgradeReq miss latency 875system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68960.660801 # average ReadExReq miss latency 876system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77149.070279 # average ReadExReq miss latency 877system.l2c.ReadExReq_avg_miss_latency::total 71573.943076 # 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average overall miss latency 889system.l2c.overall_avg_miss_latency::cpu0.data 69540.197167 # average overall miss latency 890system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 891system.l2c.overall_avg_miss_latency::cpu1.inst 72166.395901 # average overall miss latency 892system.l2c.overall_avg_miss_latency::cpu1.data 77202.379098 # average overall miss latency 893system.l2c.overall_avg_miss_latency::total 71932.138092 # average overall miss latency |
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| 991system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles | 976system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles |
| 992system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648858491 # number of ReadReq MSHR uncacheable cycles 993system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5098250 # number of ReadReq MSHR uncacheable cycles 994system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154081373749 # number of ReadReq MSHR uncacheable cycles 995system.l2c.ReadReq_mshr_uncacheable_latency::total 167080044240 # number of ReadReq MSHR uncacheable cycles 996system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272206162 # number of WriteReq MSHR uncacheable cycles 997system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486212000 # number of WriteReq MSHR uncacheable cycles 998system.l2c.WriteReq_mshr_uncacheable_latency::total 16758418162 # number of WriteReq MSHR uncacheable cycles | 977system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12649169494 # number of ReadReq MSHR uncacheable cycles 978system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5149250 # number of ReadReq MSHR uncacheable cycles 979system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154086197998 # number of ReadReq MSHR uncacheable cycles 980system.l2c.ReadReq_mshr_uncacheable_latency::total 167085230492 # number of ReadReq MSHR uncacheable cycles 981system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272194135 # number of WriteReq MSHR uncacheable cycles 982system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486232500 # number of WriteReq MSHR uncacheable cycles 983system.l2c.WriteReq_mshr_uncacheable_latency::total 16758426635 # number of WriteReq MSHR uncacheable cycles |
| 999system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles | 984system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles |
| 1000system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921064653 # number of overall MSHR uncacheable cycles 1001system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5098250 # number of overall MSHR uncacheable cycles 1002system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154567585749 # number of overall MSHR uncacheable cycles 1003system.l2c.overall_mshr_uncacheable_latency::total 183838462402 # number of overall MSHR uncacheable cycles 1004system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for ReadReq accesses 1005system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for ReadReq accesses 1006system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for ReadReq accesses 1007system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038608 # mshr miss rate for ReadReq accesses 1008system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for ReadReq accesses 1009system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses 1010system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses 1011system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses 1012system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses 1013system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses 1014system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses 1015system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses 1016system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses 1017system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses 1018system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592083 # mshr miss rate for ReadExReq accesses 1019system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses 1020system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses 1021system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for demand accesses 1022system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses 1023system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses 1024system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses 1025system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses 1026system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses 1027system.l2c.demand_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for demand accesses 1028system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses 1029system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses 1030system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses 1031system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses 1032system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses 1033system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses 1034system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses 1035system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses 1036system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses 1037system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency | 985system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921363629 # number of overall MSHR uncacheable cycles 986system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5149250 # number of overall MSHR uncacheable cycles 987system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154572430498 # number of overall MSHR uncacheable cycles 988system.l2c.overall_mshr_uncacheable_latency::total 183843657127 # number of overall MSHR uncacheable cycles 989system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses 990system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001384 # mshr miss rate for ReadReq accesses 991system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013941 # mshr miss rate for ReadReq accesses 992system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038595 # mshr miss rate for ReadReq accesses 993system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000536 # mshr miss rate for ReadReq accesses 994system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010627 # mshr miss rate for ReadReq accesses 995system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016807 # mshr miss rate for ReadReq accesses 996system.l2c.ReadReq_mshr_miss_rate::total 0.018066 # mshr miss rate for ReadReq accesses 997system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761294 # mshr miss rate for UpgradeReq accesses 998system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.883782 # mshr miss rate for UpgradeReq accesses 999system.l2c.UpgradeReq_mshr_miss_rate::total 0.813101 # mshr miss rate for UpgradeReq accesses 1000system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.598765 # mshr miss rate for SCUpgradeReq accesses 1001system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825862 # mshr miss rate for SCUpgradeReq accesses 1002system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706026 # mshr miss rate for SCUpgradeReq accesses 1003system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592150 # mshr miss rate for ReadExReq accesses 1004system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495483 # mshr miss rate for ReadExReq accesses 1005system.l2c.ReadExReq_mshr_miss_rate::total 0.557442 # mshr miss rate for ReadExReq accesses 1006system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses 1007system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001384 # mshr miss rate for demand accesses 1008system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013941 # mshr miss rate for demand accesses 1009system.l2c.demand_mshr_miss_rate::cpu0.data 0.254274 # mshr miss rate for demand accesses 1010system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000536 # mshr miss rate for demand accesses 1011system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010627 # mshr miss rate for demand accesses 1012system.l2c.demand_mshr_miss_rate::cpu1.data 0.229605 # mshr miss rate for demand accesses 1013system.l2c.demand_mshr_miss_rate::total 0.108628 # mshr miss rate for demand accesses 1014system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses 1015system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001384 # mshr miss rate for overall accesses 1016system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013941 # mshr miss rate for overall accesses 1017system.l2c.overall_mshr_miss_rate::cpu0.data 0.254274 # mshr miss rate for overall accesses 1018system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000536 # mshr miss rate for overall accesses 1019system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010627 # mshr miss rate for overall accesses 1020system.l2c.overall_mshr_miss_rate::cpu1.data 0.229605 # mshr miss rate for overall accesses 1021system.l2c.overall_mshr_miss_rate::total 0.108628 # mshr miss rate for overall accesses 1022system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average ReadReq mshr miss latency |
| 1038system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 1023system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 1039system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency 1040system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency | 1024system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average ReadReq mshr miss latency 1025system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62750.797509 # average ReadReq mshr miss latency |
| 1041system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency | 1026system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency |
| 1042system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency 1043system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency 1044system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency 1045system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency 1046system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency 1047system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency 1048system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency 1049system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency 1050system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency 1051system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency 1052system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency 1053system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency 1054system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency | 1027system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average ReadReq mshr miss latency 1028system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66057.804233 # average ReadReq mshr miss latency 1029system.l2c.ReadReq_avg_mshr_miss_latency::total 61604.186027 # average ReadReq mshr miss latency 1030system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.547900 # average UpgradeReq mshr miss latency 1031system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.172281 # average UpgradeReq mshr miss latency 1032system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.948784 # average UpgradeReq mshr miss latency 1033system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.574742 # average SCUpgradeReq mshr miss latency 1034system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.874739 # average SCUpgradeReq mshr miss latency 1035system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.685121 # average SCUpgradeReq mshr miss latency 1036system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56045.714220 # average ReadExReq mshr miss latency 1037system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64546.202494 # average ReadExReq mshr miss latency 1038system.l2c.ReadExReq_avg_mshr_miss_latency::total 58758.594590 # average ReadExReq mshr miss latency 1039system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency |
| 1055system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 1040system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 1056system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency 1057system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency | 1041system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency 1042system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency |
| 1058system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency | 1043system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency |
| 1059system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency 1060system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency 1061system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency 1062system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency | 1044system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency 1045system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency 1046system.l2c.demand_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency 1047system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency |
| 1063system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 1048system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 1064system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency 1065system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency | 1049system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency 1050system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency |
| 1066system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency | 1051system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency |
| 1067system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency 1068system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency 1069system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency | 1052system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency 1053system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency 1054system.l2c.overall_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency |
| 1070system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1071system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1072system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1073system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1074system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1075system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1076system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1077system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1082system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1083system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1084system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1085system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1086system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1087system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1088system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1089system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 1055system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1056system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1057system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1058system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1059system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1060system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1061system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1062system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1067system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1068system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1069system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1070system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1071system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1072system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1073system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1074system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 1090system.toL2Bus.throughput 118413539 # Throughput (bytes/s) 1091system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution 1092system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution | 1075system.toL2Bus.throughput 118330469 # Throughput (bytes/s) 1076system.toL2Bus.trans_dist::ReadReq 2505274 # Transaction distribution 1077system.toL2Bus.trans_dist::ReadResp 2505274 # Transaction distribution |
| 1093system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution 1094system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution | 1078system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution 1079system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution |
| 1095system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution 1096system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution 1097system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution 1098system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution 1099system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution 1100system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution 1101system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes) 1102system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes) 1103system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes) 1104system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes) 1105system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes) 1106system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes) 1107system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes) 1108system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes) 1109system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes) 1110system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes) 1111system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes) 1112system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes) 1113system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes) 1114system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes) 1115system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes) 1116system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes) 1117system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes) 1118system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes) 1119system.toL2Bus.data_through_bus 137274438 # Total data (bytes) 1120system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes) 1121system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks) | 1080system.toL2Bus.trans_dist::Writeback 576138 # Transaction distribution 1081system.toL2Bus.trans_dist::UpgradeReq 27005 # Transaction distribution 1082system.toL2Bus.trans_dist::SCUpgradeReq 16807 # Transaction distribution 1083system.toL2Bus.trans_dist::UpgradeResp 43812 # Transaction distribution 1084system.toL2Bus.trans_dist::ReadExReq 262415 # Transaction distribution 1085system.toL2Bus.trans_dist::ReadExResp 262415 # Transaction distribution 1086system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993978 # Packet count per connected master and slave (bytes) 1087system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951141 # Packet count per connected master and slave (bytes) 1088system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5841 # Packet count per connected master and slave (bytes) 1089system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14926 # Packet count per connected master and slave (bytes) 1090system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753985 # Packet count per connected master and slave (bytes) 1091system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879812 # Packet count per connected master and slave (bytes) 1092system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6193 # Packet count per connected master and slave (bytes) 1093system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 12022 # Packet count per connected master and slave (bytes) 1094system.toL2Bus.pkt_count::total 7617898 # Packet count per connected master and slave (bytes) 1095system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31385016 # Cumulative packet size per connected master and slave (bytes) 1096system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53721240 # Cumulative packet size per connected master and slave (bytes) 1097system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5780 # Cumulative packet size per connected master and slave (bytes) 1098system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18120 # Cumulative packet size per connected master and slave (bytes) 1099system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24096780 # Cumulative packet size per connected master and slave (bytes) 1100system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27936146 # Cumulative packet size per connected master and slave (bytes) 1101system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7468 # Cumulative packet size per connected master and slave (bytes) 1102system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15168 # Cumulative packet size per connected master and slave (bytes) 1103system.toL2Bus.tot_pkt_size::total 137185718 # Cumulative packet size per connected master and slave (bytes) 1104system.toL2Bus.data_through_bus 137185718 # Total data (bytes) 1105system.toL2Bus.snoop_data_through_bus 4312904 # Total snoop data (bytes) 1106system.toL2Bus.reqLayer0.occupancy 4765712727 # Layer occupancy (ticks) |
| 1122system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) | 1107system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) |
| 1123system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks) | 1108system.toL2Bus.respLayer0.occupancy 2217854478 # Layer occupancy (ticks) |
| 1124system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) | 1109system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1125system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks) | 1110system.toL2Bus.respLayer1.occupancy 2469983321 # Layer occupancy (ticks) |
| 1126system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1127system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) 1128system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1111system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1112system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) 1113system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1129system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks) | 1114system.toL2Bus.respLayer3.occupancy 10396000 # Layer occupancy (ticks) |
| 1130system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1115system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1131system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks) | 1116system.toL2Bus.respLayer4.occupancy 1698669462 # Layer occupancy (ticks) |
| 1132system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) | 1117system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) |
| 1133system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks) | 1118system.toL2Bus.respLayer5.occupancy 2208533441 # Layer occupancy (ticks) |
| 1134system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1135system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) 1136system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) | 1119system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1120system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) 1121system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) |
| 1137system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks) | 1122system.toL2Bus.respLayer7.occupancy 8230499 # Layer occupancy (ticks) |
| 1138system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) | 1123system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) |
| 1139system.iobus.throughput 45405912 # Throughput (bytes/s) | 1124system.iobus.throughput 45404559 # Throughput (bytes/s) |
| 1140system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution 1141system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution 1142system.iobus.trans_dist::WriteReq 7946 # Transaction distribution 1143system.iobus.trans_dist::WriteResp 7946 # Transaction distribution 1144system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) 1145system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes) 1146system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1147system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) --- 93 unchanged lines hidden (view full) --- 1241system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1242system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1244system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1246system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 1247system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) 1248system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) | 1125system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution 1126system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution 1127system.iobus.trans_dist::WriteReq 7946 # Transaction distribution 1128system.iobus.trans_dist::WriteResp 7946 # Transaction distribution 1129system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) --- 93 unchanged lines hidden (view full) --- 1226system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1227system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1228system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1229system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1230system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1231system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 1232system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) 1233system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1249system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks) | 1234system.iobus.respLayer1.occupancy 17777853001 # Layer occupancy (ticks) |
| 1250system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1251system.cpu0.dtb.inst_hits 0 # ITB inst hits 1252system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1235system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1236system.cpu0.dtb.inst_hits 0 # ITB inst hits 1237system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1253system.cpu0.dtb.read_hits 9652613 # DTB read hits 1254system.cpu0.dtb.read_misses 3746 # DTB read misses 1255system.cpu0.dtb.write_hits 7596890 # DTB write hits | 1238system.cpu0.dtb.read_hits 9652640 # DTB read hits 1239system.cpu0.dtb.read_misses 3742 # DTB read misses 1240system.cpu0.dtb.write_hits 7596858 # DTB write hits |
| 1256system.cpu0.dtb.write_misses 1582 # DTB write misses 1257system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1258system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1259system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1260system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1261system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB 1262system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1241system.cpu0.dtb.write_misses 1582 # DTB write misses 1242system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1243system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1244system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1245system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1246system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB 1247system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1263system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch | 1248system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch |
| 1264system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1265system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions | 1249system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1250system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions |
| 1266system.cpu0.dtb.read_accesses 9656359 # DTB read accesses 1267system.cpu0.dtb.write_accesses 7598472 # DTB write accesses | 1251system.cpu0.dtb.read_accesses 9656382 # DTB read accesses 1252system.cpu0.dtb.write_accesses 7598440 # DTB write accesses |
| 1268system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1253system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1269system.cpu0.dtb.hits 17249503 # DTB hits 1270system.cpu0.dtb.misses 5328 # DTB misses 1271system.cpu0.dtb.accesses 17254831 # DTB accesses 1272system.cpu0.itb.inst_hits 43298526 # ITB inst hits | 1254system.cpu0.dtb.hits 17249498 # DTB hits 1255system.cpu0.dtb.misses 5324 # DTB misses 1256system.cpu0.dtb.accesses 17254822 # DTB accesses 1257system.cpu0.itb.inst_hits 43298691 # ITB inst hits |
| 1273system.cpu0.itb.inst_misses 2205 # ITB inst misses 1274system.cpu0.itb.read_hits 0 # DTB read hits 1275system.cpu0.itb.read_misses 0 # DTB read misses 1276system.cpu0.itb.write_hits 0 # DTB write hits 1277system.cpu0.itb.write_misses 0 # DTB write misses 1278system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1279system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1280system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1281system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1282system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 1283system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1284system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1285system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1286system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1287system.cpu0.itb.read_accesses 0 # DTB read accesses 1288system.cpu0.itb.write_accesses 0 # DTB write accesses | 1258system.cpu0.itb.inst_misses 2205 # ITB inst misses 1259system.cpu0.itb.read_hits 0 # DTB read hits 1260system.cpu0.itb.read_misses 0 # DTB read misses 1261system.cpu0.itb.write_hits 0 # DTB write hits 1262system.cpu0.itb.write_misses 0 # DTB write misses 1263system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1264system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1265system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1266system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1267system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 1268system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1269system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1270system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1271system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1272system.cpu0.itb.read_accesses 0 # DTB read accesses 1273system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1289system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses 1290system.cpu0.itb.hits 43298526 # DTB hits | 1274system.cpu0.itb.inst_accesses 43300896 # ITB inst accesses 1275system.cpu0.itb.hits 43298691 # DTB hits |
| 1291system.cpu0.itb.misses 2205 # DTB misses | 1276system.cpu0.itb.misses 2205 # DTB misses |
| 1292system.cpu0.itb.accesses 43300731 # DTB accesses 1293system.cpu0.numCycles 2391512647 # number of cpu cycles simulated | 1277system.cpu0.itb.accesses 43300896 # DTB accesses 1278system.cpu0.numCycles 2391583901 # number of cpu cycles simulated |
| 1294system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1295system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1279system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1280system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1296system.cpu0.committedInsts 42571581 # Number of instructions committed 1297system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed 1298system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses | 1281system.cpu0.committedInsts 42571767 # Number of instructions committed 1282system.cpu0.committedOps 53302041 # Number of ops (including micro ops) committed 1283system.cpu0.num_int_alu_accesses 48059042 # Number of integer alu accesses |
| 1299system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses | 1284system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses |
| 1300system.cpu0.num_func_calls 1403638 # number of times a function call or return occured 1301system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls 1302system.cpu0.num_int_insts 48058821 # number of integer instructions | 1285system.cpu0.num_func_calls 1403630 # number of times a function call or return occured 1286system.cpu0.num_conditional_control_insts 5582817 # number of instructions that are conditional controls 1287system.cpu0.num_int_insts 48059042 # number of integer instructions |
| 1303system.cpu0.num_fp_insts 3860 # number of float instructions | 1288system.cpu0.num_fp_insts 3860 # number of float instructions |
| 1304system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read 1305system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written | 1289system.cpu0.num_int_register_reads 272441604 # number of times the integer registers were read 1290system.cpu0.num_int_register_writes 52270515 # number of times the integer registers were written |
| 1306system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1307system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 1308system.cpu0.num_mem_refs 18019009 # number of memory refs | 1291system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1292system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 1293system.cpu0.num_mem_refs 18019009 # number of memory refs |
| 1309system.cpu0.num_load_insts 10036459 # Number of load instructions 1310system.cpu0.num_store_insts 7982550 # Number of store instructions 1311system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles 1312system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles 1313system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles 1314system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles | 1294system.cpu0.num_load_insts 10036503 # Number of load instructions 1295system.cpu0.num_store_insts 7982506 # Number of store instructions 1296system.cpu0.num_idle_cycles 2151142905.888201 # Number of idle cycles 1297system.cpu0.num_busy_cycles 240440995.111799 # Number of busy cycles 1298system.cpu0.not_idle_fraction 0.100536 # Percentage of non-idle cycles 1299system.cpu0.idle_fraction 0.899464 # Percentage of idle cycles |
| 1315system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1300system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1316system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed 1317system.cpu0.icache.tags.replacements 490259 # number of replacements 1318system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use 1319system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks. 1320system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks. 1321system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks. 1322system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit. 1323system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor 1324system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy 1325system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy 1326system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits 1327system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits 1328system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits 1329system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits 1330system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits 1331system.cpu0.icache.overall_hits::total 42807737 # number of overall hits 1332system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses 1333system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses 1334system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses 1335system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses 1336system.cpu0.icache.overall_misses::cpu0.inst 490772 # number of overall misses 1337system.cpu0.icache.overall_misses::total 490772 # number of overall misses 1338system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6820513233 # number of ReadReq miss cycles 1339system.cpu0.icache.ReadReq_miss_latency::total 6820513233 # number of ReadReq miss cycles 1340system.cpu0.icache.demand_miss_latency::cpu0.inst 6820513233 # number of demand (read+write) miss cycles 1341system.cpu0.icache.demand_miss_latency::total 6820513233 # number of demand (read+write) miss cycles 1342system.cpu0.icache.overall_miss_latency::cpu0.inst 6820513233 # number of overall miss cycles 1343system.cpu0.icache.overall_miss_latency::total 6820513233 # number of overall miss cycles 1344system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298509 # number of ReadReq accesses(hits+misses) 1345system.cpu0.icache.ReadReq_accesses::total 43298509 # number of ReadReq accesses(hits+misses) 1346system.cpu0.icache.demand_accesses::cpu0.inst 43298509 # number of demand (read+write) accesses 1347system.cpu0.icache.demand_accesses::total 43298509 # number of demand (read+write) accesses 1348system.cpu0.icache.overall_accesses::cpu0.inst 43298509 # number of overall (read+write) accesses 1349system.cpu0.icache.overall_accesses::total 43298509 # number of overall (read+write) accesses 1350system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011335 # miss rate for ReadReq accesses 1351system.cpu0.icache.ReadReq_miss_rate::total 0.011335 # miss rate for ReadReq accesses 1352system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011335 # miss rate for demand accesses 1353system.cpu0.icache.demand_miss_rate::total 0.011335 # miss rate for demand accesses 1354system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011335 # miss rate for overall accesses 1355system.cpu0.icache.overall_miss_rate::total 0.011335 # miss rate for overall accesses 1356system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.519078 # average ReadReq miss latency 1357system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.519078 # average ReadReq miss latency 1358system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency 1359system.cpu0.icache.demand_avg_miss_latency::total 13897.519078 # average overall miss latency 1360system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency 1361system.cpu0.icache.overall_avg_miss_latency::total 13897.519078 # average overall miss latency | 1301system.cpu0.kern.inst.quiesce 51319 # number of quiesce instructions executed 1302system.cpu0.icache.tags.replacements 490213 # number of replacements 1303system.cpu0.icache.tags.tagsinuse 509.358566 # Cycle average of tags in use 1304system.cpu0.icache.tags.total_refs 42807948 # Total number of references to valid blocks. 1305system.cpu0.icache.tags.sampled_refs 490725 # Sample count of references to valid blocks. 1306system.cpu0.icache.tags.avg_refs 87.234088 # Average number of references to valid blocks. 1307system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. 1308system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.358566 # Average occupied blocks per requestor 1309system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994841 # Average percentage of cache occupancy 1310system.cpu0.icache.tags.occ_percent::total 0.994841 # Average percentage of cache occupancy 1311system.cpu0.icache.ReadReq_hits::cpu0.inst 42807948 # number of ReadReq hits 1312system.cpu0.icache.ReadReq_hits::total 42807948 # number of ReadReq hits 1313system.cpu0.icache.demand_hits::cpu0.inst 42807948 # number of demand (read+write) hits 1314system.cpu0.icache.demand_hits::total 42807948 # number of demand (read+write) hits 1315system.cpu0.icache.overall_hits::cpu0.inst 42807948 # number of overall hits 1316system.cpu0.icache.overall_hits::total 42807948 # number of overall hits 1317system.cpu0.icache.ReadReq_misses::cpu0.inst 490726 # number of ReadReq misses 1318system.cpu0.icache.ReadReq_misses::total 490726 # number of ReadReq misses 1319system.cpu0.icache.demand_misses::cpu0.inst 490726 # number of demand (read+write) misses 1320system.cpu0.icache.demand_misses::total 490726 # number of demand (read+write) misses 1321system.cpu0.icache.overall_misses::cpu0.inst 490726 # number of overall misses 1322system.cpu0.icache.overall_misses::total 490726 # number of overall misses 1323system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6824885728 # number of ReadReq miss cycles 1324system.cpu0.icache.ReadReq_miss_latency::total 6824885728 # number of ReadReq miss cycles 1325system.cpu0.icache.demand_miss_latency::cpu0.inst 6824885728 # number of demand (read+write) miss cycles 1326system.cpu0.icache.demand_miss_latency::total 6824885728 # number of demand (read+write) miss cycles 1327system.cpu0.icache.overall_miss_latency::cpu0.inst 6824885728 # number of overall miss cycles 1328system.cpu0.icache.overall_miss_latency::total 6824885728 # number of overall miss cycles 1329system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298674 # number of ReadReq accesses(hits+misses) 1330system.cpu0.icache.ReadReq_accesses::total 43298674 # number of ReadReq accesses(hits+misses) 1331system.cpu0.icache.demand_accesses::cpu0.inst 43298674 # number of demand (read+write) accesses 1332system.cpu0.icache.demand_accesses::total 43298674 # number of demand (read+write) accesses 1333system.cpu0.icache.overall_accesses::cpu0.inst 43298674 # number of overall (read+write) accesses 1334system.cpu0.icache.overall_accesses::total 43298674 # number of overall (read+write) accesses 1335system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011334 # miss rate for ReadReq accesses 1336system.cpu0.icache.ReadReq_miss_rate::total 0.011334 # miss rate for ReadReq accesses 1337system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011334 # miss rate for demand accesses 1338system.cpu0.icache.demand_miss_rate::total 0.011334 # miss rate for demand accesses 1339system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011334 # miss rate for overall accesses 1340system.cpu0.icache.overall_miss_rate::total 0.011334 # miss rate for overall accesses 1341system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13907.732070 # average ReadReq miss latency 1342system.cpu0.icache.ReadReq_avg_miss_latency::total 13907.732070 # average ReadReq miss latency 1343system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13907.732070 # average overall miss latency 1344system.cpu0.icache.demand_avg_miss_latency::total 13907.732070 # average overall miss latency 1345system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13907.732070 # average overall miss latency 1346system.cpu0.icache.overall_avg_miss_latency::total 13907.732070 # average overall miss latency |
| 1362system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1363system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1364system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1365system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1366system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1367system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1368system.cpu0.icache.fast_writes 0 # number of fast writes performed 1369system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1347system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1348system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1349system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1350system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1351system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1352system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1353system.cpu0.icache.fast_writes 0 # number of fast writes performed 1354system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1370system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490772 # number of ReadReq MSHR misses 1371system.cpu0.icache.ReadReq_mshr_misses::total 490772 # number of ReadReq MSHR misses 1372system.cpu0.icache.demand_mshr_misses::cpu0.inst 490772 # number of demand (read+write) MSHR misses 1373system.cpu0.icache.demand_mshr_misses::total 490772 # number of demand (read+write) MSHR misses 1374system.cpu0.icache.overall_mshr_misses::cpu0.inst 490772 # number of overall MSHR misses 1375system.cpu0.icache.overall_mshr_misses::total 490772 # number of overall MSHR misses 1376system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5836336767 # number of ReadReq MSHR miss cycles 1377system.cpu0.icache.ReadReq_mshr_miss_latency::total 5836336767 # number of ReadReq MSHR miss cycles 1378system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5836336767 # number of demand (read+write) MSHR miss cycles 1379system.cpu0.icache.demand_mshr_miss_latency::total 5836336767 # number of demand (read+write) MSHR miss cycles 1380system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5836336767 # number of overall MSHR miss cycles 1381system.cpu0.icache.overall_mshr_miss_latency::total 5836336767 # number of overall MSHR miss cycles 1382system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393250 # number of ReadReq MSHR uncacheable cycles 1383system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles 1384system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles 1385system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles 1386system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses 1387system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses 1388system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses 1389system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses 1390system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses 1391system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses 1392system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency 1393system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11892.155149 # average ReadReq mshr miss latency 1394system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency 1395system.cpu0.icache.demand_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency 1396system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency 1397system.cpu0.icache.overall_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency | 1355system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490726 # number of ReadReq MSHR misses 1356system.cpu0.icache.ReadReq_mshr_misses::total 490726 # number of ReadReq MSHR misses 1357system.cpu0.icache.demand_mshr_misses::cpu0.inst 490726 # number of demand (read+write) MSHR misses 1358system.cpu0.icache.demand_mshr_misses::total 490726 # number of demand (read+write) MSHR misses 1359system.cpu0.icache.overall_mshr_misses::cpu0.inst 490726 # number of overall MSHR misses 1360system.cpu0.icache.overall_mshr_misses::total 490726 # number of overall MSHR misses 1361system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5840816272 # number of ReadReq MSHR miss cycles 1362system.cpu0.icache.ReadReq_mshr_miss_latency::total 5840816272 # number of ReadReq MSHR miss cycles 1363system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5840816272 # number of demand (read+write) MSHR miss cycles 1364system.cpu0.icache.demand_mshr_miss_latency::total 5840816272 # number of demand (read+write) MSHR miss cycles 1365system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5840816272 # number of overall MSHR miss cycles 1366system.cpu0.icache.overall_mshr_miss_latency::total 5840816272 # number of overall MSHR miss cycles 1367system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393750 # number of ReadReq MSHR uncacheable cycles 1368system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393750 # number of ReadReq MSHR uncacheable cycles 1369system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393750 # number of overall MSHR uncacheable cycles 1370system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393750 # number of overall MSHR uncacheable cycles 1371system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011334 # mshr miss rate for ReadReq accesses 1372system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011334 # mshr miss rate for ReadReq accesses 1373system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011334 # mshr miss rate for demand accesses 1374system.cpu0.icache.demand_mshr_miss_rate::total 0.011334 # mshr miss rate for demand accesses 1375system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011334 # mshr miss rate for overall accesses 1376system.cpu0.icache.overall_mshr_miss_rate::total 0.011334 # mshr miss rate for overall accesses 1377system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average ReadReq mshr miss latency 1378system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11902.398226 # average ReadReq mshr miss latency 1379system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency 1380system.cpu0.icache.demand_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency 1381system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency 1382system.cpu0.icache.overall_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency |
| 1398system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1399system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1400system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1401system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1402system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1383system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1384system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1385system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1386system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1387system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1403system.cpu0.dcache.tags.replacements 407019 # number of replacements 1404system.cpu0.dcache.tags.tagsinuse 470.951702 # Cycle average of tags in use 1405system.cpu0.dcache.tags.total_refs 15966189 # Total number of references to valid blocks. 1406system.cpu0.dcache.tags.sampled_refs 407531 # Sample count of references to valid blocks. 1407system.cpu0.dcache.tags.avg_refs 39.177852 # Average number of references to valid blocks. | 1388system.cpu0.dcache.tags.replacements 406717 # number of replacements 1389system.cpu0.dcache.tags.tagsinuse 471.656866 # Cycle average of tags in use 1390system.cpu0.dcache.tags.total_refs 15966646 # Total number of references to valid blocks. 1391system.cpu0.dcache.tags.sampled_refs 407229 # Sample count of references to valid blocks. 1392system.cpu0.dcache.tags.avg_refs 39.208028 # Average number of references to valid blocks. |
| 1408system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit. | 1393system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit. |
| 1409system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.951702 # Average occupied blocks per requestor 1410system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919828 # Average percentage of cache occupancy 1411system.cpu0.dcache.tags.occ_percent::total 0.919828 # Average percentage of cache occupancy 1412system.cpu0.dcache.ReadReq_hits::cpu0.data 9136364 # number of ReadReq hits 1413system.cpu0.dcache.ReadReq_hits::total 9136364 # number of ReadReq hits 1414system.cpu0.dcache.WriteReq_hits::cpu0.data 6494337 # number of WriteReq hits 1415system.cpu0.dcache.WriteReq_hits::total 6494337 # number of WriteReq hits 1416system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156491 # number of LoadLockedReq hits 1417system.cpu0.dcache.LoadLockedReq_hits::total 156491 # number of LoadLockedReq hits 1418system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158920 # number of StoreCondReq hits 1419system.cpu0.dcache.StoreCondReq_hits::total 158920 # number of StoreCondReq hits 1420system.cpu0.dcache.demand_hits::cpu0.data 15630701 # number of demand (read+write) hits 1421system.cpu0.dcache.demand_hits::total 15630701 # number of demand (read+write) hits 1422system.cpu0.dcache.overall_hits::cpu0.data 15630701 # number of overall hits 1423system.cpu0.dcache.overall_hits::total 15630701 # number of overall hits 1424system.cpu0.dcache.ReadReq_misses::cpu0.data 264039 # number of ReadReq misses 1425system.cpu0.dcache.ReadReq_misses::total 264039 # number of ReadReq misses 1426system.cpu0.dcache.WriteReq_misses::cpu0.data 176698 # number of WriteReq misses 1427system.cpu0.dcache.WriteReq_misses::total 176698 # number of WriteReq misses 1428system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9925 # number of LoadLockedReq misses 1429system.cpu0.dcache.LoadLockedReq_misses::total 9925 # number of LoadLockedReq misses 1430system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7429 # number of StoreCondReq misses 1431system.cpu0.dcache.StoreCondReq_misses::total 7429 # number of StoreCondReq misses 1432system.cpu0.dcache.demand_misses::cpu0.data 440737 # number of demand (read+write) misses 1433system.cpu0.dcache.demand_misses::total 440737 # number of demand (read+write) misses 1434system.cpu0.dcache.overall_misses::cpu0.data 440737 # number of overall misses 1435system.cpu0.dcache.overall_misses::total 440737 # number of overall misses 1436system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3925412746 # number of ReadReq miss cycles 1437system.cpu0.dcache.ReadReq_miss_latency::total 3925412746 # number of ReadReq miss cycles 1438system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7893125788 # number of WriteReq miss cycles 1439system.cpu0.dcache.WriteReq_miss_latency::total 7893125788 # number of WriteReq miss cycles 1440system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98805250 # number of LoadLockedReq miss cycles 1441system.cpu0.dcache.LoadLockedReq_miss_latency::total 98805250 # number of LoadLockedReq miss cycles 1442system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40843887 # number of StoreCondReq miss cycles 1443system.cpu0.dcache.StoreCondReq_miss_latency::total 40843887 # number of StoreCondReq miss cycles 1444system.cpu0.dcache.demand_miss_latency::cpu0.data 11818538534 # number of demand (read+write) miss cycles 1445system.cpu0.dcache.demand_miss_latency::total 11818538534 # number of demand (read+write) miss cycles 1446system.cpu0.dcache.overall_miss_latency::cpu0.data 11818538534 # number of overall miss cycles 1447system.cpu0.dcache.overall_miss_latency::total 11818538534 # number of overall miss cycles 1448system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400403 # number of ReadReq accesses(hits+misses) 1449system.cpu0.dcache.ReadReq_accesses::total 9400403 # number of ReadReq accesses(hits+misses) 1450system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671035 # number of WriteReq accesses(hits+misses) 1451system.cpu0.dcache.WriteReq_accesses::total 6671035 # number of WriteReq accesses(hits+misses) 1452system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166416 # number of LoadLockedReq accesses(hits+misses) 1453system.cpu0.dcache.LoadLockedReq_accesses::total 166416 # number of LoadLockedReq accesses(hits+misses) 1454system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166349 # number of StoreCondReq accesses(hits+misses) 1455system.cpu0.dcache.StoreCondReq_accesses::total 166349 # number of StoreCondReq accesses(hits+misses) 1456system.cpu0.dcache.demand_accesses::cpu0.data 16071438 # number of demand (read+write) accesses 1457system.cpu0.dcache.demand_accesses::total 16071438 # number of demand (read+write) accesses 1458system.cpu0.dcache.overall_accesses::cpu0.data 16071438 # number of overall (read+write) accesses 1459system.cpu0.dcache.overall_accesses::total 16071438 # number of overall (read+write) accesses 1460system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028088 # miss rate for ReadReq accesses 1461system.cpu0.dcache.ReadReq_miss_rate::total 0.028088 # miss rate for ReadReq accesses 1462system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026487 # miss rate for WriteReq accesses 1463system.cpu0.dcache.WriteReq_miss_rate::total 0.026487 # miss rate for WriteReq accesses 1464system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059640 # miss rate for LoadLockedReq accesses 1465system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059640 # miss rate for LoadLockedReq accesses 1466system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044659 # miss rate for StoreCondReq accesses 1467system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044659 # miss rate for StoreCondReq accesses 1468system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027424 # miss rate for demand accesses 1469system.cpu0.dcache.demand_miss_rate::total 0.027424 # miss rate for demand accesses 1470system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027424 # miss rate for overall accesses 1471system.cpu0.dcache.overall_miss_rate::total 0.027424 # miss rate for overall accesses 1472system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14866.791444 # average ReadReq miss latency 1473system.cpu0.dcache.ReadReq_avg_miss_latency::total 14866.791444 # average ReadReq miss latency 1474system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency 1475system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency 1476system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency 1477system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency 1478system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency 1479system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency 1480system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency 1481system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency 1482system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency 1483system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency | 1394system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.656866 # Average occupied blocks per requestor 1395system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921205 # Average percentage of cache occupancy 1396system.cpu0.dcache.tags.occ_percent::total 0.921205 # Average percentage of cache occupancy 1397system.cpu0.dcache.ReadReq_hits::cpu0.data 9136610 # number of ReadReq hits 1398system.cpu0.dcache.ReadReq_hits::total 9136610 # number of ReadReq hits 1399system.cpu0.dcache.WriteReq_hits::cpu0.data 6494353 # number of WriteReq hits 1400system.cpu0.dcache.WriteReq_hits::total 6494353 # number of WriteReq hits 1401system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156522 # number of LoadLockedReq hits 1402system.cpu0.dcache.LoadLockedReq_hits::total 156522 # number of LoadLockedReq hits 1403system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158977 # number of StoreCondReq hits 1404system.cpu0.dcache.StoreCondReq_hits::total 158977 # number of StoreCondReq hits 1405system.cpu0.dcache.demand_hits::cpu0.data 15630963 # number of demand (read+write) hits 1406system.cpu0.dcache.demand_hits::total 15630963 # number of demand (read+write) hits 1407system.cpu0.dcache.overall_hits::cpu0.data 15630963 # number of overall hits 1408system.cpu0.dcache.overall_hits::total 15630963 # number of overall hits 1409system.cpu0.dcache.ReadReq_misses::cpu0.data 263803 # number of ReadReq misses 1410system.cpu0.dcache.ReadReq_misses::total 263803 # number of ReadReq misses 1411system.cpu0.dcache.WriteReq_misses::cpu0.data 176623 # number of WriteReq misses 1412system.cpu0.dcache.WriteReq_misses::total 176623 # number of WriteReq misses 1413system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9911 # number of LoadLockedReq misses 1414system.cpu0.dcache.LoadLockedReq_misses::total 9911 # number of LoadLockedReq misses 1415system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7399 # number of StoreCondReq misses 1416system.cpu0.dcache.StoreCondReq_misses::total 7399 # number of StoreCondReq misses 1417system.cpu0.dcache.demand_misses::cpu0.data 440426 # number of demand (read+write) misses 1418system.cpu0.dcache.demand_misses::total 440426 # number of demand (read+write) misses 1419system.cpu0.dcache.overall_misses::cpu0.data 440426 # number of overall misses 1420system.cpu0.dcache.overall_misses::total 440426 # number of overall misses 1421system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3917573248 # number of ReadReq miss cycles 1422system.cpu0.dcache.ReadReq_miss_latency::total 3917573248 # number of ReadReq miss cycles 1423system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7906184046 # number of WriteReq miss cycles 1424system.cpu0.dcache.WriteReq_miss_latency::total 7906184046 # number of WriteReq miss cycles 1425system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99581999 # number of LoadLockedReq miss cycles 1426system.cpu0.dcache.LoadLockedReq_miss_latency::total 99581999 # number of LoadLockedReq miss cycles 1427system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40689888 # number of StoreCondReq miss cycles 1428system.cpu0.dcache.StoreCondReq_miss_latency::total 40689888 # number of StoreCondReq miss cycles 1429system.cpu0.dcache.demand_miss_latency::cpu0.data 11823757294 # number of demand (read+write) miss cycles 1430system.cpu0.dcache.demand_miss_latency::total 11823757294 # number of demand (read+write) miss cycles 1431system.cpu0.dcache.overall_miss_latency::cpu0.data 11823757294 # number of overall miss cycles 1432system.cpu0.dcache.overall_miss_latency::total 11823757294 # number of overall miss cycles 1433system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400413 # number of ReadReq accesses(hits+misses) 1434system.cpu0.dcache.ReadReq_accesses::total 9400413 # number of ReadReq accesses(hits+misses) 1435system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670976 # number of WriteReq accesses(hits+misses) 1436system.cpu0.dcache.WriteReq_accesses::total 6670976 # number of WriteReq accesses(hits+misses) 1437system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166433 # number of LoadLockedReq accesses(hits+misses) 1438system.cpu0.dcache.LoadLockedReq_accesses::total 166433 # number of LoadLockedReq accesses(hits+misses) 1439system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166376 # number of StoreCondReq accesses(hits+misses) 1440system.cpu0.dcache.StoreCondReq_accesses::total 166376 # number of StoreCondReq accesses(hits+misses) 1441system.cpu0.dcache.demand_accesses::cpu0.data 16071389 # number of demand (read+write) accesses 1442system.cpu0.dcache.demand_accesses::total 16071389 # number of demand (read+write) accesses 1443system.cpu0.dcache.overall_accesses::cpu0.data 16071389 # number of overall (read+write) accesses 1444system.cpu0.dcache.overall_accesses::total 16071389 # number of overall (read+write) accesses 1445system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028063 # miss rate for ReadReq accesses 1446system.cpu0.dcache.ReadReq_miss_rate::total 0.028063 # miss rate for ReadReq accesses 1447system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026476 # miss rate for WriteReq accesses 1448system.cpu0.dcache.WriteReq_miss_rate::total 0.026476 # miss rate for WriteReq accesses 1449system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059549 # miss rate for LoadLockedReq accesses 1450system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059549 # miss rate for LoadLockedReq accesses 1451system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044472 # miss rate for StoreCondReq accesses 1452system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044472 # miss rate for StoreCondReq accesses 1453system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027404 # miss rate for demand accesses 1454system.cpu0.dcache.demand_miss_rate::total 0.027404 # miss rate for demand accesses 1455system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027404 # miss rate for overall accesses 1456system.cpu0.dcache.overall_miss_rate::total 0.027404 # miss rate for overall accesses 1457system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14850.374135 # average ReadReq miss latency 1458system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.374135 # average ReadReq miss latency 1459system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44763.049240 # average WriteReq miss latency 1460system.cpu0.dcache.WriteReq_avg_miss_latency::total 44763.049240 # average WriteReq miss latency 1461system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10047.623751 # average LoadLockedReq miss latency 1462system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10047.623751 # average LoadLockedReq miss latency 1463system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5499.376673 # average StoreCondReq miss latency 1464system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5499.376673 # average StoreCondReq miss latency 1465system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency 1466system.cpu0.dcache.demand_avg_miss_latency::total 26846.183681 # average overall miss latency 1467system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency 1468system.cpu0.dcache.overall_avg_miss_latency::total 26846.183681 # average overall miss latency |
| 1484system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1485system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1486system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1487system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1488system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1489system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1490system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1491system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1469system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1470system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1471system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1472system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1473system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1474system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1475system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1476system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1492system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks 1493system.cpu0.dcache.writebacks::total 376552 # number of writebacks 1494system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses 1495system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses 1496system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses 1497system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses 1498system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses 1499system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses 1500system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses 1501system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses 1502system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses 1503system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses 1504system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses 1505system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses 1506system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles 1507system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles 1508system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles 1509system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles 1510system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles 1511system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles 1512system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles 1513system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles 1514system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles 1515system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1516system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles 1517system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles 1518system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles 1519system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles 1520system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles 1521system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles 1522system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles 1523system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles 1524system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles 1525system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles 1526system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses 1527system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses 1528system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses 1529system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses 1530system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses 1531system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses 1532system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses 1533system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses 1534system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses 1535system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses 1536system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses 1537system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses 1538system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency 1539system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency 1540system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency 1541system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency 1542system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency 1543system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency 1544system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency 1545system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency | 1477system.cpu0.dcache.writebacks::writebacks 376546 # number of writebacks 1478system.cpu0.dcache.writebacks::total 376546 # number of writebacks 1479system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263803 # number of ReadReq MSHR misses 1480system.cpu0.dcache.ReadReq_mshr_misses::total 263803 # number of ReadReq MSHR misses 1481system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176623 # number of WriteReq MSHR misses 1482system.cpu0.dcache.WriteReq_mshr_misses::total 176623 # number of WriteReq MSHR misses 1483system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9911 # number of LoadLockedReq MSHR misses 1484system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9911 # number of LoadLockedReq MSHR misses 1485system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7395 # number of StoreCondReq MSHR misses 1486system.cpu0.dcache.StoreCondReq_mshr_misses::total 7395 # number of StoreCondReq MSHR misses 1487system.cpu0.dcache.demand_mshr_misses::cpu0.data 440426 # number of demand (read+write) MSHR misses 1488system.cpu0.dcache.demand_mshr_misses::total 440426 # number of demand (read+write) MSHR misses 1489system.cpu0.dcache.overall_mshr_misses::cpu0.data 440426 # number of overall MSHR misses 1490system.cpu0.dcache.overall_mshr_misses::total 440426 # number of overall MSHR misses 1491system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3387671752 # number of ReadReq MSHR miss cycles 1492system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3387671752 # number of ReadReq MSHR miss cycles 1493system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7508595954 # number of WriteReq MSHR miss cycles 1494system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7508595954 # number of WriteReq MSHR miss cycles 1495system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79710001 # number of LoadLockedReq MSHR miss cycles 1496system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79710001 # number of LoadLockedReq MSHR miss cycles 1497system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25901112 # number of StoreCondReq MSHR miss cycles 1498system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25901112 # number of StoreCondReq MSHR miss cycles 1499system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1500system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1501system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10896267706 # number of demand (read+write) MSHR miss cycles 1502system.cpu0.dcache.demand_mshr_miss_latency::total 10896267706 # number of demand (read+write) MSHR miss cycles 1503system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10896267706 # number of overall MSHR miss cycles 1504system.cpu0.dcache.overall_mshr_miss_latency::total 10896267706 # number of overall MSHR miss cycles 1505system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765830000 # number of ReadReq MSHR uncacheable cycles 1506system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765830000 # number of ReadReq MSHR uncacheable cycles 1507system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807312360 # number of WriteReq MSHR uncacheable cycles 1508system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807312360 # number of WriteReq MSHR uncacheable cycles 1509system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39573142360 # number of overall MSHR uncacheable cycles 1510system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39573142360 # number of overall MSHR uncacheable cycles 1511system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028063 # mshr miss rate for ReadReq accesses 1512system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028063 # mshr miss rate for ReadReq accesses 1513system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026476 # mshr miss rate for WriteReq accesses 1514system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026476 # mshr miss rate for WriteReq accesses 1515system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059549 # mshr miss rate for LoadLockedReq accesses 1516system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059549 # mshr miss rate for LoadLockedReq accesses 1517system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044448 # mshr miss rate for StoreCondReq accesses 1518system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044448 # mshr miss rate for StoreCondReq accesses 1519system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for demand accesses 1520system.cpu0.dcache.demand_mshr_miss_rate::total 0.027404 # mshr miss rate for demand accesses 1521system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses 1522system.cpu0.dcache.overall_mshr_miss_rate::total 0.027404 # mshr miss rate for overall accesses 1523system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.672581 # average ReadReq mshr miss latency 1524system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.672581 # average ReadReq mshr miss latency 1525system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42511.994214 # average WriteReq mshr miss latency 1526system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42511.994214 # average WriteReq mshr miss latency 1527system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8042.579054 # average LoadLockedReq mshr miss latency 1528system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8042.579054 # average LoadLockedReq mshr miss latency 1529system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.516836 # average StoreCondReq mshr miss latency 1530system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.516836 # average StoreCondReq mshr miss latency |
| 1546system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1547system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1531system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1532system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1548system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency 1549system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency 1550system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency 1551system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency | 1533system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency 1534system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency 1535system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency 1536system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency |
| 1552system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1553system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1554system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1555system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1556system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1557system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1558system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1559system.cpu1.dtb.inst_hits 0 # ITB inst hits 1560system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1537system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1538system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1539system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1540system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1541system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1542system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1543system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1544system.cpu1.dtb.inst_hits 0 # ITB inst hits 1545system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1561system.cpu1.dtb.read_hits 5708064 # DTB read hits 1562system.cpu1.dtb.read_misses 3582 # DTB read misses 1563system.cpu1.dtb.write_hits 3874465 # DTB write hits 1564system.cpu1.dtb.write_misses 647 # DTB write misses | 1546system.cpu1.dtb.read_hits 5706417 # DTB read hits 1547system.cpu1.dtb.read_misses 3586 # DTB read misses 1548system.cpu1.dtb.write_hits 3873093 # DTB write hits 1549system.cpu1.dtb.write_misses 644 # DTB write misses |
| 1565system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1566system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1567system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1568system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1569system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB 1570system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1550system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1551system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1552system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1553system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1554system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB 1555system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1571system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch | 1556system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch |
| 1572system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1573system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions | 1557system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1558system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions |
| 1574system.cpu1.dtb.read_accesses 5711646 # DTB read accesses 1575system.cpu1.dtb.write_accesses 3875112 # DTB write accesses | 1559system.cpu1.dtb.read_accesses 5710003 # DTB read accesses 1560system.cpu1.dtb.write_accesses 3873737 # DTB write accesses |
| 1576system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1561system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1577system.cpu1.dtb.hits 9582529 # DTB hits 1578system.cpu1.dtb.misses 4229 # DTB misses 1579system.cpu1.dtb.accesses 9586758 # DTB accesses 1580system.cpu1.itb.inst_hits 19382020 # ITB inst hits | 1562system.cpu1.dtb.hits 9579510 # DTB hits 1563system.cpu1.dtb.misses 4230 # DTB misses 1564system.cpu1.dtb.accesses 9583740 # DTB accesses 1565system.cpu1.itb.inst_hits 19379017 # ITB inst hits |
| 1581system.cpu1.itb.inst_misses 2171 # ITB inst misses 1582system.cpu1.itb.read_hits 0 # DTB read hits 1583system.cpu1.itb.read_misses 0 # DTB read misses 1584system.cpu1.itb.write_hits 0 # DTB write hits 1585system.cpu1.itb.write_misses 0 # DTB write misses 1586system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1587system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1588system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1589system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1590system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 1591system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1592system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1593system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1594system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1595system.cpu1.itb.read_accesses 0 # DTB read accesses 1596system.cpu1.itb.write_accesses 0 # DTB write accesses | 1566system.cpu1.itb.inst_misses 2171 # ITB inst misses 1567system.cpu1.itb.read_hits 0 # DTB read hits 1568system.cpu1.itb.read_misses 0 # DTB read misses 1569system.cpu1.itb.write_hits 0 # DTB write hits 1570system.cpu1.itb.write_misses 0 # DTB write misses 1571system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1572system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1573system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1574system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1575system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 1576system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1577system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1578system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1579system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1580system.cpu1.itb.read_accesses 0 # DTB read accesses 1581system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1597system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses 1598system.cpu1.itb.hits 19382020 # DTB hits | 1582system.cpu1.itb.inst_accesses 19381188 # ITB inst accesses 1583system.cpu1.itb.hits 19379017 # DTB hits |
| 1599system.cpu1.itb.misses 2171 # DTB misses | 1584system.cpu1.itb.misses 2171 # DTB misses |
| 1600system.cpu1.itb.accesses 19384191 # DTB accesses 1601system.cpu1.numCycles 2390063941 # number of cpu cycles simulated | 1585system.cpu1.itb.accesses 19381188 # DTB accesses 1586system.cpu1.numCycles 2390136116 # number of cpu cycles simulated |
| 1602system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1603system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1587system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1588system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1604system.cpu1.committedInsts 18801432 # Number of instructions committed 1605system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed 1606system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses | 1589system.cpu1.committedInsts 18798461 # Number of instructions committed 1590system.cpu1.committedOps 24902767 # Number of ops (including micro ops) committed 1591system.cpu1.num_int_alu_accesses 22266699 # Number of integer alu accesses |
| 1607system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses | 1592system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses |
| 1608system.cpu1.num_func_calls 796781 # number of times a function call or return occured 1609system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls 1610system.cpu1.num_int_insts 22272671 # number of integer instructions | 1593system.cpu1.num_func_calls 796691 # number of times a function call or return occured 1594system.cpu1.num_conditional_control_insts 2514546 # number of instructions that are conditional controls 1595system.cpu1.num_int_insts 22266699 # number of integer instructions |
| 1611system.cpu1.num_fp_insts 6793 # number of float instructions | 1596system.cpu1.num_fp_insts 6793 # number of float instructions |
| 1612system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read 1613system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written | 1597system.cpu1.num_int_register_reads 130767489 # number of times the integer registers were read 1598system.cpu1.num_int_register_writes 23318960 # number of times the integer registers were written |
| 1614system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1615system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written | 1599system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1600system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written |
| 1616system.cpu1.num_mem_refs 10017952 # number of memory refs 1617system.cpu1.num_load_insts 5984754 # Number of load instructions 1618system.cpu1.num_store_insts 4033198 # Number of store instructions 1619system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles 1620system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles 1621system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles 1622system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles | 1601system.cpu1.num_mem_refs 10014870 # number of memory refs 1602system.cpu1.num_load_insts 5983067 # Number of load instructions 1603system.cpu1.num_store_insts 4031803 # Number of store instructions 1604system.cpu1.num_idle_cycles 1969216562.004314 # Number of idle cycles 1605system.cpu1.num_busy_cycles 420919553.995686 # Number of busy cycles 1606system.cpu1.not_idle_fraction 0.176107 # Percentage of non-idle cycles 1607system.cpu1.idle_fraction 0.823893 # Percentage of idle cycles |
| 1623system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1608system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1624system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed 1625system.cpu1.icache.tags.replacements 376793 # number of replacements 1626system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use 1627system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks. 1628system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks. 1629system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks. 1630system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit. 1631system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor 1632system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy 1633system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy 1634system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits 1635system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits 1636system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits 1637system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits 1638system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits 1639system.cpu1.icache.overall_hits::total 19004711 # number of overall hits 1640system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses 1641system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses 1642system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses 1643system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses 1644system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses 1645system.cpu1.icache.overall_misses::total 377305 # number of overall misses 1646system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles 1647system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles 1648system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles 1649system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles 1650system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles 1651system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles 1652system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses) 1653system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses) 1654system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses 1655system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses 1656system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses 1657system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses 1658system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses 1659system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses 1660system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses 1661system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses 1662system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses 1663system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses 1664system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency 1665system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency 1666system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency 1667system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency 1668system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency 1669system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency | 1609system.cpu1.kern.inst.quiesce 39069 # number of quiesce instructions executed 1610system.cpu1.icache.tags.replacements 376769 # number of replacements 1611system.cpu1.icache.tags.tagsinuse 474.890792 # Cycle average of tags in use 1612system.cpu1.icache.tags.total_refs 19001732 # Total number of references to valid blocks. 1613system.cpu1.icache.tags.sampled_refs 377281 # Sample count of references to valid blocks. 1614system.cpu1.icache.tags.avg_refs 50.364932 # Average number of references to valid blocks. 1615system.cpu1.icache.tags.warmup_cycle 327211938000 # Cycle when the warmup percentage was hit. 1616system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.890792 # Average occupied blocks per requestor 1617system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927521 # Average percentage of cache occupancy 1618system.cpu1.icache.tags.occ_percent::total 0.927521 # Average percentage of cache occupancy 1619system.cpu1.icache.ReadReq_hits::cpu1.inst 19001732 # number of ReadReq hits 1620system.cpu1.icache.ReadReq_hits::total 19001732 # number of ReadReq hits 1621system.cpu1.icache.demand_hits::cpu1.inst 19001732 # number of demand (read+write) hits 1622system.cpu1.icache.demand_hits::total 19001732 # number of demand (read+write) hits 1623system.cpu1.icache.overall_hits::cpu1.inst 19001732 # number of overall hits 1624system.cpu1.icache.overall_hits::total 19001732 # number of overall hits 1625system.cpu1.icache.ReadReq_misses::cpu1.inst 377281 # number of ReadReq misses 1626system.cpu1.icache.ReadReq_misses::total 377281 # number of ReadReq misses 1627system.cpu1.icache.demand_misses::cpu1.inst 377281 # number of demand (read+write) misses 1628system.cpu1.icache.demand_misses::total 377281 # number of demand (read+write) misses 1629system.cpu1.icache.overall_misses::cpu1.inst 377281 # number of overall misses 1630system.cpu1.icache.overall_misses::total 377281 # number of overall misses 1631system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5163865212 # number of ReadReq miss cycles 1632system.cpu1.icache.ReadReq_miss_latency::total 5163865212 # number of ReadReq miss cycles 1633system.cpu1.icache.demand_miss_latency::cpu1.inst 5163865212 # number of demand (read+write) miss cycles 1634system.cpu1.icache.demand_miss_latency::total 5163865212 # number of demand (read+write) miss cycles 1635system.cpu1.icache.overall_miss_latency::cpu1.inst 5163865212 # number of overall miss cycles 1636system.cpu1.icache.overall_miss_latency::total 5163865212 # number of overall miss cycles 1637system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379013 # number of ReadReq accesses(hits+misses) 1638system.cpu1.icache.ReadReq_accesses::total 19379013 # number of ReadReq accesses(hits+misses) 1639system.cpu1.icache.demand_accesses::cpu1.inst 19379013 # number of demand (read+write) accesses 1640system.cpu1.icache.demand_accesses::total 19379013 # number of demand (read+write) accesses 1641system.cpu1.icache.overall_accesses::cpu1.inst 19379013 # number of overall (read+write) accesses 1642system.cpu1.icache.overall_accesses::total 19379013 # number of overall (read+write) accesses 1643system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019469 # miss rate for ReadReq accesses 1644system.cpu1.icache.ReadReq_miss_rate::total 0.019469 # miss rate for ReadReq accesses 1645system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019469 # miss rate for demand accesses 1646system.cpu1.icache.demand_miss_rate::total 0.019469 # miss rate for demand accesses 1647system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019469 # miss rate for overall accesses 1648system.cpu1.icache.overall_miss_rate::total 0.019469 # miss rate for overall accesses 1649system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13687.053448 # average ReadReq miss latency 1650system.cpu1.icache.ReadReq_avg_miss_latency::total 13687.053448 # average ReadReq miss latency 1651system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency 1652system.cpu1.icache.demand_avg_miss_latency::total 13687.053448 # average overall miss latency 1653system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency 1654system.cpu1.icache.overall_avg_miss_latency::total 13687.053448 # average overall miss latency |
| 1670system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1671system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1672system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1673system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1674system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1675system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1676system.cpu1.icache.fast_writes 0 # number of fast writes performed 1677system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1655system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1656system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1657system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1658system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1659system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1660system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1661system.cpu1.icache.fast_writes 0 # number of fast writes performed 1662system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1678system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses 1679system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses 1680system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses 1681system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses 1682system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses 1683system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses 1684system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles 1685system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles 1686system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles 1687system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles 1688system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles 1689system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles 1690system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles 1691system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles 1692system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles 1693system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles 1694system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses 1695system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses 1696system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses 1697system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses 1698system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses 1699system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses 1700system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency 1701system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency 1702system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency 1703system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency 1704system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency 1705system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency | 1663system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377281 # number of ReadReq MSHR misses 1664system.cpu1.icache.ReadReq_mshr_misses::total 377281 # number of ReadReq MSHR misses 1665system.cpu1.icache.demand_mshr_misses::cpu1.inst 377281 # number of demand (read+write) MSHR misses 1666system.cpu1.icache.demand_mshr_misses::total 377281 # number of demand (read+write) MSHR misses 1667system.cpu1.icache.overall_mshr_misses::cpu1.inst 377281 # number of overall MSHR misses 1668system.cpu1.icache.overall_mshr_misses::total 377281 # number of overall MSHR misses 1669system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4407732788 # number of ReadReq MSHR miss cycles 1670system.cpu1.icache.ReadReq_mshr_miss_latency::total 4407732788 # number of ReadReq MSHR miss cycles 1671system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4407732788 # number of demand (read+write) MSHR miss cycles 1672system.cpu1.icache.demand_mshr_miss_latency::total 4407732788 # number of demand (read+write) MSHR miss cycles 1673system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4407732788 # number of overall MSHR miss cycles 1674system.cpu1.icache.overall_mshr_miss_latency::total 4407732788 # number of overall MSHR miss cycles 1675system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6483750 # number of ReadReq MSHR uncacheable cycles 1676system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6483750 # number of ReadReq MSHR uncacheable cycles 1677system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6483750 # number of overall MSHR uncacheable cycles 1678system.cpu1.icache.overall_mshr_uncacheable_latency::total 6483750 # number of overall MSHR uncacheable cycles 1679system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for ReadReq accesses 1680system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019469 # mshr miss rate for ReadReq accesses 1681system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for demand accesses 1682system.cpu1.icache.demand_mshr_miss_rate::total 0.019469 # mshr miss rate for demand accesses 1683system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for overall accesses 1684system.cpu1.icache.overall_mshr_miss_rate::total 0.019469 # mshr miss rate for overall accesses 1685system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average ReadReq mshr miss latency 1686system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11682.890970 # average ReadReq mshr miss latency 1687system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency 1688system.cpu1.icache.demand_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency 1689system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency 1690system.cpu1.icache.overall_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency |
| 1706system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1707system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1708system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1709system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1710system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1691system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1692system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1693system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1694system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1695system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1711system.cpu1.dcache.tags.replacements 220883 # number of replacements 1712system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use 1713system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks. 1714system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks. 1715system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks. 1716system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit. 1717system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor 1718system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of cache occupancy 1719system.cpu1.dcache.tags.occ_percent::total 0.920854 # Average percentage of cache occupancy 1720system.cpu1.dcache.ReadReq_hits::cpu1.data 4390672 # number of ReadReq hits 1721system.cpu1.dcache.ReadReq_hits::total 4390672 # number of ReadReq hits 1722system.cpu1.dcache.WriteReq_hits::cpu1.data 3674527 # number of WriteReq hits 1723system.cpu1.dcache.WriteReq_hits::total 3674527 # number of WriteReq hits 1724system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73485 # number of LoadLockedReq hits 1725system.cpu1.dcache.LoadLockedReq_hits::total 73485 # number of LoadLockedReq hits 1726system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73732 # number of StoreCondReq hits 1727system.cpu1.dcache.StoreCondReq_hits::total 73732 # number of StoreCondReq hits 1728system.cpu1.dcache.demand_hits::cpu1.data 8065199 # number of demand (read+write) hits 1729system.cpu1.dcache.demand_hits::total 8065199 # number of demand (read+write) hits 1730system.cpu1.dcache.overall_hits::cpu1.data 8065199 # number of overall hits 1731system.cpu1.dcache.overall_hits::total 8065199 # number of overall hits 1732system.cpu1.dcache.ReadReq_misses::cpu1.data 134090 # number of ReadReq misses 1733system.cpu1.dcache.ReadReq_misses::total 134090 # number of ReadReq misses 1734system.cpu1.dcache.WriteReq_misses::cpu1.data 112827 # number of WriteReq misses 1735system.cpu1.dcache.WriteReq_misses::total 112827 # number of WriteReq misses 1736system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9762 # number of LoadLockedReq misses 1737system.cpu1.dcache.LoadLockedReq_misses::total 9762 # number of LoadLockedReq misses 1738system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9429 # number of StoreCondReq misses 1739system.cpu1.dcache.StoreCondReq_misses::total 9429 # number of StoreCondReq misses 1740system.cpu1.dcache.demand_misses::cpu1.data 246917 # number of demand (read+write) misses 1741system.cpu1.dcache.demand_misses::total 246917 # number of demand (read+write) misses 1742system.cpu1.dcache.overall_misses::cpu1.data 246917 # number of overall misses 1743system.cpu1.dcache.overall_misses::total 246917 # number of overall misses 1744system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1656976729 # number of ReadReq miss cycles 1745system.cpu1.dcache.ReadReq_miss_latency::total 1656976729 # number of ReadReq miss cycles 1746system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4353399476 # number of WriteReq miss cycles 1747system.cpu1.dcache.WriteReq_miss_latency::total 4353399476 # number of WriteReq miss cycles 1748system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77544499 # number of LoadLockedReq miss cycles 1749system.cpu1.dcache.LoadLockedReq_miss_latency::total 77544499 # number of LoadLockedReq miss cycles 1750system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49349978 # number of StoreCondReq miss cycles 1751system.cpu1.dcache.StoreCondReq_miss_latency::total 49349978 # number of StoreCondReq miss cycles 1752system.cpu1.dcache.demand_miss_latency::cpu1.data 6010376205 # number of demand (read+write) miss cycles 1753system.cpu1.dcache.demand_miss_latency::total 6010376205 # number of demand (read+write) miss cycles 1754system.cpu1.dcache.overall_miss_latency::cpu1.data 6010376205 # number of overall miss cycles 1755system.cpu1.dcache.overall_miss_latency::total 6010376205 # number of overall miss cycles 1756system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524762 # number of ReadReq accesses(hits+misses) 1757system.cpu1.dcache.ReadReq_accesses::total 4524762 # number of ReadReq accesses(hits+misses) 1758system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787354 # number of WriteReq accesses(hits+misses) 1759system.cpu1.dcache.WriteReq_accesses::total 3787354 # number of WriteReq accesses(hits+misses) 1760system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83247 # number of LoadLockedReq accesses(hits+misses) 1761system.cpu1.dcache.LoadLockedReq_accesses::total 83247 # number of LoadLockedReq accesses(hits+misses) 1762system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83161 # number of StoreCondReq accesses(hits+misses) 1763system.cpu1.dcache.StoreCondReq_accesses::total 83161 # number of StoreCondReq accesses(hits+misses) 1764system.cpu1.dcache.demand_accesses::cpu1.data 8312116 # number of demand (read+write) accesses 1765system.cpu1.dcache.demand_accesses::total 8312116 # number of demand (read+write) accesses 1766system.cpu1.dcache.overall_accesses::cpu1.data 8312116 # number of overall (read+write) accesses 1767system.cpu1.dcache.overall_accesses::total 8312116 # number of overall (read+write) accesses 1768system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029635 # miss rate for ReadReq accesses 1769system.cpu1.dcache.ReadReq_miss_rate::total 0.029635 # miss rate for ReadReq accesses 1770system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029790 # miss rate for WriteReq accesses 1771system.cpu1.dcache.WriteReq_miss_rate::total 0.029790 # miss rate for WriteReq accesses 1772system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117265 # miss rate for LoadLockedReq accesses 1773system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117265 # miss rate for LoadLockedReq accesses 1774system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113382 # miss rate for StoreCondReq accesses 1775system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113382 # miss rate for StoreCondReq accesses 1776system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029706 # miss rate for demand accesses 1777system.cpu1.dcache.demand_miss_rate::total 0.029706 # miss rate for demand accesses 1778system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029706 # miss rate for overall accesses 1779system.cpu1.dcache.overall_miss_rate::total 0.029706 # miss rate for overall accesses 1780system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12357.198367 # average ReadReq miss latency 1781system.cpu1.dcache.ReadReq_avg_miss_latency::total 12357.198367 # average ReadReq miss latency 1782system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38584.731279 # average WriteReq miss latency 1783system.cpu1.dcache.WriteReq_avg_miss_latency::total 38584.731279 # average WriteReq miss latency 1784system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7943.505327 # average LoadLockedReq miss latency 1785system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7943.505327 # average LoadLockedReq miss latency 1786system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5233.850673 # average StoreCondReq miss latency 1787system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5233.850673 # average StoreCondReq miss latency 1788system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency 1789system.cpu1.dcache.demand_avg_miss_latency::total 24341.686498 # average overall miss latency 1790system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency 1791system.cpu1.dcache.overall_avg_miss_latency::total 24341.686498 # average overall miss latency | 1696system.cpu1.dcache.tags.replacements 220436 # number of replacements 1697system.cpu1.dcache.tags.tagsinuse 471.379597 # Cycle average of tags in use 1698system.cpu1.dcache.tags.total_refs 8230755 # Total number of references to valid blocks. 1699system.cpu1.dcache.tags.sampled_refs 220801 # Sample count of references to valid blocks. 1700system.cpu1.dcache.tags.avg_refs 37.276801 # Average number of references to valid blocks. 1701system.cpu1.dcache.tags.warmup_cycle 106418022500 # Cycle when the warmup percentage was hit. 1702system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.379597 # Average occupied blocks per requestor 1703system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920663 # Average percentage of cache occupancy 1704system.cpu1.dcache.tags.occ_percent::total 0.920663 # Average percentage of cache occupancy 1705system.cpu1.dcache.ReadReq_hits::cpu1.data 4389351 # number of ReadReq hits 1706system.cpu1.dcache.ReadReq_hits::total 4389351 # number of ReadReq hits 1707system.cpu1.dcache.WriteReq_hits::cpu1.data 3673214 # number of WriteReq hits 1708system.cpu1.dcache.WriteReq_hits::total 3673214 # number of WriteReq hits 1709system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73456 # number of LoadLockedReq hits 1710system.cpu1.dcache.LoadLockedReq_hits::total 73456 # number of LoadLockedReq hits 1711system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73714 # number of StoreCondReq hits 1712system.cpu1.dcache.StoreCondReq_hits::total 73714 # number of StoreCondReq hits 1713system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits 1714system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits 1715system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits 1716system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits 1717system.cpu1.dcache.ReadReq_misses::cpu1.data 133803 # number of ReadReq misses 1718system.cpu1.dcache.ReadReq_misses::total 133803 # number of ReadReq misses 1719system.cpu1.dcache.WriteReq_misses::cpu1.data 112797 # number of WriteReq misses 1720system.cpu1.dcache.WriteReq_misses::total 112797 # number of WriteReq misses 1721system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9752 # number of LoadLockedReq misses 1722system.cpu1.dcache.LoadLockedReq_misses::total 9752 # number of LoadLockedReq misses 1723system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9418 # number of StoreCondReq misses 1724system.cpu1.dcache.StoreCondReq_misses::total 9418 # number of StoreCondReq misses 1725system.cpu1.dcache.demand_misses::cpu1.data 246600 # number of demand (read+write) misses 1726system.cpu1.dcache.demand_misses::total 246600 # number of demand (read+write) misses 1727system.cpu1.dcache.overall_misses::cpu1.data 246600 # number of overall misses 1728system.cpu1.dcache.overall_misses::total 246600 # number of overall misses 1729system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1647983739 # number of ReadReq miss cycles 1730system.cpu1.dcache.ReadReq_miss_latency::total 1647983739 # number of ReadReq miss cycles 1731system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4345457226 # number of WriteReq miss cycles 1732system.cpu1.dcache.WriteReq_miss_latency::total 4345457226 # number of WriteReq miss cycles 1733system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77502998 # number of LoadLockedReq miss cycles 1734system.cpu1.dcache.LoadLockedReq_miss_latency::total 77502998 # number of LoadLockedReq miss cycles 1735system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49351478 # number of StoreCondReq miss cycles 1736system.cpu1.dcache.StoreCondReq_miss_latency::total 49351478 # number of StoreCondReq miss cycles 1737system.cpu1.dcache.demand_miss_latency::cpu1.data 5993440965 # number of demand (read+write) miss cycles 1738system.cpu1.dcache.demand_miss_latency::total 5993440965 # number of demand (read+write) miss cycles 1739system.cpu1.dcache.overall_miss_latency::cpu1.data 5993440965 # number of overall miss cycles 1740system.cpu1.dcache.overall_miss_latency::total 5993440965 # number of overall miss cycles 1741system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523154 # number of ReadReq accesses(hits+misses) 1742system.cpu1.dcache.ReadReq_accesses::total 4523154 # number of ReadReq accesses(hits+misses) 1743system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786011 # number of WriteReq accesses(hits+misses) 1744system.cpu1.dcache.WriteReq_accesses::total 3786011 # number of WriteReq accesses(hits+misses) 1745system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83208 # number of LoadLockedReq accesses(hits+misses) 1746system.cpu1.dcache.LoadLockedReq_accesses::total 83208 # number of LoadLockedReq accesses(hits+misses) 1747system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83132 # number of StoreCondReq accesses(hits+misses) 1748system.cpu1.dcache.StoreCondReq_accesses::total 83132 # number of StoreCondReq accesses(hits+misses) 1749system.cpu1.dcache.demand_accesses::cpu1.data 8309165 # number of demand (read+write) accesses 1750system.cpu1.dcache.demand_accesses::total 8309165 # number of demand (read+write) accesses 1751system.cpu1.dcache.overall_accesses::cpu1.data 8309165 # number of overall (read+write) accesses 1752system.cpu1.dcache.overall_accesses::total 8309165 # number of overall (read+write) accesses 1753system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029582 # miss rate for ReadReq accesses 1754system.cpu1.dcache.ReadReq_miss_rate::total 0.029582 # miss rate for ReadReq accesses 1755system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029793 # miss rate for WriteReq accesses 1756system.cpu1.dcache.WriteReq_miss_rate::total 0.029793 # miss rate for WriteReq accesses 1757system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117200 # miss rate for LoadLockedReq accesses 1758system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117200 # miss rate for LoadLockedReq accesses 1759system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113290 # miss rate for StoreCondReq accesses 1760system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113290 # miss rate for StoreCondReq accesses 1761system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029678 # miss rate for demand accesses 1762system.cpu1.dcache.demand_miss_rate::total 0.029678 # miss rate for demand accesses 1763system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029678 # miss rate for overall accesses 1764system.cpu1.dcache.overall_miss_rate::total 0.029678 # miss rate for overall accesses 1765system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12316.493195 # average ReadReq miss latency 1766system.cpu1.dcache.ReadReq_avg_miss_latency::total 12316.493195 # average ReadReq miss latency 1767system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38524.581558 # average WriteReq miss latency 1768system.cpu1.dcache.WriteReq_avg_miss_latency::total 38524.581558 # average WriteReq miss latency 1769system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7947.395201 # average LoadLockedReq miss latency 1770system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7947.395201 # average LoadLockedReq miss latency 1771system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5240.122956 # average StoreCondReq miss latency 1772system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5240.122956 # average StoreCondReq miss latency 1773system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24304.302372 # average overall miss latency 1774system.cpu1.dcache.demand_avg_miss_latency::total 24304.302372 # average overall miss latency 1775system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24304.302372 # average overall miss latency 1776system.cpu1.dcache.overall_avg_miss_latency::total 24304.302372 # average overall miss latency |
| 1792system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1793system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1794system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1795system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1796system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1797system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1798system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1799system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1777system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1778system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1779system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1780system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1781system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1782system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1783system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1784system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1800system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks 1801system.cpu1.dcache.writebacks::total 200272 # number of writebacks 1802system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses 1803system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses 1804system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses 1805system.cpu1.dcache.WriteReq_mshr_misses::total 112827 # number of WriteReq MSHR misses 1806system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9762 # number of LoadLockedReq MSHR misses 1807system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9762 # number of LoadLockedReq MSHR misses 1808system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9426 # number of StoreCondReq MSHR misses 1809system.cpu1.dcache.StoreCondReq_mshr_misses::total 9426 # number of StoreCondReq MSHR misses 1810system.cpu1.dcache.demand_mshr_misses::cpu1.data 246917 # number of demand (read+write) MSHR misses 1811system.cpu1.dcache.demand_mshr_misses::total 246917 # number of demand (read+write) MSHR misses 1812system.cpu1.dcache.overall_mshr_misses::cpu1.data 246917 # number of overall MSHR misses 1813system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses 1814system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles 1815system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles 1816system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles 1817system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles 1818system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles 1819system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles 1820system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles 1821system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles 1822system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1823system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1824system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles 1825system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles 1826system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles 1827system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles 1828system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles 1829system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles 1830system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles 1831system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles 1832system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles 1833system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles 1834system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses 1835system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses 1836system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses 1837system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses 1838system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses 1839system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses 1840system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses 1841system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses 1842system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses 1843system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses 1844system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses 1845system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses 1846system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency 1847system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency 1848system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency 1849system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency 1850system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency 1851system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency 1852system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency 1853system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency | 1785system.cpu1.dcache.writebacks::writebacks 199592 # number of writebacks 1786system.cpu1.dcache.writebacks::total 199592 # number of writebacks 1787system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133803 # number of ReadReq MSHR misses 1788system.cpu1.dcache.ReadReq_mshr_misses::total 133803 # number of ReadReq MSHR misses 1789system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112797 # number of WriteReq MSHR misses 1790system.cpu1.dcache.WriteReq_mshr_misses::total 112797 # number of WriteReq MSHR misses 1791system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9752 # number of LoadLockedReq MSHR misses 1792system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9752 # number of LoadLockedReq MSHR misses 1793system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9415 # number of StoreCondReq MSHR misses 1794system.cpu1.dcache.StoreCondReq_mshr_misses::total 9415 # number of StoreCondReq MSHR misses 1795system.cpu1.dcache.demand_mshr_misses::cpu1.data 246600 # number of demand (read+write) MSHR misses 1796system.cpu1.dcache.demand_mshr_misses::total 246600 # number of demand (read+write) MSHR misses 1797system.cpu1.dcache.overall_mshr_misses::cpu1.data 246600 # number of overall MSHR misses 1798system.cpu1.dcache.overall_mshr_misses::total 246600 # number of overall MSHR misses 1799system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1380025261 # number of ReadReq MSHR miss cycles 1800system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1380025261 # number of ReadReq MSHR miss cycles 1801system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4109897774 # number of WriteReq MSHR miss cycles 1802system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4109897774 # number of WriteReq MSHR miss cycles 1803system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 57992002 # number of LoadLockedReq MSHR miss cycles 1804system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 57992002 # number of LoadLockedReq MSHR miss cycles 1805system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30524522 # number of StoreCondReq MSHR miss cycles 1806system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30524522 # number of StoreCondReq MSHR miss cycles 1807system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles 1808system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1809system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5489923035 # number of demand (read+write) MSHR miss cycles 1810system.cpu1.dcache.demand_mshr_miss_latency::total 5489923035 # number of demand (read+write) MSHR miss cycles 1811system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5489923035 # number of overall MSHR miss cycles 1812system.cpu1.dcache.overall_mshr_miss_latency::total 5489923035 # number of overall MSHR miss cycles 1813system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387761500 # number of ReadReq MSHR uncacheable cycles 1814system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387761500 # number of ReadReq MSHR uncacheable cycles 1815system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531061000 # number of WriteReq MSHR uncacheable cycles 1816system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531061000 # number of WriteReq MSHR uncacheable cycles 1817system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918822500 # number of overall MSHR uncacheable cycles 1818system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918822500 # number of overall MSHR uncacheable cycles 1819system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029582 # mshr miss rate for ReadReq accesses 1820system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029582 # mshr miss rate for ReadReq accesses 1821system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029793 # mshr miss rate for WriteReq accesses 1822system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029793 # mshr miss rate for WriteReq accesses 1823system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117200 # mshr miss rate for LoadLockedReq accesses 1824system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117200 # mshr miss rate for LoadLockedReq accesses 1825system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113254 # mshr miss rate for StoreCondReq accesses 1826system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113254 # mshr miss rate for StoreCondReq accesses 1827system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for demand accesses 1828system.cpu1.dcache.demand_mshr_miss_rate::total 0.029678 # mshr miss rate for demand accesses 1829system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for overall accesses 1830system.cpu1.dcache.overall_mshr_miss_rate::total 0.029678 # mshr miss rate for overall accesses 1831system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10313.858890 # average ReadReq mshr miss latency 1832system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10313.858890 # average ReadReq mshr miss latency 1833system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36436.233003 # average WriteReq mshr miss latency 1834system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36436.233003 # average WriteReq mshr miss latency 1835system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5946.677810 # average LoadLockedReq mshr miss latency 1836system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5946.677810 # average LoadLockedReq mshr miss latency 1837system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3242.115985 # average StoreCondReq mshr miss latency 1838system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3242.115985 # average StoreCondReq mshr miss latency |
| 1854system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1855system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1839system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1840system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1856system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency 1857system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency 1858system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency 1859system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency | 1841system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency 1842system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency 1843system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency 1844system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency |
| 1860system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1861system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1862system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1863system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1864system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1865system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1866system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1867system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1873system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1874system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1875system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1876system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1877system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1878system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1879system.iocache.fast_writes 0 # number of fast writes performed 1880system.iocache.cache_copies 0 # number of cache copies performed | 1845system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1846system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1847system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1848system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1849system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1850system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1851system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1852system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1858system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1859system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1860system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1861system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1862system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1863system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1864system.iocache.fast_writes 0 # number of fast writes performed 1865system.iocache.cache_copies 0 # number of cache copies performed |
| 1881system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles 1882system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles 1883system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles 1884system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles | 1866system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651879453001 # number of ReadReq MSHR uncacheable cycles 1867system.iocache.ReadReq_mshr_uncacheable_latency::total 651879453001 # number of ReadReq MSHR uncacheable cycles 1868system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651879453001 # number of overall MSHR uncacheable cycles 1869system.iocache.overall_mshr_uncacheable_latency::total 651879453001 # number of overall MSHR uncacheable cycles |
| 1885system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1886system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1887system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1888system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1889system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1890 1891---------- End Simulation Statistics ---------- | 1870system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1871system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1872system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1873system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1874system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1875 1876---------- End Simulation Statistics ---------- |