| stats.txt (9838:43d22d746e7a) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.194884 # Number of seconds simulated 4sim_ticks 1194883580500 # Number of ticks simulated 5final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.195756 # Number of seconds simulated 4sim_ticks 1195756323500 # Number of ticks simulated 5final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 298011 # Simulator instruction rate (inst/s) 8host_op_rate 379758 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5802481089 # Simulator tick rate (ticks/s) 10host_mem_usage 399660 # Number of bytes of host memory used 11host_seconds 205.93 # Real time elapsed on the host 12sim_insts 61368273 # Number of instructions simulated 13sim_ops 78202205 # Number of ops (including micro ops) simulated | 7host_inst_rate 469394 # Simulator instruction rate (inst/s) 8host_op_rate 598174 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9145402965 # Simulator tick rate (ticks/s) 10host_mem_usage 398732 # Number of bytes of host memory used 11host_seconds 130.75 # Real time elapsed on the host 12sim_insts 61373013 # Number of instructions simulated 13sim_ops 78210923 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory | 20system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 27system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory | 29system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory |
| 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory | 36system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory |
| 40system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 40system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 42system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s) | 42system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s) |
| 44system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s) |
| 57system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) | 57system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s) | 58system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s) |
| 61system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) |
| 63system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s) |
| 65system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) | 65system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller 70system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller 71system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 72system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 73system.physmem.bytesRead 425896384 # Total number of bytes read from memory 74system.physmem.bytesWritten 52573888 # Total number of bytes written to memory 75system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize() 76system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize() 77system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q 78system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed 79system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis 94system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis 95system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis 110system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis 111system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 112system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 113system.physmem.totGap 1194879167500 # Total gap between requests 114system.physmem.readPktSize::0 0 # Categorize read packet sizes 115system.physmem.readPktSize::1 0 # Categorize read packet sizes 116system.physmem.readPktSize::2 6825 # Categorize read packet sizes 117system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 118system.physmem.readPktSize::4 0 # Categorize read packet sizes 119system.physmem.readPktSize::5 0 # Categorize read packet sizes 120system.physmem.readPktSize::6 159742 # Categorize read packet sizes 121system.physmem.writePktSize::0 0 # Categorize write packet sizes 122system.physmem.writePktSize::1 0 # Categorize write packet sizes 123system.physmem.writePktSize::2 756836 # Categorize write packet sizes 124system.physmem.writePktSize::3 0 # Categorize write packet sizes 125system.physmem.writePktSize::4 0 # Categorize write packet sizes 126system.physmem.writePktSize::5 0 # Categorize write packet sizes 127system.physmem.writePktSize::6 64631 # Categorize write packet sizes 128system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see | 66system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654771 # Number of read requests accepted 70system.physmem.writeReqs 821574 # Number of write requests accepted 71system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue 72system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue 73system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM 74system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue 75system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM 76system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side 77system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side 78system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue 79system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one 80system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write 81system.physmem.perBankRdBursts::0 415729 # Per bank write bursts 82system.physmem.perBankRdBursts::1 415559 # Per bank write bursts 83system.physmem.perBankRdBursts::2 414962 # Per bank write bursts 84system.physmem.perBankRdBursts::3 415336 # Per bank write bursts 85system.physmem.perBankRdBursts::4 422370 # Per bank write bursts 86system.physmem.perBankRdBursts::5 415375 # Per bank write bursts 87system.physmem.perBankRdBursts::6 415451 # Per bank write bursts 88system.physmem.perBankRdBursts::7 415289 # Per bank write bursts 89system.physmem.perBankRdBursts::8 415350 # Per bank write bursts 90system.physmem.perBankRdBursts::9 415631 # Per bank write bursts 91system.physmem.perBankRdBursts::10 415265 # Per bank write bursts 92system.physmem.perBankRdBursts::11 414898 # Per bank write bursts 93system.physmem.perBankRdBursts::12 415464 # Per bank write bursts 94system.physmem.perBankRdBursts::13 416088 # Per bank write bursts 95system.physmem.perBankRdBursts::14 415829 # Per bank write bursts 96system.physmem.perBankRdBursts::15 415792 # Per bank write bursts 97system.physmem.perBankWrBursts::0 7314 # Per bank write bursts 98system.physmem.perBankWrBursts::1 7200 # Per bank write bursts 99system.physmem.perBankWrBursts::2 6696 # Per bank write bursts 100system.physmem.perBankWrBursts::3 6864 # Per bank write bursts 101system.physmem.perBankWrBursts::4 7395 # Per bank write bursts 102system.physmem.perBankWrBursts::5 6961 # Per bank write bursts 103system.physmem.perBankWrBursts::6 7170 # Per bank write bursts 104system.physmem.perBankWrBursts::7 6990 # Per bank write bursts 105system.physmem.perBankWrBursts::8 6985 # Per bank write bursts 106system.physmem.perBankWrBursts::9 7249 # Per bank write bursts 107system.physmem.perBankWrBursts::10 6972 # Per bank write bursts 108system.physmem.perBankWrBursts::11 6687 # Per bank write bursts 109system.physmem.perBankWrBursts::12 7224 # Per bank write bursts 110system.physmem.perBankWrBursts::13 7527 # Per bank write bursts 111system.physmem.perBankWrBursts::14 7429 # Per bank write bursts 112system.physmem.perBankWrBursts::15 7403 # Per bank write bursts 113system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 114system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 115system.physmem.totGap 1195751937000 # Total gap between requests 116system.physmem.readPktSize::0 0 # Read request sizes (log2) 117system.physmem.readPktSize::1 0 # Read request sizes (log2) 118system.physmem.readPktSize::2 6825 # Read request sizes (log2) 119system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 120system.physmem.readPktSize::4 0 # Read request sizes (log2) 121system.physmem.readPktSize::5 0 # Read request sizes (log2) 122system.physmem.readPktSize::6 159882 # Read request sizes (log2) 123system.physmem.writePktSize::0 0 # Write request sizes (log2) 124system.physmem.writePktSize::1 0 # Write request sizes (log2) 125system.physmem.writePktSize::2 756836 # Write request sizes (log2) 126system.physmem.writePktSize::3 0 # Write request sizes (log2) 127system.physmem.writePktSize::4 0 # Write request sizes (log2) 128system.physmem.writePktSize::5 0 # Write request sizes (log2) 129system.physmem.writePktSize::6 64738 # Write request sizes (log2) 130system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see |
| 146system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 148system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 160system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see |
| 183system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see | 185system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see |
| 184system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see | 186system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see |
| 185system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 187system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 192system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation 447system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays 448system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests 449system.physmem.totBusLat 33270500000 # Total cycles spent in databus access 450system.physmem.totBankLat 8590725000 # Total cycles spent in bank access 451system.physmem.avgQLat 19013.79 # Average queueing delay per request 452system.physmem.avgBankLat 1291.04 # Average bank access latency per request 453system.physmem.avgBusLat 5000.00 # Average bus latency per request 454system.physmem.avgMemAccLat 25304.84 # Average memory access latency 455system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s 456system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s 457system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s 458system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s 459system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 460system.physmem.busUtil 3.13 # Data bus utilization in percentage 461system.physmem.avgRdQLen 0.14 # Average read queue length over time 462system.physmem.avgWrQLen 14.04 # Average write queue length over time 463system.physmem.readRowHits 6636405 # Number of row buffer hits during reads 464system.physmem.writeRowHits 97666 # Number of row buffer hits during writes 465system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads 466system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes 467system.physmem.avgGap 159826.58 # Average gap between requests | 194system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11008-11015 75 0.10% 84.01% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11264-11271 96 0.13% 84.13% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11520-11527 79 0.11% 84.24% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11776-11783 29 0.04% 84.28% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.28% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::11968-11975 1 0.00% 84.28% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::12032-12039 17 0.02% 84.30% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.30% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::12288-12295 176 0.23% 84.54% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.54% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.54% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::12544-12551 83 0.11% 84.65% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.65% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::12800-12807 12 0.02% 84.67% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.67% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::13056-13063 24 0.03% 84.70% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.70% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::13312-13319 154 0.21% 84.91% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::13440-13447 2 0.00% 84.91% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::13568-13575 30 0.04% 84.95% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::13632-13639 1 0.00% 84.95% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::13824-13831 90 0.12% 85.07% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::13952-13959 1 0.00% 85.08% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::14080-14087 16 0.02% 85.10% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::14336-14343 91 0.12% 85.22% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.22% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::14592-14599 14 0.02% 85.24% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.24% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::14720-14727 2 0.00% 85.24% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::14848-14855 154 0.21% 85.45% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::15104-15111 12 0.02% 85.46% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::15360-15367 76 0.10% 85.56% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::15616-15623 82 0.11% 85.67% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::15872-15879 16 0.02% 85.69% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.70% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::16128-16135 19 0.03% 85.72% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::16256-16263 4 0.01% 85.73% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::16384-16391 270 0.36% 86.09% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.09% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.09% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.12% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::16768-16775 2 0.00% 86.12% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::16896-16903 17 0.02% 86.14% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::17152-17159 84 0.11% 86.25% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.25% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::17408-17415 77 0.10% 86.36% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::17664-17671 12 0.02% 86.37% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::17792-17799 2 0.00% 86.38% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::17920-17927 156 0.21% 86.58% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::18176-18183 14 0.02% 86.60% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.60% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::18432-18439 92 0.12% 86.73% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::18496-18503 1 0.00% 86.73% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.73% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::18688-18695 12 0.02% 86.75% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::18944-18951 95 0.13% 86.87% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.87% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::19200-19207 30 0.04% 86.91% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::19264-19271 1 0.00% 86.92% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::19456-19463 153 0.20% 87.12% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::19712-19719 23 0.03% 87.15% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::19968-19975 10 0.01% 87.16% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.16% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::20224-20231 83 0.11% 87.28% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.28% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.28% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::20480-20487 180 0.24% 87.52% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::20544-20551 2 0.00% 87.52% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.52% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::20736-20743 18 0.02% 87.55% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.55% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.58% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::21184-21191 1 0.00% 87.58% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::21248-21255 75 0.10% 87.68% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.68% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::21504-21511 92 0.12% 87.81% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.90% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::21952-21959 1 0.00% 87.90% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::22016-22023 14 0.02% 87.92% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::22272-22279 35 0.05% 87.97% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.97% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::22528-22535 142 0.19% 88.16% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::22656-22663 1 0.00% 88.16% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::22784-22791 87 0.12% 88.28% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.28% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::22976-22983 1 0.00% 88.28% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.30% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::23296-23303 4 0.01% 88.30% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::23552-23559 166 0.22% 88.52% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.52% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::23808-23815 23 0.03% 88.55% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::24064-24071 66 0.09% 88.64% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.64% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::24320-24327 30 0.04% 88.68% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.69% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::24576-24583 147 0.20% 88.88% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::24832-24839 27 0.04% 88.92% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::25088-25095 68 0.09% 89.01% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::25344-25351 24 0.03% 89.04% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::25472-25479 1 0.00% 89.04% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::25600-25607 171 0.23% 89.27% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::25856-25863 5 0.01% 89.28% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::26112-26119 19 0.03% 89.30% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::26304-26311 1 0.00% 89.30% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::26368-26375 83 0.11% 89.41% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.41% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::26624-26631 139 0.19% 89.60% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::26880-26887 34 0.05% 89.64% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.66% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.66% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::27392-27399 75 0.10% 89.76% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.76% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.76% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::27584-27591 2 0.00% 89.77% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::27648-27655 88 0.12% 89.88% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::27776-27783 2 0.00% 89.89% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::27904-27911 75 0.10% 89.99% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::28096-28103 1 0.00% 89.99% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::28160-28167 24 0.03% 90.02% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::28352-28359 1 0.00% 90.02% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::28416-28423 21 0.03% 90.05% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::28672-28679 180 0.24% 90.29% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::28800-28807 2 0.00% 90.29% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::28928-28935 82 0.11% 90.40% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::29184-29191 10 0.01% 90.41% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::29440-29447 24 0.03% 90.45% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.45% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::29696-29703 153 0.20% 90.65% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.65% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::29952-29959 28 0.04% 90.69% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::30208-30215 92 0.12% 90.81% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::30336-30343 1 0.00% 90.81% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::30464-30471 14 0.02% 90.83% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::30720-30727 87 0.12% 90.95% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::30976-30983 12 0.02% 90.97% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::31104-31111 2 0.00% 90.97% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::31232-31239 151 0.20% 91.17% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::31488-31495 11 0.01% 91.19% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.19% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.19% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::31744-31751 72 0.10% 91.28% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.28% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::32000-32007 84 0.11% 91.40% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.40% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::32256-32263 15 0.02% 91.42% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.42% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.45% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::32768-32775 273 0.36% 91.82% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::33024-33031 27 0.04% 91.85% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::33152-33159 2 0.00% 91.85% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::33280-33287 28 0.04% 91.89% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::33536-33543 83 0.11% 92.00% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::33792-33799 70 0.09% 92.10% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.11% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::34304-34311 153 0.20% 92.32% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.32% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::34560-34567 13 0.02% 92.34% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::34816-34823 85 0.11% 92.45% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::35072-35079 13 0.02% 92.47% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::35328-35335 90 0.12% 92.59% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::35584-35591 32 0.04% 92.63% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::35840-35847 150 0.20% 92.83% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.83% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.86% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::36352-36359 9 0.01% 92.87% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.99% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::36736-36743 1 0.00% 92.99% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::36864-36871 172 0.23% 93.22% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::37120-37127 19 0.03% 93.24% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::37184-37191 1 0.00% 93.24% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::37248-37255 2 0.00% 93.25% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::37376-37383 23 0.03% 93.28% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.28% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.28% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::37632-37639 70 0.09% 93.37% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::37888-37895 89 0.12% 93.49% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::37952-37959 2 0.00% 93.49% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.49% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.50% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::38144-38151 74 0.10% 93.59% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.60% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.61% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::38656-38663 31 0.04% 93.65% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::38912-38919 140 0.19% 93.84% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::39168-39175 81 0.11% 93.95% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::39232-39239 1 0.00% 93.95% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::39424-39431 14 0.02% 93.97% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::39680-39687 5 0.01% 93.97% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::39936-39943 169 0.23% 94.20% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::40064-40071 1 0.00% 94.20% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::40192-40199 23 0.03% 94.23% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.32% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::40704-40711 29 0.04% 94.36% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::40960-40967 152 0.20% 94.56% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::41216-41223 26 0.03% 94.60% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::41472-41479 66 0.09% 94.68% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::41728-41735 22 0.03% 94.71% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::41920-41927 1 0.00% 94.72% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::41984-41991 165 0.22% 94.93% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::42240-42247 4 0.01% 94.94% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.94% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::42496-42503 13 0.02% 94.96% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::42560-42567 1 0.00% 94.96% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::42752-42759 87 0.12% 95.08% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::43008-43015 139 0.19% 95.26% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::43264-43271 32 0.04% 95.30% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.32% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::43584-43591 1 0.00% 95.32% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::43776-43783 72 0.10% 95.42% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.54% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.54% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::44288-44295 72 0.10% 95.64% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.64% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::44544-44551 22 0.03% 95.67% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::44736-44743 1 0.00% 95.67% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.69% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.69% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::44992-44999 1 0.00% 95.69% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::45056-45063 169 0.23% 95.92% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.92% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::45312-45319 83 0.11% 96.03% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.03% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::45568-45575 7 0.01% 96.04% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::45824-45831 22 0.03% 96.07% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::46080-46087 150 0.20% 96.27% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.27% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::46272-46279 1 0.00% 96.27% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.31% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::46592-46599 96 0.13% 96.44% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::46848-46855 12 0.02% 96.45% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::46976-46983 2 0.00% 96.46% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.46% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::47104-47111 92 0.12% 96.58% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.58% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::47232-47239 3 0.00% 96.59% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::47360-47367 18 0.02% 96.61% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::47488-47495 2 0.00% 96.61% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::47616-47623 154 0.21% 96.82% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.82% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::47808-47815 1 0.00% 96.82% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::47872-47879 17 0.02% 96.84% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.85% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.85% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::48128-48135 94 0.13% 96.97% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.98% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.98% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.98% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::48384-48391 97 0.13% 97.11% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::48640-48647 12 0.02% 97.13% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation 586system.physmem.totQLat 159590177750 # Total ticks spent queuing 587system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM 588system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers 589system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks 590system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst 591system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst 592system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 593system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst 594system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s 595system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s 596system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s 597system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s 598system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 599system.physmem.busUtil 2.83 # Data bus utilization in percentage 600system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 601system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 602system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing 603system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing 604system.physmem.readRowHits 6598517 # Number of row buffer hits during reads 605system.physmem.writeRowHits 94894 # Number of row buffer hits during writes 606system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads 607system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes 608system.physmem.avgGap 159938.04 # Average gap between requests 609system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined 610system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state |
| 468system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 469system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 470system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 471system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 472system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 473system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 474system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 475system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 476system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 477system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 478system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 479system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 480system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 481system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 482system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 483system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 484system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 485system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) | 611system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 612system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 613system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 614system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 615system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 616system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 617system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 618system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 619system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 620system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 621system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 622system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 623system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 624system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 625system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 626system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 627system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 628system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) |
| 486system.membus.throughput 60029719 # Throughput (bytes/s) 487system.membus.trans_dist::ReadReq 7703148 # Transaction distribution 488system.membus.trans_dist::ReadResp 7703148 # Transaction distribution 489system.membus.trans_dist::WriteReq 767203 # Transaction distribution 490system.membus.trans_dist::WriteResp 767203 # Transaction distribution 491system.membus.trans_dist::Writeback 64631 # Transaction distribution 492system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution 493system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution 494system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution 495system.membus.trans_dist::ReadExReq 137763 # Transaction distribution 496system.membus.trans_dist::ReadExResp 137302 # Transaction distribution 497system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes) | 629system.membus.throughput 59999152 # Throughput (bytes/s) 630system.membus.trans_dist::ReadReq 7703168 # Transaction distribution 631system.membus.trans_dist::ReadResp 7703168 # Transaction distribution 632system.membus.trans_dist::WriteReq 767205 # Transaction distribution 633system.membus.trans_dist::WriteResp 767205 # Transaction distribution 634system.membus.trans_dist::Writeback 64738 # Transaction distribution 635system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution 636system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution 637system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution 638system.membus.trans_dist::ReadExReq 137900 # Transaction distribution 639system.membus.trans_dist::ReadExResp 137428 # Transaction distribution 640system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) |
| 498system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) | 641system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) |
| 499system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes) | 642system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) |
| 500system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) | 643system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) |
| 501system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) 502system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes) 503system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes) | 644system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) 645system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes) 646system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes) |
| 504system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 505system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) | 647system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 648system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) |
| 506system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes) 507system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes) | 649system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes) 650system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) |
| 508system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) | 651system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) |
| 509system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes) | 652system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) |
| 510system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) | 653system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) |
| 511system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) 512system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes) 513system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes) | 654system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) 655system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes) 656system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes) |
| 514system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 515system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) | 657system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 658system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) |
| 516system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes) 517system.membus.data_through_bus 71728526 # Total data (bytes) | 659system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes) 660system.membus.data_through_bus 71744366 # Total data (bytes) |
| 518system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 661system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 519system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks) | 662system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks) |
| 520system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 521system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 522system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 663system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 664system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 665system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 523system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks) | 666system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks) |
| 524system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 525system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 526system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 667system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 668system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 669system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 527system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks) | 670system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) |
| 528system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 671system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 529system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks) | 672system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks) |
| 530system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) | 673system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) |
| 531system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks) | 674system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks) |
| 532system.membus.respLayer1.utilization 0.4 # Layer utilization (%) | 675system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 533system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks) | 676system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks) |
| 534system.membus.respLayer2.utilization 1.2 # Layer utilization (%) | 677system.membus.respLayer2.utilization 1.2 # Layer utilization (%) |
| 535system.l2c.tags.replacements 69624 # number of replacements 536system.l2c.tags.tagsinuse 53154.717455 # Cycle average of tags in use 537system.l2c.tags.total_refs 1650852 # Total number of references to valid blocks. 538system.l2c.tags.sampled_refs 134785 # Sample count of references to valid blocks. 539system.l2c.tags.avg_refs 12.248039 # Average number of references to valid blocks. | 678system.l2c.tags.replacements 69764 # number of replacements 679system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use 680system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks. 681system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks. 682system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks. |
| 540system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 683system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 541system.l2c.tags.occ_blocks::writebacks 40039.692381 # Average occupied blocks per requestor 542system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667893 # Average occupied blocks per requestor 543system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor 544system.l2c.tags.occ_blocks::cpu0.inst 4638.680952 # Average occupied blocks per requestor 545system.l2c.tags.occ_blocks::cpu0.data 5789.816440 # Average occupied blocks per requestor 546system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor 547system.l2c.tags.occ_blocks::cpu1.inst 1927.067698 # Average occupied blocks per requestor 548system.l2c.tags.occ_blocks::cpu1.data 756.788910 # Average occupied blocks per requestor 549system.l2c.tags.occ_percent::writebacks 0.610957 # Average percentage of cache occupancy | 684system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor 685system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor 686system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor 687system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor 688system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor 689system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor 690system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor 691system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor 692system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy |
| 550system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy 551system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 693system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy 694system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 552system.l2c.tags.occ_percent::cpu0.inst 0.070781 # Average percentage of cache occupancy 553system.l2c.tags.occ_percent::cpu0.data 0.088346 # Average percentage of cache occupancy | 695system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy 696system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy |
| 554system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy | 697system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy |
| 555system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy 556system.l2c.tags.occ_percent::cpu1.data 0.011548 # Average percentage of cache occupancy 557system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy 558system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits 559system.l2c.ReadReq_hits::cpu0.itb.walker 1438 # number of ReadReq hits 560system.l2c.ReadReq_hits::cpu0.inst 483013 # number of ReadReq hits 561system.l2c.ReadReq_hits::cpu0.data 241892 # number of ReadReq hits 562system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits 563system.l2c.ReadReq_hits::cpu1.itb.walker 1869 # number of ReadReq hits 564system.l2c.ReadReq_hits::cpu1.inst 372280 # number of ReadReq hits 565system.l2c.ReadReq_hits::cpu1.data 110462 # number of ReadReq hits 566system.l2c.ReadReq_hits::total 1219260 # number of ReadReq hits 567system.l2c.Writeback_hits::writebacks 576006 # number of Writeback hits 568system.l2c.Writeback_hits::total 576006 # number of Writeback hits 569system.l2c.UpgradeReq_hits::cpu0.data 1292 # number of UpgradeReq hits 570system.l2c.UpgradeReq_hits::cpu1.data 416 # number of UpgradeReq hits 571system.l2c.UpgradeReq_hits::total 1708 # number of UpgradeReq hits 572system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits 573system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits 574system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits 575system.l2c.ReadExReq_hits::cpu0.data 65542 # number of ReadExReq hits 576system.l2c.ReadExReq_hits::cpu1.data 45349 # number of ReadExReq hits 577system.l2c.ReadExReq_hits::total 110891 # number of ReadExReq hits 578system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits 579system.l2c.demand_hits::cpu0.itb.walker 1438 # number of demand (read+write) hits 580system.l2c.demand_hits::cpu0.inst 483013 # number of demand (read+write) hits 581system.l2c.demand_hits::cpu0.data 307434 # number of demand (read+write) hits 582system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits 583system.l2c.demand_hits::cpu1.itb.walker 1869 # number of demand (read+write) hits 584system.l2c.demand_hits::cpu1.inst 372280 # number of demand (read+write) hits 585system.l2c.demand_hits::cpu1.data 155811 # number of demand (read+write) hits 586system.l2c.demand_hits::total 1330151 # number of demand (read+write) hits 587system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits 588system.l2c.overall_hits::cpu0.itb.walker 1438 # number of overall hits 589system.l2c.overall_hits::cpu0.inst 483013 # number of overall hits 590system.l2c.overall_hits::cpu0.data 307434 # number of overall hits 591system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits 592system.l2c.overall_hits::cpu1.itb.walker 1869 # number of overall hits 593system.l2c.overall_hits::cpu1.inst 372280 # number of overall hits 594system.l2c.overall_hits::cpu1.data 155811 # number of overall hits 595system.l2c.overall_hits::total 1330151 # number of overall hits | 698system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy 699system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache occupancy 700system.l2c.tags.occ_percent::total 0.811096 # Average percentage of cache occupancy 701system.l2c.ReadReq_hits::cpu0.dtb.walker 4686 # number of ReadReq hits 702system.l2c.ReadReq_hits::cpu0.itb.walker 1510 # number of ReadReq hits 703system.l2c.ReadReq_hits::cpu0.inst 483170 # number of ReadReq hits 704system.l2c.ReadReq_hits::cpu0.data 242041 # number of ReadReq hits 705system.l2c.ReadReq_hits::cpu1.dtb.walker 3562 # number of ReadReq hits 706system.l2c.ReadReq_hits::cpu1.itb.walker 1809 # number of ReadReq hits 707system.l2c.ReadReq_hits::cpu1.inst 372569 # number of ReadReq hits 708system.l2c.ReadReq_hits::cpu1.data 110996 # number of ReadReq hits 709system.l2c.ReadReq_hits::total 1220343 # number of ReadReq hits 710system.l2c.Writeback_hits::writebacks 576824 # number of Writeback hits 711system.l2c.Writeback_hits::total 576824 # number of Writeback hits 712system.l2c.UpgradeReq_hits::cpu0.data 1289 # number of UpgradeReq hits 713system.l2c.UpgradeReq_hits::cpu1.data 452 # number of UpgradeReq hits 714system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits 715system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits 716system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits 717system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits 718system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits 719system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits 720system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits 721system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits 722system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits 723system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits 724system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits 725system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits 726system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits 727system.l2c.demand_hits::cpu1.inst 372569 # number of demand (read+write) hits 728system.l2c.demand_hits::cpu1.data 156291 # number of demand (read+write) hits 729system.l2c.demand_hits::total 1331260 # number of demand (read+write) hits 730system.l2c.overall_hits::cpu0.dtb.walker 4686 # number of overall hits 731system.l2c.overall_hits::cpu0.itb.walker 1510 # number of overall hits 732system.l2c.overall_hits::cpu0.inst 483170 # number of overall hits 733system.l2c.overall_hits::cpu0.data 307663 # number of overall hits 734system.l2c.overall_hits::cpu1.dtb.walker 3562 # number of overall hits 735system.l2c.overall_hits::cpu1.itb.walker 1809 # number of overall hits 736system.l2c.overall_hits::cpu1.inst 372569 # number of overall hits 737system.l2c.overall_hits::cpu1.data 156291 # number of overall hits 738system.l2c.overall_hits::total 1331260 # number of overall hits |
| 596system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 597system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 739system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 740system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 598system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses 599system.l2c.ReadReq_misses::cpu0.data 9716 # number of ReadReq misses | 741system.l2c.ReadReq_misses::cpu0.inst 6835 # number of ReadReq misses 742system.l2c.ReadReq_misses::cpu0.data 9720 # number of ReadReq misses |
| 600system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses | 743system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses |
| 601system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses 602system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses 603system.l2c.ReadReq_misses::total 22441 # number of ReadReq misses 604system.l2c.UpgradeReq_misses::cpu0.data 3974 # number of UpgradeReq misses 605system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses 606system.l2c.UpgradeReq_misses::total 7345 # number of UpgradeReq misses 607system.l2c.SCUpgradeReq_misses::cpu0.data 385 # number of SCUpgradeReq misses 608system.l2c.SCUpgradeReq_misses::cpu1.data 476 # number of SCUpgradeReq misses 609system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses 610system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses 611system.l2c.ReadExReq_misses::cpu1.data 44603 # number of ReadExReq misses 612system.l2c.ReadExReq_misses::total 139739 # number of ReadExReq misses | 744system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses 745system.l2c.ReadReq_misses::cpu1.data 1892 # number of ReadReq misses 746system.l2c.ReadReq_misses::total 22455 # number of ReadReq misses 747system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses 748system.l2c.UpgradeReq_misses::cpu1.data 3383 # number of UpgradeReq misses 749system.l2c.UpgradeReq_misses::total 7371 # number of UpgradeReq misses 750system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses 751system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses 752system.l2c.SCUpgradeReq_misses::total 866 # number of SCUpgradeReq misses 753system.l2c.ReadExReq_misses::cpu0.data 95249 # number of ReadExReq misses 754system.l2c.ReadExReq_misses::cpu1.data 44598 # number of ReadExReq misses 755system.l2c.ReadExReq_misses::total 139847 # number of ReadExReq misses |
| 613system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 614system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 756system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 757system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 615system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses 616system.l2c.demand_misses::cpu0.data 104852 # number of demand (read+write) misses | 758system.l2c.demand_misses::cpu0.inst 6835 # number of demand (read+write) misses 759system.l2c.demand_misses::cpu0.data 104969 # number of demand (read+write) misses |
| 617system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses | 760system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses |
| 618system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses 619system.l2c.demand_misses::cpu1.data 46493 # number of demand (read+write) misses 620system.l2c.demand_misses::total 162180 # number of demand (read+write) misses | 761system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses 762system.l2c.demand_misses::cpu1.data 46490 # number of demand (read+write) misses 763system.l2c.demand_misses::total 162302 # number of demand (read+write) misses |
| 621system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 622system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 764system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 765system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 623system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses 624system.l2c.overall_misses::cpu0.data 104852 # number of overall misses | 766system.l2c.overall_misses::cpu0.inst 6835 # number of overall misses 767system.l2c.overall_misses::cpu0.data 104969 # number of overall misses |
| 625system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses | 768system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses |
| 626system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses 627system.l2c.overall_misses::cpu1.data 46493 # number of overall misses 628system.l2c.overall_misses::total 162180 # number of overall misses 629system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 687750 # number of ReadReq miss cycles 630system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles 631system.l2c.ReadReq_miss_latency::cpu0.inst 482771250 # number of ReadReq miss cycles 632system.l2c.ReadReq_miss_latency::cpu0.data 688091749 # number of ReadReq miss cycles 633system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles 634system.l2c.ReadReq_miss_latency::cpu1.inst 282183750 # number of ReadReq miss cycles 635system.l2c.ReadReq_miss_latency::cpu1.data 151111000 # number of ReadReq miss cycles 636system.l2c.ReadReq_miss_latency::total 1605057249 # number of ReadReq miss cycles 637system.l2c.UpgradeReq_miss_latency::cpu0.data 11611000 # number of UpgradeReq miss cycles 638system.l2c.UpgradeReq_miss_latency::cpu1.data 12427970 # number of UpgradeReq miss cycles 639system.l2c.UpgradeReq_miss_latency::total 24038970 # number of UpgradeReq miss cycles 640system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1906918 # number of SCUpgradeReq miss cycles 641system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117452 # number of SCUpgradeReq miss cycles 642system.l2c.SCUpgradeReq_miss_latency::total 3024370 # number of SCUpgradeReq miss cycles 643system.l2c.ReadExReq_miss_latency::cpu0.data 6193599427 # number of ReadExReq miss cycles 644system.l2c.ReadExReq_miss_latency::cpu1.data 2824169884 # number of ReadExReq miss cycles 645system.l2c.ReadExReq_miss_latency::total 9017769311 # number of ReadExReq miss cycles 646system.l2c.demand_miss_latency::cpu0.dtb.walker 687750 # number of demand (read+write) miss cycles 647system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles 648system.l2c.demand_miss_latency::cpu0.inst 482771250 # number of demand (read+write) miss cycles 649system.l2c.demand_miss_latency::cpu0.data 6881691176 # number of demand (read+write) miss cycles 650system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles 651system.l2c.demand_miss_latency::cpu1.inst 282183750 # number of demand (read+write) miss cycles 652system.l2c.demand_miss_latency::cpu1.data 2975280884 # number of demand (read+write) miss cycles 653system.l2c.demand_miss_latency::total 10622826560 # number of demand (read+write) miss cycles 654system.l2c.overall_miss_latency::cpu0.dtb.walker 687750 # number of overall miss cycles 655system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles 656system.l2c.overall_miss_latency::cpu0.inst 482771250 # number of overall miss cycles 657system.l2c.overall_miss_latency::cpu0.data 6881691176 # number of overall miss cycles 658system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles 659system.l2c.overall_miss_latency::cpu1.inst 282183750 # number of overall miss cycles 660system.l2c.overall_miss_latency::cpu1.data 2975280884 # number of overall miss cycles 661system.l2c.overall_miss_latency::total 10622826560 # number of overall miss cycles 662system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses) 663system.l2c.ReadReq_accesses::cpu0.itb.walker 1440 # number of ReadReq accesses(hits+misses) 664system.l2c.ReadReq_accesses::cpu0.inst 489845 # number of ReadReq accesses(hits+misses) 665system.l2c.ReadReq_accesses::cpu0.data 251608 # number of ReadReq accesses(hits+misses) 666system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses) 667system.l2c.ReadReq_accesses::cpu1.itb.walker 1870 # number of ReadReq accesses(hits+misses) 668system.l2c.ReadReq_accesses::cpu1.inst 376276 # number of ReadReq accesses(hits+misses) 669system.l2c.ReadReq_accesses::cpu1.data 112352 # number of ReadReq accesses(hits+misses) 670system.l2c.ReadReq_accesses::total 1241701 # number of ReadReq accesses(hits+misses) 671system.l2c.Writeback_accesses::writebacks 576006 # number of Writeback accesses(hits+misses) 672system.l2c.Writeback_accesses::total 576006 # number of Writeback accesses(hits+misses) 673system.l2c.UpgradeReq_accesses::cpu0.data 5266 # number of UpgradeReq accesses(hits+misses) 674system.l2c.UpgradeReq_accesses::cpu1.data 3787 # number of UpgradeReq accesses(hits+misses) 675system.l2c.UpgradeReq_accesses::total 9053 # number of UpgradeReq accesses(hits+misses) 676system.l2c.SCUpgradeReq_accesses::cpu0.data 640 # number of SCUpgradeReq accesses(hits+misses) 677system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses) 678system.l2c.SCUpgradeReq_accesses::total 1216 # number of SCUpgradeReq accesses(hits+misses) 679system.l2c.ReadExReq_accesses::cpu0.data 160678 # number of ReadExReq accesses(hits+misses) 680system.l2c.ReadExReq_accesses::cpu1.data 89952 # number of ReadExReq accesses(hits+misses) 681system.l2c.ReadExReq_accesses::total 250630 # number of ReadExReq accesses(hits+misses) 682system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses 683system.l2c.demand_accesses::cpu0.itb.walker 1440 # number of demand (read+write) accesses 684system.l2c.demand_accesses::cpu0.inst 489845 # number of demand (read+write) accesses 685system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses 686system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses 687system.l2c.demand_accesses::cpu1.itb.walker 1870 # number of demand (read+write) accesses 688system.l2c.demand_accesses::cpu1.inst 376276 # number of demand (read+write) accesses 689system.l2c.demand_accesses::cpu1.data 202304 # number of demand (read+write) accesses 690system.l2c.demand_accesses::total 1492331 # number of demand (read+write) accesses 691system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses 692system.l2c.overall_accesses::cpu0.itb.walker 1440 # number of overall (read+write) accesses 693system.l2c.overall_accesses::cpu0.inst 489845 # number of overall (read+write) accesses 694system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses 695system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses 696system.l2c.overall_accesses::cpu1.itb.walker 1870 # number of overall (read+write) accesses 697system.l2c.overall_accesses::cpu1.inst 376276 # number of overall (read+write) accesses 698system.l2c.overall_accesses::cpu1.data 202304 # number of overall (read+write) accesses 699system.l2c.overall_accesses::total 1492331 # number of overall (read+write) accesses 700system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses 701system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001389 # miss rate for ReadReq accesses 702system.l2c.ReadReq_miss_rate::cpu0.inst 0.013947 # miss rate for ReadReq accesses 703system.l2c.ReadReq_miss_rate::cpu0.data 0.038616 # miss rate for ReadReq accesses 704system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses 705system.l2c.ReadReq_miss_rate::cpu1.inst 0.010620 # miss rate for ReadReq accesses 706system.l2c.ReadReq_miss_rate::cpu1.data 0.016822 # miss rate for ReadReq accesses 707system.l2c.ReadReq_miss_rate::total 0.018073 # miss rate for ReadReq accesses 708system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754652 # miss rate for UpgradeReq accesses 709system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890151 # miss rate for UpgradeReq accesses 710system.l2c.UpgradeReq_miss_rate::total 0.811333 # miss rate for UpgradeReq accesses 711system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601562 # miss rate for SCUpgradeReq accesses 712system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826389 # miss rate for SCUpgradeReq accesses 713system.l2c.SCUpgradeReq_miss_rate::total 0.708059 # miss rate for SCUpgradeReq accesses 714system.l2c.ReadExReq_miss_rate::cpu0.data 0.592091 # miss rate for ReadExReq accesses 715system.l2c.ReadExReq_miss_rate::cpu1.data 0.495853 # miss rate for ReadExReq accesses 716system.l2c.ReadExReq_miss_rate::total 0.557551 # miss rate for ReadExReq accesses 717system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses 718system.l2c.demand_miss_rate::cpu0.itb.walker 0.001389 # miss rate for demand accesses 719system.l2c.demand_miss_rate::cpu0.inst 0.013947 # miss rate for demand accesses 720system.l2c.demand_miss_rate::cpu0.data 0.254319 # miss rate for demand accesses 721system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses 722system.l2c.demand_miss_rate::cpu1.inst 0.010620 # miss rate for demand accesses 723system.l2c.demand_miss_rate::cpu1.data 0.229818 # miss rate for demand accesses 724system.l2c.demand_miss_rate::total 0.108676 # miss rate for demand accesses 725system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses 726system.l2c.overall_miss_rate::cpu0.itb.walker 0.001389 # miss rate for overall accesses 727system.l2c.overall_miss_rate::cpu0.inst 0.013947 # miss rate for overall accesses 728system.l2c.overall_miss_rate::cpu0.data 0.254319 # miss rate for overall accesses 729system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses 730system.l2c.overall_miss_rate::cpu1.inst 0.010620 # miss rate for overall accesses 731system.l2c.overall_miss_rate::cpu1.data 0.229818 # miss rate for overall accesses 732system.l2c.overall_miss_rate::total 0.108676 # miss rate for overall accesses 733system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average ReadReq miss latency 734system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency 735system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70663.239169 # average ReadReq miss latency 736system.l2c.ReadReq_avg_miss_latency::cpu0.data 70820.476431 # average ReadReq miss latency 737system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency 738system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70616.554054 # average ReadReq miss latency 739system.l2c.ReadReq_avg_miss_latency::cpu1.data 79952.910053 # average ReadReq miss latency 740system.l2c.ReadReq_avg_miss_latency::total 71523.428056 # average ReadReq miss latency 741system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2921.741319 # average UpgradeReq miss latency 742system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3686.730940 # average UpgradeReq miss latency 743system.l2c.UpgradeReq_avg_miss_latency::total 3272.834581 # average UpgradeReq miss latency 744system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4953.033766 # average SCUpgradeReq miss latency 745system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2347.588235 # average SCUpgradeReq miss latency 746system.l2c.SCUpgradeReq_avg_miss_latency::total 3512.624855 # average SCUpgradeReq miss latency 747system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65102.583953 # average ReadExReq miss latency 748system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63317.935655 # average ReadExReq miss latency 749system.l2c.ReadExReq_avg_miss_latency::total 64532.945785 # average ReadExReq miss latency 750system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency 751system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency 752system.l2c.demand_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency 753system.l2c.demand_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency 754system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency 755system.l2c.demand_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency 756system.l2c.demand_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency 757system.l2c.demand_avg_miss_latency::total 65500.225429 # average overall miss latency 758system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency 759system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency 760system.l2c.overall_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency 761system.l2c.overall_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency 762system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency 763system.l2c.overall_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency 764system.l2c.overall_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency 765system.l2c.overall_avg_miss_latency::total 65500.225429 # average overall miss latency | 769system.l2c.overall_misses::cpu1.inst 4001 # number of overall misses 770system.l2c.overall_misses::cpu1.data 46490 # number of overall misses 771system.l2c.overall_misses::total 162302 # number of overall misses 772system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 302000 # number of ReadReq miss cycles 773system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles 774system.l2c.ReadReq_miss_latency::cpu0.inst 491601250 # number of ReadReq miss cycles 775system.l2c.ReadReq_miss_latency::cpu0.data 735185497 # number of ReadReq miss cycles 776system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles 777system.l2c.ReadReq_miss_latency::cpu1.inst 283983750 # number of ReadReq miss cycles 778system.l2c.ReadReq_miss_latency::cpu1.data 151633750 # number of ReadReq miss cycles 779system.l2c.ReadReq_miss_latency::total 1662931247 # number of ReadReq miss cycles 780system.l2c.UpgradeReq_miss_latency::cpu0.data 11383008 # number of UpgradeReq miss cycles 781system.l2c.UpgradeReq_miss_latency::cpu1.data 12410968 # number of UpgradeReq miss cycles 782system.l2c.UpgradeReq_miss_latency::total 23793976 # number of UpgradeReq miss cycles 783system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1839921 # number of SCUpgradeReq miss cycles 784system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117953 # number of SCUpgradeReq miss cycles 785system.l2c.SCUpgradeReq_miss_latency::total 2957874 # number of SCUpgradeReq miss cycles 786system.l2c.ReadExReq_miss_latency::cpu0.data 6545912193 # number of ReadExReq miss cycles 787system.l2c.ReadExReq_miss_latency::cpu1.data 3449006386 # number of ReadExReq miss cycles 788system.l2c.ReadExReq_miss_latency::total 9994918579 # number of ReadExReq miss cycles 789system.l2c.demand_miss_latency::cpu0.dtb.walker 302000 # number of demand (read+write) miss cycles 790system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles 791system.l2c.demand_miss_latency::cpu0.inst 491601250 # number of demand (read+write) miss cycles 792system.l2c.demand_miss_latency::cpu0.data 7281097690 # number of demand (read+write) miss cycles 793system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles 794system.l2c.demand_miss_latency::cpu1.inst 283983750 # number of demand (read+write) miss cycles 795system.l2c.demand_miss_latency::cpu1.data 3600640136 # number of demand (read+write) miss cycles 796system.l2c.demand_miss_latency::total 11657849826 # number of demand (read+write) miss cycles 797system.l2c.overall_miss_latency::cpu0.dtb.walker 302000 # number of overall miss cycles 798system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles 799system.l2c.overall_miss_latency::cpu0.inst 491601250 # number of overall miss cycles 800system.l2c.overall_miss_latency::cpu0.data 7281097690 # number of overall miss cycles 801system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles 802system.l2c.overall_miss_latency::cpu1.inst 283983750 # number of overall miss cycles 803system.l2c.overall_miss_latency::cpu1.data 3600640136 # number of overall miss cycles 804system.l2c.overall_miss_latency::total 11657849826 # number of overall miss cycles 805system.l2c.ReadReq_accesses::cpu0.dtb.walker 4690 # number of ReadReq accesses(hits+misses) 806system.l2c.ReadReq_accesses::cpu0.itb.walker 1512 # number of ReadReq accesses(hits+misses) 807system.l2c.ReadReq_accesses::cpu0.inst 490005 # number of ReadReq accesses(hits+misses) 808system.l2c.ReadReq_accesses::cpu0.data 251761 # number of ReadReq accesses(hits+misses) 809system.l2c.ReadReq_accesses::cpu1.dtb.walker 3562 # number of ReadReq accesses(hits+misses) 810system.l2c.ReadReq_accesses::cpu1.itb.walker 1810 # number of ReadReq accesses(hits+misses) 811system.l2c.ReadReq_accesses::cpu1.inst 376570 # number of ReadReq accesses(hits+misses) 812system.l2c.ReadReq_accesses::cpu1.data 112888 # number of ReadReq accesses(hits+misses) 813system.l2c.ReadReq_accesses::total 1242798 # number of ReadReq accesses(hits+misses) 814system.l2c.Writeback_accesses::writebacks 576824 # number of Writeback accesses(hits+misses) 815system.l2c.Writeback_accesses::total 576824 # number of Writeback accesses(hits+misses) 816system.l2c.UpgradeReq_accesses::cpu0.data 5277 # number of UpgradeReq accesses(hits+misses) 817system.l2c.UpgradeReq_accesses::cpu1.data 3835 # number of UpgradeReq accesses(hits+misses) 818system.l2c.UpgradeReq_accesses::total 9112 # number of UpgradeReq accesses(hits+misses) 819system.l2c.SCUpgradeReq_accesses::cpu0.data 655 # number of SCUpgradeReq accesses(hits+misses) 820system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses) 821system.l2c.SCUpgradeReq_accesses::total 1232 # number of SCUpgradeReq accesses(hits+misses) 822system.l2c.ReadExReq_accesses::cpu0.data 160871 # number of ReadExReq accesses(hits+misses) 823system.l2c.ReadExReq_accesses::cpu1.data 89893 # number of ReadExReq accesses(hits+misses) 824system.l2c.ReadExReq_accesses::total 250764 # number of ReadExReq accesses(hits+misses) 825system.l2c.demand_accesses::cpu0.dtb.walker 4690 # number of demand (read+write) accesses 826system.l2c.demand_accesses::cpu0.itb.walker 1512 # number of demand (read+write) accesses 827system.l2c.demand_accesses::cpu0.inst 490005 # number of demand (read+write) accesses 828system.l2c.demand_accesses::cpu0.data 412632 # number of demand (read+write) accesses 829system.l2c.demand_accesses::cpu1.dtb.walker 3562 # number of demand (read+write) accesses 830system.l2c.demand_accesses::cpu1.itb.walker 1810 # number of demand (read+write) accesses 831system.l2c.demand_accesses::cpu1.inst 376570 # number of demand (read+write) accesses 832system.l2c.demand_accesses::cpu1.data 202781 # number of demand (read+write) accesses 833system.l2c.demand_accesses::total 1493562 # number of demand (read+write) accesses 834system.l2c.overall_accesses::cpu0.dtb.walker 4690 # number of overall (read+write) accesses 835system.l2c.overall_accesses::cpu0.itb.walker 1512 # number of overall (read+write) accesses 836system.l2c.overall_accesses::cpu0.inst 490005 # number of overall (read+write) accesses 837system.l2c.overall_accesses::cpu0.data 412632 # number of overall (read+write) accesses 838system.l2c.overall_accesses::cpu1.dtb.walker 3562 # number of overall (read+write) accesses 839system.l2c.overall_accesses::cpu1.itb.walker 1810 # number of overall (read+write) accesses 840system.l2c.overall_accesses::cpu1.inst 376570 # number of overall (read+write) accesses 841system.l2c.overall_accesses::cpu1.data 202781 # number of overall (read+write) accesses 842system.l2c.overall_accesses::total 1493562 # number of overall (read+write) accesses 843system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for ReadReq accesses 844system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001323 # miss rate for ReadReq accesses 845system.l2c.ReadReq_miss_rate::cpu0.inst 0.013949 # miss rate for ReadReq accesses 846system.l2c.ReadReq_miss_rate::cpu0.data 0.038608 # miss rate for ReadReq accesses 847system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000552 # miss rate for ReadReq accesses 848system.l2c.ReadReq_miss_rate::cpu1.inst 0.010625 # miss rate for ReadReq accesses 849system.l2c.ReadReq_miss_rate::cpu1.data 0.016760 # miss rate for ReadReq accesses 850system.l2c.ReadReq_miss_rate::total 0.018068 # miss rate for ReadReq accesses 851system.l2c.UpgradeReq_miss_rate::cpu0.data 0.755732 # miss rate for UpgradeReq accesses 852system.l2c.UpgradeReq_miss_rate::cpu1.data 0.882138 # miss rate for UpgradeReq accesses 853system.l2c.UpgradeReq_miss_rate::total 0.808933 # miss rate for UpgradeReq accesses 854system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.590840 # miss rate for SCUpgradeReq accesses 855system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830156 # miss rate for SCUpgradeReq accesses 856system.l2c.SCUpgradeReq_miss_rate::total 0.702922 # miss rate for SCUpgradeReq accesses 857system.l2c.ReadExReq_miss_rate::cpu0.data 0.592083 # miss rate for ReadExReq accesses 858system.l2c.ReadExReq_miss_rate::cpu1.data 0.496123 # miss rate for ReadExReq accesses 859system.l2c.ReadExReq_miss_rate::total 0.557684 # miss rate for ReadExReq accesses 860system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for demand accesses 861system.l2c.demand_miss_rate::cpu0.itb.walker 0.001323 # miss rate for demand accesses 862system.l2c.demand_miss_rate::cpu0.inst 0.013949 # miss rate for demand accesses 863system.l2c.demand_miss_rate::cpu0.data 0.254389 # miss rate for demand accesses 864system.l2c.demand_miss_rate::cpu1.itb.walker 0.000552 # miss rate for demand accesses 865system.l2c.demand_miss_rate::cpu1.inst 0.010625 # miss rate for demand accesses 866system.l2c.demand_miss_rate::cpu1.data 0.229262 # miss rate for demand accesses 867system.l2c.demand_miss_rate::total 0.108668 # miss rate for demand accesses 868system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for overall accesses 869system.l2c.overall_miss_rate::cpu0.itb.walker 0.001323 # miss rate for overall accesses 870system.l2c.overall_miss_rate::cpu0.inst 0.013949 # miss rate for overall accesses 871system.l2c.overall_miss_rate::cpu0.data 0.254389 # miss rate for overall accesses 872system.l2c.overall_miss_rate::cpu1.itb.walker 0.000552 # miss rate for overall accesses 873system.l2c.overall_miss_rate::cpu1.inst 0.010625 # miss rate for overall accesses 874system.l2c.overall_miss_rate::cpu1.data 0.229262 # miss rate for overall accesses 875system.l2c.overall_miss_rate::total 0.108668 # miss rate for overall accesses 876system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75500 # average ReadReq miss latency 877system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 878system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71924.103877 # average ReadReq miss latency 879system.l2c.ReadReq_avg_miss_latency::cpu0.data 75636.368004 # average ReadReq miss latency 880system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency 881system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70978.192952 # average ReadReq miss latency 882system.l2c.ReadReq_avg_miss_latency::cpu1.data 80144.688161 # average ReadReq miss latency 883system.l2c.ReadReq_avg_miss_latency::total 74056.167758 # average ReadReq miss latency 884system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2854.314945 # average UpgradeReq miss latency 885system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3668.627845 # average UpgradeReq miss latency 886system.l2c.UpgradeReq_avg_miss_latency::total 3228.052639 # average UpgradeReq miss latency 887system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4754.317829 # average SCUpgradeReq miss latency 888system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2333.931106 # average SCUpgradeReq miss latency 889system.l2c.SCUpgradeReq_avg_miss_latency::total 3415.558891 # average SCUpgradeReq miss latency 890system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68724.209105 # average ReadExReq miss latency 891system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77335.449706 # average ReadExReq miss latency 892system.l2c.ReadExReq_avg_miss_latency::total 71470.382482 # average ReadExReq miss latency 893system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency 894system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 895system.l2c.demand_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency 896system.l2c.demand_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency 897system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency 898system.l2c.demand_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency 899system.l2c.demand_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency 900system.l2c.demand_avg_miss_latency::total 71828.134133 # average overall miss latency 901system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency 902system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 903system.l2c.overall_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency 904system.l2c.overall_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency 905system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency 906system.l2c.overall_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency 907system.l2c.overall_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency 908system.l2c.overall_avg_miss_latency::total 71828.134133 # average overall miss latency |
| 766system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 767system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 768system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 769system.l2c.blocked::no_targets 0 # number of cycles access was blocked 770system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 771system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 772system.l2c.fast_writes 0 # number of fast writes performed 773system.l2c.cache_copies 0 # number of cache copies performed | 909system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 910system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 912system.l2c.blocked::no_targets 0 # number of cycles access was blocked 913system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 914system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 915system.l2c.fast_writes 0 # number of fast writes performed 916system.l2c.cache_copies 0 # number of cache copies performed |
| 774system.l2c.writebacks::writebacks 64631 # number of writebacks 775system.l2c.writebacks::total 64631 # number of writebacks | 917system.l2c.writebacks::writebacks 64738 # number of writebacks 918system.l2c.writebacks::total 64738 # number of writebacks |
| 776system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 777system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 778system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 779system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 780system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 781system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 782system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses 783system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses | 919system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 920system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 921system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 922system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 923system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 924system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 925system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses 926system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses |
| 784system.l2c.ReadReq_mshr_misses::cpu0.inst 6831 # number of ReadReq MSHR misses 785system.l2c.ReadReq_mshr_misses::cpu0.data 9716 # number of ReadReq MSHR misses | 927system.l2c.ReadReq_mshr_misses::cpu0.inst 6834 # number of ReadReq MSHR misses 928system.l2c.ReadReq_mshr_misses::cpu0.data 9720 # number of ReadReq MSHR misses |
| 786system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses | 929system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses |
| 787system.l2c.ReadReq_mshr_misses::cpu1.inst 3996 # number of ReadReq MSHR misses 788system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses 789system.l2c.ReadReq_mshr_misses::total 22440 # number of ReadReq MSHR misses 790system.l2c.UpgradeReq_mshr_misses::cpu0.data 3974 # number of UpgradeReq MSHR misses 791system.l2c.UpgradeReq_mshr_misses::cpu1.data 3371 # number of UpgradeReq MSHR misses 792system.l2c.UpgradeReq_mshr_misses::total 7345 # number of UpgradeReq MSHR misses 793system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 385 # number of SCUpgradeReq MSHR misses 794system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 476 # number of SCUpgradeReq MSHR misses 795system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses 796system.l2c.ReadExReq_mshr_misses::cpu0.data 95136 # number of ReadExReq MSHR misses 797system.l2c.ReadExReq_mshr_misses::cpu1.data 44603 # number of ReadExReq MSHR misses 798system.l2c.ReadExReq_mshr_misses::total 139739 # number of ReadExReq MSHR misses | 930system.l2c.ReadReq_mshr_misses::cpu1.inst 4001 # number of ReadReq MSHR misses 931system.l2c.ReadReq_mshr_misses::cpu1.data 1892 # number of ReadReq MSHR misses 932system.l2c.ReadReq_mshr_misses::total 22454 # number of ReadReq MSHR misses 933system.l2c.UpgradeReq_mshr_misses::cpu0.data 3988 # number of UpgradeReq MSHR misses 934system.l2c.UpgradeReq_mshr_misses::cpu1.data 3383 # number of UpgradeReq MSHR misses 935system.l2c.UpgradeReq_mshr_misses::total 7371 # number of UpgradeReq MSHR misses 936system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 387 # number of SCUpgradeReq MSHR misses 937system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses 938system.l2c.SCUpgradeReq_mshr_misses::total 866 # number of SCUpgradeReq MSHR misses 939system.l2c.ReadExReq_mshr_misses::cpu0.data 95249 # number of ReadExReq MSHR misses 940system.l2c.ReadExReq_mshr_misses::cpu1.data 44598 # number of ReadExReq MSHR misses 941system.l2c.ReadExReq_mshr_misses::total 139847 # number of ReadExReq MSHR misses |
| 799system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses 800system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses | 942system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses 943system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses |
| 801system.l2c.demand_mshr_misses::cpu0.inst 6831 # number of demand (read+write) MSHR misses 802system.l2c.demand_mshr_misses::cpu0.data 104852 # number of demand (read+write) MSHR misses | 944system.l2c.demand_mshr_misses::cpu0.inst 6834 # number of demand (read+write) MSHR misses 945system.l2c.demand_mshr_misses::cpu0.data 104969 # number of demand (read+write) MSHR misses |
| 803system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses | 946system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses |
| 804system.l2c.demand_mshr_misses::cpu1.inst 3996 # number of demand (read+write) MSHR misses 805system.l2c.demand_mshr_misses::cpu1.data 46493 # number of demand (read+write) MSHR misses 806system.l2c.demand_mshr_misses::total 162179 # number of demand (read+write) MSHR misses | 947system.l2c.demand_mshr_misses::cpu1.inst 4001 # number of demand (read+write) MSHR misses 948system.l2c.demand_mshr_misses::cpu1.data 46490 # number of demand (read+write) MSHR misses 949system.l2c.demand_mshr_misses::total 162301 # number of demand (read+write) MSHR misses |
| 807system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses 808system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses | 950system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses 951system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses |
| 809system.l2c.overall_mshr_misses::cpu0.inst 6831 # number of overall MSHR misses 810system.l2c.overall_mshr_misses::cpu0.data 104852 # number of overall MSHR misses | 952system.l2c.overall_mshr_misses::cpu0.inst 6834 # number of overall MSHR misses 953system.l2c.overall_mshr_misses::cpu0.data 104969 # number of overall MSHR misses |
| 811system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses | 954system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses |
| 812system.l2c.overall_mshr_misses::cpu1.inst 3996 # number of overall MSHR misses 813system.l2c.overall_mshr_misses::cpu1.data 46493 # number of overall MSHR misses 814system.l2c.overall_mshr_misses::total 162179 # number of overall MSHR misses 815system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 635750 # number of ReadReq MSHR miss cycles 816system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles 817system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 396501000 # number of ReadReq MSHR miss cycles 818system.l2c.ReadReq_mshr_miss_latency::cpu0.data 564859249 # number of ReadReq MSHR miss cycles 819system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles 820system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 231739250 # number of ReadReq MSHR miss cycles 821system.l2c.ReadReq_mshr_miss_latency::cpu1.data 127085000 # number of ReadReq MSHR miss cycles 822system.l2c.ReadReq_mshr_miss_latency::total 1320993999 # number of ReadReq MSHR miss cycles 823system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39771967 # number of UpgradeReq MSHR miss cycles 824system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33821856 # number of UpgradeReq MSHR miss cycles 825system.l2c.UpgradeReq_mshr_miss_latency::total 73593823 # number of UpgradeReq MSHR miss cycles 826system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3851884 # number of SCUpgradeReq MSHR miss cycles 827system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768975 # number of SCUpgradeReq MSHR miss cycles 828system.l2c.SCUpgradeReq_mshr_miss_latency::total 8620859 # number of SCUpgradeReq MSHR miss cycles 829system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5000986069 # number of ReadExReq MSHR miss cycles 830system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2264195114 # number of ReadExReq MSHR miss cycles 831system.l2c.ReadExReq_mshr_miss_latency::total 7265181183 # number of ReadExReq MSHR miss cycles 832system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 635750 # number of demand (read+write) MSHR miss cycles 833system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles 834system.l2c.demand_mshr_miss_latency::cpu0.inst 396501000 # number of demand (read+write) MSHR miss cycles 835system.l2c.demand_mshr_miss_latency::cpu0.data 5565845318 # number of demand (read+write) MSHR miss cycles 836system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles 837system.l2c.demand_mshr_miss_latency::cpu1.inst 231739250 # number of demand (read+write) MSHR miss cycles 838system.l2c.demand_mshr_miss_latency::cpu1.data 2391280114 # number of demand (read+write) MSHR miss cycles 839system.l2c.demand_mshr_miss_latency::total 8586175182 # number of demand (read+write) MSHR miss cycles 840system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 635750 # number of overall MSHR miss cycles 841system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles 842system.l2c.overall_mshr_miss_latency::cpu0.inst 396501000 # number of overall MSHR miss cycles 843system.l2c.overall_mshr_miss_latency::cpu0.data 5565845318 # number of overall MSHR miss cycles 844system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles 845system.l2c.overall_mshr_miss_latency::cpu1.inst 231739250 # number of overall MSHR miss cycles 846system.l2c.overall_mshr_miss_latency::cpu1.data 2391280114 # number of overall MSHR miss cycles 847system.l2c.overall_mshr_miss_latency::total 8586175182 # number of overall MSHR miss cycles 848system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 323836500 # number of ReadReq MSHR uncacheable cycles 849system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647640494 # number of ReadReq MSHR uncacheable cycles 850system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles 851system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070543500 # number of ReadReq MSHR uncacheable cycles 852system.l2c.ReadReq_mshr_uncacheable_latency::total 167046869994 # number of ReadReq MSHR uncacheable cycles 853system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272049535 # number of WriteReq MSHR uncacheable cycles 854system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486218500 # number of WriteReq MSHR uncacheable cycles 855system.l2c.WriteReq_mshr_uncacheable_latency::total 16758268035 # number of WriteReq MSHR uncacheable cycles 856system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 323836500 # number of overall MSHR uncacheable cycles 857system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919690029 # number of overall MSHR uncacheable cycles 858system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles 859system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556762000 # number of overall MSHR uncacheable cycles 860system.l2c.overall_mshr_uncacheable_latency::total 183805138029 # number of overall MSHR uncacheable cycles 861system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses 862system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for ReadReq accesses 863system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for ReadReq accesses 864system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038616 # mshr miss rate for ReadReq accesses 865system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses 866system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for ReadReq accesses 867system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016822 # mshr miss rate for ReadReq accesses 868system.l2c.ReadReq_mshr_miss_rate::total 0.018072 # mshr miss rate for ReadReq accesses 869system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754652 # mshr miss rate for UpgradeReq accesses 870system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890151 # mshr miss rate for UpgradeReq accesses 871system.l2c.UpgradeReq_mshr_miss_rate::total 0.811333 # mshr miss rate for UpgradeReq accesses 872system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601562 # mshr miss rate for SCUpgradeReq accesses 873system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826389 # mshr miss rate for SCUpgradeReq accesses 874system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708059 # mshr miss rate for SCUpgradeReq accesses 875system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592091 # mshr miss rate for ReadExReq accesses 876system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495853 # mshr miss rate for ReadExReq accesses 877system.l2c.ReadExReq_mshr_miss_rate::total 0.557551 # mshr miss rate for ReadExReq accesses 878system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses 879system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for demand accesses 880system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for demand accesses 881system.l2c.demand_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for demand accesses 882system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses 883system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for demand accesses 884system.l2c.demand_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for demand accesses 885system.l2c.demand_mshr_miss_rate::total 0.108675 # mshr miss rate for demand accesses 886system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses 887system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for overall accesses 888system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for overall accesses 889system.l2c.overall_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for overall accesses 890system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses 891system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for overall accesses 892system.l2c.overall_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for overall accesses 893system.l2c.overall_mshr_miss_rate::total 0.108675 # mshr miss rate for overall accesses 894system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average ReadReq mshr miss latency 895system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency 896system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average ReadReq mshr miss latency 897system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58137.016159 # average ReadReq mshr miss latency 898system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency 899system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average ReadReq mshr miss latency 900system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67240.740741 # average ReadReq mshr miss latency 901system.l2c.ReadReq_avg_mshr_miss_latency::total 58867.825267 # average ReadReq mshr miss latency 902system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036 # average UpgradeReq mshr miss latency 903system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845 # average UpgradeReq mshr miss latency 904system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076 # average UpgradeReq mshr miss latency 905system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506 # average SCUpgradeReq mshr miss latency 906system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042 # average SCUpgradeReq mshr miss latency 907system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079 # average SCUpgradeReq mshr miss latency 908system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233 # average ReadExReq mshr miss latency 909system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021 # average ReadExReq mshr miss latency 910system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530 # average ReadExReq mshr miss latency 911system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency 912system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency 913system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency 914system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency 915system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 916system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency 917system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency 918system.l2c.demand_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency 919system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency 920system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency 921system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency 922system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency 923system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 924system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency 925system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency 926system.l2c.overall_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency | 955system.l2c.overall_mshr_misses::cpu1.inst 4001 # number of overall MSHR misses 956system.l2c.overall_mshr_misses::cpu1.data 46490 # number of overall MSHR misses 957system.l2c.overall_mshr_misses::total 162301 # number of overall MSHR misses 958system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 254000 # number of ReadReq MSHR miss cycles 959system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 960system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 405760500 # number of ReadReq MSHR miss cycles 961system.l2c.ReadReq_mshr_miss_latency::cpu0.data 614009497 # number of ReadReq MSHR miss cycles 962system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 963system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233748250 # number of ReadReq MSHR miss cycles 964system.l2c.ReadReq_mshr_miss_latency::cpu1.data 128083750 # number of ReadReq MSHR miss cycles 965system.l2c.ReadReq_mshr_miss_latency::total 1382043497 # number of ReadReq MSHR miss cycles 966system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39929483 # number of UpgradeReq MSHR miss cycles 967system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33964367 # number of UpgradeReq MSHR miss cycles 968system.l2c.UpgradeReq_mshr_miss_latency::total 73893850 # number of UpgradeReq MSHR miss cycles 969system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3876386 # number of SCUpgradeReq MSHR miss cycles 970system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4797478 # number of SCUpgradeReq MSHR miss cycles 971system.l2c.SCUpgradeReq_mshr_miss_latency::total 8673864 # number of SCUpgradeReq MSHR miss cycles 972system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5351778297 # number of ReadExReq MSHR miss cycles 973system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2889281614 # number of ReadExReq MSHR miss cycles 974system.l2c.ReadExReq_mshr_miss_latency::total 8241059911 # number of ReadExReq MSHR miss cycles 975system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 254000 # number of demand (read+write) MSHR miss cycles 976system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 977system.l2c.demand_mshr_miss_latency::cpu0.inst 405760500 # number of demand (read+write) MSHR miss cycles 978system.l2c.demand_mshr_miss_latency::cpu0.data 5965787794 # number of demand (read+write) MSHR miss cycles 979system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 980system.l2c.demand_mshr_miss_latency::cpu1.inst 233748250 # number of demand (read+write) MSHR miss cycles 981system.l2c.demand_mshr_miss_latency::cpu1.data 3017365364 # number of demand (read+write) MSHR miss cycles 982system.l2c.demand_mshr_miss_latency::total 9623103408 # number of demand (read+write) MSHR miss cycles 983system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 254000 # number of overall MSHR miss cycles 984system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 985system.l2c.overall_mshr_miss_latency::cpu0.inst 405760500 # number of overall MSHR miss cycles 986system.l2c.overall_mshr_miss_latency::cpu0.data 5965787794 # number of overall MSHR miss cycles 987system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles 988system.l2c.overall_mshr_miss_latency::cpu1.inst 233748250 # number of overall MSHR miss cycles 989system.l2c.overall_mshr_miss_latency::cpu1.data 3017365364 # number of overall MSHR miss cycles 990system.l2c.overall_mshr_miss_latency::total 9623103408 # number of overall MSHR miss cycles 991system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles 992system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648858491 # number of ReadReq MSHR uncacheable cycles 993system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5098250 # number of ReadReq MSHR uncacheable cycles 994system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154081373749 # number of ReadReq MSHR uncacheable cycles 995system.l2c.ReadReq_mshr_uncacheable_latency::total 167080044240 # number of ReadReq MSHR uncacheable cycles 996system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272206162 # number of WriteReq MSHR uncacheable cycles 997system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486212000 # number of WriteReq MSHR uncacheable cycles 998system.l2c.WriteReq_mshr_uncacheable_latency::total 16758418162 # number of WriteReq MSHR uncacheable cycles 999system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles 1000system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921064653 # number of overall MSHR uncacheable cycles 1001system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5098250 # number of overall MSHR uncacheable cycles 1002system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154567585749 # number of overall MSHR uncacheable cycles 1003system.l2c.overall_mshr_uncacheable_latency::total 183838462402 # number of overall MSHR uncacheable cycles 1004system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for ReadReq accesses 1005system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for ReadReq accesses 1006system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for ReadReq accesses 1007system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038608 # mshr miss rate for ReadReq accesses 1008system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for ReadReq accesses 1009system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses 1010system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses 1011system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses 1012system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses 1013system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses 1014system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses 1015system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses 1016system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses 1017system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses 1018system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592083 # mshr miss rate for ReadExReq accesses 1019system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses 1020system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses 1021system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for demand accesses 1022system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses 1023system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses 1024system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses 1025system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses 1026system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses 1027system.l2c.demand_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for demand accesses 1028system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses 1029system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses 1030system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses 1031system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses 1032system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses 1033system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses 1034system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses 1035system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses 1036system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses 1037system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency 1038system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 1039system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency 1040system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency 1041system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 1042system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency 1043system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency 1044system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency 1045system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency 1046system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency 1047system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency 1048system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency 1049system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency 1050system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency 1051system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency 1052system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency 1053system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency 1054system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency 1055system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1056system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency 1057system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency 1058system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1059system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency 1060system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency 1061system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency 1062system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency 1063system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1064system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency 1065system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency 1066system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1067system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency 1068system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency 1069system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency |
| 927system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 928system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 929system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 930system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 931system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 932system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 933system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 934system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 939system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 940system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 941system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 942system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 943system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 944system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 945system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 946system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 1070system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1071system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1072system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1073system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1074system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1075system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1076system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1077system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1082system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1083system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1084system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1085system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1086system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1087system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1088system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1089system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 947system.toL2Bus.throughput 118384606 # Throughput (bytes/s) 948system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution 949system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution 950system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution 951system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution 952system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution 953system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution 954system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution 955system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution 956system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution 957system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution 958system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes) 959system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes) 960system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes) 961system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes) 962system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes) 963system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes) 964system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes) 965system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes) 966system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes) 967system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes) 968system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes) 969system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes) 970system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes) 971system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes) 972system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes) 973system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes) 974system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes) 975system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes) 976system.toL2Bus.data_through_bus 137140510 # Total data (bytes) 977system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes) 978system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks) | 1090system.toL2Bus.throughput 118413539 # Throughput (bytes/s) 1091system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution 1092system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution 1093system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution 1094system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution 1095system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution 1096system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution 1097system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution 1098system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution 1099system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution 1100system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution 1101system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes) 1102system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes) 1103system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes) 1104system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes) 1105system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes) 1106system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes) 1107system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes) 1108system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes) 1109system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes) 1110system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes) 1111system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes) 1112system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes) 1113system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes) 1114system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes) 1115system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes) 1116system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes) 1117system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes) 1118system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes) 1119system.toL2Bus.data_through_bus 137274438 # Total data (bytes) 1120system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes) 1121system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks) |
| 979system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) | 1122system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) |
| 980system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks) | 1123system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks) |
| 981system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) | 1124system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 982system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks) | 1125system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks) |
| 983system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) | 1126system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 984system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) | 1127system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) |
| 985system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1128system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 986system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks) | 1129system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks) |
| 987system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1130system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 988system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks) | 1131system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks) |
| 989system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) | 1132system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) |
| 990system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks) | 1133system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks) |
| 991system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) | 1134system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) |
| 992system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) | 1135system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) |
| 993system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) | 1136system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) |
| 994system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) | 1137system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks) |
| 995system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) | 1138system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) |
| 996system.iobus.throughput 45439063 # Throughput (bytes/s) 997system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution 998system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution | 1139system.iobus.throughput 45405912 # Throughput (bytes/s) 1140system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution 1141system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution |
| 999system.iobus.trans_dist::WriteReq 7946 # Transaction distribution 1000system.iobus.trans_dist::WriteResp 7946 # Transaction distribution 1001system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) | 1142system.iobus.trans_dist::WriteReq 7946 # Transaction distribution 1143system.iobus.trans_dist::WriteResp 7946 # Transaction distribution 1144system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) |
| 1002system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) | 1145system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes) |
| 1003system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) | 1146system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 1004system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) | 1147system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) |
| 1005system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1006system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1007system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) 1008system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1009system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1010system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1011system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1012system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1013system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1014system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1015system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1016system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1017system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1018system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1019system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1020system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1021system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1022system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 1148system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1149system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1150system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) 1151system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1152system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1153system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1154system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1155system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1156system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1157system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1158system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1159system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 1024system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes) | 1167system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes) |
| 1025system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 1026system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) | 1168system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) |
| 1027system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes) | 1170system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes) |
| 1028system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) | 1171system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) |
| 1029system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) | 1172system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes) |
| 1030system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) | 1173system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) |
| 1031system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) | 1174system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) |
| 1032system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1033system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1034system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) 1035system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1036system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1037system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1038system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1039system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1040system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1041system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1042system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1043system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1044system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1045system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1175system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1176system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1177system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) 1178system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1179system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1180system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1181system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 1051system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes) | 1194system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) |
| 1052system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 1053system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) | 1195system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) |
| 1054system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes) 1055system.iobus.data_through_bus 54294390 # Total data (bytes) | 1197system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.data_through_bus 54294406 # Total data (bytes) |
| 1056system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) 1057system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1199system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) 1200system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1058system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) | 1201system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks) |
| 1059system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1060system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1061system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1202system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1203system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1204system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1062system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) | 1205system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) |
| 1063system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1064system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1065system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1066system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1067system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1068system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) 1069system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1070system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) --- 25 unchanged lines hidden (view full) --- 1096system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1097system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1098system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1099system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1100system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1101system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1102system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1103system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) | 1206system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1207system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1208system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1209system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1210system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1211system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) 1212system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1213system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) --- 25 unchanged lines hidden (view full) --- 1239system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1240system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1241system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1242system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1244system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1246system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) |
| 1104system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks) | 1247system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) |
| 1105system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) | 1248system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1106system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks) | 1249system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks) |
| 1107system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1108system.cpu0.dtb.inst_hits 0 # ITB inst hits 1109system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1250system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1251system.cpu0.dtb.inst_hits 0 # ITB inst hits 1252system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1110system.cpu0.dtb.read_hits 9653247 # DTB read hits 1111system.cpu0.dtb.read_misses 3738 # DTB read misses 1112system.cpu0.dtb.write_hits 7597488 # DTB write hits 1113system.cpu0.dtb.write_misses 1585 # DTB write misses | 1253system.cpu0.dtb.read_hits 9652613 # DTB read hits 1254system.cpu0.dtb.read_misses 3746 # DTB read misses 1255system.cpu0.dtb.write_hits 7596890 # DTB write hits 1256system.cpu0.dtb.write_misses 1582 # DTB write misses |
| 1114system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1115system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1116system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1117system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1118system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB 1119system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1257system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1258system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1259system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1260system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1261system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB 1262system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1120system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch | 1263system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch |
| 1121system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1122system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions | 1264system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1265system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions |
| 1123system.cpu0.dtb.read_accesses 9656985 # DTB read accesses 1124system.cpu0.dtb.write_accesses 7599073 # DTB write accesses | 1266system.cpu0.dtb.read_accesses 9656359 # DTB read accesses 1267system.cpu0.dtb.write_accesses 7598472 # DTB write accesses |
| 1125system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1268system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1126system.cpu0.dtb.hits 17250735 # DTB hits 1127system.cpu0.dtb.misses 5323 # DTB misses 1128system.cpu0.dtb.accesses 17256058 # DTB accesses 1129system.cpu0.itb.inst_hits 43297764 # ITB inst hits | 1269system.cpu0.dtb.hits 17249503 # DTB hits 1270system.cpu0.dtb.misses 5328 # DTB misses 1271system.cpu0.dtb.accesses 17254831 # DTB accesses 1272system.cpu0.itb.inst_hits 43298526 # ITB inst hits |
| 1130system.cpu0.itb.inst_misses 2205 # ITB inst misses 1131system.cpu0.itb.read_hits 0 # DTB read hits 1132system.cpu0.itb.read_misses 0 # DTB read misses 1133system.cpu0.itb.write_hits 0 # DTB write hits 1134system.cpu0.itb.write_misses 0 # DTB write misses 1135system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1136system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1137system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1138system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1139system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 1140system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1141system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1142system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1143system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1144system.cpu0.itb.read_accesses 0 # DTB read accesses 1145system.cpu0.itb.write_accesses 0 # DTB write accesses | 1273system.cpu0.itb.inst_misses 2205 # ITB inst misses 1274system.cpu0.itb.read_hits 0 # DTB read hits 1275system.cpu0.itb.read_misses 0 # DTB read misses 1276system.cpu0.itb.write_hits 0 # DTB write hits 1277system.cpu0.itb.write_misses 0 # DTB write misses 1278system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1279system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1280system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1281system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1282system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 1283system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1284system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1285system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1286system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1287system.cpu0.itb.read_accesses 0 # DTB read accesses 1288system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1146system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses 1147system.cpu0.itb.hits 43297764 # DTB hits | 1289system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses 1290system.cpu0.itb.hits 43298526 # DTB hits |
| 1148system.cpu0.itb.misses 2205 # DTB misses | 1291system.cpu0.itb.misses 2205 # DTB misses |
| 1149system.cpu0.itb.accesses 43299969 # DTB accesses 1150system.cpu0.numCycles 2389767161 # number of cpu cycles simulated | 1292system.cpu0.itb.accesses 43300731 # DTB accesses 1293system.cpu0.numCycles 2391512647 # number of cpu cycles simulated |
| 1151system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1152system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1294system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1295system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1153system.cpu0.committedInsts 42570861 # Number of instructions committed 1154system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed 1155system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses | 1296system.cpu0.committedInsts 42571581 # Number of instructions committed 1297system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed 1298system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses |
| 1156system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses | 1299system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses |
| 1157system.cpu0.num_func_calls 1403492 # number of times a function call or return occured 1158system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls 1159system.cpu0.num_int_insts 48060351 # number of integer instructions | 1300system.cpu0.num_func_calls 1403638 # number of times a function call or return occured 1301system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls 1302system.cpu0.num_int_insts 48058821 # number of integer instructions |
| 1160system.cpu0.num_fp_insts 3860 # number of float instructions | 1303system.cpu0.num_fp_insts 3860 # number of float instructions |
| 1161system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read 1162system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written | 1304system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read 1305system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written |
| 1163system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1164system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written | 1306system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1307system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written |
| 1165system.cpu0.num_mem_refs 18020156 # number of memory refs 1166system.cpu0.num_load_insts 10037111 # Number of load instructions 1167system.cpu0.num_store_insts 7983045 # Number of store instructions 1168system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles 1169system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles 1170system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles 1171system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles | 1308system.cpu0.num_mem_refs 18019009 # number of memory refs 1309system.cpu0.num_load_insts 10036459 # Number of load instructions 1310system.cpu0.num_store_insts 7982550 # Number of store instructions 1311system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles 1312system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles 1313system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles 1314system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles |
| 1172system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1315system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1173system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed 1174system.cpu0.icache.tags.replacements 490078 # number of replacements 1175system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use 1176system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks. 1177system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks. 1178system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks. 1179system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit. 1180system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor 1181system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy 1182system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy 1183system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits 1184system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits 1185system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits 1186system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits 1187system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits 1188system.cpu0.icache.overall_hits::total 42807156 # number of overall hits 1189system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses 1190system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses 1191system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses 1192system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses 1193system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses 1194system.cpu0.icache.overall_misses::total 490591 # number of overall misses 1195system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles 1196system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles 1197system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles 1198system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles 1199system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles 1200system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles 1201system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses) 1202system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses) 1203system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses 1204system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses 1205system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses 1206system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses 1207system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses 1208system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses 1209system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses 1210system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses 1211system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses 1212system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses 1213system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency 1214system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency 1215system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency 1216system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency 1217system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency 1218system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency | 1316system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed 1317system.cpu0.icache.tags.replacements 490259 # number of replacements 1318system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use 1319system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks. 1320system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks. 1321system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks. 1322system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit. 1323system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor 1324system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy 1325system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy 1326system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits 1327system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits 1328system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits 1329system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits 1330system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits 1331system.cpu0.icache.overall_hits::total 42807737 # number of overall hits 1332system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses 1333system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses 1334system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses 1335system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses 1336system.cpu0.icache.overall_misses::cpu0.inst 490772 # number of overall misses 1337system.cpu0.icache.overall_misses::total 490772 # number of overall misses 1338system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6820513233 # number of ReadReq miss cycles 1339system.cpu0.icache.ReadReq_miss_latency::total 6820513233 # number of ReadReq miss cycles 1340system.cpu0.icache.demand_miss_latency::cpu0.inst 6820513233 # number of demand (read+write) miss cycles 1341system.cpu0.icache.demand_miss_latency::total 6820513233 # number of demand (read+write) miss cycles 1342system.cpu0.icache.overall_miss_latency::cpu0.inst 6820513233 # number of overall miss cycles 1343system.cpu0.icache.overall_miss_latency::total 6820513233 # number of overall miss cycles 1344system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298509 # number of ReadReq accesses(hits+misses) 1345system.cpu0.icache.ReadReq_accesses::total 43298509 # number of ReadReq accesses(hits+misses) 1346system.cpu0.icache.demand_accesses::cpu0.inst 43298509 # number of demand (read+write) accesses 1347system.cpu0.icache.demand_accesses::total 43298509 # number of demand (read+write) accesses 1348system.cpu0.icache.overall_accesses::cpu0.inst 43298509 # number of overall (read+write) accesses 1349system.cpu0.icache.overall_accesses::total 43298509 # number of overall (read+write) accesses 1350system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011335 # miss rate for ReadReq accesses 1351system.cpu0.icache.ReadReq_miss_rate::total 0.011335 # miss rate for ReadReq accesses 1352system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011335 # miss rate for demand accesses 1353system.cpu0.icache.demand_miss_rate::total 0.011335 # miss rate for demand accesses 1354system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011335 # miss rate for overall accesses 1355system.cpu0.icache.overall_miss_rate::total 0.011335 # miss rate for overall accesses 1356system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.519078 # average ReadReq miss latency 1357system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.519078 # average ReadReq miss latency 1358system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency 1359system.cpu0.icache.demand_avg_miss_latency::total 13897.519078 # average overall miss latency 1360system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency 1361system.cpu0.icache.overall_avg_miss_latency::total 13897.519078 # average overall miss latency |
| 1219system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1220system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1221system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1222system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1223system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1224system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1225system.cpu0.icache.fast_writes 0 # number of fast writes performed 1226system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1362system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1363system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1364system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1365system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1366system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1367system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1368system.cpu0.icache.fast_writes 0 # number of fast writes performed 1369system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1227system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses 1228system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses 1229system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses 1230system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses 1231system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses 1232system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses 1233system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles 1234system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles 1235system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles 1237system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles 1238system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles 1239system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles 1240system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles 1241system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles 1242system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles 1243system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses 1244system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses 1245system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses 1246system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses 1247system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses 1248system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses 1249system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency 1250system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency 1251system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency 1252system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency 1253system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency 1254system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency | 1370system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490772 # number of ReadReq MSHR misses 1371system.cpu0.icache.ReadReq_mshr_misses::total 490772 # number of ReadReq MSHR misses 1372system.cpu0.icache.demand_mshr_misses::cpu0.inst 490772 # number of demand (read+write) MSHR misses 1373system.cpu0.icache.demand_mshr_misses::total 490772 # number of demand (read+write) MSHR misses 1374system.cpu0.icache.overall_mshr_misses::cpu0.inst 490772 # number of overall MSHR misses 1375system.cpu0.icache.overall_mshr_misses::total 490772 # number of overall MSHR misses 1376system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5836336767 # number of ReadReq MSHR miss cycles 1377system.cpu0.icache.ReadReq_mshr_miss_latency::total 5836336767 # number of ReadReq MSHR miss cycles 1378system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5836336767 # number of demand (read+write) MSHR miss cycles 1379system.cpu0.icache.demand_mshr_miss_latency::total 5836336767 # number of demand (read+write) MSHR miss cycles 1380system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5836336767 # number of overall MSHR miss cycles 1381system.cpu0.icache.overall_mshr_miss_latency::total 5836336767 # number of overall MSHR miss cycles 1382system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393250 # number of ReadReq MSHR uncacheable cycles 1383system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles 1384system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles 1385system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles 1386system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses 1387system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses 1388system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses 1389system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses 1390system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses 1391system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses 1392system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency 1393system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11892.155149 # average ReadReq mshr miss latency 1394system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency 1395system.cpu0.icache.demand_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency 1396system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency 1397system.cpu0.icache.overall_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency |
| 1255system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1256system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1257system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1258system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1259system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1398system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1399system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1400system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1401system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1402system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1260system.cpu0.dcache.tags.replacements 406634 # number of replacements 1261system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use 1262system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks. 1263system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks. 1264system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks. 1265system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit. 1266system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor 1267system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy 1268system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy 1269system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits 1270system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits 1271system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # number of WriteReq hits 1272system.cpu0.dcache.WriteReq_hits::total 6494912 # number of WriteReq hits 1273system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156532 # number of LoadLockedReq hits 1274system.cpu0.dcache.LoadLockedReq_hits::total 156532 # number of LoadLockedReq hits 1275system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159004 # number of StoreCondReq hits 1276system.cpu0.dcache.StoreCondReq_hits::total 159004 # number of StoreCondReq hits 1277system.cpu0.dcache.demand_hits::cpu0.data 15632259 # number of demand (read+write) hits 1278system.cpu0.dcache.demand_hits::total 15632259 # number of demand (read+write) hits 1279system.cpu0.dcache.overall_hits::cpu0.data 15632259 # number of overall hits 1280system.cpu0.dcache.overall_hits::total 15632259 # number of overall hits 1281system.cpu0.dcache.ReadReq_misses::cpu0.data 263669 # number of ReadReq misses 1282system.cpu0.dcache.ReadReq_misses::total 263669 # number of ReadReq misses 1283system.cpu0.dcache.WriteReq_misses::cpu0.data 176685 # number of WriteReq misses 1284system.cpu0.dcache.WriteReq_misses::total 176685 # number of WriteReq misses 1285system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9910 # number of LoadLockedReq misses 1286system.cpu0.dcache.LoadLockedReq_misses::total 9910 # number of LoadLockedReq misses 1287system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7384 # number of StoreCondReq misses 1288system.cpu0.dcache.StoreCondReq_misses::total 7384 # number of StoreCondReq misses 1289system.cpu0.dcache.demand_misses::cpu0.data 440354 # number of demand (read+write) misses 1290system.cpu0.dcache.demand_misses::total 440354 # number of demand (read+write) misses 1291system.cpu0.dcache.overall_misses::cpu0.data 440354 # number of overall misses 1292system.cpu0.dcache.overall_misses::total 440354 # number of overall misses 1293system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3876875497 # number of ReadReq miss cycles 1294system.cpu0.dcache.ReadReq_miss_latency::total 3876875497 # number of ReadReq miss cycles 1295system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7541622539 # number of WriteReq miss cycles 1296system.cpu0.dcache.WriteReq_miss_latency::total 7541622539 # number of WriteReq miss cycles 1297system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98733750 # number of LoadLockedReq miss cycles 1298system.cpu0.dcache.LoadLockedReq_miss_latency::total 98733750 # number of LoadLockedReq miss cycles 1299system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40506385 # number of StoreCondReq miss cycles 1300system.cpu0.dcache.StoreCondReq_miss_latency::total 40506385 # number of StoreCondReq miss cycles 1301system.cpu0.dcache.demand_miss_latency::cpu0.data 11418498036 # number of demand (read+write) miss cycles 1302system.cpu0.dcache.demand_miss_latency::total 11418498036 # number of demand (read+write) miss cycles 1303system.cpu0.dcache.overall_miss_latency::cpu0.data 11418498036 # number of overall miss cycles 1304system.cpu0.dcache.overall_miss_latency::total 11418498036 # number of overall miss cycles 1305system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401016 # number of ReadReq accesses(hits+misses) 1306system.cpu0.dcache.ReadReq_accesses::total 9401016 # number of ReadReq accesses(hits+misses) 1307system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671597 # number of WriteReq accesses(hits+misses) 1308system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses) 1309system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses) 1310system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses) 1311system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses) 1312system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses) 1313system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses 1314system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses 1315system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses 1316system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses 1317system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # miss rate for ReadReq accesses 1318system.cpu0.dcache.ReadReq_miss_rate::total 0.028047 # miss rate for ReadReq accesses 1319system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026483 # miss rate for WriteReq accesses 1320system.cpu0.dcache.WriteReq_miss_rate::total 0.026483 # miss rate for WriteReq accesses 1321system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059540 # miss rate for LoadLockedReq accesses 1322system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059540 # miss rate for LoadLockedReq accesses 1323system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044378 # miss rate for StoreCondReq accesses 1324system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044378 # miss rate for StoreCondReq accesses 1325system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses 1326system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses 1327system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses 1328system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses 1329system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616 # average ReadReq miss latency 1330system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616 # average ReadReq miss latency 1331system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994 # average WriteReq miss latency 1332system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994 # average WriteReq miss latency 1333system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9963.042381 # average LoadLockedReq miss latency 1334system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9963.042381 # average LoadLockedReq miss latency 1335system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5485.696777 # average StoreCondReq miss latency 1336system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5485.696777 # average StoreCondReq miss latency 1337system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency 1338system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819 # average overall miss latency 1339system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency 1340system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency | 1403system.cpu0.dcache.tags.replacements 407019 # number of replacements 1404system.cpu0.dcache.tags.tagsinuse 470.951702 # Cycle average of tags in use 1405system.cpu0.dcache.tags.total_refs 15966189 # Total number of references to valid blocks. 1406system.cpu0.dcache.tags.sampled_refs 407531 # Sample count of references to valid blocks. 1407system.cpu0.dcache.tags.avg_refs 39.177852 # Average number of references to valid blocks. 1408system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit. 1409system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.951702 # Average occupied blocks per requestor 1410system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919828 # Average percentage of cache occupancy 1411system.cpu0.dcache.tags.occ_percent::total 0.919828 # Average percentage of cache occupancy 1412system.cpu0.dcache.ReadReq_hits::cpu0.data 9136364 # number of ReadReq hits 1413system.cpu0.dcache.ReadReq_hits::total 9136364 # number of ReadReq hits 1414system.cpu0.dcache.WriteReq_hits::cpu0.data 6494337 # number of WriteReq hits 1415system.cpu0.dcache.WriteReq_hits::total 6494337 # number of WriteReq hits 1416system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156491 # number of LoadLockedReq hits 1417system.cpu0.dcache.LoadLockedReq_hits::total 156491 # number of LoadLockedReq hits 1418system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158920 # number of StoreCondReq hits 1419system.cpu0.dcache.StoreCondReq_hits::total 158920 # number of StoreCondReq hits 1420system.cpu0.dcache.demand_hits::cpu0.data 15630701 # number of demand (read+write) hits 1421system.cpu0.dcache.demand_hits::total 15630701 # number of demand (read+write) hits 1422system.cpu0.dcache.overall_hits::cpu0.data 15630701 # number of overall hits 1423system.cpu0.dcache.overall_hits::total 15630701 # number of overall hits 1424system.cpu0.dcache.ReadReq_misses::cpu0.data 264039 # number of ReadReq misses 1425system.cpu0.dcache.ReadReq_misses::total 264039 # number of ReadReq misses 1426system.cpu0.dcache.WriteReq_misses::cpu0.data 176698 # number of WriteReq misses 1427system.cpu0.dcache.WriteReq_misses::total 176698 # number of WriteReq misses 1428system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9925 # number of LoadLockedReq misses 1429system.cpu0.dcache.LoadLockedReq_misses::total 9925 # number of LoadLockedReq misses 1430system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7429 # number of StoreCondReq misses 1431system.cpu0.dcache.StoreCondReq_misses::total 7429 # number of StoreCondReq misses 1432system.cpu0.dcache.demand_misses::cpu0.data 440737 # number of demand (read+write) misses 1433system.cpu0.dcache.demand_misses::total 440737 # number of demand (read+write) misses 1434system.cpu0.dcache.overall_misses::cpu0.data 440737 # number of overall misses 1435system.cpu0.dcache.overall_misses::total 440737 # number of overall misses 1436system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3925412746 # number of ReadReq miss cycles 1437system.cpu0.dcache.ReadReq_miss_latency::total 3925412746 # number of ReadReq miss cycles 1438system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7893125788 # number of WriteReq miss cycles 1439system.cpu0.dcache.WriteReq_miss_latency::total 7893125788 # number of WriteReq miss cycles 1440system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98805250 # number of LoadLockedReq miss cycles 1441system.cpu0.dcache.LoadLockedReq_miss_latency::total 98805250 # number of LoadLockedReq miss cycles 1442system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40843887 # number of StoreCondReq miss cycles 1443system.cpu0.dcache.StoreCondReq_miss_latency::total 40843887 # number of StoreCondReq miss cycles 1444system.cpu0.dcache.demand_miss_latency::cpu0.data 11818538534 # number of demand (read+write) miss cycles 1445system.cpu0.dcache.demand_miss_latency::total 11818538534 # number of demand (read+write) miss cycles 1446system.cpu0.dcache.overall_miss_latency::cpu0.data 11818538534 # number of overall miss cycles 1447system.cpu0.dcache.overall_miss_latency::total 11818538534 # number of overall miss cycles 1448system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400403 # number of ReadReq accesses(hits+misses) 1449system.cpu0.dcache.ReadReq_accesses::total 9400403 # number of ReadReq accesses(hits+misses) 1450system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671035 # number of WriteReq accesses(hits+misses) 1451system.cpu0.dcache.WriteReq_accesses::total 6671035 # number of WriteReq accesses(hits+misses) 1452system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166416 # number of LoadLockedReq accesses(hits+misses) 1453system.cpu0.dcache.LoadLockedReq_accesses::total 166416 # number of LoadLockedReq accesses(hits+misses) 1454system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166349 # number of StoreCondReq accesses(hits+misses) 1455system.cpu0.dcache.StoreCondReq_accesses::total 166349 # number of StoreCondReq accesses(hits+misses) 1456system.cpu0.dcache.demand_accesses::cpu0.data 16071438 # number of demand (read+write) accesses 1457system.cpu0.dcache.demand_accesses::total 16071438 # number of demand (read+write) accesses 1458system.cpu0.dcache.overall_accesses::cpu0.data 16071438 # number of overall (read+write) accesses 1459system.cpu0.dcache.overall_accesses::total 16071438 # number of overall (read+write) accesses 1460system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028088 # miss rate for ReadReq accesses 1461system.cpu0.dcache.ReadReq_miss_rate::total 0.028088 # miss rate for ReadReq accesses 1462system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026487 # miss rate for WriteReq accesses 1463system.cpu0.dcache.WriteReq_miss_rate::total 0.026487 # miss rate for WriteReq accesses 1464system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059640 # miss rate for LoadLockedReq accesses 1465system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059640 # miss rate for LoadLockedReq accesses 1466system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044659 # miss rate for StoreCondReq accesses 1467system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044659 # miss rate for StoreCondReq accesses 1468system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027424 # miss rate for demand accesses 1469system.cpu0.dcache.demand_miss_rate::total 0.027424 # miss rate for demand accesses 1470system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027424 # miss rate for overall accesses 1471system.cpu0.dcache.overall_miss_rate::total 0.027424 # miss rate for overall accesses 1472system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14866.791444 # average ReadReq miss latency 1473system.cpu0.dcache.ReadReq_avg_miss_latency::total 14866.791444 # average ReadReq miss latency 1474system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency 1475system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency 1476system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency 1477system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency 1478system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency 1479system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency 1480system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency 1481system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency 1482system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency 1483system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency |
| 1341system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1342system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1343system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1344system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1345system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1346system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1347system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1348system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1484system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1485system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1486system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1487system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1488system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1489system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1490system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1491system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1349system.cpu0.dcache.writebacks::writebacks 376568 # number of writebacks 1350system.cpu0.dcache.writebacks::total 376568 # number of writebacks 1351system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263669 # number of ReadReq MSHR misses 1352system.cpu0.dcache.ReadReq_mshr_misses::total 263669 # number of ReadReq MSHR misses 1353system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176685 # number of WriteReq MSHR misses 1354system.cpu0.dcache.WriteReq_mshr_misses::total 176685 # number of WriteReq MSHR misses 1355system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9910 # number of LoadLockedReq MSHR misses 1356system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9910 # number of LoadLockedReq MSHR misses 1357system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7379 # number of StoreCondReq MSHR misses 1358system.cpu0.dcache.StoreCondReq_mshr_misses::total 7379 # number of StoreCondReq MSHR misses 1359system.cpu0.dcache.demand_mshr_misses::cpu0.data 440354 # number of demand (read+write) MSHR misses 1360system.cpu0.dcache.demand_mshr_misses::total 440354 # number of demand (read+write) MSHR misses 1361system.cpu0.dcache.overall_mshr_misses::cpu0.data 440354 # number of overall MSHR misses 1362system.cpu0.dcache.overall_mshr_misses::total 440354 # number of overall MSHR misses 1363system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3344880503 # number of ReadReq MSHR miss cycles 1364system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3344880503 # number of ReadReq MSHR miss cycles 1365system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7142186461 # number of WriteReq MSHR miss cycles 1366system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7142186461 # number of WriteReq MSHR miss cycles 1367system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78848250 # number of LoadLockedReq MSHR miss cycles 1368system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78848250 # number of LoadLockedReq MSHR miss cycles 1369system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25751615 # number of StoreCondReq MSHR miss cycles 1370system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25751615 # number of StoreCondReq MSHR miss cycles | 1492system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks 1493system.cpu0.dcache.writebacks::total 376552 # number of writebacks 1494system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses 1495system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses 1496system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses 1497system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses 1498system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses 1499system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses 1500system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses 1501system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses 1502system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses 1503system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses 1504system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses 1505system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses 1506system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles 1507system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles 1508system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles 1509system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles 1510system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles 1511system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles 1512system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles 1513system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles |
| 1371system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles 1372system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles | 1514system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles 1515system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles |
| 1373system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10487066964 # number of demand (read+write) MSHR miss cycles 1374system.cpu0.dcache.demand_mshr_miss_latency::total 10487066964 # number of demand (read+write) MSHR miss cycles 1375system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10487066964 # number of overall MSHR miss cycles 1376system.cpu0.dcache.overall_mshr_miss_latency::total 10487066964 # number of overall MSHR miss cycles 1377system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764220500 # number of ReadReq MSHR uncacheable cycles 1378system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764220500 # number of ReadReq MSHR uncacheable cycles 1379system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807115461 # number of WriteReq MSHR uncacheable cycles 1380system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807115461 # number of WriteReq MSHR uncacheable cycles 1381system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39571335961 # number of overall MSHR uncacheable cycles 1382system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles 1383system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028047 # mshr miss rate for ReadReq accesses 1384system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028047 # mshr miss rate for ReadReq accesses 1385system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026483 # mshr miss rate for WriteReq accesses 1386system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026483 # mshr miss rate for WriteReq accesses 1387system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059540 # mshr miss rate for LoadLockedReq accesses 1388system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059540 # mshr miss rate for LoadLockedReq accesses 1389system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044348 # mshr miss rate for StoreCondReq accesses 1390system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044348 # mshr miss rate for StoreCondReq accesses 1391system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses 1392system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses 1393system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses 1394system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses 1395system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency 1396system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency 1397system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency 1398system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency 1399system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency 1400system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency 1401system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency 1402system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency | 1516system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles 1517system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles 1518system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles 1519system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles 1520system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles 1521system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles 1522system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles 1523system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles 1524system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles 1525system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles 1526system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses 1527system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses 1528system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses 1529system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses 1530system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses 1531system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses 1532system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses 1533system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses 1534system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses 1535system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses 1536system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses 1537system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses 1538system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency 1539system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency 1540system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency 1541system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency 1542system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency 1543system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency 1544system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency 1545system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency |
| 1403system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1404system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1546system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1547system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1405system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency 1406system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency 1407system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency 1408system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency | 1548system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency 1549system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency 1550system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency 1551system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency |
| 1409system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1410system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1411system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1412system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1413system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1414system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1415system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1416system.cpu1.dtb.inst_hits 0 # ITB inst hits 1417system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1552system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1553system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1554system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1555system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1556system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1557system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1558system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1559system.cpu1.dtb.inst_hits 0 # ITB inst hits 1560system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1418system.cpu1.dtb.read_hits 5705173 # DTB read hits 1419system.cpu1.dtb.read_misses 3576 # DTB read misses 1420system.cpu1.dtb.write_hits 3872049 # DTB write hits 1421system.cpu1.dtb.write_misses 645 # DTB write misses | 1561system.cpu1.dtb.read_hits 5708064 # DTB read hits 1562system.cpu1.dtb.read_misses 3582 # DTB read misses 1563system.cpu1.dtb.write_hits 3874465 # DTB write hits 1564system.cpu1.dtb.write_misses 647 # DTB write misses |
| 1422system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1423system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1424system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1425system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1426system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB 1427system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1565system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1566system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1567system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1568system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1569system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB 1570system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1428system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch | 1571system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch |
| 1429system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1430system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions | 1572system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1573system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions |
| 1431system.cpu1.dtb.read_accesses 5708749 # DTB read accesses 1432system.cpu1.dtb.write_accesses 3872694 # DTB write accesses | 1574system.cpu1.dtb.read_accesses 5711646 # DTB read accesses 1575system.cpu1.dtb.write_accesses 3875112 # DTB write accesses |
| 1433system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1576system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1434system.cpu1.dtb.hits 9577222 # DTB hits 1435system.cpu1.dtb.misses 4221 # DTB misses 1436system.cpu1.dtb.accesses 9581443 # DTB accesses 1437system.cpu1.itb.inst_hits 19377969 # ITB inst hits | 1577system.cpu1.dtb.hits 9582529 # DTB hits 1578system.cpu1.dtb.misses 4229 # DTB misses 1579system.cpu1.dtb.accesses 9586758 # DTB accesses 1580system.cpu1.itb.inst_hits 19382020 # ITB inst hits |
| 1438system.cpu1.itb.inst_misses 2171 # ITB inst misses 1439system.cpu1.itb.read_hits 0 # DTB read hits 1440system.cpu1.itb.read_misses 0 # DTB read misses 1441system.cpu1.itb.write_hits 0 # DTB write hits 1442system.cpu1.itb.write_misses 0 # DTB write misses 1443system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1444system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1445system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1446system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1447system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 1448system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1449system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1450system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1451system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1452system.cpu1.itb.read_accesses 0 # DTB read accesses 1453system.cpu1.itb.write_accesses 0 # DTB write accesses | 1581system.cpu1.itb.inst_misses 2171 # ITB inst misses 1582system.cpu1.itb.read_hits 0 # DTB read hits 1583system.cpu1.itb.read_misses 0 # DTB read misses 1584system.cpu1.itb.write_hits 0 # DTB write hits 1585system.cpu1.itb.write_misses 0 # DTB write misses 1586system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1587system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1588system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1589system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1590system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 1591system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1592system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1593system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1594system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1595system.cpu1.itb.read_accesses 0 # DTB read accesses 1596system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1454system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses 1455system.cpu1.itb.hits 19377969 # DTB hits | 1597system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses 1598system.cpu1.itb.hits 19382020 # DTB hits |
| 1456system.cpu1.itb.misses 2171 # DTB misses | 1599system.cpu1.itb.misses 2171 # DTB misses |
| 1457system.cpu1.itb.accesses 19380140 # DTB accesses 1458system.cpu1.numCycles 2388332817 # number of cpu cycles simulated | 1600system.cpu1.itb.accesses 19384191 # DTB accesses 1601system.cpu1.numCycles 2390063941 # number of cpu cycles simulated |
| 1459system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1460system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1602system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1603system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1461system.cpu1.committedInsts 18797412 # Number of instructions committed 1462system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed 1463system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses | 1604system.cpu1.committedInsts 18801432 # Number of instructions committed 1605system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed 1606system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses |
| 1464system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses | 1607system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses |
| 1465system.cpu1.num_func_calls 796668 # number of times a function call or return occured 1466system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls 1467system.cpu1.num_int_insts 22263010 # number of integer instructions | 1608system.cpu1.num_func_calls 796781 # number of times a function call or return occured 1609system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls 1610system.cpu1.num_int_insts 22272671 # number of integer instructions |
| 1468system.cpu1.num_fp_insts 6793 # number of float instructions | 1611system.cpu1.num_fp_insts 6793 # number of float instructions |
| 1469system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read 1470system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written | 1612system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read 1613system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written |
| 1471system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1472system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written | 1614system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1615system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written |
| 1473system.cpu1.num_mem_refs 10012651 # number of memory refs 1474system.cpu1.num_load_insts 5981805 # Number of load instructions 1475system.cpu1.num_store_insts 4030846 # Number of store instructions 1476system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles 1477system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles 1478system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles 1479system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles | 1616system.cpu1.num_mem_refs 10017952 # number of memory refs 1617system.cpu1.num_load_insts 5984754 # Number of load instructions 1618system.cpu1.num_store_insts 4033198 # Number of store instructions 1619system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles 1620system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles 1621system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles 1622system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles |
| 1480system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1623system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1481system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed 1482system.cpu1.icache.tags.replacements 376539 # number of replacements 1483system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use 1484system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks. 1485system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks. 1486system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks. 1487system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit. 1488system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor 1489system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy 1490system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy 1491system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits 1492system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits 1493system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits 1494system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits 1495system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits 1496system.cpu1.icache.overall_hits::total 19000914 # number of overall hits 1497system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses 1498system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses 1499system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses 1500system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses 1501system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses 1502system.cpu1.icache.overall_misses::total 377051 # number of overall misses 1503system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles 1504system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles 1505system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles 1506system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles 1507system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles 1508system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles 1509system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses) 1510system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses) 1511system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses 1512system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses 1513system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses 1514system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses 1515system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses 1516system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses 1517system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses 1518system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses 1519system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses 1520system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses 1521system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency 1522system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency 1523system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency 1524system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency 1525system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency 1526system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency | 1624system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed 1625system.cpu1.icache.tags.replacements 376793 # number of replacements 1626system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use 1627system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks. 1628system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks. 1629system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks. 1630system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit. 1631system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor 1632system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy 1633system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy 1634system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits 1635system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits 1636system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits 1637system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits 1638system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits 1639system.cpu1.icache.overall_hits::total 19004711 # number of overall hits 1640system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses 1641system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses 1642system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses 1643system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses 1644system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses 1645system.cpu1.icache.overall_misses::total 377305 # number of overall misses 1646system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles 1647system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles 1648system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles 1649system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles 1650system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles 1651system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles 1652system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses) 1653system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses) 1654system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses 1655system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses 1656system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses 1657system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses 1658system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses 1659system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses 1660system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses 1661system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses 1662system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses 1663system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses 1664system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency 1665system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency 1666system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency 1667system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency 1668system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency 1669system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency |
| 1527system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1528system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1529system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1530system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1531system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1532system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1533system.cpu1.icache.fast_writes 0 # number of fast writes performed 1534system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1670system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1671system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1672system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1673system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1674system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1675system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1676system.cpu1.icache.fast_writes 0 # number of fast writes performed 1677system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1535system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses 1536system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses 1537system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses 1538system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses 1539system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses 1540system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses 1541system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles 1542system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles 1543system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles 1544system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles 1545system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles 1546system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles 1547system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles 1548system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles 1549system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles 1550system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles 1551system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses 1552system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses 1553system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses 1554system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses 1555system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses 1556system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses 1557system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency 1558system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729 # average ReadReq mshr miss latency 1559system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency 1560system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency 1561system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency 1562system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency | 1678system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses 1679system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses 1680system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses 1681system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses 1682system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses 1683system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses 1684system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles 1685system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles 1686system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles 1687system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles 1688system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles 1689system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles 1690system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles 1691system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles 1692system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles 1693system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles 1694system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses 1695system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses 1696system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses 1697system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses 1698system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses 1699system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses 1700system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency 1701system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency 1702system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency 1703system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency 1704system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency 1705system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency |
| 1563system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1564system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1565system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1566system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1567system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1706system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1707system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1708system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1709system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1710system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1568system.cpu1.dcache.tags.replacements 220336 # number of replacements 1569system.cpu1.dcache.tags.tagsinuse 471.526784 # Cycle average of tags in use 1570system.cpu1.dcache.tags.total_refs 8228665 # Total number of references to valid blocks. 1571system.cpu1.dcache.tags.sampled_refs 220703 # Sample count of references to valid blocks. 1572system.cpu1.dcache.tags.avg_refs 37.283884 # Average number of references to valid blocks. 1573system.cpu1.dcache.tags.warmup_cycle 106211109000 # Cycle when the warmup percentage was hit. 1574system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.526784 # Average occupied blocks per requestor 1575system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920951 # Average percentage of cache occupancy 1576system.cpu1.dcache.tags.occ_percent::total 0.920951 # Average percentage of cache occupancy 1577system.cpu1.dcache.ReadReq_hits::cpu1.data 4388185 # number of ReadReq hits 1578system.cpu1.dcache.ReadReq_hits::total 4388185 # number of ReadReq hits 1579system.cpu1.dcache.WriteReq_hits::cpu1.data 3672248 # number of WriteReq hits 1580system.cpu1.dcache.WriteReq_hits::total 3672248 # number of WriteReq hits 1581system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73451 # number of LoadLockedReq hits 1582system.cpu1.dcache.LoadLockedReq_hits::total 73451 # number of LoadLockedReq hits 1583system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73727 # number of StoreCondReq hits 1584system.cpu1.dcache.StoreCondReq_hits::total 73727 # number of StoreCondReq hits 1585system.cpu1.dcache.demand_hits::cpu1.data 8060433 # number of demand (read+write) hits 1586system.cpu1.dcache.demand_hits::total 8060433 # number of demand (read+write) hits 1587system.cpu1.dcache.overall_hits::cpu1.data 8060433 # number of overall hits 1588system.cpu1.dcache.overall_hits::total 8060433 # number of overall hits 1589system.cpu1.dcache.ReadReq_misses::cpu1.data 133748 # number of ReadReq misses 1590system.cpu1.dcache.ReadReq_misses::total 133748 # number of ReadReq misses 1591system.cpu1.dcache.WriteReq_misses::cpu1.data 112730 # number of WriteReq misses 1592system.cpu1.dcache.WriteReq_misses::total 112730 # number of WriteReq misses 1593system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9735 # number of LoadLockedReq misses 1594system.cpu1.dcache.LoadLockedReq_misses::total 9735 # number of LoadLockedReq misses 1595system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9394 # number of StoreCondReq misses 1596system.cpu1.dcache.StoreCondReq_misses::total 9394 # number of StoreCondReq misses 1597system.cpu1.dcache.demand_misses::cpu1.data 246478 # number of demand (read+write) misses 1598system.cpu1.dcache.demand_misses::total 246478 # number of demand (read+write) misses 1599system.cpu1.dcache.overall_misses::cpu1.data 246478 # number of overall misses 1600system.cpu1.dcache.overall_misses::total 246478 # number of overall misses 1601system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1649486235 # number of ReadReq miss cycles 1602system.cpu1.dcache.ReadReq_miss_latency::total 1649486235 # number of ReadReq miss cycles 1603system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3739097468 # number of WriteReq miss cycles 1604system.cpu1.dcache.WriteReq_miss_latency::total 3739097468 # number of WriteReq miss cycles 1605system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77937249 # number of LoadLockedReq miss cycles 1606system.cpu1.dcache.LoadLockedReq_miss_latency::total 77937249 # number of LoadLockedReq miss cycles 1607system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49168975 # number of StoreCondReq miss cycles 1608system.cpu1.dcache.StoreCondReq_miss_latency::total 49168975 # number of StoreCondReq miss cycles 1609system.cpu1.dcache.demand_miss_latency::cpu1.data 5388583703 # number of demand (read+write) miss cycles 1610system.cpu1.dcache.demand_miss_latency::total 5388583703 # number of demand (read+write) miss cycles 1611system.cpu1.dcache.overall_miss_latency::cpu1.data 5388583703 # number of overall miss cycles 1612system.cpu1.dcache.overall_miss_latency::total 5388583703 # number of overall miss cycles 1613system.cpu1.dcache.ReadReq_accesses::cpu1.data 4521933 # number of ReadReq accesses(hits+misses) 1614system.cpu1.dcache.ReadReq_accesses::total 4521933 # number of ReadReq accesses(hits+misses) 1615system.cpu1.dcache.WriteReq_accesses::cpu1.data 3784978 # number of WriteReq accesses(hits+misses) 1616system.cpu1.dcache.WriteReq_accesses::total 3784978 # number of WriteReq accesses(hits+misses) 1617system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83186 # number of LoadLockedReq accesses(hits+misses) 1618system.cpu1.dcache.LoadLockedReq_accesses::total 83186 # number of LoadLockedReq accesses(hits+misses) 1619system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83121 # number of StoreCondReq accesses(hits+misses) 1620system.cpu1.dcache.StoreCondReq_accesses::total 83121 # number of StoreCondReq accesses(hits+misses) 1621system.cpu1.dcache.demand_accesses::cpu1.data 8306911 # number of demand (read+write) accesses 1622system.cpu1.dcache.demand_accesses::total 8306911 # number of demand (read+write) accesses 1623system.cpu1.dcache.overall_accesses::cpu1.data 8306911 # number of overall (read+write) accesses 1624system.cpu1.dcache.overall_accesses::total 8306911 # number of overall (read+write) accesses 1625system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029578 # miss rate for ReadReq accesses 1626system.cpu1.dcache.ReadReq_miss_rate::total 0.029578 # miss rate for ReadReq accesses 1627system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029784 # miss rate for WriteReq accesses 1628system.cpu1.dcache.WriteReq_miss_rate::total 0.029784 # miss rate for WriteReq accesses 1629system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117027 # miss rate for LoadLockedReq accesses 1630system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117027 # miss rate for LoadLockedReq accesses 1631system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113016 # miss rate for StoreCondReq accesses 1632system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113016 # miss rate for StoreCondReq accesses 1633system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029671 # miss rate for demand accesses 1634system.cpu1.dcache.demand_miss_rate::total 0.029671 # miss rate for demand accesses 1635system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029671 # miss rate for overall accesses 1636system.cpu1.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses 1637system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12332.791780 # average ReadReq miss latency 1638system.cpu1.dcache.ReadReq_avg_miss_latency::total 12332.791780 # average ReadReq miss latency 1639system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33168.610556 # average WriteReq miss latency 1640system.cpu1.dcache.WriteReq_avg_miss_latency::total 33168.610556 # average WriteReq miss latency 1641system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8005.880740 # average LoadLockedReq miss latency 1642system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8005.880740 # average LoadLockedReq miss latency 1643system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5234.082925 # average StoreCondReq miss latency 1644system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5234.082925 # average StoreCondReq miss latency 1645system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency 1646system.cpu1.dcache.demand_avg_miss_latency::total 21862.331336 # average overall miss latency 1647system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency 1648system.cpu1.dcache.overall_avg_miss_latency::total 21862.331336 # average overall miss latency | 1711system.cpu1.dcache.tags.replacements 220883 # number of replacements 1712system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use 1713system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks. 1714system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks. 1715system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks. 1716system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit. 1717system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor 1718system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of cache occupancy 1719system.cpu1.dcache.tags.occ_percent::total 0.920854 # Average percentage of cache occupancy 1720system.cpu1.dcache.ReadReq_hits::cpu1.data 4390672 # number of ReadReq hits 1721system.cpu1.dcache.ReadReq_hits::total 4390672 # number of ReadReq hits 1722system.cpu1.dcache.WriteReq_hits::cpu1.data 3674527 # number of WriteReq hits 1723system.cpu1.dcache.WriteReq_hits::total 3674527 # number of WriteReq hits 1724system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73485 # number of LoadLockedReq hits 1725system.cpu1.dcache.LoadLockedReq_hits::total 73485 # number of LoadLockedReq hits 1726system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73732 # number of StoreCondReq hits 1727system.cpu1.dcache.StoreCondReq_hits::total 73732 # number of StoreCondReq hits 1728system.cpu1.dcache.demand_hits::cpu1.data 8065199 # number of demand (read+write) hits 1729system.cpu1.dcache.demand_hits::total 8065199 # number of demand (read+write) hits 1730system.cpu1.dcache.overall_hits::cpu1.data 8065199 # number of overall hits 1731system.cpu1.dcache.overall_hits::total 8065199 # number of overall hits 1732system.cpu1.dcache.ReadReq_misses::cpu1.data 134090 # number of ReadReq misses 1733system.cpu1.dcache.ReadReq_misses::total 134090 # number of ReadReq misses 1734system.cpu1.dcache.WriteReq_misses::cpu1.data 112827 # number of WriteReq misses 1735system.cpu1.dcache.WriteReq_misses::total 112827 # number of WriteReq misses 1736system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9762 # number of LoadLockedReq misses 1737system.cpu1.dcache.LoadLockedReq_misses::total 9762 # number of LoadLockedReq misses 1738system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9429 # number of StoreCondReq misses 1739system.cpu1.dcache.StoreCondReq_misses::total 9429 # number of StoreCondReq misses 1740system.cpu1.dcache.demand_misses::cpu1.data 246917 # number of demand (read+write) misses 1741system.cpu1.dcache.demand_misses::total 246917 # number of demand (read+write) misses 1742system.cpu1.dcache.overall_misses::cpu1.data 246917 # number of overall misses 1743system.cpu1.dcache.overall_misses::total 246917 # number of overall misses 1744system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1656976729 # number of ReadReq miss cycles 1745system.cpu1.dcache.ReadReq_miss_latency::total 1656976729 # number of ReadReq miss cycles 1746system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4353399476 # number of WriteReq miss cycles 1747system.cpu1.dcache.WriteReq_miss_latency::total 4353399476 # number of WriteReq miss cycles 1748system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77544499 # number of LoadLockedReq miss cycles 1749system.cpu1.dcache.LoadLockedReq_miss_latency::total 77544499 # number of LoadLockedReq miss cycles 1750system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49349978 # number of StoreCondReq miss cycles 1751system.cpu1.dcache.StoreCondReq_miss_latency::total 49349978 # number of StoreCondReq miss cycles 1752system.cpu1.dcache.demand_miss_latency::cpu1.data 6010376205 # number of demand (read+write) miss cycles 1753system.cpu1.dcache.demand_miss_latency::total 6010376205 # number of demand (read+write) miss cycles 1754system.cpu1.dcache.overall_miss_latency::cpu1.data 6010376205 # number of overall miss cycles 1755system.cpu1.dcache.overall_miss_latency::total 6010376205 # number of overall miss cycles 1756system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524762 # number of ReadReq accesses(hits+misses) 1757system.cpu1.dcache.ReadReq_accesses::total 4524762 # number of ReadReq accesses(hits+misses) 1758system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787354 # number of WriteReq accesses(hits+misses) 1759system.cpu1.dcache.WriteReq_accesses::total 3787354 # number of WriteReq accesses(hits+misses) 1760system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83247 # number of LoadLockedReq accesses(hits+misses) 1761system.cpu1.dcache.LoadLockedReq_accesses::total 83247 # number of LoadLockedReq accesses(hits+misses) 1762system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83161 # number of StoreCondReq accesses(hits+misses) 1763system.cpu1.dcache.StoreCondReq_accesses::total 83161 # number of StoreCondReq accesses(hits+misses) 1764system.cpu1.dcache.demand_accesses::cpu1.data 8312116 # number of demand (read+write) accesses 1765system.cpu1.dcache.demand_accesses::total 8312116 # number of demand (read+write) accesses 1766system.cpu1.dcache.overall_accesses::cpu1.data 8312116 # number of overall (read+write) accesses 1767system.cpu1.dcache.overall_accesses::total 8312116 # number of overall (read+write) accesses 1768system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029635 # miss rate for ReadReq accesses 1769system.cpu1.dcache.ReadReq_miss_rate::total 0.029635 # miss rate for ReadReq accesses 1770system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029790 # miss rate for WriteReq accesses 1771system.cpu1.dcache.WriteReq_miss_rate::total 0.029790 # miss rate for WriteReq accesses 1772system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117265 # miss rate for LoadLockedReq accesses 1773system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117265 # miss rate for LoadLockedReq accesses 1774system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113382 # miss rate for StoreCondReq accesses 1775system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113382 # miss rate for StoreCondReq accesses 1776system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029706 # miss rate for demand accesses 1777system.cpu1.dcache.demand_miss_rate::total 0.029706 # miss rate for demand accesses 1778system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029706 # miss rate for overall accesses 1779system.cpu1.dcache.overall_miss_rate::total 0.029706 # miss rate for overall accesses 1780system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12357.198367 # average ReadReq miss latency 1781system.cpu1.dcache.ReadReq_avg_miss_latency::total 12357.198367 # average ReadReq miss latency 1782system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38584.731279 # average WriteReq miss latency 1783system.cpu1.dcache.WriteReq_avg_miss_latency::total 38584.731279 # average WriteReq miss latency 1784system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7943.505327 # average LoadLockedReq miss latency 1785system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7943.505327 # average LoadLockedReq miss latency 1786system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5233.850673 # average StoreCondReq miss latency 1787system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5233.850673 # average StoreCondReq miss latency 1788system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency 1789system.cpu1.dcache.demand_avg_miss_latency::total 24341.686498 # average overall miss latency 1790system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency 1791system.cpu1.dcache.overall_avg_miss_latency::total 24341.686498 # average overall miss latency |
| 1649system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1650system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1651system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1652system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1653system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1654system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1655system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1656system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1792system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1793system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1794system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1795system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1796system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1797system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1798system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1799system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1657system.cpu1.dcache.writebacks::writebacks 199438 # number of writebacks 1658system.cpu1.dcache.writebacks::total 199438 # number of writebacks 1659system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133748 # number of ReadReq MSHR misses 1660system.cpu1.dcache.ReadReq_mshr_misses::total 133748 # number of ReadReq MSHR misses 1661system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112730 # number of WriteReq MSHR misses 1662system.cpu1.dcache.WriteReq_mshr_misses::total 112730 # number of WriteReq MSHR misses 1663system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9735 # number of LoadLockedReq MSHR misses 1664system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9735 # number of LoadLockedReq MSHR misses 1665system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9393 # number of StoreCondReq MSHR misses 1666system.cpu1.dcache.StoreCondReq_mshr_misses::total 9393 # number of StoreCondReq MSHR misses 1667system.cpu1.dcache.demand_mshr_misses::cpu1.data 246478 # number of demand (read+write) MSHR misses 1668system.cpu1.dcache.demand_mshr_misses::total 246478 # number of demand (read+write) MSHR misses 1669system.cpu1.dcache.overall_mshr_misses::cpu1.data 246478 # number of overall MSHR misses 1670system.cpu1.dcache.overall_mshr_misses::total 246478 # number of overall MSHR misses 1671system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1381071765 # number of ReadReq MSHR miss cycles 1672system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1381071765 # number of ReadReq MSHR miss cycles 1673system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles 1674system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles 1675system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles 1676system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles 1677system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles 1678system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles | 1800system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks 1801system.cpu1.dcache.writebacks::total 200272 # number of writebacks 1802system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses 1803system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses 1804system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses 1805system.cpu1.dcache.WriteReq_mshr_misses::total 112827 # number of WriteReq MSHR misses 1806system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9762 # number of LoadLockedReq MSHR misses 1807system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9762 # number of LoadLockedReq MSHR misses 1808system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9426 # number of StoreCondReq MSHR misses 1809system.cpu1.dcache.StoreCondReq_mshr_misses::total 9426 # number of StoreCondReq MSHR misses 1810system.cpu1.dcache.demand_mshr_misses::cpu1.data 246917 # number of demand (read+write) MSHR misses 1811system.cpu1.dcache.demand_mshr_misses::total 246917 # number of demand (read+write) MSHR misses 1812system.cpu1.dcache.overall_mshr_misses::cpu1.data 246917 # number of overall MSHR misses 1813system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses 1814system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles 1815system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles 1816system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles 1817system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles 1818system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles 1819system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles 1820system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles 1821system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles |
| 1679system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1680system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles | 1822system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1823system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles |
| 1681system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles 1682system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles 1683system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles 1684system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles 1685system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles 1686system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles 1687system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles 1688system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles 1689system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles 1690system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles 1691system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses 1692system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses 1693system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses 1694system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses 1695system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses 1696system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses 1697system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses 1698system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses 1699system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses 1700system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses 1701system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses 1702system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses 1703system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency 1704system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency 1705system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency 1706system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency 1707system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency 1708system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency 1709system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency 1710system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency | 1824system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles 1825system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles 1826system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles 1827system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles 1828system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles 1829system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles 1830system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles 1831system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles 1832system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles 1833system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles 1834system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses 1835system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses 1836system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses 1837system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses 1838system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses 1839system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses 1840system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses 1841system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses 1842system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses 1843system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses 1844system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses 1845system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses 1846system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency 1847system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency 1848system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency 1849system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency 1850system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency 1851system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency 1852system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency 1853system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency |
| 1711system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1712system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1854system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1855system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1713system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency 1714system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency 1715system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency 1716system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency | 1856system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency 1857system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency 1858system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency 1859system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency |
| 1717system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1718system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1719system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1720system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1721system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1722system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1723system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1724system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1730system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1731system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1732system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1733system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1734system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1735system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1736system.iocache.fast_writes 0 # number of fast writes performed 1737system.iocache.cache_copies 0 # number of cache copies performed | 1860system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1861system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1862system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1863system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1864system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1865system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1866system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1867system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1873system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1874system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1875system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1876system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1877system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1878system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1879system.iocache.fast_writes 0 # number of fast writes performed 1880system.iocache.cache_copies 0 # number of cache copies performed |
| 1738system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles 1739system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles 1740system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles 1741system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles | 1881system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles 1882system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles 1883system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles 1884system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles |
| 1742system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1743system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1744system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1745system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1746system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1747 1748---------- End Simulation Statistics ---------- | 1885system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1886system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1887system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1888system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1889system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1890 1891---------- End Simulation Statistics ---------- |