| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.183438 # Number of seconds simulated 4sim_ticks 1183437503500 # Number of ticks simulated 5final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.194897 # Number of seconds simulated 4sim_ticks 1194896580500 # Number of ticks simulated 5final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 462248 # Simulator instruction rate (inst/s) 8host_op_rate 589061 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8900686287 # Simulator tick rate (ticks/s) 10host_mem_usage 440324 # Number of bytes of host memory used 11host_seconds 132.96 # Real time elapsed on the host 12sim_insts 61460532 # Number of instructions simulated 13sim_ops 78321652 # Number of ops (including micro ops) simulated | 7host_inst_rate 311660 # Simulator instruction rate (inst/s) 8host_op_rate 397163 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6068013925 # Simulator tick rate (ticks/s) 10host_mem_usage 403588 # Number of bytes of host memory used 11host_seconds 196.92 # Real time elapsed on the host 12sim_insts 61371297 # Number of instructions simulated 13sim_ops 78208202 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory | 17system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory |
| 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory | 31system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3481005 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6615920 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654550 # Total number of read requests seen 70system.physmem.writeReqs 821204 # Total number of write requests seen 71system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 425891200 # Total number of bytes read from memory 73system.physmem.bytesWritten 52557056 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 415695 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 415259 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 415928 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 415873 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 415149 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 415167 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 415977 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 415766 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 415709 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 415657 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 415044 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 414930 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 415676 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 51328 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51156 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 50890 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51482 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51387 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 50751 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51440 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51875 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51227 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51302 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51806 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51729 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51213 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis | 33system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 4079 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 388295 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 214107 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 2430570 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654628 # Total number of read requests seen 70system.physmem.writeReqs 821464 # Total number of write requests seen 71system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 425896192 # Total number of bytes read from memory 73system.physmem.bytesWritten 52573696 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 415298 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 416079 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 415727 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 51324 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51464 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51694 # Track writes on a per bank basis |
| 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 112system.physmem.totGap 1183433014000 # Total gap between requests | 112system.physmem.totGap 1194892168500 # Total gap between requests |
| 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 6825 # Categorize read packet sizes 116system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes | 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 6825 # Categorize read packet sizes 116system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 119system.physmem.readPktSize::6 159661 # Categorize read packet sizes | 119system.physmem.readPktSize::6 159739 # Categorize read packet sizes |
| 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes 122system.physmem.writePktSize::2 756836 # Categorize write packet sizes 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes | 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes 122system.physmem.writePktSize::2 756836 # Categorize write packet sizes 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 126system.physmem.writePktSize::6 64368 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 571102 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 408461 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 415701 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1537889 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 1165282 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1169319 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 1141412 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 29559 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 27546 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 48416 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 68998 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 48154 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 5894 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 5718 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 5549 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 5372 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see | 126system.physmem.writePktSize::6 64628 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 581008 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 419779 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 439715 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1589810 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 1189300 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1185139 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 1157962 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 13029 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 10446 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 15424 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 20310 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 15138 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 4570 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 4445 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 4292 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 4046 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see |
| 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::0 35455 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 35679 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 35685 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 35691 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 35695 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 35705 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 35705 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 35705 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 35705 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 35705 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 35704 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 35704 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 35704 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 35704 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 35704 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 35704 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 35704 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 35704 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 35704 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 35704 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 35704 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 250 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 26 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::0 35692 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 35713 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 35715 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 35715 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 35716 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 35716 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 35716 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 35716 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 35716 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 35716 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 35716 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 35716 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 35716 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 35715 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 35715 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 35715 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 35715 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see |
| 189system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 189system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 191system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays 192system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests 193system.physmem.totBusLat 33272265000 # Total cycles spent in databus access 194system.physmem.totBankLat 9048957500 # Total cycles spent in bank access 195system.physmem.avgQLat 22096.54 # Average queueing delay per request 196system.physmem.avgBankLat 1359.83 # Average bank access latency per request | 191system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::2368-2431 27 0.08% 77.39% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::2432-2495 13 0.04% 77.42% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.50% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.54% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2624-2687 9 0.03% 77.56% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2688-2751 14 0.04% 77.60% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2752-2815 11 0.03% 77.64% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2816-2879 12 0.03% 77.67% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2880-2943 14 0.04% 77.71% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2944-3007 6 0.02% 77.73% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3008-3071 7 0.02% 77.75% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3072-3135 15 0.04% 77.79% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3136-3199 4 0.01% 77.80% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::3200-3263 7 0.02% 77.82% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::3264-3327 4 0.01% 77.84% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::3328-3391 14 0.04% 77.88% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::3392-3455 11 0.03% 77.91% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::3456-3519 7 0.02% 77.93% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::3520-3583 7 0.02% 77.95% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3584-3647 11 0.03% 77.98% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3712-3775 5 0.01% 78.02% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3776-3839 12 0.03% 78.05% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.06% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.08% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3968-4031 8 0.02% 78.10% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.12% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4096-4159 41 0.12% 78.24% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4160-4223 3 0.01% 78.25% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::4224-4287 4 0.01% 78.26% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.27% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::4352-4415 4 0.01% 78.28% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::4416-4479 5 0.01% 78.30% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::4480-4543 4 0.01% 78.31% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::4544-4607 5 0.01% 78.32% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4608-4671 9 0.03% 78.35% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.36% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.37% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.38% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.39% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4928-4991 1 0.00% 78.39% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4992-5055 5 0.01% 78.41% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5056-5119 3 0.01% 78.42% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::5120-5183 10 0.03% 78.44% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::5184-5247 3 0.01% 78.45% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::5312-5375 2 0.01% 78.46% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::5376-5439 5 0.01% 78.47% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::5440-5503 2 0.01% 78.48% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.49% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::5632-5695 3 0.01% 78.50% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::5696-5759 6 0.02% 78.52% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5760-5823 2 0.01% 78.53% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5824-5887 3 0.01% 78.53% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5888-5951 5 0.01% 78.55% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5952-6015 4 0.01% 78.56% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6016-6079 3 0.01% 78.57% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6080-6143 3 0.01% 78.58% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6144-6207 170 0.49% 79.07% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6208-6271 3 0.01% 79.08% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::6272-6335 1 0.00% 79.08% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::6336-6399 4 0.01% 79.09% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6400-6463 4 0.01% 79.10% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.11% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6592-6655 2 0.01% 79.11% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6656-6719 5 0.01% 79.13% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6720-6783 3 0.01% 79.14% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::6848-6911 3 0.01% 79.20% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7040-7103 1 0.00% 79.21% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7104-7167 1 0.00% 79.21% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7168-7231 4 0.01% 79.23% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::7232-7295 3 0.01% 79.23% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::7296-7359 2 0.01% 79.24% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.24% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::7424-7487 3 0.01% 79.25% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::7488-7551 4 0.01% 79.26% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.28% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::7680-7743 4 0.01% 79.29% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.30% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::7872-7935 5 0.01% 79.31% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::7936-7999 2 0.01% 79.32% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::8000-8063 2 0.01% 79.32% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.34% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::8128-8191 4 0.01% 79.36% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::8192-8255 318 0.92% 80.27% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::8448-8511 1 0.00% 80.28% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.28% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::8960-9023 2 0.01% 80.29% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::9216-9279 4 0.01% 80.30% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.30% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::9472-9535 2 0.01% 80.31% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.31% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::9728-9791 2 0.01% 80.31% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::10240-10303 17 0.05% 80.36% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.37% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::10752-10815 1 0.00% 80.37% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11008-11071 2 0.01% 80.38% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11200-11263 1 0.00% 80.38% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::11520-11583 2 0.01% 80.39% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::12736-12799 1 0.00% 80.40% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::13312-13375 1 0.00% 80.40% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::13568-13631 2 0.01% 80.41% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.41% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.41% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::15360-15423 2 0.01% 80.42% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.42% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15872-15935 1 0.00% 80.42% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::16128-16191 1 0.00% 80.43% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.43% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::16704-16767 1 0.00% 80.43% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::17152-17215 1 0.00% 80.44% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::17280-17343 1 0.00% 80.44% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::17408-17471 2 0.01% 80.44% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::17728-17791 1 0.00% 80.45% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::17856-17919 1 0.00% 80.45% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::18176-18239 1 0.00% 80.45% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::18432-18495 2 0.01% 80.46% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::19200-19263 1 0.00% 80.46% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.50% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.50% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::20992-21055 1 0.00% 80.51% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.51% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.51% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::22528-22591 3 0.01% 80.52% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.53% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::23040-23103 2 0.01% 80.53% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::23552-23615 3 0.01% 80.54% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::23808-23871 1 0.00% 80.54% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::24064-24127 1 0.00% 80.55% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::24128-24191 1 0.00% 80.55% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::24320-24383 1 0.00% 80.55% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::24576-24639 1 0.00% 80.55% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::24832-24895 2 0.01% 80.56% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::25216-25279 1 0.00% 80.56% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.57% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::25856-25919 2 0.01% 80.58% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::26624-26687 1 0.00% 80.58% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::26880-26943 3 0.01% 80.59% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::27136-27199 1 0.00% 80.59% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.60% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.60% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::27840-27903 1 0.00% 80.60% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::27904-27967 1 0.00% 80.61% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::27968-28031 1 0.00% 80.61% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.61% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::28672-28735 2 0.01% 80.62% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::28928-28991 2 0.01% 80.62% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::29184-29247 1 0.00% 80.63% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.63% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::29696-29759 4 0.01% 80.64% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::29952-30015 5 0.01% 80.66% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::30208-30271 1 0.00% 80.66% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::30464-30527 1 0.00% 80.66% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::30720-30783 1 0.00% 80.66% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::31040-31103 1 0.00% 80.67% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::31360-31423 1 0.00% 80.67% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::31680-31743 1 0.00% 80.67% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.68% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::32000-32063 2 0.01% 80.68% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.69% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::32768-32831 6 0.02% 80.70% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::33280-33343 1 0.00% 80.71% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::33472-33535 5 0.01% 80.72% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::33536-33599 49 0.14% 80.86% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::33600-33663 2 0.01% 80.87% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::34816-34879 1 0.00% 80.87% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::35072-35135 1 0.00% 80.87% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.88% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::38016-38079 1 0.00% 80.88% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.88% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::39424-39487 1 0.00% 80.89% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::40960-41023 1 0.00% 80.89% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::41984-42047 2 0.01% 80.90% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::42112-42175 1 0.00% 80.90% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.90% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::43264-43327 1 0.00% 80.90% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::46848-46911 1 0.00% 80.91% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::48384-48447 1 0.00% 80.91% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::48576-48639 1 0.00% 80.91% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::53248-53311 1 0.00% 80.92% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::53504-53567 1 0.00% 80.92% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::53760-53823 1 0.00% 80.92% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::54016-54079 1 0.00% 80.92% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::54272-54335 1 0.00% 80.93% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::54528-54591 1 0.00% 80.93% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.93% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::55744-55807 1 0.00% 80.94% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::55808-55871 2 0.01% 80.94% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::56320-56383 3 0.01% 80.95% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::56576-56639 1 0.00% 80.95% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::58880-58943 1 0.00% 80.96% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::59520-59583 1 0.00% 80.96% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::60416-60479 1 0.00% 80.96% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::60608-60671 1 0.00% 80.96% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::62464-62527 1 0.00% 80.97% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::63488-63551 1 0.00% 80.97% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::65024-65087 7 0.02% 80.99% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.00% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.00% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.00% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.02% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::65536-65599 6201 17.92% 98.94% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::65920-65983 1 0.00% 98.94% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::66304-66367 1 0.00% 98.94% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::74240-74303 1 0.00% 98.95% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::76480-76543 1 0.00% 98.95% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::76864-76927 1 0.00% 98.95% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::84416-84479 1 0.00% 98.95% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::86848-86911 1 0.00% 98.96% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::87040-87103 1 0.00% 98.96% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::87424-87487 1 0.00% 98.96% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::97024-97087 1 0.00% 98.97% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::97472-97535 1 0.00% 98.97% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::97600-97663 1 0.00% 98.97% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.97% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::111168-111231 1 0.00% 98.98% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::114496-114559 1 0.00% 98.99% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::120896-120959 1 0.00% 98.99% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::121152-121215 1 0.00% 98.99% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::121728-121791 1 0.00% 98.99% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::122112-122175 1 0.00% 99.00% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation 468system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays 469system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests 470system.physmem.totBusLat 33272445000 # Total cycles spent in databus access 471system.physmem.totBankLat 8542600000 # Total cycles spent in bank access 472system.physmem.avgQLat 20154.36 # Average queueing delay per request 473system.physmem.avgBankLat 1283.73 # Average bank access latency per request |
| 197system.physmem.avgBusLat 5000.00 # Average bus latency per request | 474system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 198system.physmem.avgMemAccLat 28456.37 # Average memory access latency 199system.physmem.avgRdBW 359.88 # Average achieved read bandwidth in MB/s 200system.physmem.avgWrBW 44.41 # Average achieved write bandwidth in MB/s 201system.physmem.avgConsumedRdBW 52.52 # Average consumed read bandwidth in MB/s 202system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s | 475system.physmem.avgMemAccLat 26438.10 # Average memory access latency 476system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s 477system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s 478system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s 479system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s |
| 203system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 480system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 204system.physmem.busUtil 3.16 # Data bus utilization in percentage 205system.physmem.avgRdQLen 0.16 # Average read queue length over time 206system.physmem.avgWrQLen 11.75 # Average write queue length over time 207system.physmem.readRowHits 6612404 # Number of row buffer hits during reads 208system.physmem.writeRowHits 800418 # Number of row buffer hits during writes 209system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads 210system.physmem.writeRowHitRate 97.47 # Row buffer hit rate for writes 211system.physmem.avgGap 158302.83 # Average gap between requests | 481system.physmem.busUtil 3.13 # Data bus utilization in percentage 482system.physmem.avgRdQLen 0.15 # Average read queue length over time 483system.physmem.avgWrQLen 12.03 # Average write queue length over time 484system.physmem.readRowHits 6636609 # Number of row buffer hits during reads 485system.physmem.writeRowHits 804716 # Number of row buffer hits during writes 486system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads 487system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes 488system.physmem.avgGap 159828.45 # Average gap between requests |
| 212system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 213system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 214system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 215system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 216system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 217system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 218system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 219system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 220system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 221system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) | 489system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 490system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 491system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 492system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 493system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 494system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 495system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 496system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 497system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 498system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) |
| 222system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) | 499system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) |
| 223system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 224system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) | 500system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 501system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) |
| 225system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) | 502system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) |
| 226system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) | 503system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 504system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) |
| 228system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) | 505system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) |
| 229system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) | 506system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) |
| 230system.l2c.replacements 69541 # number of replacements 231system.l2c.tagsinuse 53035.489918 # Cycle average of tags in use 232system.l2c.total_refs 1672596 # Total number of references to valid blocks. 233system.l2c.sampled_refs 134740 # Sample count of references to valid blocks. 234system.l2c.avg_refs 12.413507 # Average number of references to valid blocks. | 507system.membus.throughput 60028731 # Throughput (bytes/s) 508system.membus.trans_dist::ReadReq 7703147 # Transaction distribution 509system.membus.trans_dist::ReadResp 7703147 # Transaction distribution 510system.membus.trans_dist::WriteReq 767201 # Transaction distribution 511system.membus.trans_dist::WriteResp 767201 # Transaction distribution 512system.membus.trans_dist::Writeback 64628 # Transaction distribution 513system.membus.trans_dist::UpgradeReq 27727 # Transaction distribution 514system.membus.trans_dist::SCUpgradeReq 16403 # Transaction distribution 515system.membus.trans_dist::UpgradeResp 10646 # Transaction distribution 516system.membus.trans_dist::ReadExReq 137752 # Transaction distribution 517system.membus.trans_dist::ReadExResp 137298 # Transaction distribution 518system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) 519system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 520system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966658 # Packet count per connected master and slave (bytes) 521system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) 522system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 523system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) 524system.membus.pkt_count_system.l2c.mem_side::total 4359022 # Packet count per connected master and slave (bytes) 525system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 526system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) 527system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) 528system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 529system.membus.pkt_count::system.physmem.port 14942786 # Packet count per connected master and slave (bytes) 530system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) 531system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 532system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) 533system.membus.pkt_count::total 17335150 # Packet count per connected master and slave (bytes) 534system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) 535system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 536system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) 537system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) 538system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 539system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) 540system.membus.tot_pkt_size_system.l2c.mem_side::total 19823614 # Cumulative packet size per connected master and slave (bytes) 541system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 542system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) 543system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) 544system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 545system.membus.tot_pkt_size::system.physmem.port 69318644 # Cumulative packet size per connected master and slave (bytes) 546system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) 547system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 548system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) 549system.membus.tot_pkt_size::total 71728126 # Cumulative packet size per connected master and slave (bytes) 550system.membus.data_through_bus 71728126 # Total data (bytes) 551system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 552system.membus.reqLayer0.occupancy 1224802500 # Layer occupancy (ticks) 553system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 554system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 555system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 556system.membus.reqLayer2.occupancy 9206920000 # Layer occupancy (ticks) 557system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) 558system.membus.reqLayer3.occupancy 7965000 # Layer occupancy (ticks) 559system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 560system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) 561system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 562system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) 563system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) 564system.membus.respLayer1.occupancy 5076821641 # Layer occupancy (ticks) 565system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 566system.membus.respLayer2.occupancy 14663419999 # Layer occupancy (ticks) 567system.membus.respLayer2.utilization 1.2 # Layer utilization (%) 568system.l2c.replacements 69621 # number of replacements 569system.l2c.tagsinuse 53152.412760 # Cycle average of tags in use 570system.l2c.total_refs 1651309 # Total number of references to valid blocks. 571system.l2c.sampled_refs 134782 # Sample count of references to valid blocks. 572system.l2c.avg_refs 12.251703 # Average number of references to valid blocks. |
| 235system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 573system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 236system.l2c.occ_blocks::writebacks 40180.165903 # Average occupied blocks per requestor 237system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor 238system.l2c.occ_blocks::cpu0.itb.walker 0.001420 # Average occupied blocks per requestor 239system.l2c.occ_blocks::cpu0.inst 3726.817906 # Average occupied blocks per requestor 240system.l2c.occ_blocks::cpu0.data 4242.402809 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu1.dtb.walker 2.742182 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu1.inst 2823.857423 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu1.data 2059.501869 # Average occupied blocks per requestor 244system.l2c.occ_percent::writebacks 0.613101 # Average percentage of cache occupancy 245system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy | 574system.l2c.occ_blocks::writebacks 40039.064508 # Average occupied blocks per requestor 575system.l2c.occ_blocks::cpu0.dtb.walker 2.667880 # Average occupied blocks per requestor 576system.l2c.occ_blocks::cpu0.itb.walker 0.001518 # Average occupied blocks per requestor 577system.l2c.occ_blocks::cpu0.inst 4643.192238 # Average occupied blocks per requestor 578system.l2c.occ_blocks::cpu0.data 5788.281913 # Average occupied blocks per requestor 579system.l2c.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor 580system.l2c.occ_blocks::cpu1.inst 1923.389950 # Average occupied blocks per requestor 581system.l2c.occ_blocks::cpu1.data 755.813095 # Average occupied blocks per requestor 582system.l2c.occ_percent::writebacks 0.610948 # Average percentage of cache occupancy 583system.l2c.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy |
| 246system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 584system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 247system.l2c.occ_percent::cpu0.inst 0.056867 # Average percentage of cache occupancy 248system.l2c.occ_percent::cpu0.data 0.064734 # Average percentage of cache occupancy 249system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 250system.l2c.occ_percent::cpu1.inst 0.043089 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu1.data 0.031426 # Average percentage of cache occupancy 252system.l2c.occ_percent::total 0.809257 # Average percentage of cache occupancy 253system.l2c.ReadReq_hits::cpu0.dtb.walker 3941 # number of ReadReq hits 254system.l2c.ReadReq_hits::cpu0.itb.walker 1769 # number of ReadReq hits 255system.l2c.ReadReq_hits::cpu0.inst 419774 # number of ReadReq hits 256system.l2c.ReadReq_hits::cpu0.data 205645 # number of ReadReq hits 257system.l2c.ReadReq_hits::cpu1.dtb.walker 5809 # number of ReadReq hits 258system.l2c.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits 259system.l2c.ReadReq_hits::cpu1.inst 464124 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu1.data 143605 # number of ReadReq hits 261system.l2c.ReadReq_hits::total 1246682 # number of ReadReq hits 262system.l2c.Writeback_hits::writebacks 571448 # number of Writeback hits 263system.l2c.Writeback_hits::total 571448 # number of Writeback hits 264system.l2c.UpgradeReq_hits::cpu0.data 1206 # number of UpgradeReq hits 265system.l2c.UpgradeReq_hits::cpu1.data 615 # number of UpgradeReq hits 266system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits 267system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits 268system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits 269system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits 270system.l2c.ReadExReq_hits::cpu0.data 56897 # number of ReadExReq hits 271system.l2c.ReadExReq_hits::cpu1.data 52477 # number of ReadExReq hits 272system.l2c.ReadExReq_hits::total 109374 # number of ReadExReq hits 273system.l2c.demand_hits::cpu0.dtb.walker 3941 # number of demand (read+write) hits 274system.l2c.demand_hits::cpu0.itb.walker 1769 # number of demand (read+write) hits 275system.l2c.demand_hits::cpu0.inst 419774 # number of demand (read+write) hits 276system.l2c.demand_hits::cpu0.data 262542 # number of demand (read+write) hits 277system.l2c.demand_hits::cpu1.dtb.walker 5809 # number of demand (read+write) hits 278system.l2c.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits 279system.l2c.demand_hits::cpu1.inst 464124 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu1.data 196082 # number of demand (read+write) hits 281system.l2c.demand_hits::total 1356056 # number of demand (read+write) hits 282system.l2c.overall_hits::cpu0.dtb.walker 3941 # number of overall hits 283system.l2c.overall_hits::cpu0.itb.walker 1769 # number of overall hits 284system.l2c.overall_hits::cpu0.inst 419774 # number of overall hits 285system.l2c.overall_hits::cpu0.data 262542 # number of overall hits 286system.l2c.overall_hits::cpu1.dtb.walker 5809 # number of overall hits 287system.l2c.overall_hits::cpu1.itb.walker 2015 # number of overall hits 288system.l2c.overall_hits::cpu1.inst 464124 # number of overall hits 289system.l2c.overall_hits::cpu1.data 196082 # number of overall hits 290system.l2c.overall_hits::total 1356056 # number of overall hits 291system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses | 585system.l2c.occ_percent::cpu0.inst 0.070849 # Average percentage of cache occupancy 586system.l2c.occ_percent::cpu0.data 0.088322 # Average percentage of cache occupancy 587system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 588system.l2c.occ_percent::cpu1.inst 0.029349 # Average percentage of cache occupancy 589system.l2c.occ_percent::cpu1.data 0.011533 # Average percentage of cache occupancy 590system.l2c.occ_percent::total 0.811041 # Average percentage of cache occupancy 591system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits 592system.l2c.ReadReq_hits::cpu0.itb.walker 1439 # number of ReadReq hits 593system.l2c.ReadReq_hits::cpu0.inst 483114 # number of ReadReq hits 594system.l2c.ReadReq_hits::cpu0.data 241880 # number of ReadReq hits 595system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits 596system.l2c.ReadReq_hits::cpu1.itb.walker 1868 # number of ReadReq hits 597system.l2c.ReadReq_hits::cpu1.inst 372301 # number of ReadReq hits 598system.l2c.ReadReq_hits::cpu1.data 110577 # number of ReadReq hits 599system.l2c.ReadReq_hits::total 1219485 # number of ReadReq hits 600system.l2c.Writeback_hits::writebacks 576235 # number of Writeback hits 601system.l2c.Writeback_hits::total 576235 # number of Writeback hits 602system.l2c.UpgradeReq_hits::cpu0.data 1306 # number of UpgradeReq hits 603system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits 604system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits 605system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits 606system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits 607system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits 608system.l2c.ReadExReq_hits::cpu0.data 65556 # number of ReadExReq hits 609system.l2c.ReadExReq_hits::cpu1.data 45402 # number of ReadExReq hits 610system.l2c.ReadExReq_hits::total 110958 # number of ReadExReq hits 611system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits 612system.l2c.demand_hits::cpu0.itb.walker 1439 # number of demand (read+write) hits 613system.l2c.demand_hits::cpu0.inst 483114 # number of demand (read+write) hits 614system.l2c.demand_hits::cpu0.data 307436 # number of demand (read+write) hits 615system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits 616system.l2c.demand_hits::cpu1.itb.walker 1868 # number of demand (read+write) hits 617system.l2c.demand_hits::cpu1.inst 372301 # number of demand (read+write) hits 618system.l2c.demand_hits::cpu1.data 155979 # number of demand (read+write) hits 619system.l2c.demand_hits::total 1330443 # number of demand (read+write) hits 620system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits 621system.l2c.overall_hits::cpu0.itb.walker 1439 # number of overall hits 622system.l2c.overall_hits::cpu0.inst 483114 # number of overall hits 623system.l2c.overall_hits::cpu0.data 307436 # number of overall hits 624system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits 625system.l2c.overall_hits::cpu1.itb.walker 1868 # number of overall hits 626system.l2c.overall_hits::cpu1.inst 372301 # number of overall hits 627system.l2c.overall_hits::cpu1.data 155979 # number of overall hits 628system.l2c.overall_hits::total 1330443 # number of overall hits 629system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses |
| 292system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 630system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 293system.l2c.ReadReq_misses::cpu0.inst 5740 # number of ReadReq misses 294system.l2c.ReadReq_misses::cpu0.data 7867 # number of ReadReq misses 295system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 296system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses 297system.l2c.ReadReq_misses::cpu1.data 3619 # number of ReadReq misses 298system.l2c.ReadReq_misses::total 22277 # number of ReadReq misses 299system.l2c.UpgradeReq_misses::cpu0.data 4714 # number of UpgradeReq misses 300system.l2c.UpgradeReq_misses::cpu1.data 3582 # number of UpgradeReq misses 301system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses 302system.l2c.SCUpgradeReq_misses::cpu0.data 566 # number of SCUpgradeReq misses 303system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses 304system.l2c.SCUpgradeReq_misses::total 1045 # number of SCUpgradeReq misses 305system.l2c.ReadExReq_misses::cpu0.data 67030 # number of ReadExReq misses 306system.l2c.ReadExReq_misses::cpu1.data 72802 # number of ReadExReq misses 307system.l2c.ReadExReq_misses::total 139832 # number of ReadExReq misses 308system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses | 631system.l2c.ReadReq_misses::cpu0.inst 6836 # number of ReadReq misses 632system.l2c.ReadReq_misses::cpu0.data 9717 # number of ReadReq misses 633system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 634system.l2c.ReadReq_misses::cpu1.inst 3992 # number of ReadReq misses 635system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses 636system.l2c.ReadReq_misses::total 22442 # number of ReadReq misses 637system.l2c.UpgradeReq_misses::cpu0.data 3986 # number of UpgradeReq misses 638system.l2c.UpgradeReq_misses::cpu1.data 3365 # number of UpgradeReq misses 639system.l2c.UpgradeReq_misses::total 7351 # number of UpgradeReq misses 640system.l2c.SCUpgradeReq_misses::cpu0.data 384 # number of SCUpgradeReq misses 641system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses 642system.l2c.SCUpgradeReq_misses::total 859 # number of SCUpgradeReq misses 643system.l2c.ReadExReq_misses::cpu0.data 95133 # number of ReadExReq misses 644system.l2c.ReadExReq_misses::cpu1.data 44601 # number of ReadExReq misses 645system.l2c.ReadExReq_misses::total 139734 # number of ReadExReq misses 646system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses |
| 309system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 647system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 310system.l2c.demand_misses::cpu0.inst 5740 # number of demand (read+write) misses 311system.l2c.demand_misses::cpu0.data 74897 # number of demand (read+write) misses 312system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 313system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses 314system.l2c.demand_misses::cpu1.data 76421 # number of demand (read+write) misses 315system.l2c.demand_misses::total 162109 # number of demand (read+write) misses 316system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses | 648system.l2c.demand_misses::cpu0.inst 6836 # number of demand (read+write) misses 649system.l2c.demand_misses::cpu0.data 104850 # number of demand (read+write) misses 650system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 651system.l2c.demand_misses::cpu1.inst 3992 # number of demand (read+write) misses 652system.l2c.demand_misses::cpu1.data 46491 # number of demand (read+write) misses 653system.l2c.demand_misses::total 162176 # number of demand (read+write) misses 654system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses |
| 317system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 655system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 318system.l2c.overall_misses::cpu0.inst 5740 # number of overall misses 319system.l2c.overall_misses::cpu0.data 74897 # number of overall misses 320system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 321system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses 322system.l2c.overall_misses::cpu1.data 76421 # number of overall misses 323system.l2c.overall_misses::total 162109 # number of overall misses 324system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles 325system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles 326system.l2c.ReadReq_miss_latency::cpu0.inst 301916500 # number of ReadReq miss cycles 327system.l2c.ReadReq_miss_latency::cpu0.data 419391498 # number of ReadReq miss cycles 328system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles 329system.l2c.ReadReq_miss_latency::cpu1.inst 276443000 # number of ReadReq miss cycles 330system.l2c.ReadReq_miss_latency::cpu1.data 222520500 # number of ReadReq miss cycles 331system.l2c.ReadReq_miss_latency::total 1220670498 # number of ReadReq miss cycles 332system.l2c.UpgradeReq_miss_latency::cpu0.data 12958000 # number of UpgradeReq miss cycles 333system.l2c.UpgradeReq_miss_latency::cpu1.data 12012000 # number of UpgradeReq miss cycles 334system.l2c.UpgradeReq_miss_latency::total 24970000 # number of UpgradeReq miss cycles 335system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1618000 # number of SCUpgradeReq miss cycles 336system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2458500 # number of SCUpgradeReq miss cycles 337system.l2c.SCUpgradeReq_miss_latency::total 4076500 # number of SCUpgradeReq miss cycles 338system.l2c.ReadExReq_miss_latency::cpu0.data 3033840500 # number of ReadExReq miss cycles 339system.l2c.ReadExReq_miss_latency::cpu1.data 3448903999 # number of ReadExReq miss cycles 340system.l2c.ReadExReq_miss_latency::total 6482744499 # number of ReadExReq miss cycles 341system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles 342system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles 343system.l2c.demand_miss_latency::cpu0.inst 301916500 # number of demand (read+write) miss cycles 344system.l2c.demand_miss_latency::cpu0.data 3453231998 # number of demand (read+write) miss cycles 345system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles 346system.l2c.demand_miss_latency::cpu1.inst 276443000 # number of demand (read+write) miss cycles 347system.l2c.demand_miss_latency::cpu1.data 3671424499 # number of demand (read+write) miss cycles 348system.l2c.demand_miss_latency::total 7703414997 # number of demand (read+write) miss cycles 349system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles 350system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles 351system.l2c.overall_miss_latency::cpu0.inst 301916500 # number of overall miss cycles 352system.l2c.overall_miss_latency::cpu0.data 3453231998 # number of overall miss cycles 353system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles 354system.l2c.overall_miss_latency::cpu1.inst 276443000 # number of overall miss cycles 355system.l2c.overall_miss_latency::cpu1.data 3671424499 # number of overall miss cycles 356system.l2c.overall_miss_latency::total 7703414997 # number of overall miss cycles 357system.l2c.ReadReq_accesses::cpu0.dtb.walker 3942 # number of ReadReq accesses(hits+misses) 358system.l2c.ReadReq_accesses::cpu0.itb.walker 1771 # number of ReadReq accesses(hits+misses) 359system.l2c.ReadReq_accesses::cpu0.inst 425514 # number of ReadReq accesses(hits+misses) 360system.l2c.ReadReq_accesses::cpu0.data 213512 # number of ReadReq accesses(hits+misses) 361system.l2c.ReadReq_accesses::cpu1.dtb.walker 5813 # number of ReadReq accesses(hits+misses) 362system.l2c.ReadReq_accesses::cpu1.itb.walker 2015 # number of ReadReq accesses(hits+misses) 363system.l2c.ReadReq_accesses::cpu1.inst 469168 # number of ReadReq accesses(hits+misses) 364system.l2c.ReadReq_accesses::cpu1.data 147224 # number of ReadReq accesses(hits+misses) 365system.l2c.ReadReq_accesses::total 1268959 # number of ReadReq accesses(hits+misses) 366system.l2c.Writeback_accesses::writebacks 571448 # number of Writeback accesses(hits+misses) 367system.l2c.Writeback_accesses::total 571448 # number of Writeback accesses(hits+misses) 368system.l2c.UpgradeReq_accesses::cpu0.data 5920 # number of UpgradeReq accesses(hits+misses) 369system.l2c.UpgradeReq_accesses::cpu1.data 4197 # number of UpgradeReq accesses(hits+misses) 370system.l2c.UpgradeReq_accesses::total 10117 # number of UpgradeReq accesses(hits+misses) 371system.l2c.SCUpgradeReq_accesses::cpu0.data 780 # number of SCUpgradeReq accesses(hits+misses) 372system.l2c.SCUpgradeReq_accesses::cpu1.data 583 # number of SCUpgradeReq accesses(hits+misses) 373system.l2c.SCUpgradeReq_accesses::total 1363 # number of SCUpgradeReq accesses(hits+misses) 374system.l2c.ReadExReq_accesses::cpu0.data 123927 # number of ReadExReq accesses(hits+misses) 375system.l2c.ReadExReq_accesses::cpu1.data 125279 # number of ReadExReq accesses(hits+misses) 376system.l2c.ReadExReq_accesses::total 249206 # number of ReadExReq accesses(hits+misses) 377system.l2c.demand_accesses::cpu0.dtb.walker 3942 # number of demand (read+write) accesses 378system.l2c.demand_accesses::cpu0.itb.walker 1771 # number of demand (read+write) accesses 379system.l2c.demand_accesses::cpu0.inst 425514 # number of demand (read+write) accesses 380system.l2c.demand_accesses::cpu0.data 337439 # number of demand (read+write) accesses 381system.l2c.demand_accesses::cpu1.dtb.walker 5813 # number of demand (read+write) accesses 382system.l2c.demand_accesses::cpu1.itb.walker 2015 # number of demand (read+write) accesses 383system.l2c.demand_accesses::cpu1.inst 469168 # number of demand (read+write) accesses 384system.l2c.demand_accesses::cpu1.data 272503 # number of demand (read+write) accesses 385system.l2c.demand_accesses::total 1518165 # number of demand (read+write) accesses 386system.l2c.overall_accesses::cpu0.dtb.walker 3942 # number of overall (read+write) accesses 387system.l2c.overall_accesses::cpu0.itb.walker 1771 # number of overall (read+write) accesses 388system.l2c.overall_accesses::cpu0.inst 425514 # number of overall (read+write) accesses 389system.l2c.overall_accesses::cpu0.data 337439 # number of overall (read+write) accesses 390system.l2c.overall_accesses::cpu1.dtb.walker 5813 # number of overall (read+write) accesses 391system.l2c.overall_accesses::cpu1.itb.walker 2015 # number of overall (read+write) accesses 392system.l2c.overall_accesses::cpu1.inst 469168 # number of overall (read+write) accesses 393system.l2c.overall_accesses::cpu1.data 272503 # number of overall (read+write) accesses 394system.l2c.overall_accesses::total 1518165 # number of overall (read+write) accesses 395system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for ReadReq accesses 396system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001129 # miss rate for ReadReq accesses 397system.l2c.ReadReq_miss_rate::cpu0.inst 0.013490 # miss rate for ReadReq accesses 398system.l2c.ReadReq_miss_rate::cpu0.data 0.036846 # miss rate for ReadReq accesses 399system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for ReadReq accesses 400system.l2c.ReadReq_miss_rate::cpu1.inst 0.010751 # miss rate for ReadReq accesses 401system.l2c.ReadReq_miss_rate::cpu1.data 0.024582 # miss rate for ReadReq accesses 402system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses 403system.l2c.UpgradeReq_miss_rate::cpu0.data 0.796284 # miss rate for UpgradeReq accesses 404system.l2c.UpgradeReq_miss_rate::cpu1.data 0.853467 # miss rate for UpgradeReq accesses 405system.l2c.UpgradeReq_miss_rate::total 0.820006 # miss rate for UpgradeReq accesses 406system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.725641 # miss rate for SCUpgradeReq accesses 407system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.821612 # miss rate for SCUpgradeReq accesses 408system.l2c.SCUpgradeReq_miss_rate::total 0.766691 # miss rate for SCUpgradeReq accesses 409system.l2c.ReadExReq_miss_rate::cpu0.data 0.540883 # miss rate for ReadExReq accesses 410system.l2c.ReadExReq_miss_rate::cpu1.data 0.581119 # miss rate for ReadExReq accesses 411system.l2c.ReadExReq_miss_rate::total 0.561110 # miss rate for ReadExReq accesses 412system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for demand accesses 413system.l2c.demand_miss_rate::cpu0.itb.walker 0.001129 # miss rate for demand accesses 414system.l2c.demand_miss_rate::cpu0.inst 0.013490 # miss rate for demand accesses 415system.l2c.demand_miss_rate::cpu0.data 0.221957 # miss rate for demand accesses 416system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for demand accesses 417system.l2c.demand_miss_rate::cpu1.inst 0.010751 # miss rate for demand accesses 418system.l2c.demand_miss_rate::cpu1.data 0.280441 # miss rate for demand accesses 419system.l2c.demand_miss_rate::total 0.106780 # miss rate for demand accesses 420system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for overall accesses 421system.l2c.overall_miss_rate::cpu0.itb.walker 0.001129 # miss rate for overall accesses 422system.l2c.overall_miss_rate::cpu0.inst 0.013490 # miss rate for overall accesses 423system.l2c.overall_miss_rate::cpu0.data 0.221957 # miss rate for overall accesses 424system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for overall accesses 425system.l2c.overall_miss_rate::cpu1.inst 0.010751 # miss rate for overall accesses 426system.l2c.overall_miss_rate::cpu1.data 0.280441 # miss rate for overall accesses 427system.l2c.overall_miss_rate::total 0.106780 # miss rate for overall accesses 428system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency 429system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency 430system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52598.693380 # average ReadReq miss latency 431system.l2c.ReadReq_avg_miss_latency::cpu0.data 53310.219652 # average ReadReq miss latency 432system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency 433system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54806.304520 # average ReadReq miss latency 434system.l2c.ReadReq_avg_miss_latency::cpu1.data 61486.736668 # average ReadReq miss latency 435system.l2c.ReadReq_avg_miss_latency::total 54795.102482 # average ReadReq miss latency 436system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2748.833263 # average UpgradeReq miss latency 437system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3353.433836 # average UpgradeReq miss latency 438system.l2c.UpgradeReq_avg_miss_latency::total 3009.884282 # average UpgradeReq miss latency 439system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2858.657244 # average SCUpgradeReq miss latency 440system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5132.567850 # average SCUpgradeReq miss latency 441system.l2c.SCUpgradeReq_avg_miss_latency::total 3900.956938 # average SCUpgradeReq miss latency 442system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45260.935402 # average ReadExReq miss latency 443system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47373.753455 # average ReadExReq miss latency 444system.l2c.ReadExReq_avg_miss_latency::total 46360.950991 # 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average overall miss latency 456system.l2c.overall_avg_miss_latency::cpu0.data 46106.412780 # average overall miss latency 457system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency 458system.l2c.overall_avg_miss_latency::cpu1.inst 54806.304520 # average overall miss latency 459system.l2c.overall_avg_miss_latency::cpu1.data 48042.089203 # average overall miss latency 460system.l2c.overall_avg_miss_latency::total 47519.971112 # average overall miss latency | 656system.l2c.overall_misses::cpu0.inst 6836 # number of overall misses 657system.l2c.overall_misses::cpu0.data 104850 # number of overall misses 658system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 659system.l2c.overall_misses::cpu1.inst 3992 # number of overall misses 660system.l2c.overall_misses::cpu1.data 46491 # number of overall misses 661system.l2c.overall_misses::total 162176 # number of overall misses 662system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 395000 # number of ReadReq miss cycles 663system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # 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number of SCUpgradeReq accesses(hits+misses) 710system.l2c.SCUpgradeReq_accesses::cpu1.data 574 # number of SCUpgradeReq accesses(hits+misses) 711system.l2c.SCUpgradeReq_accesses::total 1215 # number of SCUpgradeReq accesses(hits+misses) 712system.l2c.ReadExReq_accesses::cpu0.data 160689 # number of ReadExReq accesses(hits+misses) 713system.l2c.ReadExReq_accesses::cpu1.data 90003 # number of ReadExReq accesses(hits+misses) 714system.l2c.ReadExReq_accesses::total 250692 # number of ReadExReq accesses(hits+misses) 715system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses 716system.l2c.demand_accesses::cpu0.itb.walker 1441 # number of demand (read+write) accesses 717system.l2c.demand_accesses::cpu0.inst 489950 # number of demand (read+write) accesses 718system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses 719system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses 720system.l2c.demand_accesses::cpu1.itb.walker 1869 # number of demand (read+write) accesses 721system.l2c.demand_accesses::cpu1.inst 376293 # number of demand (read+write) accesses 722system.l2c.demand_accesses::cpu1.data 202470 # number of demand (read+write) accesses 723system.l2c.demand_accesses::total 1492619 # number of demand (read+write) accesses 724system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses 725system.l2c.overall_accesses::cpu0.itb.walker 1441 # number of overall (read+write) accesses 726system.l2c.overall_accesses::cpu0.inst 489950 # number of overall (read+write) accesses 727system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses 728system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses 729system.l2c.overall_accesses::cpu1.itb.walker 1869 # number of overall (read+write) accesses 730system.l2c.overall_accesses::cpu1.inst 376293 # number of overall (read+write) accesses 731system.l2c.overall_accesses::cpu1.data 202470 # number of overall (read+write) accesses 732system.l2c.overall_accesses::total 1492619 # number of overall (read+write) accesses 733system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses 734system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001388 # miss rate for ReadReq accesses 735system.l2c.ReadReq_miss_rate::cpu0.inst 0.013952 # miss rate for ReadReq accesses 736system.l2c.ReadReq_miss_rate::cpu0.data 0.038621 # miss rate for ReadReq accesses 737system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses 738system.l2c.ReadReq_miss_rate::cpu1.inst 0.010609 # miss rate for ReadReq accesses 739system.l2c.ReadReq_miss_rate::cpu1.data 0.016805 # miss rate for ReadReq accesses 740system.l2c.ReadReq_miss_rate::total 0.018070 # miss rate for ReadReq accesses 741system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753212 # miss rate for UpgradeReq accesses 742system.l2c.UpgradeReq_miss_rate::cpu1.data 0.886459 # miss rate for UpgradeReq accesses 743system.l2c.UpgradeReq_miss_rate::total 0.808869 # miss rate for UpgradeReq accesses 744system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599064 # miss rate for SCUpgradeReq accesses 745system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.827526 # miss rate for SCUpgradeReq accesses 746system.l2c.SCUpgradeReq_miss_rate::total 0.706996 # miss rate for SCUpgradeReq accesses 747system.l2c.ReadExReq_miss_rate::cpu0.data 0.592032 # miss rate for ReadExReq accesses 748system.l2c.ReadExReq_miss_rate::cpu1.data 0.495550 # miss rate for ReadExReq accesses 749system.l2c.ReadExReq_miss_rate::total 0.557393 # miss rate for ReadExReq accesses 750system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses 751system.l2c.demand_miss_rate::cpu0.itb.walker 0.001388 # miss rate for demand accesses 752system.l2c.demand_miss_rate::cpu0.inst 0.013952 # miss rate for demand accesses 753system.l2c.demand_miss_rate::cpu0.data 0.254314 # miss rate for demand accesses 754system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses 755system.l2c.demand_miss_rate::cpu1.inst 0.010609 # miss rate for demand accesses 756system.l2c.demand_miss_rate::cpu1.data 0.229619 # miss rate for demand accesses 757system.l2c.demand_miss_rate::total 0.108652 # miss rate for demand accesses 758system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses 759system.l2c.overall_miss_rate::cpu0.itb.walker 0.001388 # miss rate for overall accesses 760system.l2c.overall_miss_rate::cpu0.inst 0.013952 # miss rate for overall accesses 761system.l2c.overall_miss_rate::cpu0.data 0.254314 # miss rate for overall accesses 762system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses 763system.l2c.overall_miss_rate::cpu1.inst 0.010609 # miss rate for overall accesses 764system.l2c.overall_miss_rate::cpu1.data 0.229619 # miss rate for overall accesses 765system.l2c.overall_miss_rate::total 0.108652 # miss rate for overall accesses 766system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98750 # average ReadReq miss latency 767system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency 768system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71264.921006 # average ReadReq miss latency 769system.l2c.ReadReq_avg_miss_latency::cpu0.data 70688.072347 # average ReadReq miss latency 770system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89000 # average ReadReq miss latency 771system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71121.367735 # average ReadReq miss latency 772system.l2c.ReadReq_avg_miss_latency::cpu1.data 81360.052910 # average ReadReq miss latency 773system.l2c.ReadReq_avg_miss_latency::total 71844.599367 # average ReadReq miss latency 774system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2847.717010 # average UpgradeReq miss latency 775system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3612.332838 # average UpgradeReq miss latency 776system.l2c.UpgradeReq_avg_miss_latency::total 3197.728200 # average UpgradeReq miss latency 777system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4799.479167 # average SCUpgradeReq miss latency 778system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2208.421053 # average SCUpgradeReq miss latency 779system.l2c.SCUpgradeReq_avg_miss_latency::total 3366.705471 # average SCUpgradeReq miss latency 780system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65287.802277 # average ReadExReq miss latency 781system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63005.100782 # average ReadExReq miss latency 782system.l2c.ReadExReq_avg_miss_latency::total 64559.198148 # average ReadExReq miss latency 783system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency 784system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency 785system.l2c.demand_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency 786system.l2c.demand_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency 787system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency 788system.l2c.demand_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency 789system.l2c.demand_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency 790system.l2c.demand_avg_miss_latency::total 65567.355792 # average overall miss latency 791system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency 792system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency 793system.l2c.overall_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency 794system.l2c.overall_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency 795system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency 796system.l2c.overall_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency 797system.l2c.overall_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency 798system.l2c.overall_avg_miss_latency::total 65567.355792 # average overall miss latency |
| 461system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 464system.l2c.blocked::no_targets 0 # number of cycles access was blocked 465system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 467system.l2c.fast_writes 0 # number of fast writes performed 468system.l2c.cache_copies 0 # number of cache copies performed | 799system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 802system.l2c.blocked::no_targets 0 # number of cycles access was blocked 803system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.l2c.fast_writes 0 # number of fast writes performed 806system.l2c.cache_copies 0 # number of cache copies performed |
| 469system.l2c.writebacks::writebacks 64368 # number of writebacks 470system.l2c.writebacks::total 64368 # number of writebacks | 807system.l2c.writebacks::writebacks 64628 # number of writebacks 808system.l2c.writebacks::total 64628 # number of writebacks |
| 471system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 472system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 473system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 474system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 475system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 476system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits | 809system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 810system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 811system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 812system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 813system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 814system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 477system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses | 815system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses |
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average UpgradeReq mshr miss latency 598system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.376047 # average UpgradeReq mshr miss latency 599system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.352097 # average UpgradeReq mshr miss latency 600system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10033.666078 # average SCUpgradeReq mshr miss latency 601system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.524008 # average SCUpgradeReq mshr miss latency 602system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.434450 # average SCUpgradeReq mshr miss latency 603system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32591.685499 # average ReadExReq mshr miss latency 604system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34860.480797 # average ReadExReq mshr miss latency 605system.l2c.ReadExReq_avg_mshr_miss_latency::total 33772.908934 # average ReadExReq mshr miss latency 606system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency 607system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency 608system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency 609system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency 610system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency 611system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency 612system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency 613system.l2c.demand_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency 614system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency 615system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency 616system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency 617system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33458.436773 # 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number of demand (read+write) MSHR miss cycles 870system.l2c.demand_mshr_miss_latency::cpu1.inst 233821750 # number of demand (read+write) MSHR miss cycles 871system.l2c.demand_mshr_miss_latency::cpu1.data 2388981363 # number of demand (read+write) MSHR miss cycles 872system.l2c.demand_mshr_miss_latency::total 8595486925 # number of demand (read+write) MSHR miss cycles 873system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 345500 # number of overall MSHR miss cycles 874system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles 875system.l2c.overall_mshr_miss_latency::cpu0.inst 401430000 # number of overall MSHR miss cycles 876system.l2c.overall_mshr_miss_latency::cpu0.data 5570734562 # number of overall MSHR miss cycles 877system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles 878system.l2c.overall_mshr_miss_latency::cpu1.inst 233821750 # number of overall MSHR miss cycles 879system.l2c.overall_mshr_miss_latency::cpu1.data 2388981363 # number of overall MSHR miss cycles 880system.l2c.overall_mshr_miss_latency::total 8595486925 # number of overall MSHR miss cycles 881system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340227750 # number of ReadReq MSHR uncacheable cycles 882system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648650244 # number of ReadReq MSHR uncacheable cycles 883system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4863250 # number of ReadReq MSHR uncacheable cycles 884system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154086171248 # number of ReadReq MSHR uncacheable cycles 885system.l2c.ReadReq_mshr_uncacheable_latency::total 167079912492 # number of ReadReq MSHR uncacheable cycles 886system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16271278232 # number of WriteReq MSHR uncacheable cycles 887system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486203500 # number of WriteReq MSHR uncacheable cycles 888system.l2c.WriteReq_mshr_uncacheable_latency::total 16757481732 # number of WriteReq MSHR uncacheable cycles 889system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340227750 # number of overall MSHR uncacheable cycles 890system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919928476 # number of overall MSHR uncacheable cycles 891system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4863250 # number of overall MSHR uncacheable cycles 892system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154572374748 # number of overall MSHR uncacheable cycles 893system.l2c.overall_mshr_uncacheable_latency::total 183837394224 # number of overall MSHR uncacheable cycles 894system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses 895system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for ReadReq accesses 896system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for ReadReq accesses 897system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038621 # mshr miss rate for ReadReq accesses 898system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses 899system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for ReadReq accesses 900system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016805 # mshr miss rate for ReadReq accesses 901system.l2c.ReadReq_mshr_miss_rate::total 0.018070 # mshr miss rate for ReadReq accesses 902system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753212 # mshr miss rate for UpgradeReq accesses 903system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.886459 # mshr miss rate for UpgradeReq accesses 904system.l2c.UpgradeReq_mshr_miss_rate::total 0.808869 # mshr miss rate for UpgradeReq accesses 905system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599064 # mshr miss rate for SCUpgradeReq accesses 906system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827526 # mshr miss rate for SCUpgradeReq accesses 907system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706996 # mshr miss rate for SCUpgradeReq accesses 908system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592032 # mshr miss rate for ReadExReq accesses 909system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495550 # mshr miss rate for ReadExReq accesses 910system.l2c.ReadExReq_mshr_miss_rate::total 0.557393 # mshr miss rate for ReadExReq accesses 911system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses 912system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for demand accesses 913system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for demand accesses 914system.l2c.demand_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for demand accesses 915system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses 916system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for demand accesses 917system.l2c.demand_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for demand accesses 918system.l2c.demand_mshr_miss_rate::total 0.108651 # mshr miss rate for demand accesses 919system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses 920system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for overall accesses 921system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for overall accesses 922system.l2c.overall_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for overall accesses 923system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses 924system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for overall accesses 925system.l2c.overall_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for overall accesses 926system.l2c.overall_mshr_miss_rate::total 0.108651 # mshr miss rate for overall accesses 927system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average ReadReq mshr miss latency 928system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency 929system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average ReadReq mshr miss latency 930system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58235.386333 # average ReadReq mshr miss latency 931system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency 932system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average ReadReq mshr miss latency 933system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68885.978836 # average ReadReq mshr miss latency 934system.l2c.ReadReq_avg_mshr_miss_latency::total 59348.458135 # average ReadReq mshr miss latency 935system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.778726 # average UpgradeReq mshr miss latency 936system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.009510 # average UpgradeReq mshr miss latency 937system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.497347 # average UpgradeReq mshr miss latency 938system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.825521 # average SCUpgradeReq mshr miss latency 939system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.892632 # average SCUpgradeReq mshr miss latency 940system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.263097 # average SCUpgradeReq mshr miss latency 941system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52609.097926 # average ReadExReq mshr miss latency 942system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50644.309836 # average ReadExReq mshr miss latency 943system.l2c.ReadExReq_avg_mshr_miss_latency::total 51981.966994 # average ReadExReq mshr miss latency 944system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency 945system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency 946system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency 947system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency 948system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 949system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency 950system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency 951system.l2c.demand_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency 952system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency 953system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency 954system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency 955system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency 956system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 957system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency 958system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency 959system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency |
| 622system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 623system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 625system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 626system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 627system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 628system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 629system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 634system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 635system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 636system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 637system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 638system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 639system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 640system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 641system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 960system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 961system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 962system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 963system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 964system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 965system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 966system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 967system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 972system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 973system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 974system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 975system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 976system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 977system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 978system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 979system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 980system.toL2Bus.throughput 118409228 # Throughput (bytes/s) 981system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution 982system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution 983system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution 984system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution 985system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution 986system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution 987system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution 988system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution 989system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution 990system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution 991system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes) 992system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes) 993system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes) 994system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes) 995system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes) 996system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes) 997system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes) 998system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes) 999system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes) 1000system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes) 1001system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes) 1002system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes) 1003system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes) 1004system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes) 1005system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes) 1006system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes) 1007system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes) 1008system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes) 1009system.toL2Bus.data_through_bus 137173582 # Total data (bytes) 1010system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes) 1011system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks) 1012system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 1013system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks) 1014system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1015system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks) 1016system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1017system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) 1018system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1019system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks) 1020system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1021system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks) 1022system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) 1023system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks) 1024system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) 1025system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks) 1026system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) 1027system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) 1028system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) 1029system.iobus.throughput 45438572 # Throughput (bytes/s) 1030system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution 1031system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution 1032system.iobus.trans_dist::WriteReq 7946 # Transaction distribution 1033system.iobus.trans_dist::WriteResp 7946 # Transaction distribution 1034system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) 1035system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) 1036system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1037system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) 1038system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1039system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1040system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) 1041system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1042system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1043system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1044system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1045system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1046system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1047system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1048system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1049system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1050system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1051system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1052system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1053system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1054system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1055system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1056system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1057system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes) 1058system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 1059system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) 1060system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) 1061system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) 1062system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1063system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) 1064system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1065system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1066system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) 1067system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1068system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1069system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1070system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1071system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1072system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1073system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1074system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1075system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1076system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1077system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1078system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1079system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1080system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes) 1085system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) 1086system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) 1087system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1088system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) 1089system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1090system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1091system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) 1092system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1093system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1094system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1095system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1096system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1097system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1098system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1099system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1100system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1101system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1102system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1103system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1104system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1105system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1131system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1132system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1133system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1134system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 1135system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes) 1136system.iobus.data_through_bus 54294394 # Total data (bytes) 1137system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) 1138system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1139system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks) 1140system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1141system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1142system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1143system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) 1144system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1145system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1146system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1147system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1148system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1149system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) 1150system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1151system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 1152system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) 1153system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1154system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1155system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1156system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1157system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 1158system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1159system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 1160system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1161system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1162system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1163system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1164system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1165system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1166system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1167system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 1168system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1169system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1170system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1171system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1172system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1173system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 1174system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1175system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1176system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1177system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1178system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1179system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1180system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1181system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1182system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1183system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1184system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 1185system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) 1186system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) 1187system.iobus.respLayer1.occupancy 12976128000 # Layer occupancy (ticks) 1188system.iobus.respLayer1.utilization 1.1 # Layer utilization (%) |
|
| 642system.cpu0.dtb.inst_hits 0 # ITB inst hits 643system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1189system.cpu0.dtb.inst_hits 0 # ITB inst hits 1190system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 644system.cpu0.dtb.read_hits 7074446 # DTB read hits 645system.cpu0.dtb.read_misses 3765 # DTB read misses 646system.cpu0.dtb.write_hits 5659669 # DTB write hits 647system.cpu0.dtb.write_misses 803 # DTB write misses | 1191system.cpu0.dtb.read_hits 9653493 # DTB read hits 1192system.cpu0.dtb.read_misses 3738 # DTB read misses 1193system.cpu0.dtb.write_hits 7597651 # DTB write hits 1194system.cpu0.dtb.write_misses 1585 # DTB write misses |
| 648system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 649system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 650system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 651system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1195system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1196system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1197system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1198system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 652system.cpu0.dtb.flush_entries 1806 # Number of entries that have been flushed from TLB | 1199system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB |
| 653system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1200system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 654system.cpu0.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch | 1201system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch |
| 655system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 656system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions | 1202system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1203system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions |
| 657system.cpu0.dtb.read_accesses 7078211 # DTB read accesses 658system.cpu0.dtb.write_accesses 5660472 # DTB write accesses | 1204system.cpu0.dtb.read_accesses 9657231 # DTB read accesses 1205system.cpu0.dtb.write_accesses 7599236 # DTB write accesses |
| 659system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1206system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 660system.cpu0.dtb.hits 12734115 # DTB hits 661system.cpu0.dtb.misses 4568 # DTB misses 662system.cpu0.dtb.accesses 12738683 # DTB accesses 663system.cpu0.itb.inst_hits 29576941 # ITB inst hits | 1207system.cpu0.dtb.hits 17251144 # DTB hits 1208system.cpu0.dtb.misses 5323 # DTB misses 1209system.cpu0.dtb.accesses 17256467 # DTB accesses 1210system.cpu0.itb.inst_hits 43299111 # ITB inst hits |
| 664system.cpu0.itb.inst_misses 2205 # ITB inst misses 665system.cpu0.itb.read_hits 0 # DTB read hits 666system.cpu0.itb.read_misses 0 # DTB read misses 667system.cpu0.itb.write_hits 0 # DTB write hits 668system.cpu0.itb.write_misses 0 # DTB write misses 669system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 670system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 671system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 672system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 673system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 674system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 675system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 676system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 677system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 678system.cpu0.itb.read_accesses 0 # DTB read accesses 679system.cpu0.itb.write_accesses 0 # DTB write accesses | 1211system.cpu0.itb.inst_misses 2205 # ITB inst misses 1212system.cpu0.itb.read_hits 0 # DTB read hits 1213system.cpu0.itb.read_misses 0 # DTB read misses 1214system.cpu0.itb.write_hits 0 # DTB write hits 1215system.cpu0.itb.write_misses 0 # DTB write misses 1216system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1217system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1218system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1219system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1220system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 1221system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1222system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1223system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1224system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1225system.cpu0.itb.read_accesses 0 # DTB read accesses 1226system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 680system.cpu0.itb.inst_accesses 29579146 # ITB inst accesses 681system.cpu0.itb.hits 29576941 # DTB hits | 1227system.cpu0.itb.inst_accesses 43301316 # ITB inst accesses 1228system.cpu0.itb.hits 43299111 # DTB hits |
| 682system.cpu0.itb.misses 2205 # DTB misses | 1229system.cpu0.itb.misses 2205 # DTB misses |
| 683system.cpu0.itb.accesses 29579146 # DTB accesses 684system.cpu0.numCycles 2366875007 # number of cpu cycles simulated | 1230system.cpu0.itb.accesses 43301316 # DTB accesses 1231system.cpu0.numCycles 2389793161 # number of cpu cycles simulated |
| 685system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 686system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1232system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1233system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 687system.cpu0.committedInsts 28878978 # Number of instructions committed 688system.cpu0.committedOps 37226861 # Number of ops (including micro ops) committed 689system.cpu0.num_int_alu_accesses 33113061 # Number of integer alu accesses | 1234system.cpu0.committedInsts 42572187 # Number of instructions committed 1235system.cpu0.committedOps 53304847 # Number of ops (including micro ops) committed 1236system.cpu0.num_int_alu_accesses 48061724 # Number of integer alu accesses |
| 690system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses | 1237system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses |
| 691system.cpu0.num_func_calls 1241874 # number of times a function call or return occured 692system.cpu0.num_conditional_control_insts 4373945 # number of instructions that are conditional controls 693system.cpu0.num_int_insts 33113061 # number of integer instructions | 1238system.cpu0.num_func_calls 1403541 # number of times a function call or return occured 1239system.cpu0.num_conditional_control_insts 5582883 # number of instructions that are conditional controls 1240system.cpu0.num_int_insts 48061724 # number of integer instructions |
| 694system.cpu0.num_fp_insts 3860 # number of float instructions | 1241system.cpu0.num_fp_insts 3860 # number of float instructions |
| 695system.cpu0.num_int_register_reads 190134215 # number of times the integer registers were read 696system.cpu0.num_int_register_writes 36237784 # number of times the integer registers were written | 1242system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read 1243system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written |
| 697system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 698system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written | 1244system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1245system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written |
| 699system.cpu0.num_mem_refs 13402466 # number of memory refs 700system.cpu0.num_load_insts 7412077 # Number of load instructions 701system.cpu0.num_store_insts 5990389 # Number of store instructions 702system.cpu0.num_idle_cycles 2224972760.370120 # Number of idle cycles 703system.cpu0.num_busy_cycles 141902246.629880 # Number of busy cycles 704system.cpu0.not_idle_fraction 0.059953 # Percentage of non-idle cycles 705system.cpu0.idle_fraction 0.940047 # Percentage of idle cycles | 1246system.cpu0.num_mem_refs 18020656 # number of memory refs 1247system.cpu0.num_load_insts 10037354 # Number of load instructions 1248system.cpu0.num_store_insts 7983302 # Number of store instructions 1249system.cpu0.num_idle_cycles 2150335736.878201 # Number of idle cycles 1250system.cpu0.num_busy_cycles 239457424.121800 # Number of busy cycles 1251system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles 1252system.cpu0.idle_fraction 0.899800 # Percentage of idle cycles |
| 706system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1253system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 707system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed 708system.cpu0.icache.replacements 425548 # number of replacements 709system.cpu0.icache.tagsinuse 509.590371 # Cycle average of tags in use 710system.cpu0.icache.total_refs 29150863 # Total number of references to valid blocks. 711system.cpu0.icache.sampled_refs 426060 # Sample count of references to valid blocks. 712system.cpu0.icache.avg_refs 68.419619 # Average number of references to valid blocks. 713system.cpu0.icache.warmup_cycle 75070085000 # Cycle when the warmup percentage was hit. 714system.cpu0.icache.occ_blocks::cpu0.inst 509.590371 # Average occupied blocks per requestor 715system.cpu0.icache.occ_percent::cpu0.inst 0.995294 # Average percentage of cache occupancy 716system.cpu0.icache.occ_percent::total 0.995294 # Average percentage of cache occupancy 717system.cpu0.icache.ReadReq_hits::cpu0.inst 29150863 # number of ReadReq hits 718system.cpu0.icache.ReadReq_hits::total 29150863 # number of ReadReq hits 719system.cpu0.icache.demand_hits::cpu0.inst 29150863 # number of demand (read+write) hits 720system.cpu0.icache.demand_hits::total 29150863 # number of demand (read+write) hits 721system.cpu0.icache.overall_hits::cpu0.inst 29150863 # number of overall hits 722system.cpu0.icache.overall_hits::total 29150863 # number of overall hits 723system.cpu0.icache.ReadReq_misses::cpu0.inst 426061 # number of ReadReq misses 724system.cpu0.icache.ReadReq_misses::total 426061 # number of ReadReq misses 725system.cpu0.icache.demand_misses::cpu0.inst 426061 # number of demand (read+write) misses 726system.cpu0.icache.demand_misses::total 426061 # number of demand (read+write) misses 727system.cpu0.icache.overall_misses::cpu0.inst 426061 # number of overall misses 728system.cpu0.icache.overall_misses::total 426061 # number of overall misses 729system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5812849500 # number of ReadReq miss cycles 730system.cpu0.icache.ReadReq_miss_latency::total 5812849500 # number of ReadReq miss cycles 731system.cpu0.icache.demand_miss_latency::cpu0.inst 5812849500 # number of demand (read+write) miss cycles 732system.cpu0.icache.demand_miss_latency::total 5812849500 # number of demand (read+write) miss cycles 733system.cpu0.icache.overall_miss_latency::cpu0.inst 5812849500 # number of overall miss cycles 734system.cpu0.icache.overall_miss_latency::total 5812849500 # number of overall miss cycles 735system.cpu0.icache.ReadReq_accesses::cpu0.inst 29576924 # number of ReadReq accesses(hits+misses) 736system.cpu0.icache.ReadReq_accesses::total 29576924 # number of ReadReq accesses(hits+misses) 737system.cpu0.icache.demand_accesses::cpu0.inst 29576924 # number of demand (read+write) accesses 738system.cpu0.icache.demand_accesses::total 29576924 # number of demand (read+write) accesses 739system.cpu0.icache.overall_accesses::cpu0.inst 29576924 # number of overall (read+write) accesses 740system.cpu0.icache.overall_accesses::total 29576924 # number of overall (read+write) accesses 741system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses 742system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses 743system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses 744system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses 745system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses 746system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses 747system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13643.233011 # average ReadReq miss latency 748system.cpu0.icache.ReadReq_avg_miss_latency::total 13643.233011 # average ReadReq miss latency 749system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency 750system.cpu0.icache.demand_avg_miss_latency::total 13643.233011 # average overall miss latency 751system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency 752system.cpu0.icache.overall_avg_miss_latency::total 13643.233011 # average overall miss latency | 1254system.cpu0.kern.inst.quiesce 51313 # number of quiesce instructions executed 1255system.cpu0.icache.replacements 490180 # number of replacements 1256system.cpu0.icache.tagsinuse 509.396236 # Cycle average of tags in use 1257system.cpu0.icache.total_refs 42808401 # Total number of references to valid blocks. 1258system.cpu0.icache.sampled_refs 490692 # Sample count of references to valid blocks. 1259system.cpu0.icache.avg_refs 87.240878 # Average number of references to valid blocks. 1260system.cpu0.icache.warmup_cycle 76020026000 # Cycle when the warmup percentage was hit. 1261system.cpu0.icache.occ_blocks::cpu0.inst 509.396236 # Average occupied blocks per requestor 1262system.cpu0.icache.occ_percent::cpu0.inst 0.994915 # Average percentage of cache occupancy 1263system.cpu0.icache.occ_percent::total 0.994915 # Average percentage of cache occupancy 1264system.cpu0.icache.ReadReq_hits::cpu0.inst 42808401 # number of ReadReq hits 1265system.cpu0.icache.ReadReq_hits::total 42808401 # number of ReadReq hits 1266system.cpu0.icache.demand_hits::cpu0.inst 42808401 # number of demand (read+write) hits 1267system.cpu0.icache.demand_hits::total 42808401 # number of demand (read+write) hits 1268system.cpu0.icache.overall_hits::cpu0.inst 42808401 # number of overall hits 1269system.cpu0.icache.overall_hits::total 42808401 # number of overall hits 1270system.cpu0.icache.ReadReq_misses::cpu0.inst 490693 # number of ReadReq misses 1271system.cpu0.icache.ReadReq_misses::total 490693 # number of ReadReq misses 1272system.cpu0.icache.demand_misses::cpu0.inst 490693 # number of demand (read+write) misses 1273system.cpu0.icache.demand_misses::total 490693 # number of demand (read+write) misses 1274system.cpu0.icache.overall_misses::cpu0.inst 490693 # number of overall misses 1275system.cpu0.icache.overall_misses::total 490693 # number of overall misses 1276system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812744000 # number of ReadReq miss cycles 1277system.cpu0.icache.ReadReq_miss_latency::total 6812744000 # number of ReadReq miss cycles 1278system.cpu0.icache.demand_miss_latency::cpu0.inst 6812744000 # number of demand (read+write) miss cycles 1279system.cpu0.icache.demand_miss_latency::total 6812744000 # number of demand (read+write) miss cycles 1280system.cpu0.icache.overall_miss_latency::cpu0.inst 6812744000 # number of overall miss cycles 1281system.cpu0.icache.overall_miss_latency::total 6812744000 # number of overall miss cycles 1282system.cpu0.icache.ReadReq_accesses::cpu0.inst 43299094 # number of ReadReq accesses(hits+misses) 1283system.cpu0.icache.ReadReq_accesses::total 43299094 # number of ReadReq accesses(hits+misses) 1284system.cpu0.icache.demand_accesses::cpu0.inst 43299094 # number of demand (read+write) accesses 1285system.cpu0.icache.demand_accesses::total 43299094 # number of demand (read+write) accesses 1286system.cpu0.icache.overall_accesses::cpu0.inst 43299094 # number of overall (read+write) accesses 1287system.cpu0.icache.overall_accesses::total 43299094 # number of overall (read+write) accesses 1288system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011333 # miss rate for ReadReq accesses 1289system.cpu0.icache.ReadReq_miss_rate::total 0.011333 # miss rate for ReadReq accesses 1290system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011333 # miss rate for demand accesses 1291system.cpu0.icache.demand_miss_rate::total 0.011333 # miss rate for demand accesses 1292system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011333 # miss rate for overall accesses 1293system.cpu0.icache.overall_miss_rate::total 0.011333 # miss rate for overall accesses 1294system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13883.923349 # average ReadReq miss latency 1295system.cpu0.icache.ReadReq_avg_miss_latency::total 13883.923349 # average ReadReq miss latency 1296system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency 1297system.cpu0.icache.demand_avg_miss_latency::total 13883.923349 # average overall miss latency 1298system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency 1299system.cpu0.icache.overall_avg_miss_latency::total 13883.923349 # average overall miss latency |
| 753system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu0.icache.fast_writes 0 # number of fast writes performed 760system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1300system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1301system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1302system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1303system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1304system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1305system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1306system.cpu0.icache.fast_writes 0 # number of fast writes performed 1307system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 761system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 426061 # number of ReadReq MSHR misses 762system.cpu0.icache.ReadReq_mshr_misses::total 426061 # number of ReadReq MSHR misses 763system.cpu0.icache.demand_mshr_misses::cpu0.inst 426061 # number of demand (read+write) MSHR misses 764system.cpu0.icache.demand_mshr_misses::total 426061 # number of demand (read+write) MSHR misses 765system.cpu0.icache.overall_mshr_misses::cpu0.inst 426061 # number of overall MSHR misses 766system.cpu0.icache.overall_mshr_misses::total 426061 # number of overall MSHR misses 767system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4960727500 # number of ReadReq MSHR miss cycles 768system.cpu0.icache.ReadReq_mshr_miss_latency::total 4960727500 # number of ReadReq MSHR miss cycles 769system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4960727500 # number of demand (read+write) MSHR miss cycles 770system.cpu0.icache.demand_mshr_miss_latency::total 4960727500 # number of demand (read+write) MSHR miss cycles 771system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4960727500 # number of overall MSHR miss cycles 772system.cpu0.icache.overall_mshr_miss_latency::total 4960727500 # number of overall MSHR miss cycles 773system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles 774system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles 775system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles 776system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles 777system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses 778system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses 779system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses 780system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses 781system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses 782system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses 783system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average ReadReq mshr miss latency 784system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11643.233011 # average ReadReq mshr miss latency 785system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency 786system.cpu0.icache.demand_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency 787system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency 788system.cpu0.icache.overall_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency | 1308system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490693 # number of ReadReq MSHR misses 1309system.cpu0.icache.ReadReq_mshr_misses::total 490693 # number of ReadReq MSHR misses 1310system.cpu0.icache.demand_mshr_misses::cpu0.inst 490693 # number of demand (read+write) MSHR misses 1311system.cpu0.icache.demand_mshr_misses::total 490693 # number of demand (read+write) MSHR misses 1312system.cpu0.icache.overall_mshr_misses::cpu0.inst 490693 # number of overall MSHR misses 1313system.cpu0.icache.overall_mshr_misses::total 490693 # number of overall MSHR misses 1314system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5831313090 # number of ReadReq MSHR miss cycles 1315system.cpu0.icache.ReadReq_mshr_miss_latency::total 5831313090 # number of ReadReq MSHR miss cycles 1316system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5831313090 # number of demand (read+write) MSHR miss cycles 1317system.cpu0.icache.demand_mshr_miss_latency::total 5831313090 # number of demand (read+write) MSHR miss cycles 1318system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5831313090 # number of overall MSHR miss cycles 1319system.cpu0.icache.overall_mshr_miss_latency::total 5831313090 # number of overall MSHR miss cycles 1320system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430167000 # number of ReadReq MSHR uncacheable cycles 1321system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430167000 # number of ReadReq MSHR uncacheable cycles 1322system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430167000 # number of overall MSHR uncacheable cycles 1323system.cpu0.icache.overall_mshr_uncacheable_latency::total 430167000 # number of overall MSHR uncacheable cycles 1324system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for ReadReq accesses 1325system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011333 # mshr miss rate for ReadReq accesses 1326system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for demand accesses 1327system.cpu0.icache.demand_mshr_miss_rate::total 0.011333 # mshr miss rate for demand accesses 1328system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for overall accesses 1329system.cpu0.icache.overall_mshr_miss_rate::total 0.011333 # mshr miss rate for overall accesses 1330system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average ReadReq mshr miss latency 1331system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11883.831826 # average ReadReq mshr miss latency 1332system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency 1333system.cpu0.icache.demand_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency 1334system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency 1335system.cpu0.icache.overall_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency |
| 789system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 790system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 791system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 792system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 793system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1336system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1337system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1338system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1339system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1340system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 794system.cpu0.dcache.replacements 330262 # number of replacements 795system.cpu0.dcache.tagsinuse 452.976504 # Cycle average of tags in use 796system.cpu0.dcache.total_refs 12279097 # Total number of references to valid blocks. 797system.cpu0.dcache.sampled_refs 330774 # Sample count of references to valid blocks. 798system.cpu0.dcache.avg_refs 37.122316 # Average number of references to valid blocks. 799system.cpu0.dcache.warmup_cycle 473556000 # Cycle when the warmup percentage was hit. 800system.cpu0.dcache.occ_blocks::cpu0.data 452.976504 # Average occupied blocks per requestor 801system.cpu0.dcache.occ_percent::cpu0.data 0.884720 # Average percentage of cache occupancy 802system.cpu0.dcache.occ_percent::total 0.884720 # Average percentage of cache occupancy 803system.cpu0.dcache.ReadReq_hits::cpu0.data 6604621 # number of ReadReq hits 804system.cpu0.dcache.ReadReq_hits::total 6604621 # number of ReadReq hits 805system.cpu0.dcache.WriteReq_hits::cpu0.data 5354486 # number of WriteReq hits 806system.cpu0.dcache.WriteReq_hits::total 5354486 # number of WriteReq hits 807system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147953 # number of LoadLockedReq hits 808system.cpu0.dcache.LoadLockedReq_hits::total 147953 # number of LoadLockedReq hits 809system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149702 # number of StoreCondReq hits 810system.cpu0.dcache.StoreCondReq_hits::total 149702 # number of StoreCondReq hits 811system.cpu0.dcache.demand_hits::cpu0.data 11959107 # number of demand (read+write) hits 812system.cpu0.dcache.demand_hits::total 11959107 # number of demand (read+write) hits 813system.cpu0.dcache.overall_hits::cpu0.data 11959107 # number of overall hits 814system.cpu0.dcache.overall_hits::total 11959107 # number of overall hits 815system.cpu0.dcache.ReadReq_misses::cpu0.data 227474 # number of ReadReq misses 816system.cpu0.dcache.ReadReq_misses::total 227474 # number of ReadReq misses 817system.cpu0.dcache.WriteReq_misses::cpu0.data 141720 # number of WriteReq misses 818system.cpu0.dcache.WriteReq_misses::total 141720 # number of WriteReq misses 819system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9335 # number of LoadLockedReq misses 820system.cpu0.dcache.LoadLockedReq_misses::total 9335 # number of LoadLockedReq misses 821system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7505 # number of StoreCondReq misses 822system.cpu0.dcache.StoreCondReq_misses::total 7505 # number of StoreCondReq misses 823system.cpu0.dcache.demand_misses::cpu0.data 369194 # number of demand (read+write) misses 824system.cpu0.dcache.demand_misses::total 369194 # number of demand (read+write) misses 825system.cpu0.dcache.overall_misses::cpu0.data 369194 # number of overall misses 826system.cpu0.dcache.overall_misses::total 369194 # number of overall misses 827system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3141338000 # number of ReadReq miss cycles 828system.cpu0.dcache.ReadReq_miss_latency::total 3141338000 # number of ReadReq miss cycles 829system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4161237500 # number of WriteReq miss cycles 830system.cpu0.dcache.WriteReq_miss_latency::total 4161237500 # number of WriteReq miss cycles 831system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88637000 # number of LoadLockedReq miss cycles 832system.cpu0.dcache.LoadLockedReq_miss_latency::total 88637000 # number of LoadLockedReq miss cycles 833system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44352500 # number of StoreCondReq miss cycles 834system.cpu0.dcache.StoreCondReq_miss_latency::total 44352500 # number of StoreCondReq miss cycles 835system.cpu0.dcache.demand_miss_latency::cpu0.data 7302575500 # number of demand (read+write) miss cycles 836system.cpu0.dcache.demand_miss_latency::total 7302575500 # number of demand (read+write) miss cycles 837system.cpu0.dcache.overall_miss_latency::cpu0.data 7302575500 # number of overall miss cycles 838system.cpu0.dcache.overall_miss_latency::total 7302575500 # number of overall miss cycles 839system.cpu0.dcache.ReadReq_accesses::cpu0.data 6832095 # number of ReadReq accesses(hits+misses) 840system.cpu0.dcache.ReadReq_accesses::total 6832095 # number of ReadReq accesses(hits+misses) 841system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496206 # number of WriteReq accesses(hits+misses) 842system.cpu0.dcache.WriteReq_accesses::total 5496206 # number of WriteReq accesses(hits+misses) 843system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157288 # number of LoadLockedReq accesses(hits+misses) 844system.cpu0.dcache.LoadLockedReq_accesses::total 157288 # number of LoadLockedReq accesses(hits+misses) 845system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157207 # number of StoreCondReq accesses(hits+misses) 846system.cpu0.dcache.StoreCondReq_accesses::total 157207 # number of StoreCondReq accesses(hits+misses) 847system.cpu0.dcache.demand_accesses::cpu0.data 12328301 # number of demand (read+write) accesses 848system.cpu0.dcache.demand_accesses::total 12328301 # number of demand (read+write) accesses 849system.cpu0.dcache.overall_accesses::cpu0.data 12328301 # number of overall (read+write) accesses 850system.cpu0.dcache.overall_accesses::total 12328301 # number of overall (read+write) accesses 851system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033295 # miss rate for ReadReq accesses 852system.cpu0.dcache.ReadReq_miss_rate::total 0.033295 # miss rate for ReadReq accesses 853system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025785 # miss rate for WriteReq accesses 854system.cpu0.dcache.WriteReq_miss_rate::total 0.025785 # miss rate for WriteReq accesses 855system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059350 # miss rate for LoadLockedReq accesses 856system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059350 # miss rate for LoadLockedReq accesses 857system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047740 # miss rate for StoreCondReq accesses 858system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047740 # miss rate for StoreCondReq accesses 859system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029947 # miss rate for demand accesses 860system.cpu0.dcache.demand_miss_rate::total 0.029947 # miss rate for demand accesses 861system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029947 # miss rate for overall accesses 862system.cpu0.dcache.overall_miss_rate::total 0.029947 # miss rate for overall accesses 863system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13809.657367 # average ReadReq miss latency 864system.cpu0.dcache.ReadReq_avg_miss_latency::total 13809.657367 # average ReadReq miss latency 865system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29362.387101 # average WriteReq miss latency 866system.cpu0.dcache.WriteReq_avg_miss_latency::total 29362.387101 # average WriteReq miss latency 867system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9495.125870 # average LoadLockedReq miss latency 868system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9495.125870 # average LoadLockedReq miss latency 869system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5909.726849 # average StoreCondReq miss latency 870system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5909.726849 # average StoreCondReq miss latency 871system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency 872system.cpu0.dcache.demand_avg_miss_latency::total 19779.778382 # average overall miss latency 873system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency 874system.cpu0.dcache.overall_avg_miss_latency::total 19779.778382 # average overall miss latency | 1341system.cpu0.dcache.replacements 406656 # number of replacements 1342system.cpu0.dcache.tagsinuse 471.250698 # Cycle average of tags in use 1343system.cpu0.dcache.total_refs 15968393 # Total number of references to valid blocks. 1344system.cpu0.dcache.sampled_refs 407168 # Sample count of references to valid blocks. 1345system.cpu0.dcache.avg_refs 39.218192 # Average number of references to valid blocks. 1346system.cpu0.dcache.warmup_cycle 652579000 # Cycle when the warmup percentage was hit. 1347system.cpu0.dcache.occ_blocks::cpu0.data 471.250698 # Average occupied blocks per requestor 1348system.cpu0.dcache.occ_percent::cpu0.data 0.920412 # Average percentage of cache occupancy 1349system.cpu0.dcache.occ_percent::total 0.920412 # Average percentage of cache occupancy 1350system.cpu0.dcache.ReadReq_hits::cpu0.data 9137588 # number of ReadReq hits 1351system.cpu0.dcache.ReadReq_hits::total 9137588 # number of ReadReq hits 1352system.cpu0.dcache.WriteReq_hits::cpu0.data 6495058 # number of WriteReq hits 1353system.cpu0.dcache.WriteReq_hits::total 6495058 # number of WriteReq hits 1354system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156529 # number of LoadLockedReq hits 1355system.cpu0.dcache.LoadLockedReq_hits::total 156529 # number of LoadLockedReq hits 1356system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159015 # number of StoreCondReq hits 1357system.cpu0.dcache.StoreCondReq_hits::total 159015 # number of StoreCondReq hits 1358system.cpu0.dcache.demand_hits::cpu0.data 15632646 # number of demand (read+write) hits 1359system.cpu0.dcache.demand_hits::total 15632646 # number of demand (read+write) hits 1360system.cpu0.dcache.overall_hits::cpu0.data 15632646 # number of overall hits 1361system.cpu0.dcache.overall_hits::total 15632646 # number of overall hits 1362system.cpu0.dcache.ReadReq_misses::cpu0.data 263671 # number of ReadReq misses 1363system.cpu0.dcache.ReadReq_misses::total 263671 # number of ReadReq misses 1364system.cpu0.dcache.WriteReq_misses::cpu0.data 176701 # number of WriteReq misses 1365system.cpu0.dcache.WriteReq_misses::total 176701 # number of WriteReq misses 1366system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9917 # number of LoadLockedReq misses 1367system.cpu0.dcache.LoadLockedReq_misses::total 9917 # number of LoadLockedReq misses 1368system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7374 # number of StoreCondReq misses 1369system.cpu0.dcache.StoreCondReq_misses::total 7374 # number of StoreCondReq misses 1370system.cpu0.dcache.demand_misses::cpu0.data 440372 # number of demand (read+write) misses 1371system.cpu0.dcache.demand_misses::total 440372 # number of demand (read+write) misses 1372system.cpu0.dcache.overall_misses::cpu0.data 440372 # number of overall misses 1373system.cpu0.dcache.overall_misses::total 440372 # number of overall misses 1374system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3870373500 # number of ReadReq miss cycles 1375system.cpu0.dcache.ReadReq_miss_latency::total 3870373500 # number of ReadReq miss cycles 1376system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7511792500 # number of WriteReq miss cycles 1377system.cpu0.dcache.WriteReq_miss_latency::total 7511792500 # number of WriteReq miss cycles 1378system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99127000 # number of LoadLockedReq miss cycles 1379system.cpu0.dcache.LoadLockedReq_miss_latency::total 99127000 # number of LoadLockedReq miss cycles 1380system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40277500 # number of StoreCondReq miss cycles 1381system.cpu0.dcache.StoreCondReq_miss_latency::total 40277500 # number of StoreCondReq miss cycles 1382system.cpu0.dcache.demand_miss_latency::cpu0.data 11382166000 # number of demand (read+write) miss cycles 1383system.cpu0.dcache.demand_miss_latency::total 11382166000 # number of demand (read+write) miss cycles 1384system.cpu0.dcache.overall_miss_latency::cpu0.data 11382166000 # number of overall miss cycles 1385system.cpu0.dcache.overall_miss_latency::total 11382166000 # number of overall miss cycles 1386system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401259 # number of ReadReq accesses(hits+misses) 1387system.cpu0.dcache.ReadReq_accesses::total 9401259 # number of ReadReq accesses(hits+misses) 1388system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671759 # number of WriteReq accesses(hits+misses) 1389system.cpu0.dcache.WriteReq_accesses::total 6671759 # number of WriteReq accesses(hits+misses) 1390system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166446 # number of LoadLockedReq accesses(hits+misses) 1391system.cpu0.dcache.LoadLockedReq_accesses::total 166446 # number of LoadLockedReq accesses(hits+misses) 1392system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166389 # number of StoreCondReq accesses(hits+misses) 1393system.cpu0.dcache.StoreCondReq_accesses::total 166389 # number of StoreCondReq accesses(hits+misses) 1394system.cpu0.dcache.demand_accesses::cpu0.data 16073018 # number of demand (read+write) accesses 1395system.cpu0.dcache.demand_accesses::total 16073018 # number of demand (read+write) accesses 1396system.cpu0.dcache.overall_accesses::cpu0.data 16073018 # number of overall (read+write) accesses 1397system.cpu0.dcache.overall_accesses::total 16073018 # number of overall (read+write) accesses 1398system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028046 # miss rate for ReadReq accesses 1399system.cpu0.dcache.ReadReq_miss_rate::total 0.028046 # miss rate for ReadReq accesses 1400system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026485 # miss rate for WriteReq accesses 1401system.cpu0.dcache.WriteReq_miss_rate::total 0.026485 # miss rate for WriteReq accesses 1402system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059581 # miss rate for LoadLockedReq accesses 1403system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059581 # miss rate for LoadLockedReq accesses 1404system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044318 # miss rate for StoreCondReq accesses 1405system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044318 # miss rate for StoreCondReq accesses 1406system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses 1407system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses 1408system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses 1409system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses 1410system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14678.798579 # average ReadReq miss latency 1411system.cpu0.dcache.ReadReq_avg_miss_latency::total 14678.798579 # average ReadReq miss latency 1412system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42511.318555 # average WriteReq miss latency 1413system.cpu0.dcache.WriteReq_avg_miss_latency::total 42511.318555 # average WriteReq miss latency 1414system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9995.664011 # average LoadLockedReq miss latency 1415system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9995.664011 # average LoadLockedReq miss latency 1416system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5462.096555 # average StoreCondReq miss latency 1417system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5462.096555 # average StoreCondReq miss latency 1418system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency 1419system.cpu0.dcache.demand_avg_miss_latency::total 25846.706875 # average overall miss latency 1420system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency 1421system.cpu0.dcache.overall_avg_miss_latency::total 25846.706875 # average overall miss latency |
| 875system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 876system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 877system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 878system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 879system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 880system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 881system.cpu0.dcache.fast_writes 0 # number of fast writes performed 882system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1422system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1423system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1424system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1425system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1426system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1427system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1428system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1429system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 883system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks 884system.cpu0.dcache.writebacks::total 306255 # number of writebacks 885system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227474 # number of ReadReq MSHR misses 886system.cpu0.dcache.ReadReq_mshr_misses::total 227474 # number of ReadReq MSHR misses 887system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141720 # number of WriteReq MSHR misses 888system.cpu0.dcache.WriteReq_mshr_misses::total 141720 # number of WriteReq MSHR misses 889system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9335 # number of LoadLockedReq MSHR misses 890system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9335 # number of LoadLockedReq MSHR misses 891system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7498 # number of StoreCondReq MSHR misses 892system.cpu0.dcache.StoreCondReq_mshr_misses::total 7498 # number of StoreCondReq MSHR misses 893system.cpu0.dcache.demand_mshr_misses::cpu0.data 369194 # number of demand (read+write) MSHR misses 894system.cpu0.dcache.demand_mshr_misses::total 369194 # number of demand (read+write) MSHR misses 895system.cpu0.dcache.overall_mshr_misses::cpu0.data 369194 # number of overall MSHR misses 896system.cpu0.dcache.overall_mshr_misses::total 369194 # number of overall MSHR misses 897system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2686390000 # number of ReadReq MSHR miss cycles 898system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2686390000 # number of ReadReq MSHR miss cycles 899system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3877797500 # number of WriteReq MSHR miss cycles 900system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3877797500 # number of WriteReq MSHR miss cycles 901system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69967000 # number of LoadLockedReq MSHR miss cycles 902system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69967000 # number of LoadLockedReq MSHR miss cycles 903system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29358500 # number of StoreCondReq MSHR miss cycles 904system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29358500 # number of StoreCondReq MSHR miss cycles | 1430system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks 1431system.cpu0.dcache.writebacks::total 376588 # number of writebacks 1432system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses 1433system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses 1434system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses 1435system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses 1436system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses 1437system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # number of LoadLockedReq MSHR misses 1438system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7370 # number of StoreCondReq MSHR misses 1439system.cpu0.dcache.StoreCondReq_mshr_misses::total 7370 # number of StoreCondReq MSHR misses 1440system.cpu0.dcache.demand_mshr_misses::cpu0.data 440372 # number of demand (read+write) MSHR misses 1441system.cpu0.dcache.demand_mshr_misses::total 440372 # number of demand (read+write) MSHR misses 1442system.cpu0.dcache.overall_mshr_misses::cpu0.data 440372 # number of overall MSHR misses 1443system.cpu0.dcache.overall_mshr_misses::total 440372 # number of overall MSHR misses 1444system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3343027009 # number of ReadReq MSHR miss cycles 1445system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3343027009 # number of ReadReq MSHR miss cycles 1446system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7158388504 # number of WriteReq MSHR miss cycles 1447system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7158388504 # number of WriteReq MSHR miss cycles 1448system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79292501 # number of LoadLockedReq MSHR miss cycles 1449system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79292501 # number of LoadLockedReq MSHR miss cycles 1450system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25539500 # number of StoreCondReq MSHR miss cycles 1451system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25539500 # number of StoreCondReq MSHR miss cycles |
| 905system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 906system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles | 1452system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1453system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles |
| 907system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles 908system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles 909system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6564187500 # number of overall MSHR miss cycles 910system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles 911system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles 912system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles 913system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles 914system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles 915system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles 916system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles 917system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses 918system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses 919system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses 920system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses 921system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses 922system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses 923system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses 924system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses 925system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses 926system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses 927system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses 928system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses 929system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency 930system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency 931system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency 932system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency 933system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency 934system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency 935system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency 936system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency | 1454system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10501415513 # number of demand (read+write) MSHR miss cycles 1455system.cpu0.dcache.demand_mshr_miss_latency::total 10501415513 # number of demand (read+write) MSHR miss cycles 1456system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10501415513 # number of overall MSHR miss cycles 1457system.cpu0.dcache.overall_mshr_miss_latency::total 10501415513 # number of overall MSHR miss cycles 1458system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765210500 # number of ReadReq MSHR uncacheable cycles 1459system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765210500 # number of ReadReq MSHR uncacheable cycles 1460system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807067504 # number of WriteReq MSHR uncacheable cycles 1461system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807067504 # number of WriteReq MSHR uncacheable cycles 1462system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572278004 # number of overall MSHR uncacheable cycles 1463system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572278004 # number of overall MSHR uncacheable cycles 1464system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028046 # mshr miss rate for ReadReq accesses 1465system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028046 # mshr miss rate for ReadReq accesses 1466system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026485 # mshr miss rate for WriteReq accesses 1467system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026485 # mshr miss rate for WriteReq accesses 1468system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059581 # mshr miss rate for LoadLockedReq accesses 1469system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059581 # mshr miss rate for LoadLockedReq accesses 1470system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses 1471system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses 1472system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses 1473system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses 1474system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses 1475system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses 1476system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12678.781546 # average ReadReq mshr miss latency 1477system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency 1478system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency 1479system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency 1480system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency 1481system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency 1482system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency 1483system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency |
| 937system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 938system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1484system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1485system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 939system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency 940system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency 941system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency 942system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency | 1486system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency 1487system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency 1488system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency 1489system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency |
| 943system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 944system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 945system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 946system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 947system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 948system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 949system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 950system.cpu1.dtb.inst_hits 0 # ITB inst hits 951system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1490system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1491system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1492system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1493system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1494system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1495system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1496system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1497system.cpu1.dtb.inst_hits 0 # ITB inst hits 1498system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 952system.cpu1.dtb.read_hits 8312224 # DTB read hits 953system.cpu1.dtb.read_misses 3649 # DTB read misses 954system.cpu1.dtb.write_hits 5828610 # DTB write hits 955system.cpu1.dtb.write_misses 1432 # DTB write misses | 1499system.cpu1.dtb.read_hits 5706432 # DTB read hits 1500system.cpu1.dtb.read_misses 3576 # DTB read misses 1501system.cpu1.dtb.write_hits 3873109 # DTB write hits 1502system.cpu1.dtb.write_misses 645 # DTB write misses |
| 956system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 957system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 958system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 959system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1503system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1504system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1505system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1506system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 960system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB | 1507system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB |
| 961system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1508system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 962system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch | 1509system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch |
| 963system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 964system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions | 1510system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1511system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions |
| 965system.cpu1.dtb.read_accesses 8315873 # DTB read accesses 966system.cpu1.dtb.write_accesses 5830042 # DTB write accesses | 1512system.cpu1.dtb.read_accesses 5710008 # DTB read accesses 1513system.cpu1.dtb.write_accesses 3873754 # DTB write accesses |
| 967system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1514system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 968system.cpu1.dtb.hits 14140834 # DTB hits 969system.cpu1.dtb.misses 5081 # DTB misses 970system.cpu1.dtb.accesses 14145915 # DTB accesses 971system.cpu1.itb.inst_hits 33192056 # ITB inst hits | 1515system.cpu1.dtb.hits 9579541 # DTB hits 1516system.cpu1.dtb.misses 4221 # DTB misses 1517system.cpu1.dtb.accesses 9583762 # DTB accesses 1518system.cpu1.itb.inst_hits 19379683 # ITB inst hits |
| 972system.cpu1.itb.inst_misses 2171 # ITB inst misses 973system.cpu1.itb.read_hits 0 # DTB read hits 974system.cpu1.itb.read_misses 0 # DTB read misses 975system.cpu1.itb.write_hits 0 # DTB write hits 976system.cpu1.itb.write_misses 0 # DTB write misses 977system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 978system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 979system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 980system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 981system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 982system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 983system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 984system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 985system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 986system.cpu1.itb.read_accesses 0 # DTB read accesses 987system.cpu1.itb.write_accesses 0 # DTB write accesses | 1519system.cpu1.itb.inst_misses 2171 # ITB inst misses 1520system.cpu1.itb.read_hits 0 # DTB read hits 1521system.cpu1.itb.read_misses 0 # DTB read misses 1522system.cpu1.itb.write_hits 0 # DTB write hits 1523system.cpu1.itb.write_misses 0 # DTB write misses 1524system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1525system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1526system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1527system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1528system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 1529system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1530system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1531system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1532system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1533system.cpu1.itb.read_accesses 0 # DTB read accesses 1534system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 988system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses 989system.cpu1.itb.hits 33192056 # DTB hits | 1535system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses 1536system.cpu1.itb.hits 19379683 # DTB hits |
| 990system.cpu1.itb.misses 2171 # DTB misses | 1537system.cpu1.itb.misses 2171 # DTB misses |
| 991system.cpu1.itb.accesses 33194227 # DTB accesses 992system.cpu1.numCycles 2365415230 # number of cpu cycles simulated | 1538system.cpu1.itb.accesses 19381854 # DTB accesses 1539system.cpu1.numCycles 2388360365 # number of cpu cycles simulated |
| 993system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 994system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1540system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1541system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 995system.cpu1.committedInsts 32581554 # Number of instructions committed 996system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed 997system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses | 1542system.cpu1.committedInsts 18799110 # Number of instructions committed 1543system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed 1544system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses |
| 998system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses | 1545system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses |
| 999system.cpu1.num_func_calls 962092 # number of times a function call or return occured 1000system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls 1001system.cpu1.num_int_insts 37318858 # number of integer instructions | 1546system.cpu1.num_func_calls 796685 # number of times a function call or return occured 1547system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls 1548system.cpu1.num_int_insts 22267252 # number of integer instructions |
| 1002system.cpu1.num_fp_insts 6793 # number of float instructions | 1549system.cpu1.num_fp_insts 6793 # number of float instructions |
| 1003system.cpu1.num_int_register_reads 213696952 # number of times the integer registers were read 1004system.cpu1.num_int_register_writes 39459665 # number of times the integer registers were written | 1550system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read 1551system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written |
| 1005system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1006system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written | 1552system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1553system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written |
| 1007system.cpu1.num_mem_refs 14678596 # number of memory refs 1008system.cpu1.num_load_insts 8634126 # Number of load instructions 1009system.cpu1.num_store_insts 6044470 # Number of store instructions 1010system.cpu1.num_idle_cycles 1868274479.951726 # Number of idle cycles 1011system.cpu1.num_busy_cycles 497140750.048273 # Number of busy cycles 1012system.cpu1.not_idle_fraction 0.210171 # Percentage of non-idle cycles 1013system.cpu1.idle_fraction 0.789829 # Percentage of idle cycles | 1554system.cpu1.num_mem_refs 10014978 # number of memory refs 1555system.cpu1.num_load_insts 5983060 # Number of load instructions 1556system.cpu1.num_store_insts 4031918 # Number of store instructions 1557system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles 1558system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles 1559system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles 1560system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles |
| 1014system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1561system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1015system.cpu1.kern.inst.quiesce 43886 # number of quiesce instructions executed 1016system.cpu1.icache.replacements 469169 # number of replacements 1017system.cpu1.icache.tagsinuse 478.729775 # Cycle average of tags in use 1018system.cpu1.icache.total_refs 32722371 # Total number of references to valid blocks. 1019system.cpu1.icache.sampled_refs 469681 # Sample count of references to valid blocks. 1020system.cpu1.icache.avg_refs 69.669352 # Average number of references to valid blocks. 1021system.cpu1.icache.warmup_cycle 92399174500 # Cycle when the warmup percentage was hit. 1022system.cpu1.icache.occ_blocks::cpu1.inst 478.729775 # Average occupied blocks per requestor 1023system.cpu1.icache.occ_percent::cpu1.inst 0.935019 # Average percentage of cache occupancy 1024system.cpu1.icache.occ_percent::total 0.935019 # Average percentage of cache occupancy 1025system.cpu1.icache.ReadReq_hits::cpu1.inst 32722371 # number of ReadReq hits 1026system.cpu1.icache.ReadReq_hits::total 32722371 # number of ReadReq hits 1027system.cpu1.icache.demand_hits::cpu1.inst 32722371 # number of demand (read+write) hits 1028system.cpu1.icache.demand_hits::total 32722371 # number of demand (read+write) hits 1029system.cpu1.icache.overall_hits::cpu1.inst 32722371 # number of overall hits 1030system.cpu1.icache.overall_hits::total 32722371 # number of overall hits 1031system.cpu1.icache.ReadReq_misses::cpu1.inst 469681 # number of ReadReq misses 1032system.cpu1.icache.ReadReq_misses::total 469681 # number of ReadReq misses 1033system.cpu1.icache.demand_misses::cpu1.inst 469681 # number of demand (read+write) misses 1034system.cpu1.icache.demand_misses::total 469681 # number of demand (read+write) misses 1035system.cpu1.icache.overall_misses::cpu1.inst 469681 # number of overall misses 1036system.cpu1.icache.overall_misses::total 469681 # number of overall misses 1037system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6362521500 # number of ReadReq miss cycles 1038system.cpu1.icache.ReadReq_miss_latency::total 6362521500 # number of ReadReq miss cycles 1039system.cpu1.icache.demand_miss_latency::cpu1.inst 6362521500 # number of demand (read+write) miss cycles 1040system.cpu1.icache.demand_miss_latency::total 6362521500 # number of demand (read+write) miss cycles 1041system.cpu1.icache.overall_miss_latency::cpu1.inst 6362521500 # number of overall miss cycles 1042system.cpu1.icache.overall_miss_latency::total 6362521500 # number of overall miss cycles 1043system.cpu1.icache.ReadReq_accesses::cpu1.inst 33192052 # number of ReadReq accesses(hits+misses) 1044system.cpu1.icache.ReadReq_accesses::total 33192052 # number of ReadReq accesses(hits+misses) 1045system.cpu1.icache.demand_accesses::cpu1.inst 33192052 # number of demand (read+write) accesses 1046system.cpu1.icache.demand_accesses::total 33192052 # number of demand (read+write) accesses 1047system.cpu1.icache.overall_accesses::cpu1.inst 33192052 # number of overall (read+write) accesses 1048system.cpu1.icache.overall_accesses::total 33192052 # number of overall (read+write) accesses 1049system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014150 # miss rate for ReadReq accesses 1050system.cpu1.icache.ReadReq_miss_rate::total 0.014150 # miss rate for ReadReq accesses 1051system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014150 # miss rate for demand accesses 1052system.cpu1.icache.demand_miss_rate::total 0.014150 # miss rate for demand accesses 1053system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014150 # miss rate for overall accesses 1054system.cpu1.icache.overall_miss_rate::total 0.014150 # miss rate for overall accesses 1055system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13546.474096 # average ReadReq miss latency 1056system.cpu1.icache.ReadReq_avg_miss_latency::total 13546.474096 # average ReadReq miss latency 1057system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency 1058system.cpu1.icache.demand_avg_miss_latency::total 13546.474096 # average overall miss latency 1059system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency 1060system.cpu1.icache.overall_avg_miss_latency::total 13546.474096 # average overall miss latency | 1562system.cpu1.kern.inst.quiesce 39066 # number of quiesce instructions executed 1563system.cpu1.icache.replacements 376556 # number of replacements 1564system.cpu1.icache.tagsinuse 474.951242 # Cycle average of tags in use 1565system.cpu1.icache.total_refs 19002611 # Total number of references to valid blocks. 1566system.cpu1.icache.sampled_refs 377068 # Sample count of references to valid blocks. 1567system.cpu1.icache.avg_refs 50.395714 # Average number of references to valid blocks. 1568system.cpu1.icache.warmup_cycle 327008186500 # Cycle when the warmup percentage was hit. 1569system.cpu1.icache.occ_blocks::cpu1.inst 474.951242 # Average occupied blocks per requestor 1570system.cpu1.icache.occ_percent::cpu1.inst 0.927639 # Average percentage of cache occupancy 1571system.cpu1.icache.occ_percent::total 0.927639 # Average percentage of cache occupancy 1572system.cpu1.icache.ReadReq_hits::cpu1.inst 19002611 # number of ReadReq hits 1573system.cpu1.icache.ReadReq_hits::total 19002611 # number of ReadReq hits 1574system.cpu1.icache.demand_hits::cpu1.inst 19002611 # number of demand (read+write) hits 1575system.cpu1.icache.demand_hits::total 19002611 # number of demand (read+write) hits 1576system.cpu1.icache.overall_hits::cpu1.inst 19002611 # number of overall hits 1577system.cpu1.icache.overall_hits::total 19002611 # number of overall hits 1578system.cpu1.icache.ReadReq_misses::cpu1.inst 377068 # number of ReadReq misses 1579system.cpu1.icache.ReadReq_misses::total 377068 # number of ReadReq misses 1580system.cpu1.icache.demand_misses::cpu1.inst 377068 # number of demand (read+write) misses 1581system.cpu1.icache.demand_misses::total 377068 # number of demand (read+write) misses 1582system.cpu1.icache.overall_misses::cpu1.inst 377068 # number of overall misses 1583system.cpu1.icache.overall_misses::total 377068 # number of overall misses 1584system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5155062500 # number of ReadReq miss cycles 1585system.cpu1.icache.ReadReq_miss_latency::total 5155062500 # number of ReadReq miss cycles 1586system.cpu1.icache.demand_miss_latency::cpu1.inst 5155062500 # number of demand (read+write) miss cycles 1587system.cpu1.icache.demand_miss_latency::total 5155062500 # number of demand (read+write) miss cycles 1588system.cpu1.icache.overall_miss_latency::cpu1.inst 5155062500 # number of overall miss cycles 1589system.cpu1.icache.overall_miss_latency::total 5155062500 # number of overall miss cycles 1590system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379679 # number of ReadReq accesses(hits+misses) 1591system.cpu1.icache.ReadReq_accesses::total 19379679 # number of ReadReq accesses(hits+misses) 1592system.cpu1.icache.demand_accesses::cpu1.inst 19379679 # number of demand (read+write) accesses 1593system.cpu1.icache.demand_accesses::total 19379679 # number of demand (read+write) accesses 1594system.cpu1.icache.overall_accesses::cpu1.inst 19379679 # number of overall (read+write) accesses 1595system.cpu1.icache.overall_accesses::total 19379679 # number of overall (read+write) accesses 1596system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019457 # miss rate for ReadReq accesses 1597system.cpu1.icache.ReadReq_miss_rate::total 0.019457 # miss rate for ReadReq accesses 1598system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019457 # miss rate for demand accesses 1599system.cpu1.icache.demand_miss_rate::total 0.019457 # miss rate for demand accesses 1600system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019457 # miss rate for overall accesses 1601system.cpu1.icache.overall_miss_rate::total 0.019457 # miss rate for overall accesses 1602system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439899 # average ReadReq miss latency 1603system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.439899 # average ReadReq miss latency 1604system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency 1605system.cpu1.icache.demand_avg_miss_latency::total 13671.439899 # average overall miss latency 1606system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency 1607system.cpu1.icache.overall_avg_miss_latency::total 13671.439899 # average overall miss latency |
| 1061system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1067system.cpu1.icache.fast_writes 0 # number of fast writes performed 1068system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1608system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1609system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1610system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1611system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1612system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1613system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1614system.cpu1.icache.fast_writes 0 # number of fast writes performed 1615system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1069system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469681 # number of ReadReq MSHR misses 1070system.cpu1.icache.ReadReq_mshr_misses::total 469681 # number of ReadReq MSHR misses 1071system.cpu1.icache.demand_mshr_misses::cpu1.inst 469681 # number of demand (read+write) MSHR misses 1072system.cpu1.icache.demand_mshr_misses::total 469681 # number of demand (read+write) MSHR misses 1073system.cpu1.icache.overall_mshr_misses::cpu1.inst 469681 # number of overall MSHR misses 1074system.cpu1.icache.overall_mshr_misses::total 469681 # number of overall MSHR misses 1075system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5423159500 # number of ReadReq MSHR miss cycles 1076system.cpu1.icache.ReadReq_mshr_miss_latency::total 5423159500 # number of ReadReq MSHR miss cycles 1077system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5423159500 # number of demand (read+write) MSHR miss cycles 1078system.cpu1.icache.demand_mshr_miss_latency::total 5423159500 # number of demand (read+write) MSHR miss cycles 1079system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5423159500 # number of overall MSHR miss cycles 1080system.cpu1.icache.overall_mshr_miss_latency::total 5423159500 # number of overall MSHR miss cycles 1081system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4481000 # number of ReadReq MSHR uncacheable cycles 1082system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4481000 # number of ReadReq MSHR uncacheable cycles 1083system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4481000 # number of overall MSHR uncacheable cycles 1084system.cpu1.icache.overall_mshr_uncacheable_latency::total 4481000 # number of overall MSHR uncacheable cycles 1085system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for ReadReq accesses 1086system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014150 # mshr miss rate for ReadReq accesses 1087system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for demand accesses 1088system.cpu1.icache.demand_mshr_miss_rate::total 0.014150 # mshr miss rate for demand accesses 1089system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for overall accesses 1090system.cpu1.icache.overall_mshr_miss_rate::total 0.014150 # mshr miss rate for overall accesses 1091system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average ReadReq mshr miss latency 1092system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11546.474096 # average ReadReq mshr miss latency 1093system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency 1094system.cpu1.icache.demand_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency 1095system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency 1096system.cpu1.icache.overall_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency | 1616system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377068 # number of ReadReq MSHR misses 1617system.cpu1.icache.ReadReq_mshr_misses::total 377068 # number of ReadReq MSHR misses 1618system.cpu1.icache.demand_mshr_misses::cpu1.inst 377068 # number of demand (read+write) MSHR misses 1619system.cpu1.icache.demand_mshr_misses::total 377068 # number of demand (read+write) MSHR misses 1620system.cpu1.icache.overall_mshr_misses::cpu1.inst 377068 # number of overall MSHR misses 1621system.cpu1.icache.overall_mshr_misses::total 377068 # number of overall MSHR misses 1622system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4400893067 # number of ReadReq MSHR miss cycles 1623system.cpu1.icache.ReadReq_mshr_miss_latency::total 4400893067 # number of ReadReq MSHR miss cycles 1624system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4400893067 # number of demand (read+write) MSHR miss cycles 1625system.cpu1.icache.demand_mshr_miss_latency::total 4400893067 # number of demand (read+write) MSHR miss cycles 1626system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4400893067 # number of overall MSHR miss cycles 1627system.cpu1.icache.overall_mshr_miss_latency::total 4400893067 # number of overall MSHR miss cycles 1628system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6177000 # number of ReadReq MSHR uncacheable cycles 1629system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6177000 # number of ReadReq MSHR uncacheable cycles 1630system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6177000 # number of overall MSHR uncacheable cycles 1631system.cpu1.icache.overall_mshr_uncacheable_latency::total 6177000 # number of overall MSHR uncacheable cycles 1632system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for ReadReq accesses 1633system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019457 # mshr miss rate for ReadReq accesses 1634system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for demand accesses 1635system.cpu1.icache.demand_mshr_miss_rate::total 0.019457 # mshr miss rate for demand accesses 1636system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for overall accesses 1637system.cpu1.icache.overall_mshr_miss_rate::total 0.019457 # mshr miss rate for overall accesses 1638system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average ReadReq mshr miss latency 1639system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.351234 # average ReadReq mshr miss latency 1640system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency 1641system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency 1642system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency 1643system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency |
| 1097system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1098system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1099system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1100system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1101system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1644system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1645system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1646system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1647system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1648system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1102system.cpu1.dcache.replacements 292058 # number of replacements 1103system.cpu1.dcache.tagsinuse 471.819179 # Cycle average of tags in use 1104system.cpu1.dcache.total_refs 11963833 # Total number of references to valid blocks. 1105system.cpu1.dcache.sampled_refs 292409 # Sample count of references to valid blocks. 1106system.cpu1.dcache.avg_refs 40.914722 # Average number of references to valid blocks. 1107system.cpu1.dcache.warmup_cycle 83872114000 # Cycle when the warmup percentage was hit. 1108system.cpu1.dcache.occ_blocks::cpu1.data 471.819179 # Average occupied blocks per requestor 1109system.cpu1.dcache.occ_percent::cpu1.data 0.921522 # Average percentage of cache occupancy 1110system.cpu1.dcache.occ_percent::total 0.921522 # Average percentage of cache occupancy 1111system.cpu1.dcache.ReadReq_hits::cpu1.data 6947661 # number of ReadReq hits 1112system.cpu1.dcache.ReadReq_hits::total 6947661 # number of ReadReq hits 1113system.cpu1.dcache.WriteReq_hits::cpu1.data 4828322 # number of WriteReq hits 1114system.cpu1.dcache.WriteReq_hits::total 4828322 # number of WriteReq hits 1115system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81798 # number of LoadLockedReq hits 1116system.cpu1.dcache.LoadLockedReq_hits::total 81798 # number of LoadLockedReq hits 1117system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82734 # number of StoreCondReq hits 1118system.cpu1.dcache.StoreCondReq_hits::total 82734 # number of StoreCondReq hits 1119system.cpu1.dcache.demand_hits::cpu1.data 11775983 # number of demand (read+write) hits 1120system.cpu1.dcache.demand_hits::total 11775983 # number of demand (read+write) hits 1121system.cpu1.dcache.overall_hits::cpu1.data 11775983 # number of overall hits 1122system.cpu1.dcache.overall_hits::total 11775983 # number of overall hits 1123system.cpu1.dcache.ReadReq_misses::cpu1.data 170592 # number of ReadReq misses 1124system.cpu1.dcache.ReadReq_misses::total 170592 # number of ReadReq misses 1125system.cpu1.dcache.WriteReq_misses::cpu1.data 149961 # number of WriteReq misses 1126system.cpu1.dcache.WriteReq_misses::total 149961 # number of WriteReq misses 1127system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11053 # number of LoadLockedReq misses 1128system.cpu1.dcache.LoadLockedReq_misses::total 11053 # number of LoadLockedReq misses 1129system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10044 # number of StoreCondReq misses 1130system.cpu1.dcache.StoreCondReq_misses::total 10044 # number of StoreCondReq misses 1131system.cpu1.dcache.demand_misses::cpu1.data 320553 # number of demand (read+write) misses 1132system.cpu1.dcache.demand_misses::total 320553 # number of demand (read+write) misses 1133system.cpu1.dcache.overall_misses::cpu1.data 320553 # number of overall misses 1134system.cpu1.dcache.overall_misses::total 320553 # number of overall misses 1135system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2164105500 # number of ReadReq miss cycles 1136system.cpu1.dcache.ReadReq_miss_latency::total 2164105500 # number of ReadReq miss cycles 1137system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4535823500 # number of WriteReq miss cycles 1138system.cpu1.dcache.WriteReq_miss_latency::total 4535823500 # number of WriteReq miss cycles 1139system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92227500 # number of LoadLockedReq miss cycles 1140system.cpu1.dcache.LoadLockedReq_miss_latency::total 92227500 # number of LoadLockedReq miss cycles 1141system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51992500 # number of StoreCondReq miss cycles 1142system.cpu1.dcache.StoreCondReq_miss_latency::total 51992500 # number of StoreCondReq miss cycles 1143system.cpu1.dcache.demand_miss_latency::cpu1.data 6699929000 # number of demand (read+write) miss cycles 1144system.cpu1.dcache.demand_miss_latency::total 6699929000 # number of demand (read+write) miss cycles 1145system.cpu1.dcache.overall_miss_latency::cpu1.data 6699929000 # number of overall miss cycles 1146system.cpu1.dcache.overall_miss_latency::total 6699929000 # number of overall miss cycles 1147system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118253 # number of ReadReq accesses(hits+misses) 1148system.cpu1.dcache.ReadReq_accesses::total 7118253 # number of ReadReq accesses(hits+misses) 1149system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978283 # number of WriteReq accesses(hits+misses) 1150system.cpu1.dcache.WriteReq_accesses::total 4978283 # number of WriteReq accesses(hits+misses) 1151system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92851 # number of LoadLockedReq accesses(hits+misses) 1152system.cpu1.dcache.LoadLockedReq_accesses::total 92851 # number of LoadLockedReq accesses(hits+misses) 1153system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92778 # number of StoreCondReq accesses(hits+misses) 1154system.cpu1.dcache.StoreCondReq_accesses::total 92778 # number of StoreCondReq accesses(hits+misses) 1155system.cpu1.dcache.demand_accesses::cpu1.data 12096536 # number of demand (read+write) accesses 1156system.cpu1.dcache.demand_accesses::total 12096536 # number of demand (read+write) accesses 1157system.cpu1.dcache.overall_accesses::cpu1.data 12096536 # number of overall (read+write) accesses 1158system.cpu1.dcache.overall_accesses::total 12096536 # number of overall (read+write) accesses 1159system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023965 # miss rate for ReadReq accesses 1160system.cpu1.dcache.ReadReq_miss_rate::total 0.023965 # miss rate for ReadReq accesses 1161system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses 1162system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses 1163system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119040 # miss rate for LoadLockedReq accesses 1164system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119040 # miss rate for LoadLockedReq accesses 1165system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108258 # miss rate for StoreCondReq accesses 1166system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108258 # miss rate for StoreCondReq accesses 1167system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026500 # miss rate for demand accesses 1168system.cpu1.dcache.demand_miss_rate::total 0.026500 # miss rate for demand accesses 1169system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026500 # miss rate for overall accesses 1170system.cpu1.dcache.overall_miss_rate::total 0.026500 # miss rate for overall accesses 1171system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12685.855726 # average ReadReq miss latency 1172system.cpu1.dcache.ReadReq_avg_miss_latency::total 12685.855726 # average ReadReq miss latency 1173system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30246.687472 # average WriteReq miss latency 1174system.cpu1.dcache.WriteReq_avg_miss_latency::total 30246.687472 # average WriteReq miss latency 1175system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8344.114720 # average LoadLockedReq miss latency 1176system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8344.114720 # average LoadLockedReq miss latency 1177system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5176.473517 # average StoreCondReq miss latency 1178system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5176.473517 # average StoreCondReq miss latency 1179system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency 1180system.cpu1.dcache.demand_avg_miss_latency::total 20901.158311 # average overall miss latency 1181system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency 1182system.cpu1.dcache.overall_avg_miss_latency::total 20901.158311 # average overall miss latency | 1649system.cpu1.dcache.replacements 220463 # number of replacements 1650system.cpu1.dcache.tagsinuse 471.524014 # Cycle average of tags in use 1651system.cpu1.dcache.total_refs 8230847 # Total number of references to valid blocks. 1652system.cpu1.dcache.sampled_refs 220830 # Sample count of references to valid blocks. 1653system.cpu1.dcache.avg_refs 37.272323 # Average number of references to valid blocks. 1654system.cpu1.dcache.warmup_cycle 106217593500 # Cycle when the warmup percentage was hit. 1655system.cpu1.dcache.occ_blocks::cpu1.data 471.524014 # Average occupied blocks per requestor 1656system.cpu1.dcache.occ_percent::cpu1.data 0.920945 # Average percentage of cache occupancy 1657system.cpu1.dcache.occ_percent::total 0.920945 # Average percentage of cache occupancy 1658system.cpu1.dcache.ReadReq_hits::cpu1.data 4389322 # number of ReadReq hits 1659system.cpu1.dcache.ReadReq_hits::total 4389322 # number of ReadReq hits 1660system.cpu1.dcache.WriteReq_hits::cpu1.data 3673243 # number of WriteReq hits 1661system.cpu1.dcache.WriteReq_hits::total 3673243 # number of WriteReq hits 1662system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73459 # number of LoadLockedReq hits 1663system.cpu1.dcache.LoadLockedReq_hits::total 73459 # number of LoadLockedReq hits 1664system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73734 # number of StoreCondReq hits 1665system.cpu1.dcache.StoreCondReq_hits::total 73734 # number of StoreCondReq hits 1666system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits 1667system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits 1668system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits 1669system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits 1670system.cpu1.dcache.ReadReq_misses::cpu1.data 133853 # number of ReadReq misses 1671system.cpu1.dcache.ReadReq_misses::total 133853 # number of ReadReq misses 1672system.cpu1.dcache.WriteReq_misses::cpu1.data 112791 # number of WriteReq misses 1673system.cpu1.dcache.WriteReq_misses::total 112791 # number of WriteReq misses 1674system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9745 # number of LoadLockedReq misses 1675system.cpu1.dcache.LoadLockedReq_misses::total 9745 # number of LoadLockedReq misses 1676system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9392 # number of StoreCondReq misses 1677system.cpu1.dcache.StoreCondReq_misses::total 9392 # number of StoreCondReq misses 1678system.cpu1.dcache.demand_misses::cpu1.data 246644 # number of demand (read+write) misses 1679system.cpu1.dcache.demand_misses::total 246644 # number of demand (read+write) misses 1680system.cpu1.dcache.overall_misses::cpu1.data 246644 # number of overall misses 1681system.cpu1.dcache.overall_misses::total 246644 # number of overall misses 1682system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1652691000 # number of ReadReq miss cycles 1683system.cpu1.dcache.ReadReq_miss_latency::total 1652691000 # number of ReadReq miss cycles 1684system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3703180000 # number of WriteReq miss cycles 1685system.cpu1.dcache.WriteReq_miss_latency::total 3703180000 # number of WriteReq miss cycles 1686system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77927500 # number of LoadLockedReq miss cycles 1687system.cpu1.dcache.LoadLockedReq_miss_latency::total 77927500 # number of LoadLockedReq miss cycles 1688system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48937000 # number of StoreCondReq miss cycles 1689system.cpu1.dcache.StoreCondReq_miss_latency::total 48937000 # number of StoreCondReq miss cycles 1690system.cpu1.dcache.demand_miss_latency::cpu1.data 5355871000 # number of demand (read+write) miss cycles 1691system.cpu1.dcache.demand_miss_latency::total 5355871000 # number of demand (read+write) miss cycles 1692system.cpu1.dcache.overall_miss_latency::cpu1.data 5355871000 # number of overall miss cycles 1693system.cpu1.dcache.overall_miss_latency::total 5355871000 # number of overall miss cycles 1694system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523175 # number of ReadReq accesses(hits+misses) 1695system.cpu1.dcache.ReadReq_accesses::total 4523175 # number of ReadReq accesses(hits+misses) 1696system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786034 # number of WriteReq accesses(hits+misses) 1697system.cpu1.dcache.WriteReq_accesses::total 3786034 # number of WriteReq accesses(hits+misses) 1698system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83204 # number of LoadLockedReq accesses(hits+misses) 1699system.cpu1.dcache.LoadLockedReq_accesses::total 83204 # number of LoadLockedReq accesses(hits+misses) 1700system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83126 # number of StoreCondReq accesses(hits+misses) 1701system.cpu1.dcache.StoreCondReq_accesses::total 83126 # number of StoreCondReq accesses(hits+misses) 1702system.cpu1.dcache.demand_accesses::cpu1.data 8309209 # number of demand (read+write) accesses 1703system.cpu1.dcache.demand_accesses::total 8309209 # number of demand (read+write) accesses 1704system.cpu1.dcache.overall_accesses::cpu1.data 8309209 # number of overall (read+write) accesses 1705system.cpu1.dcache.overall_accesses::total 8309209 # number of overall (read+write) accesses 1706system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029593 # miss rate for ReadReq accesses 1707system.cpu1.dcache.ReadReq_miss_rate::total 0.029593 # miss rate for ReadReq accesses 1708system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029791 # miss rate for WriteReq accesses 1709system.cpu1.dcache.WriteReq_miss_rate::total 0.029791 # miss rate for WriteReq accesses 1710system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117122 # miss rate for LoadLockedReq accesses 1711system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117122 # miss rate for LoadLockedReq accesses 1712system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112985 # miss rate for StoreCondReq accesses 1713system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112985 # miss rate for StoreCondReq accesses 1714system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029683 # miss rate for demand accesses 1715system.cpu1.dcache.demand_miss_rate::total 0.029683 # miss rate for demand accesses 1716system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029683 # miss rate for overall accesses 1717system.cpu1.dcache.overall_miss_rate::total 0.029683 # miss rate for overall accesses 1718system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12347.059834 # average ReadReq miss latency 1719system.cpu1.dcache.ReadReq_avg_miss_latency::total 12347.059834 # average ReadReq miss latency 1720system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32832.229522 # average WriteReq miss latency 1721system.cpu1.dcache.WriteReq_avg_miss_latency::total 32832.229522 # average WriteReq miss latency 1722system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7996.664956 # average LoadLockedReq miss latency 1723system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7996.664956 # average LoadLockedReq miss latency 1724system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5210.498296 # average StoreCondReq miss latency 1725system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5210.498296 # average StoreCondReq miss latency 1726system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency 1727system.cpu1.dcache.demand_avg_miss_latency::total 21714.985972 # average overall miss latency 1728system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency 1729system.cpu1.dcache.overall_avg_miss_latency::total 21714.985972 # average overall miss latency |
| 1183system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1190system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1730system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1731system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1732system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1733system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1734system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1735system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1736system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1737system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1191system.cpu1.dcache.writebacks::writebacks 265193 # number of writebacks 1192system.cpu1.dcache.writebacks::total 265193 # number of writebacks 1193system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170592 # number of ReadReq MSHR misses 1194system.cpu1.dcache.ReadReq_mshr_misses::total 170592 # number of ReadReq MSHR misses 1195system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149961 # number of WriteReq MSHR misses 1196system.cpu1.dcache.WriteReq_mshr_misses::total 149961 # number of WriteReq MSHR misses 1197system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11053 # number of LoadLockedReq MSHR misses 1198system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11053 # number of LoadLockedReq MSHR misses 1199system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10042 # number of StoreCondReq MSHR misses 1200system.cpu1.dcache.StoreCondReq_mshr_misses::total 10042 # number of StoreCondReq MSHR misses 1201system.cpu1.dcache.demand_mshr_misses::cpu1.data 320553 # number of demand (read+write) MSHR misses 1202system.cpu1.dcache.demand_mshr_misses::total 320553 # number of demand (read+write) MSHR misses 1203system.cpu1.dcache.overall_mshr_misses::cpu1.data 320553 # number of overall MSHR misses 1204system.cpu1.dcache.overall_mshr_misses::total 320553 # number of overall MSHR misses 1205system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1822921500 # number of ReadReq MSHR miss cycles 1206system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1822921500 # number of ReadReq MSHR miss cycles 1207system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4235901500 # number of WriteReq MSHR miss cycles 1208system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4235901500 # number of WriteReq MSHR miss cycles 1209system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70121500 # number of LoadLockedReq MSHR miss cycles 1210system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70121500 # number of LoadLockedReq MSHR miss cycles 1211system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31910500 # number of StoreCondReq MSHR miss cycles 1212system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31910500 # number of StoreCondReq MSHR miss cycles | 1738system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks 1739system.cpu1.dcache.writebacks::total 199647 # number of writebacks 1740system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses 1741system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # number of ReadReq MSHR misses 1742system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112791 # number of WriteReq MSHR misses 1743system.cpu1.dcache.WriteReq_mshr_misses::total 112791 # number of WriteReq MSHR misses 1744system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses 1745system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses 1746system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses 1747system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses 1748system.cpu1.dcache.demand_mshr_misses::cpu1.data 246644 # number of demand (read+write) MSHR misses 1749system.cpu1.dcache.demand_mshr_misses::total 246644 # number of demand (read+write) MSHR misses 1750system.cpu1.dcache.overall_mshr_misses::cpu1.data 246644 # number of overall MSHR misses 1751system.cpu1.dcache.overall_mshr_misses::total 246644 # number of overall MSHR misses 1752system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384976517 # number of ReadReq MSHR miss cycles 1753system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384976517 # number of ReadReq MSHR miss cycles 1754system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3477593010 # number of WriteReq MSHR miss cycles 1755system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3477593010 # number of WriteReq MSHR miss cycles 1756system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58436502 # number of LoadLockedReq MSHR miss cycles 1757system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58436502 # number of LoadLockedReq MSHR miss cycles 1758system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles 1759system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles |
| 1213system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1214system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles | 1760system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1761system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles |
| 1215system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6058823000 # number of demand (read+write) MSHR miss cycles 1216system.cpu1.dcache.demand_mshr_miss_latency::total 6058823000 # number of demand (read+write) MSHR miss cycles 1217system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6058823000 # number of overall MSHR miss cycles 1218system.cpu1.dcache.overall_mshr_miss_latency::total 6058823000 # number of overall MSHR miss cycles 1219system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642031500 # number of ReadReq MSHR uncacheable cycles 1220system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642031500 # number of ReadReq MSHR uncacheable cycles 1221system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668268500 # number of WriteReq MSHR uncacheable cycles 1222system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668268500 # number of WriteReq MSHR uncacheable cycles 1223system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186310300000 # number of overall MSHR uncacheable cycles 1224system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186310300000 # number of overall MSHR uncacheable cycles 1225system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023965 # mshr miss rate for ReadReq accesses 1226system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023965 # mshr miss rate for ReadReq accesses 1227system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses 1228system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses 1229system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119040 # mshr miss rate for LoadLockedReq accesses 1230system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119040 # mshr miss rate for LoadLockedReq accesses 1231system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108237 # mshr miss rate for StoreCondReq accesses 1232system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108237 # mshr miss rate for StoreCondReq accesses 1233system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for demand accesses 1234system.cpu1.dcache.demand_mshr_miss_rate::total 0.026500 # mshr miss rate for demand accesses 1235system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for overall accesses 1236system.cpu1.dcache.overall_mshr_miss_rate::total 0.026500 # mshr miss rate for overall accesses 1237system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency 1238system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10685.855726 # average ReadReq mshr miss latency 1239system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28246.687472 # average WriteReq mshr miss latency 1240system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28246.687472 # average WriteReq mshr miss latency 1241system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6344.114720 # average LoadLockedReq mshr miss latency 1242system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6344.114720 # average LoadLockedReq mshr miss latency 1243system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3177.703645 # average StoreCondReq mshr miss latency 1244system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3177.703645 # average StoreCondReq mshr miss latency | 1762system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles 1763system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles 1764system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles 1765system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles 1766system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles 1767system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles 1768system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles 1769system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles 1770system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles 1771system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles 1772system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses 1773system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses 1774system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses 1775system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses 1776system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses 1777system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses 1778system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses 1779system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses 1780system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses 1781system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses 1782system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses 1783system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses 1784system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency 1785system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency 1786system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency 1787system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency 1788system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency 1789system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency 1790system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency 1791system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency |
| 1245system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1246system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1792system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1793system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1247system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency 1248system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency 1249system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency 1250system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency | 1794system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency 1795system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency 1796system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency 1797system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency |
| 1251system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1252system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1253system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1254system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1255system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1256system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1257system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1258system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1264system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1265system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1266system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1267system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1268system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1269system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1270system.iocache.fast_writes 0 # number of fast writes performed 1271system.iocache.cache_copies 0 # number of cache copies performed | 1798system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1799system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1800system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1801system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1802system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1803system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1804system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1805system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1811system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1812system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1813system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1814system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1815system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1816system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1817system.iocache.fast_writes 0 # number of fast writes performed 1818system.iocache.cache_copies 0 # number of cache copies performed |
| 1272system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles 1273system.iocache.ReadReq_mshr_uncacheable_latency::total 509664351240 # number of ReadReq MSHR uncacheable cycles 1274system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles 1275system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles | 1819system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles 1820system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles 1821system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles 1822system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles |
| 1276system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1277system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1278system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1279system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1280system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1281 1282---------- End Simulation Statistics ---------- | 1823system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1824system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1825system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1826system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1827system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1828 1829---------- End Simulation Statistics ---------- |