| stats.txt (9490:e6a09d97bdc9) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.183003 # Number of seconds simulated 4sim_ticks 1183003114000 # Number of ticks simulated 5final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.182958 # Number of seconds simulated 4sim_ticks 1182958259000 # Number of ticks simulated 5final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 673901 # Simulator instruction rate (inst/s) 8host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12970235901 # Simulator tick rate (ticks/s) 10host_mem_usage 408748 # Number of bytes of host memory used 11host_seconds 91.21 # Real time elapsed on the host 12sim_insts 61465824 # Number of instructions simulated 13sim_ops 78326377 # Number of ops (including micro ops) simulated | 7host_inst_rate 332432 # Simulator instruction rate (inst/s) 8host_op_rate 423606 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6399087906 # Simulator tick rate (ticks/s) 10host_mem_usage 408760 # Number of bytes of host memory used 11host_seconds 184.86 # Real time elapsed on the host 12sim_insts 61454647 # Number of instructions simulated 13sim_ops 78309315 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory | 20system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory | 29system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory |
| 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory | 36system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory |
| 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
| 42system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) | 42system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s) |
| 44system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) |
| 45system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) | 45system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s) |
| 61system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) |
| 62system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) | 62system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s) |
| 65system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) | 65system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654023 # Total number of read requests seen 70system.physmem.writeReqs 820738 # Total number of write requests seen 71system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 425857472 # Total number of bytes read from memory 73system.physmem.bytesWritten 52527232 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() | 66system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654489 # Total number of read requests seen 70system.physmem.writeReqs 821150 # Total number of write requests seen 71system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 425887296 # Total number of bytes read from memory 73system.physmem.bytesWritten 52553600 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize() |
| 76system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q | 76system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q |
| 77system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis | 77system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis |
| 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 112system.physmem.totGap 1182998675500 # Total gap between requests | 112system.physmem.totGap 1182953705000 # Total gap between requests |
| 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 6825 # Categorize read packet sizes 116system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes | 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 6825 # Categorize read packet sizes 116system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 119system.physmem.readPktSize::6 159134 # Categorize read packet sizes 120system.physmem.readPktSize::7 0 # Categorize read packet sizes 121system.physmem.readPktSize::8 0 # Categorize read packet sizes 122system.physmem.writePktSize::0 0 # categorize write packet sizes 123system.physmem.writePktSize::1 0 # categorize write packet sizes 124system.physmem.writePktSize::2 756836 # categorize write packet sizes 125system.physmem.writePktSize::3 0 # categorize write packet sizes 126system.physmem.writePktSize::4 0 # categorize write packet sizes 127system.physmem.writePktSize::5 0 # categorize write packet sizes 128system.physmem.writePktSize::6 63902 # categorize write packet sizes 129system.physmem.writePktSize::7 0 # categorize write packet sizes 130system.physmem.writePktSize::8 0 # categorize write packet sizes 131system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 132system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 133system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 134system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 135system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 136system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 137system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes 138system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 139system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 140system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see | 119system.physmem.readPktSize::6 159600 # Categorize read packet sizes 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes 122system.physmem.writePktSize::2 756836 # Categorize write packet sizes 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes 126system.physmem.writePktSize::6 64314 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see |
| 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 144system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 172system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::0 35451 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 35684 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 35689 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 35694 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 35698 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 35700 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 35702 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 35702 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 35702 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 35702 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 35702 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 35702 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 35702 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 35702 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 35702 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 35702 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 35702 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 35702 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 35702 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 35702 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 35702 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 252 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see |
| 201system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see | 187system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see |
| 202system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 206system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays 207system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests 208system.physmem.totBusLat 33269555000 # Total cycles spent in databus access 209system.physmem.totBankLat 9041986250 # Total cycles spent in bank access 210system.physmem.avgQLat 22090.22 # Average queueing delay per request 211system.physmem.avgBankLat 1358.90 # Average bank access latency per request | 188system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 191system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays 192system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests 193system.physmem.totBusLat 33271885000 # Total cycles spent in databus access 194system.physmem.totBankLat 9050992500 # Total cycles spent in bank access 195system.physmem.avgQLat 22093.24 # Average queueing delay per request 196system.physmem.avgBankLat 1360.16 # Average bank access latency per request |
| 212system.physmem.avgBusLat 5000.00 # Average bus latency per request | 197system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 213system.physmem.avgMemAccLat 28449.12 # Average memory access latency 214system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s 215system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s 216system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s 217system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s | 198system.physmem.avgMemAccLat 28453.39 # Average memory access latency 199system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s 200system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s 201system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s 202system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s |
| 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 219system.physmem.busUtil 3.16 # Data bus utilization in percentage 220system.physmem.avgRdQLen 0.16 # Average read queue length over time | 203system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 204system.physmem.busUtil 3.16 # Data bus utilization in percentage 205system.physmem.avgRdQLen 0.16 # Average read queue length over time |
| 221system.physmem.avgWrQLen 12.54 # Average write queue length over time 222system.physmem.readRowHits 6611960 # Number of row buffer hits during reads 223system.physmem.writeRowHits 800133 # Number of row buffer hits during writes | 206system.physmem.avgWrQLen 12.52 # Average write queue length over time 207system.physmem.readRowHits 6612346 # Number of row buffer hits during reads 208system.physmem.writeRowHits 800481 # Number of row buffer hits during writes |
| 224system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads | 209system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads |
| 225system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes 226system.physmem.avgGap 158265.75 # Average gap between requests | 210system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes 211system.physmem.avgGap 158241.15 # Average gap between requests |
| 227system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 228system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 229system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 230system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 231system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 232system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 233system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 234system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 235system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 236system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 237system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 238system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 239system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 240system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 241system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 242system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 243system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 244system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) | 212system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 213system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 214system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 215system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 216system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 217system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 218system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 219system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 220system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 221system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 222system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 223system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 224system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 225system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 228system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 229system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) |
| 245system.l2c.replacements 69015 # number of replacements 246system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use 247system.l2c.total_refs 1678594 # Total number of references to valid blocks. 248system.l2c.sampled_refs 134211 # Sample count of references to valid blocks. 249system.l2c.avg_refs 12.507127 # Average number of references to valid blocks. | 230system.l2c.replacements 69480 # number of replacements 231system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use 232system.l2c.total_refs 1677464 # Total number of references to valid blocks. 233system.l2c.sampled_refs 134656 # Sample count of references to valid blocks. 234system.l2c.avg_refs 12.457403 # Average number of references to valid blocks. |
| 250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 235system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 251system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor | 236system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor |
| 252system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor | 237system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor |
| 253system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor 254system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor 255system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor 256system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor 257system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor 258system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor 259system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy | 238system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor 239system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor 240system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor 244system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy |
| 260system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 261system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 245system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 246system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 262system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy 263system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy | 247system.l2c.occ_percent::cpu0.inst 0.056871 # Average percentage of cache occupancy 248system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy |
| 264system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy | 249system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy |
| 265system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy 266system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy 267system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits 278system.l2c.Writeback_hits::total 573205 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits 281system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits 282system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits 283system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits 284system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits 285system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits 286system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits 287system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits 288system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits 289system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits 290system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits 291system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits 292system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits 293system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits 294system.l2c.demand_hits::cpu1.inst 534803 # number of demand (read+write) hits 295system.l2c.demand_hits::cpu1.data 243393 # number of demand (read+write) hits 296system.l2c.demand_hits::total 1358024 # number of demand (read+write) hits 297system.l2c.overall_hits::cpu0.dtb.walker 3013 # number of overall hits 298system.l2c.overall_hits::cpu0.itb.walker 1662 # number of overall hits 299system.l2c.overall_hits::cpu0.inst 349398 # number of overall hits 300system.l2c.overall_hits::cpu0.data 217423 # number of overall hits 301system.l2c.overall_hits::cpu1.dtb.walker 6389 # number of overall hits 302system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits 303system.l2c.overall_hits::cpu1.inst 534803 # number of overall hits 304system.l2c.overall_hits::cpu1.data 243393 # number of overall hits 305system.l2c.overall_hits::total 1358024 # number of overall hits | 250system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu1.data 0.031453 # Average percentage of cache occupancy 252system.l2c.occ_percent::total 0.809346 # Average percentage of cache occupancy 253system.l2c.ReadReq_hits::cpu0.dtb.walker 3740 # number of ReadReq hits 254system.l2c.ReadReq_hits::cpu0.itb.walker 1661 # number of ReadReq hits 255system.l2c.ReadReq_hits::cpu0.inst 419713 # number of ReadReq hits 256system.l2c.ReadReq_hits::cpu0.data 206323 # number of ReadReq hits 257system.l2c.ReadReq_hits::cpu1.dtb.walker 5388 # number of ReadReq hits 258system.l2c.ReadReq_hits::cpu1.itb.walker 1856 # number of ReadReq hits 259system.l2c.ReadReq_hits::cpu1.inst 464159 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu1.data 143887 # number of ReadReq hits 261system.l2c.ReadReq_hits::total 1246727 # number of ReadReq hits 262system.l2c.Writeback_hits::writebacks 572264 # number of Writeback hits 263system.l2c.Writeback_hits::total 572264 # number of Writeback hits 264system.l2c.UpgradeReq_hits::cpu0.data 1120 # number of UpgradeReq hits 265system.l2c.UpgradeReq_hits::cpu1.data 606 # number of UpgradeReq hits 266system.l2c.UpgradeReq_hits::total 1726 # number of UpgradeReq hits 267system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits 268system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits 269system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits 270system.l2c.ReadExReq_hits::cpu0.data 57066 # number of ReadExReq hits 271system.l2c.ReadExReq_hits::cpu1.data 52392 # number of ReadExReq hits 272system.l2c.ReadExReq_hits::total 109458 # number of ReadExReq hits 273system.l2c.demand_hits::cpu0.dtb.walker 3740 # number of demand (read+write) hits 274system.l2c.demand_hits::cpu0.itb.walker 1661 # number of demand (read+write) hits 275system.l2c.demand_hits::cpu0.inst 419713 # number of demand (read+write) hits 276system.l2c.demand_hits::cpu0.data 263389 # number of demand (read+write) hits 277system.l2c.demand_hits::cpu1.dtb.walker 5388 # number of demand (read+write) hits 278system.l2c.demand_hits::cpu1.itb.walker 1856 # number of demand (read+write) hits 279system.l2c.demand_hits::cpu1.inst 464159 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu1.data 196279 # number of demand (read+write) hits 281system.l2c.demand_hits::total 1356185 # number of demand (read+write) hits 282system.l2c.overall_hits::cpu0.dtb.walker 3740 # number of overall hits 283system.l2c.overall_hits::cpu0.itb.walker 1661 # number of overall hits 284system.l2c.overall_hits::cpu0.inst 419713 # number of overall hits 285system.l2c.overall_hits::cpu0.data 263389 # number of overall hits 286system.l2c.overall_hits::cpu1.dtb.walker 5388 # number of overall hits 287system.l2c.overall_hits::cpu1.itb.walker 1856 # number of overall hits 288system.l2c.overall_hits::cpu1.inst 464159 # number of overall hits 289system.l2c.overall_hits::cpu1.data 196279 # number of overall hits 290system.l2c.overall_hits::total 1356185 # number of overall hits |
| 306system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses | 291system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses |
| 307system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 308system.l2c.ReadReq_misses::cpu0.inst 5520 # number of ReadReq misses 309system.l2c.ReadReq_misses::cpu0.data 7838 # number of ReadReq misses | 292system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 293system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses 294system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses |
| 310system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses | 295system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses |
| 311system.l2c.ReadReq_misses::cpu1.inst 5255 # number of ReadReq misses 312system.l2c.ReadReq_misses::cpu1.data 3644 # number of ReadReq misses 313system.l2c.ReadReq_misses::total 22265 # number of ReadReq misses 314system.l2c.UpgradeReq_misses::cpu0.data 3583 # number of UpgradeReq misses 315system.l2c.UpgradeReq_misses::cpu1.data 4723 # number of UpgradeReq misses 316system.l2c.UpgradeReq_misses::total 8306 # number of UpgradeReq misses 317system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses 318system.l2c.SCUpgradeReq_misses::cpu1.data 461 # number of SCUpgradeReq misses | 296system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses 297system.l2c.ReadReq_misses::cpu1.data 3624 # number of ReadReq misses 298system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses 299system.l2c.UpgradeReq_misses::cpu0.data 4701 # number of UpgradeReq misses 300system.l2c.UpgradeReq_misses::cpu1.data 3596 # number of UpgradeReq misses 301system.l2c.UpgradeReq_misses::total 8297 # number of UpgradeReq misses 302system.l2c.SCUpgradeReq_misses::cpu0.data 563 # number of SCUpgradeReq misses 303system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses |
| 319system.l2c.SCUpgradeReq_misses::total 1032 # number of SCUpgradeReq misses | 304system.l2c.SCUpgradeReq_misses::total 1032 # number of SCUpgradeReq misses |
| 320system.l2c.ReadExReq_misses::cpu0.data 63840 # number of ReadExReq misses 321system.l2c.ReadExReq_misses::cpu1.data 75452 # number of ReadExReq misses 322system.l2c.ReadExReq_misses::total 139292 # number of ReadExReq misses | 305system.l2c.ReadExReq_misses::cpu0.data 67050 # number of ReadExReq misses 306system.l2c.ReadExReq_misses::cpu1.data 72720 # number of ReadExReq misses 307system.l2c.ReadExReq_misses::total 139770 # number of ReadExReq misses |
| 323system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses | 308system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses |
| 324system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 325system.l2c.demand_misses::cpu0.inst 5520 # number of demand (read+write) misses 326system.l2c.demand_misses::cpu0.data 71678 # number of demand (read+write) misses | 309system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 310system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses 311system.l2c.demand_misses::cpu0.data 74913 # number of demand (read+write) misses |
| 327system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses | 312system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses |
| 328system.l2c.demand_misses::cpu1.inst 5255 # number of demand (read+write) misses 329system.l2c.demand_misses::cpu1.data 79096 # number of demand (read+write) misses 330system.l2c.demand_misses::total 161557 # number of demand (read+write) misses | 313system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses 314system.l2c.demand_misses::cpu1.data 76344 # number of demand (read+write) misses 315system.l2c.demand_misses::total 162041 # number of demand (read+write) misses |
| 331system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses | 316system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses |
| 332system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 333system.l2c.overall_misses::cpu0.inst 5520 # number of overall misses 334system.l2c.overall_misses::cpu0.data 71678 # number of overall misses | 317system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 318system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses 319system.l2c.overall_misses::cpu0.data 74913 # number of overall misses |
| 335system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses | 320system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses |
| 336system.l2c.overall_misses::cpu1.inst 5255 # number of overall misses 337system.l2c.overall_misses::cpu1.data 79096 # number of overall misses 338system.l2c.overall_misses::total 161557 # number of overall misses | 321system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses 322system.l2c.overall_misses::cpu1.data 76344 # number of overall misses 323system.l2c.overall_misses::total 162041 # number of overall misses |
| 339system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles | 324system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles |
| 340system.l2c.ReadReq_miss_latency::cpu0.itb.walker 151500 # number of ReadReq miss cycles 341system.l2c.ReadReq_miss_latency::cpu0.inst 286631500 # number of ReadReq miss cycles 342system.l2c.ReadReq_miss_latency::cpu0.data 416021500 # number of ReadReq miss cycles | 325system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles 326system.l2c.ReadReq_miss_latency::cpu0.inst 299840500 # number of ReadReq miss cycles 327system.l2c.ReadReq_miss_latency::cpu0.data 416754500 # number of ReadReq miss cycles |
| 343system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles | 328system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles |
| 344system.l2c.ReadReq_miss_latency::cpu1.inst 290826000 # number of ReadReq miss cycles 345system.l2c.ReadReq_miss_latency::cpu1.data 222550500 # number of ReadReq miss cycles 346system.l2c.ReadReq_miss_latency::total 1216497500 # number of ReadReq miss cycles 347system.l2c.UpgradeReq_miss_latency::cpu0.data 10882997 # number of UpgradeReq miss cycles 348system.l2c.UpgradeReq_miss_latency::cpu1.data 13761999 # number of UpgradeReq miss cycles 349system.l2c.UpgradeReq_miss_latency::total 24644996 # number of UpgradeReq miss cycles 350system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1755500 # number of SCUpgradeReq miss cycles 351system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2248500 # number of SCUpgradeReq miss cycles 352system.l2c.SCUpgradeReq_miss_latency::total 4004000 # number of SCUpgradeReq miss cycles 353system.l2c.ReadExReq_miss_latency::cpu0.data 2848043983 # number of ReadExReq miss cycles 354system.l2c.ReadExReq_miss_latency::cpu1.data 3574373499 # number of ReadExReq miss cycles 355system.l2c.ReadExReq_miss_latency::total 6422417482 # number of ReadExReq miss cycles | 329system.l2c.ReadReq_miss_latency::cpu1.inst 276698000 # number of ReadReq miss cycles 330system.l2c.ReadReq_miss_latency::cpu1.data 223564500 # number of ReadReq miss cycles 331system.l2c.ReadReq_miss_latency::total 1217256500 # number of ReadReq miss cycles 332system.l2c.UpgradeReq_miss_latency::cpu0.data 12757497 # number of UpgradeReq miss cycles 333system.l2c.UpgradeReq_miss_latency::cpu1.data 11938999 # number of UpgradeReq miss cycles 334system.l2c.UpgradeReq_miss_latency::total 24696496 # number of UpgradeReq miss cycles 335system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1598500 # number of SCUpgradeReq miss cycles 336system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles 337system.l2c.SCUpgradeReq_miss_latency::total 4007000 # number of SCUpgradeReq miss cycles 338system.l2c.ReadExReq_miss_latency::cpu0.data 3004157980 # number of ReadExReq miss cycles 339system.l2c.ReadExReq_miss_latency::cpu1.data 3438233497 # number of ReadExReq miss cycles 340system.l2c.ReadExReq_miss_latency::total 6442391477 # number of ReadExReq miss cycles |
| 356system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles | 341system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles |
| 357system.l2c.demand_miss_latency::cpu0.itb.walker 151500 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu0.inst 286631500 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::cpu0.data 3264065483 # number of demand (read+write) miss cycles | 342system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles 343system.l2c.demand_miss_latency::cpu0.inst 299840500 # number of demand (read+write) miss cycles 344system.l2c.demand_miss_latency::cpu0.data 3420912480 # number of demand (read+write) miss cycles |
| 360system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles | 345system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles |
| 361system.l2c.demand_miss_latency::cpu1.inst 290826000 # number of demand (read+write) miss cycles 362system.l2c.demand_miss_latency::cpu1.data 3796923999 # number of demand (read+write) miss cycles 363system.l2c.demand_miss_latency::total 7638914982 # number of demand (read+write) miss cycles | 346system.l2c.demand_miss_latency::cpu1.inst 276698000 # number of demand (read+write) miss cycles 347system.l2c.demand_miss_latency::cpu1.data 3661797997 # number of demand (read+write) miss cycles 348system.l2c.demand_miss_latency::total 7659647977 # number of demand (read+write) miss cycles |
| 364system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles | 349system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles |
| 365system.l2c.overall_miss_latency::cpu0.itb.walker 151500 # number of overall miss cycles 366system.l2c.overall_miss_latency::cpu0.inst 286631500 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu0.data 3264065483 # number of overall miss cycles | 350system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles 351system.l2c.overall_miss_latency::cpu0.inst 299840500 # number of overall miss cycles 352system.l2c.overall_miss_latency::cpu0.data 3420912480 # number of overall miss cycles |
| 368system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles | 353system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles |
| 369system.l2c.overall_miss_latency::cpu1.inst 290826000 # number of overall miss cycles 370system.l2c.overall_miss_latency::cpu1.data 3796923999 # number of overall miss cycles 371system.l2c.overall_miss_latency::total 7638914982 # number of overall miss cycles 372system.l2c.ReadReq_accesses::cpu0.dtb.walker 3014 # number of ReadReq accesses(hits+misses) 373system.l2c.ReadReq_accesses::cpu0.itb.walker 1665 # number of ReadReq accesses(hits+misses) 374system.l2c.ReadReq_accesses::cpu0.inst 354918 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu0.data 177753 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.dtb.walker 6393 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses) 378system.l2c.ReadReq_accesses::cpu1.inst 540058 # number of ReadReq accesses(hits+misses) 379system.l2c.ReadReq_accesses::cpu1.data 184457 # number of ReadReq accesses(hits+misses) 380system.l2c.ReadReq_accesses::total 1270201 # number of ReadReq accesses(hits+misses) 381system.l2c.Writeback_accesses::writebacks 573205 # number of Writeback accesses(hits+misses) 382system.l2c.Writeback_accesses::total 573205 # number of Writeback accesses(hits+misses) 383system.l2c.UpgradeReq_accesses::cpu0.data 4704 # number of UpgradeReq accesses(hits+misses) 384system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses) 385system.l2c.UpgradeReq_accesses::total 10038 # number of UpgradeReq accesses(hits+misses) 386system.l2c.SCUpgradeReq_accesses::cpu0.data 800 # number of SCUpgradeReq accesses(hits+misses) 387system.l2c.SCUpgradeReq_accesses::cpu1.data 539 # number of SCUpgradeReq accesses(hits+misses) 388system.l2c.SCUpgradeReq_accesses::total 1339 # number of SCUpgradeReq accesses(hits+misses) 389system.l2c.ReadExReq_accesses::cpu0.data 111348 # number of ReadExReq accesses(hits+misses) 390system.l2c.ReadExReq_accesses::cpu1.data 138032 # number of ReadExReq accesses(hits+misses) 391system.l2c.ReadExReq_accesses::total 249380 # number of ReadExReq accesses(hits+misses) 392system.l2c.demand_accesses::cpu0.dtb.walker 3014 # number of demand (read+write) accesses 393system.l2c.demand_accesses::cpu0.itb.walker 1665 # number of demand (read+write) accesses 394system.l2c.demand_accesses::cpu0.inst 354918 # number of demand (read+write) accesses 395system.l2c.demand_accesses::cpu0.data 289101 # number of demand (read+write) accesses 396system.l2c.demand_accesses::cpu1.dtb.walker 6393 # number of demand (read+write) accesses 397system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses 398system.l2c.demand_accesses::cpu1.inst 540058 # number of demand (read+write) accesses 399system.l2c.demand_accesses::cpu1.data 322489 # number of demand (read+write) accesses 400system.l2c.demand_accesses::total 1519581 # number of demand (read+write) accesses 401system.l2c.overall_accesses::cpu0.dtb.walker 3014 # number of overall (read+write) accesses 402system.l2c.overall_accesses::cpu0.itb.walker 1665 # number of overall (read+write) accesses 403system.l2c.overall_accesses::cpu0.inst 354918 # number of overall (read+write) accesses 404system.l2c.overall_accesses::cpu0.data 289101 # number of overall (read+write) accesses 405system.l2c.overall_accesses::cpu1.dtb.walker 6393 # number of overall (read+write) accesses 406system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses 407system.l2c.overall_accesses::cpu1.inst 540058 # number of overall (read+write) accesses 408system.l2c.overall_accesses::cpu1.data 322489 # number of overall (read+write) accesses 409system.l2c.overall_accesses::total 1519581 # number of overall (read+write) accesses 410system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for ReadReq accesses 411system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001802 # miss rate for ReadReq accesses 412system.l2c.ReadReq_miss_rate::cpu0.inst 0.015553 # miss rate for ReadReq accesses 413system.l2c.ReadReq_miss_rate::cpu0.data 0.044095 # miss rate for ReadReq accesses 414system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for ReadReq accesses 415system.l2c.ReadReq_miss_rate::cpu1.inst 0.009730 # miss rate for ReadReq accesses 416system.l2c.ReadReq_miss_rate::cpu1.data 0.019755 # miss rate for ReadReq accesses 417system.l2c.ReadReq_miss_rate::total 0.017529 # miss rate for ReadReq accesses 418system.l2c.UpgradeReq_miss_rate::cpu0.data 0.761692 # miss rate for UpgradeReq accesses 419system.l2c.UpgradeReq_miss_rate::cpu1.data 0.885452 # miss rate for UpgradeReq accesses 420system.l2c.UpgradeReq_miss_rate::total 0.827456 # miss rate for UpgradeReq accesses 421system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.713750 # miss rate for SCUpgradeReq accesses 422system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.855288 # miss rate for SCUpgradeReq accesses 423system.l2c.SCUpgradeReq_miss_rate::total 0.770724 # miss rate for SCUpgradeReq accesses 424system.l2c.ReadExReq_miss_rate::cpu0.data 0.573338 # miss rate for ReadExReq accesses 425system.l2c.ReadExReq_miss_rate::cpu1.data 0.546627 # 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miss rate for overall accesses 438system.l2c.overall_miss_rate::cpu0.data 0.247934 # miss rate for overall accesses 439system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for overall accesses 440system.l2c.overall_miss_rate::cpu1.inst 0.009730 # miss rate for overall accesses 441system.l2c.overall_miss_rate::cpu1.data 0.245267 # miss rate for overall accesses 442system.l2c.overall_miss_rate::total 0.106317 # miss rate for overall accesses | 354system.l2c.overall_miss_latency::cpu1.inst 276698000 # number of overall miss cycles 355system.l2c.overall_miss_latency::cpu1.data 3661797997 # number of overall miss cycles 356system.l2c.overall_miss_latency::total 7659647977 # number of overall miss cycles 357system.l2c.ReadReq_accesses::cpu0.dtb.walker 3741 # number of ReadReq accesses(hits+misses) 358system.l2c.ReadReq_accesses::cpu0.itb.walker 1663 # number of ReadReq accesses(hits+misses) 359system.l2c.ReadReq_accesses::cpu0.inst 425446 # number of ReadReq accesses(hits+misses) 360system.l2c.ReadReq_accesses::cpu0.data 214186 # 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number of SCUpgradeReq accesses(hits+misses) 372system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses) 373system.l2c.SCUpgradeReq_accesses::total 1348 # number of SCUpgradeReq accesses(hits+misses) 374system.l2c.ReadExReq_accesses::cpu0.data 124116 # number of ReadExReq accesses(hits+misses) 375system.l2c.ReadExReq_accesses::cpu1.data 125112 # number of ReadExReq accesses(hits+misses) 376system.l2c.ReadExReq_accesses::total 249228 # number of ReadExReq accesses(hits+misses) 377system.l2c.demand_accesses::cpu0.dtb.walker 3741 # number of demand (read+write) accesses 378system.l2c.demand_accesses::cpu0.itb.walker 1663 # number of demand (read+write) accesses 379system.l2c.demand_accesses::cpu0.inst 425446 # number of demand (read+write) accesses 380system.l2c.demand_accesses::cpu0.data 338302 # number of demand (read+write) accesses 381system.l2c.demand_accesses::cpu1.dtb.walker 5392 # number of demand (read+write) accesses 382system.l2c.demand_accesses::cpu1.itb.walker 1856 # number of demand (read+write) accesses 383system.l2c.demand_accesses::cpu1.inst 469203 # number of demand (read+write) accesses 384system.l2c.demand_accesses::cpu1.data 272623 # number of demand (read+write) accesses 385system.l2c.demand_accesses::total 1518226 # number of demand (read+write) accesses 386system.l2c.overall_accesses::cpu0.dtb.walker 3741 # number of overall (read+write) accesses 387system.l2c.overall_accesses::cpu0.itb.walker 1663 # number of overall (read+write) accesses 388system.l2c.overall_accesses::cpu0.inst 425446 # number of overall (read+write) accesses 389system.l2c.overall_accesses::cpu0.data 338302 # number of overall (read+write) accesses 390system.l2c.overall_accesses::cpu1.dtb.walker 5392 # number of overall (read+write) accesses 391system.l2c.overall_accesses::cpu1.itb.walker 1856 # number of overall (read+write) accesses 392system.l2c.overall_accesses::cpu1.inst 469203 # number of overall (read+write) accesses 393system.l2c.overall_accesses::cpu1.data 272623 # number of overall (read+write) accesses 394system.l2c.overall_accesses::total 1518226 # number of overall (read+write) accesses 395system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for ReadReq accesses 396system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001203 # miss rate for ReadReq accesses 397system.l2c.ReadReq_miss_rate::cpu0.inst 0.013475 # miss rate for ReadReq accesses 398system.l2c.ReadReq_miss_rate::cpu0.data 0.036711 # miss rate for ReadReq accesses 399system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for ReadReq accesses 400system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses 401system.l2c.ReadReq_miss_rate::cpu1.data 0.024568 # miss rate for ReadReq accesses 402system.l2c.ReadReq_miss_rate::total 0.017550 # miss rate for ReadReq accesses 403system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807593 # miss rate for UpgradeReq accesses 404system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855783 # miss rate for UpgradeReq accesses 405system.l2c.UpgradeReq_miss_rate::total 0.827796 # miss rate for UpgradeReq accesses 406system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722721 # miss rate for SCUpgradeReq accesses 407system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.824253 # miss rate for SCUpgradeReq accesses 408system.l2c.SCUpgradeReq_miss_rate::total 0.765579 # miss rate for SCUpgradeReq accesses 409system.l2c.ReadExReq_miss_rate::cpu0.data 0.540220 # miss rate for ReadExReq accesses 410system.l2c.ReadExReq_miss_rate::cpu1.data 0.581239 # miss rate for ReadExReq accesses 411system.l2c.ReadExReq_miss_rate::total 0.560812 # miss rate for ReadExReq accesses 412system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for demand accesses 413system.l2c.demand_miss_rate::cpu0.itb.walker 0.001203 # miss rate for demand accesses 414system.l2c.demand_miss_rate::cpu0.inst 0.013475 # miss rate for demand accesses 415system.l2c.demand_miss_rate::cpu0.data 0.221438 # miss rate for demand accesses 416system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for demand accesses 417system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses 418system.l2c.demand_miss_rate::cpu1.data 0.280035 # miss rate for demand accesses 419system.l2c.demand_miss_rate::total 0.106730 # miss rate for demand accesses 420system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for overall accesses 421system.l2c.overall_miss_rate::cpu0.itb.walker 0.001203 # miss rate for overall accesses 422system.l2c.overall_miss_rate::cpu0.inst 0.013475 # miss rate for overall accesses 423system.l2c.overall_miss_rate::cpu0.data 0.221438 # miss rate for overall accesses 424system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for overall accesses 425system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses 426system.l2c.overall_miss_rate::cpu1.data 0.280035 # miss rate for overall accesses 427system.l2c.overall_miss_rate::total 0.106730 # miss rate for overall accesses |
| 443system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency | 428system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency |
| 444system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 50500 # average ReadReq miss latency 445system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51925.996377 # average ReadReq miss latency 446system.l2c.ReadReq_avg_miss_latency::cpu0.data 53077.507017 # average ReadReq miss latency | 429system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency 430system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52300.802372 # average ReadReq miss latency 431system.l2c.ReadReq_avg_miss_latency::cpu0.data 53001.971258 # average ReadReq miss latency |
| 447system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency | 432system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency |
| 448system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55342.721218 # average ReadReq miss latency 449system.l2c.ReadReq_avg_miss_latency::cpu1.data 61073.133919 # average ReadReq miss latency 450system.l2c.ReadReq_avg_miss_latency::total 54637.210869 # average ReadReq miss latency 451system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3037.397991 # average UpgradeReq miss latency 452system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2913.825746 # average UpgradeReq miss latency 453system.l2c.UpgradeReq_avg_miss_latency::total 2967.131712 # average UpgradeReq miss latency 454system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3074.430823 # average SCUpgradeReq miss latency 455system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4877.440347 # average SCUpgradeReq miss latency 456system.l2c.SCUpgradeReq_avg_miss_latency::total 3879.844961 # average SCUpgradeReq miss latency 457system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44612.217779 # average ReadExReq miss latency 458system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47372.813166 # average ReadExReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::total 46107.583221 # average ReadExReq miss latency | 433system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54856.859635 # average ReadReq miss latency 434system.l2c.ReadReq_avg_miss_latency::cpu1.data 61689.983444 # average ReadReq miss latency 435system.l2c.ReadReq_avg_miss_latency::total 54656.571326 # average ReadReq miss latency 436system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2713.783663 # average UpgradeReq miss latency 437system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3320.077586 # average UpgradeReq miss latency 438system.l2c.UpgradeReq_avg_miss_latency::total 2976.557310 # average UpgradeReq miss latency 439system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2839.253996 # average SCUpgradeReq miss latency 440system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5135.394456 # average SCUpgradeReq miss latency 441system.l2c.SCUpgradeReq_avg_miss_latency::total 3882.751938 # average SCUpgradeReq miss latency 442system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44804.742431 # average ReadExReq miss latency 443system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47280.438628 # average ReadExReq miss latency 444system.l2c.ReadExReq_avg_miss_latency::total 46092.805874 # average ReadExReq miss latency |
| 460system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency | 445system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency |
| 461system.l2c.demand_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency 462system.l2c.demand_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency 463system.l2c.demand_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency | 446system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency 447system.l2c.demand_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency 448system.l2c.demand_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency |
| 464system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency | 449system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency |
| 465system.l2c.demand_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency 467system.l2c.demand_avg_miss_latency::total 47283.095019 # average overall miss latency | 450system.l2c.demand_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency 451system.l2c.demand_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency 452system.l2c.demand_avg_miss_latency::total 47269.814288 # average overall miss latency |
| 468system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency | 453system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency |
| 469system.l2c.overall_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency 470system.l2c.overall_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency 471system.l2c.overall_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency | 454system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency 455system.l2c.overall_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency 456system.l2c.overall_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency |
| 472system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency | 457system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency |
| 473system.l2c.overall_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency 474system.l2c.overall_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency 475system.l2c.overall_avg_miss_latency::total 47283.095019 # average overall miss latency | 458system.l2c.overall_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency 459system.l2c.overall_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency 460system.l2c.overall_avg_miss_latency::total 47269.814288 # average overall miss latency |
| 476system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 477system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 478system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 479system.l2c.blocked::no_targets 0 # number of cycles access was blocked 480system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 481system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 482system.l2c.fast_writes 0 # number of fast writes performed 483system.l2c.cache_copies 0 # number of cache copies performed | 461system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 464system.l2c.blocked::no_targets 0 # number of cycles access was blocked 465system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 467system.l2c.fast_writes 0 # number of fast writes performed 468system.l2c.cache_copies 0 # number of cache copies performed |
| 484system.l2c.writebacks::writebacks 63902 # number of writebacks 485system.l2c.writebacks::total 63902 # number of writebacks | 469system.l2c.writebacks::writebacks 64314 # number of writebacks 470system.l2c.writebacks::total 64314 # number of writebacks |
| 486system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 487system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 488system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 489system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 490system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 491system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 492system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses | 471system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 472system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 473system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 474system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 475system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 476system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 477system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses |
| 493system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses 494system.l2c.ReadReq_mshr_misses::cpu0.inst 5519 # number of ReadReq MSHR misses 495system.l2c.ReadReq_mshr_misses::cpu0.data 7838 # number of ReadReq MSHR misses | 478system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 479system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses 480system.l2c.ReadReq_mshr_misses::cpu0.data 7863 # number of ReadReq MSHR misses |
| 496system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses | 481system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses |
| 497system.l2c.ReadReq_mshr_misses::cpu1.inst 5255 # number of ReadReq MSHR misses 498system.l2c.ReadReq_mshr_misses::cpu1.data 3644 # number of ReadReq MSHR misses 499system.l2c.ReadReq_mshr_misses::total 22264 # number of ReadReq MSHR misses 500system.l2c.UpgradeReq_mshr_misses::cpu0.data 3583 # number of UpgradeReq MSHR misses 501system.l2c.UpgradeReq_mshr_misses::cpu1.data 4723 # number of UpgradeReq MSHR misses 502system.l2c.UpgradeReq_mshr_misses::total 8306 # number of UpgradeReq MSHR misses 503system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 571 # number of SCUpgradeReq MSHR misses 504system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 461 # number of SCUpgradeReq MSHR misses | 482system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses 483system.l2c.ReadReq_mshr_misses::cpu1.data 3624 # number of ReadReq MSHR misses 484system.l2c.ReadReq_mshr_misses::total 22270 # number of ReadReq MSHR misses 485system.l2c.UpgradeReq_mshr_misses::cpu0.data 4701 # number of UpgradeReq MSHR misses 486system.l2c.UpgradeReq_mshr_misses::cpu1.data 3596 # number of UpgradeReq MSHR misses 487system.l2c.UpgradeReq_mshr_misses::total 8297 # number of UpgradeReq MSHR misses 488system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 563 # number of SCUpgradeReq MSHR misses 489system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 469 # number of SCUpgradeReq MSHR misses |
| 505system.l2c.SCUpgradeReq_mshr_misses::total 1032 # number of SCUpgradeReq MSHR misses | 490system.l2c.SCUpgradeReq_mshr_misses::total 1032 # number of SCUpgradeReq MSHR misses |
| 506system.l2c.ReadExReq_mshr_misses::cpu0.data 63840 # number of ReadExReq MSHR misses 507system.l2c.ReadExReq_mshr_misses::cpu1.data 75452 # number of ReadExReq MSHR misses 508system.l2c.ReadExReq_mshr_misses::total 139292 # number of ReadExReq MSHR misses | 491system.l2c.ReadExReq_mshr_misses::cpu0.data 67050 # number of ReadExReq MSHR misses 492system.l2c.ReadExReq_mshr_misses::cpu1.data 72720 # number of ReadExReq MSHR misses 493system.l2c.ReadExReq_mshr_misses::total 139770 # number of ReadExReq MSHR misses |
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| 513system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses | 498system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses |
| 514system.l2c.demand_mshr_misses::cpu1.inst 5255 # number of demand (read+write) MSHR misses 515system.l2c.demand_mshr_misses::cpu1.data 79096 # number of demand (read+write) MSHR misses 516system.l2c.demand_mshr_misses::total 161556 # number of demand (read+write) MSHR misses | 499system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses 500system.l2c.demand_mshr_misses::cpu1.data 76344 # number of demand (read+write) MSHR misses 501system.l2c.demand_mshr_misses::total 162040 # number of demand (read+write) MSHR misses |
| 517system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses | 502system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses |
| 518system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 519system.l2c.overall_mshr_misses::cpu0.inst 5519 # number of overall MSHR misses 520system.l2c.overall_mshr_misses::cpu0.data 71678 # number of overall MSHR misses | 503system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 504system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses 505system.l2c.overall_mshr_misses::cpu0.data 74913 # number of overall MSHR misses |
| 521system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses | 506system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses |
| 522system.l2c.overall_mshr_misses::cpu1.inst 5255 # number of overall MSHR misses 523system.l2c.overall_mshr_misses::cpu1.data 79096 # number of overall MSHR misses 524system.l2c.overall_mshr_misses::total 161556 # number of overall MSHR misses 525system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56252 # number of ReadReq MSHR miss cycles 526system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 113756 # number of ReadReq MSHR miss cycles 527system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 217401709 # number of ReadReq MSHR miss cycles 528system.l2c.ReadReq_mshr_miss_latency::cpu0.data 318301323 # number of ReadReq MSHR miss cycles 529system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197508 # number of ReadReq MSHR miss cycles 530system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 225003397 # number of ReadReq MSHR miss cycles 531system.l2c.ReadReq_mshr_miss_latency::cpu1.data 176993433 # number of ReadReq MSHR miss cycles 532system.l2c.ReadReq_mshr_miss_latency::total 938067378 # number of ReadReq MSHR miss cycles 533system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 35910048 # number of UpgradeReq MSHR miss cycles 534system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47375165 # number of UpgradeReq MSHR miss cycles 535system.l2c.UpgradeReq_mshr_miss_latency::total 83285213 # number of UpgradeReq MSHR miss cycles 536system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5731560 # number of SCUpgradeReq MSHR miss cycles 537system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4624957 # number of SCUpgradeReq MSHR miss cycles 538system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356517 # number of SCUpgradeReq MSHR miss cycles 539system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2039757737 # number of ReadExReq MSHR miss cycles 540system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2629528179 # number of ReadExReq MSHR miss cycles 541system.l2c.ReadExReq_mshr_miss_latency::total 4669285916 # number of ReadExReq MSHR miss cycles 542system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56252 # 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number of ReadReq MSHR uncacheable cycles 563system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 994820748 # number of WriteReq MSHR uncacheable cycles 564system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214915040 # number of WriteReq MSHR uncacheable cycles 565system.l2c.WriteReq_mshr_uncacheable_latency::total 9209735788 # number of WriteReq MSHR uncacheable cycles 566system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209640082 # number of overall MSHR uncacheable cycles 567system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12213229606 # number of overall MSHR uncacheable cycles 568system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082174 # number of overall MSHR uncacheable cycles 569system.l2c.overall_mshr_uncacheable_latency::cpu1.data 163780024832 # number of overall MSHR uncacheable cycles 570system.l2c.overall_mshr_uncacheable_latency::total 176205976694 # number of overall MSHR uncacheable cycles 571system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000332 # 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mshr miss rate for demand accesses 577system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for demand accesses 578system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses 579system.l2c.demand_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for demand accesses 580system.l2c.demand_mshr_miss_rate::total 0.106730 # mshr miss rate for demand accesses 581system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for overall accesses 582system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for overall accesses 583system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses 584system.l2c.overall_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for overall accesses 585system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for overall accesses 586system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses 587system.l2c.overall_mshr_miss_rate::cpu1.data 0.280035 # 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average UpgradeReq mshr miss latency 598system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.461902 # average UpgradeReq mshr miss latency 599system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.418465 # average UpgradeReq mshr miss latency 600system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10049.822380 # average SCUpgradeReq mshr miss latency 601system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.648188 # average SCUpgradeReq mshr miss latency 602system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.745155 # average SCUpgradeReq mshr miss latency 603system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.778001 # average ReadExReq mshr miss latency 604system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34767.810300 # average ReadExReq mshr miss latency 605system.l2c.ReadExReq_avg_mshr_miss_latency::total 33505.660228 # average ReadExReq mshr miss latency 606system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency 607system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency 608system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency 609system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency 610system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency 611system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency 612system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency 613system.l2c.demand_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency 614system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency 615system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency 616system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency 617system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency 618system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency 619system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency 620system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency 621system.l2c.overall_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency |
| 637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 638system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 639system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 640system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 641system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 642system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 643system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 644system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 651system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 652system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 653system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 654system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 655system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 656system.cf0.dma_write_txs 0 # Number of DMA write transactions. 657system.cpu0.dtb.inst_hits 0 # ITB inst hits 658system.cpu0.dtb.inst_misses 0 # ITB inst misses | 622system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 623system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 625system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 626system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 627system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 628system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 629system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 636system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 637system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 638system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 639system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 640system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 641system.cf0.dma_write_txs 0 # Number of DMA write transactions. 642system.cpu0.dtb.inst_hits 0 # ITB inst hits 643system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 659system.cpu0.dtb.read_hits 5883553 # DTB read hits 660system.cpu0.dtb.read_misses 2148 # DTB read misses 661system.cpu0.dtb.write_hits 4842455 # DTB write hits 662system.cpu0.dtb.write_misses 405 # DTB write misses | 644system.cpu0.dtb.read_hits 7073604 # DTB read hits 645system.cpu0.dtb.read_misses 3763 # DTB read misses 646system.cpu0.dtb.write_hits 5658971 # DTB write hits 647system.cpu0.dtb.write_misses 806 # DTB write misses |
| 663system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 664system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 665system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 666system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 648system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 649system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 650system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 651system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 667system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB | 652system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB |
| 668system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 653system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 669system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch | 654system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch |
| 670system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 655system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 671system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions 672system.cpu0.dtb.read_accesses 5885701 # DTB read accesses 673system.cpu0.dtb.write_accesses 4842860 # DTB write accesses | 656system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 657system.cpu0.dtb.read_accesses 7077367 # DTB read accesses 658system.cpu0.dtb.write_accesses 5659777 # DTB write accesses |
| 674system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 659system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 675system.cpu0.dtb.hits 10726008 # DTB hits 676system.cpu0.dtb.misses 2553 # DTB misses 677system.cpu0.dtb.accesses 10728561 # DTB accesses 678system.cpu0.itb.inst_hits 24779849 # ITB inst hits 679system.cpu0.itb.inst_misses 1350 # ITB inst misses | 660system.cpu0.dtb.hits 12732575 # DTB hits 661system.cpu0.dtb.misses 4569 # DTB misses 662system.cpu0.dtb.accesses 12737144 # DTB accesses 663system.cpu0.itb.inst_hits 29573368 # ITB inst hits 664system.cpu0.itb.inst_misses 2205 # ITB inst misses |
| 680system.cpu0.itb.read_hits 0 # DTB read hits 681system.cpu0.itb.read_misses 0 # DTB read misses 682system.cpu0.itb.write_hits 0 # DTB write hits 683system.cpu0.itb.write_misses 0 # DTB write misses 684system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 685system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 686system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 687system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 665system.cpu0.itb.read_hits 0 # DTB read hits 666system.cpu0.itb.read_misses 0 # DTB read misses 667system.cpu0.itb.write_hits 0 # DTB write hits 668system.cpu0.itb.write_misses 0 # DTB write misses 669system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 670system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 671system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 672system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 688system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB | 673system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB |
| 689system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 690system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 691system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 692system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 693system.cpu0.itb.read_accesses 0 # DTB read accesses 694system.cpu0.itb.write_accesses 0 # DTB write accesses | 674system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 675system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 676system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 677system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 678system.cpu0.itb.read_accesses 0 # DTB read accesses 679system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 695system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses 696system.cpu0.itb.hits 24779849 # DTB hits 697system.cpu0.itb.misses 1350 # DTB misses 698system.cpu0.itb.accesses 24781199 # DTB accesses 699system.cpu0.numCycles 2364565551 # number of cpu cycles simulated | 680system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses 681system.cpu0.itb.hits 29573368 # DTB hits 682system.cpu0.itb.misses 2205 # DTB misses 683system.cpu0.itb.accesses 29575573 # DTB accesses 684system.cpu0.numCycles 2365916518 # number of cpu cycles simulated |
| 700system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 701system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 685system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 686system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 702system.cpu0.committedInsts 24381823 # Number of instructions committed 703system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed 704system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses 705system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses 706system.cpu0.num_func_calls 1070639 # number of times a function call or return occured 707system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls 708system.cpu0.num_int_insts 28075203 # number of integer instructions 709system.cpu0.num_fp_insts 4364 # number of float instructions 710system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read 711system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written 712system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read 713system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written 714system.cpu0.num_mem_refs 11318426 # number of memory refs 715system.cpu0.num_load_insts 6163151 # Number of load instructions 716system.cpu0.num_store_insts 5155275 # Number of store instructions 717system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles 718system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles 719system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles 720system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles | 687system.cpu0.committedInsts 28875412 # Number of instructions committed 688system.cpu0.committedOps 37222765 # Number of ops (including micro ops) committed 689system.cpu0.num_int_alu_accesses 33109279 # Number of integer alu accesses 690system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 691system.cpu0.num_func_calls 1241807 # number of times a function call or return occured 692system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls 693system.cpu0.num_int_insts 33109279 # number of integer instructions 694system.cpu0.num_fp_insts 3860 # number of float instructions 695system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read 696system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written 697system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 698system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 699system.cpu0.num_mem_refs 13400902 # number of memory refs 700system.cpu0.num_load_insts 7411207 # Number of load instructions 701system.cpu0.num_store_insts 5989695 # Number of store instructions 702system.cpu0.num_idle_cycles 2224988060.360119 # Number of idle cycles 703system.cpu0.num_busy_cycles 140928457.639881 # Number of busy cycles 704system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles 705system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles |
| 721system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 706system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 722system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed 723system.cpu0.icache.replacements 354669 # number of replacements 724system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use 725system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks. 726system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks. 727system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks. | 707system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed 708system.cpu0.icache.replacements 425482 # number of replacements 709system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use 710system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks. 711system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks. 712system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks. |
| 728system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. | 713system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. |
| 729system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor | 714system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor |
| 730system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy 731system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy | 715system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy 716system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy |
| 732system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits 733system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits 734system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits 735system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits 736system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits 737system.cpu0.icache.overall_hits::total 24424650 # number of overall hits 738system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses 739system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses 740system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses 741system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses 742system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses 743system.cpu0.icache.overall_misses::total 355182 # number of overall misses 744system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles 745system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles 746system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles 747system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles 748system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles 749system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles 750system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses) 751system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses) 752system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses 753system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses 754system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses 755system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses 756system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses 757system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses 758system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses 759system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses 760system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses 761system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses 762system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency 763system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency 764system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency 765system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency 766system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency 767system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency | 717system.cpu0.icache.ReadReq_hits::cpu0.inst 29147356 # number of ReadReq hits 718system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits 719system.cpu0.icache.demand_hits::cpu0.inst 29147356 # number of demand (read+write) hits 720system.cpu0.icache.demand_hits::total 29147356 # number of demand (read+write) hits 721system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits 722system.cpu0.icache.overall_hits::total 29147356 # number of overall hits 723system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses 724system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses 725system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses 726system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses 727system.cpu0.icache.overall_misses::cpu0.inst 425995 # number of overall misses 728system.cpu0.icache.overall_misses::total 425995 # number of overall misses 729system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles 730system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles 731system.cpu0.icache.demand_miss_latency::cpu0.inst 5809941500 # number of demand (read+write) miss cycles 732system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles 733system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles 734system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles 735system.cpu0.icache.ReadReq_accesses::cpu0.inst 29573351 # number of ReadReq accesses(hits+misses) 736system.cpu0.icache.ReadReq_accesses::total 29573351 # number of ReadReq accesses(hits+misses) 737system.cpu0.icache.demand_accesses::cpu0.inst 29573351 # number of demand (read+write) accesses 738system.cpu0.icache.demand_accesses::total 29573351 # number of demand (read+write) accesses 739system.cpu0.icache.overall_accesses::cpu0.inst 29573351 # number of overall (read+write) accesses 740system.cpu0.icache.overall_accesses::total 29573351 # number of overall (read+write) accesses 741system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses 742system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses 743system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses 744system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses 745system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses 746system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses 747system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13638.520405 # average ReadReq miss latency 748system.cpu0.icache.ReadReq_avg_miss_latency::total 13638.520405 # average ReadReq miss latency 749system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency 750system.cpu0.icache.demand_avg_miss_latency::total 13638.520405 # average overall miss latency 751system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency 752system.cpu0.icache.overall_avg_miss_latency::total 13638.520405 # average overall miss latency |
| 768system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 771system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 772system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 773system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu0.icache.fast_writes 0 # number of fast writes performed 775system.cpu0.icache.cache_copies 0 # number of cache copies performed | 753system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu0.icache.fast_writes 0 # number of fast writes performed 760system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 776system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses 777system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses 778system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses 779system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses 780system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses 781system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses 782system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles 783system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles 784system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles 785system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles 786system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles 787system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles | 761system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425995 # number of ReadReq MSHR misses 762system.cpu0.icache.ReadReq_mshr_misses::total 425995 # number of ReadReq MSHR misses 763system.cpu0.icache.demand_mshr_misses::cpu0.inst 425995 # number of demand (read+write) MSHR misses 764system.cpu0.icache.demand_mshr_misses::total 425995 # number of demand (read+write) MSHR misses 765system.cpu0.icache.overall_mshr_misses::cpu0.inst 425995 # number of overall MSHR misses 766system.cpu0.icache.overall_mshr_misses::total 425995 # number of overall MSHR misses 767system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4957951500 # number of ReadReq MSHR miss cycles 768system.cpu0.icache.ReadReq_mshr_miss_latency::total 4957951500 # number of ReadReq MSHR miss cycles 769system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4957951500 # number of demand (read+write) MSHR miss cycles 770system.cpu0.icache.demand_mshr_miss_latency::total 4957951500 # number of demand (read+write) MSHR miss cycles 771system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4957951500 # number of overall MSHR miss cycles 772system.cpu0.icache.overall_mshr_miss_latency::total 4957951500 # number of overall MSHR miss cycles |
| 788system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles 789system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles 790system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles 791system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles | 773system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles 774system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles 775system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles 776system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles |
| 792system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses 793system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses 794system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses 795system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses 796system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses 797system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses 798system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency 799system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency 800system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency 801system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency 802system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency 803system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency | 777system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses 778system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses 779system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses 780system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses 781system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses 782system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses 783system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average ReadReq mshr miss latency 784system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11638.520405 # average ReadReq mshr miss latency 785system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency 786system.cpu0.icache.demand_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency 787system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency 788system.cpu0.icache.overall_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency |
| 804system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 805system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 806system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 807system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 789system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 790system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 791system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 792system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 793system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 809system.cpu0.dcache.replacements 279602 # number of replacements 810system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use 811system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks. 812system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks. 813system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks. | 794system.cpu0.dcache.replacements 331027 # number of replacements 795system.cpu0.dcache.tagsinuse 453.640914 # Cycle average of tags in use 796system.cpu0.dcache.total_refs 12276777 # Total number of references to valid blocks. 797system.cpu0.dcache.sampled_refs 331539 # Sample count of references to valid blocks. 798system.cpu0.dcache.avg_refs 37.029662 # Average number of references to valid blocks. |
| 814system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. | 799system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. |
| 815system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor 816system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy 817system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy 818system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits 819system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits 820system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits 821system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits 822system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits 823system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits 824system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits 825system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits 826system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits 827system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits 828system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits 829system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits 830system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses 831system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses 832system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses 833system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses 834system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses 835system.cpu0.dcache.LoadLockedReq_misses::total 8645 # number of LoadLockedReq misses 836system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7703 # number of StoreCondReq misses 837system.cpu0.dcache.StoreCondReq_misses::total 7703 # number of StoreCondReq misses 838system.cpu0.dcache.demand_misses::cpu0.data 318278 # number of demand (read+write) misses 839system.cpu0.dcache.demand_misses::total 318278 # number of demand (read+write) misses 840system.cpu0.dcache.overall_misses::cpu0.data 318278 # number of overall misses 841system.cpu0.dcache.overall_misses::total 318278 # number of overall misses 842system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles 843system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles 844system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles 845system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles 846system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles 847system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles 848system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles 849system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles 850system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles 851system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles 852system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles 853system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles 854system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses) 855system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses) 856system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses) 857system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses) 858system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses) 859system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses) 860system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses) 861system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses) 862system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses 863system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses 864system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses 865system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses 866system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses 867system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses 868system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses 869system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses 870system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses 871system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses 872system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses 873system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses 874system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses 875system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses 876system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses 877system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses 878system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency 879system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency 880system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency 881system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency 882system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency 883system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency 884system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency 885system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency 886system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency 887system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency 888system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency 889system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency | 800system.cpu0.dcache.occ_blocks::cpu0.data 453.640914 # Average occupied blocks per requestor 801system.cpu0.dcache.occ_percent::cpu0.data 0.886017 # Average percentage of cache occupancy 802system.cpu0.dcache.occ_percent::total 0.886017 # Average percentage of cache occupancy 803system.cpu0.dcache.ReadReq_hits::cpu0.data 6603200 # number of ReadReq hits 804system.cpu0.dcache.ReadReq_hits::total 6603200 # number of ReadReq hits 805system.cpu0.dcache.WriteReq_hits::cpu0.data 5353855 # number of WriteReq hits 806system.cpu0.dcache.WriteReq_hits::total 5353855 # number of WriteReq hits 807system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147936 # number of LoadLockedReq hits 808system.cpu0.dcache.LoadLockedReq_hits::total 147936 # number of LoadLockedReq hits 809system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149699 # number of StoreCondReq hits 810system.cpu0.dcache.StoreCondReq_hits::total 149699 # number of StoreCondReq hits 811system.cpu0.dcache.demand_hits::cpu0.data 11957055 # number of demand (read+write) hits 812system.cpu0.dcache.demand_hits::total 11957055 # number of demand (read+write) hits 813system.cpu0.dcache.overall_hits::cpu0.data 11957055 # number of overall hits 814system.cpu0.dcache.overall_hits::total 11957055 # number of overall hits 815system.cpu0.dcache.ReadReq_misses::cpu0.data 228068 # number of ReadReq misses 816system.cpu0.dcache.ReadReq_misses::total 228068 # number of ReadReq misses 817system.cpu0.dcache.WriteReq_misses::cpu0.data 141674 # number of WriteReq misses 818system.cpu0.dcache.WriteReq_misses::total 141674 # number of WriteReq misses 819system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9338 # number of LoadLockedReq misses 820system.cpu0.dcache.LoadLockedReq_misses::total 9338 # number of LoadLockedReq misses 821system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7490 # number of StoreCondReq misses 822system.cpu0.dcache.StoreCondReq_misses::total 7490 # number of StoreCondReq misses 823system.cpu0.dcache.demand_misses::cpu0.data 369742 # number of demand (read+write) misses 824system.cpu0.dcache.demand_misses::total 369742 # number of demand (read+write) misses 825system.cpu0.dcache.overall_misses::cpu0.data 369742 # number of overall misses 826system.cpu0.dcache.overall_misses::total 369742 # number of overall misses 827system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3146768000 # number of ReadReq miss cycles 828system.cpu0.dcache.ReadReq_miss_latency::total 3146768000 # number of ReadReq miss cycles 829system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4132891500 # number of WriteReq miss cycles 830system.cpu0.dcache.WriteReq_miss_latency::total 4132891500 # number of WriteReq miss cycles 831system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88585500 # number of LoadLockedReq miss cycles 832system.cpu0.dcache.LoadLockedReq_miss_latency::total 88585500 # number of LoadLockedReq miss cycles 833system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44513500 # number of StoreCondReq miss cycles 834system.cpu0.dcache.StoreCondReq_miss_latency::total 44513500 # number of StoreCondReq miss cycles 835system.cpu0.dcache.demand_miss_latency::cpu0.data 7279659500 # number of demand (read+write) miss cycles 836system.cpu0.dcache.demand_miss_latency::total 7279659500 # number of demand (read+write) miss cycles 837system.cpu0.dcache.overall_miss_latency::cpu0.data 7279659500 # number of overall miss cycles 838system.cpu0.dcache.overall_miss_latency::total 7279659500 # number of overall miss cycles 839system.cpu0.dcache.ReadReq_accesses::cpu0.data 6831268 # number of ReadReq accesses(hits+misses) 840system.cpu0.dcache.ReadReq_accesses::total 6831268 # number of ReadReq accesses(hits+misses) 841system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495529 # number of WriteReq accesses(hits+misses) 842system.cpu0.dcache.WriteReq_accesses::total 5495529 # number of WriteReq accesses(hits+misses) 843system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157274 # number of LoadLockedReq accesses(hits+misses) 844system.cpu0.dcache.LoadLockedReq_accesses::total 157274 # number of LoadLockedReq accesses(hits+misses) 845system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157189 # number of StoreCondReq accesses(hits+misses) 846system.cpu0.dcache.StoreCondReq_accesses::total 157189 # number of StoreCondReq accesses(hits+misses) 847system.cpu0.dcache.demand_accesses::cpu0.data 12326797 # number of demand (read+write) accesses 848system.cpu0.dcache.demand_accesses::total 12326797 # number of demand (read+write) accesses 849system.cpu0.dcache.overall_accesses::cpu0.data 12326797 # number of overall (read+write) accesses 850system.cpu0.dcache.overall_accesses::total 12326797 # number of overall (read+write) accesses 851system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033386 # miss rate for ReadReq accesses 852system.cpu0.dcache.ReadReq_miss_rate::total 0.033386 # miss rate for ReadReq accesses 853system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025780 # miss rate for WriteReq accesses 854system.cpu0.dcache.WriteReq_miss_rate::total 0.025780 # miss rate for WriteReq accesses 855system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059374 # miss rate for LoadLockedReq accesses 856system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059374 # miss rate for LoadLockedReq accesses 857system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses 858system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses 859system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029995 # miss rate for demand accesses 860system.cpu0.dcache.demand_miss_rate::total 0.029995 # miss rate for demand accesses 861system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029995 # miss rate for overall accesses 862system.cpu0.dcache.overall_miss_rate::total 0.029995 # miss rate for overall accesses 863system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.498992 # average ReadReq miss latency 864system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.498992 # average ReadReq miss latency 865system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29171.841693 # average WriteReq miss latency 866system.cpu0.dcache.WriteReq_avg_miss_latency::total 29171.841693 # average WriteReq miss latency 867system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9486.560291 # average LoadLockedReq miss latency 868system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9486.560291 # average LoadLockedReq miss latency 869system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5943.057410 # average StoreCondReq miss latency 870system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5943.057410 # average StoreCondReq miss latency 871system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency 872system.cpu0.dcache.demand_avg_miss_latency::total 19688.484132 # average overall miss latency 873system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency 874system.cpu0.dcache.overall_avg_miss_latency::total 19688.484132 # average overall miss latency |
| 890system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 891system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 892system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 894system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 895system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 896system.cpu0.dcache.fast_writes 0 # number of fast writes performed 897system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 875system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 876system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 877system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 878system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 879system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 880system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 881system.cpu0.dcache.fast_writes 0 # number of fast writes performed 882system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 898system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks 899system.cpu0.dcache.writebacks::total 257540 # number of writebacks 900system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses 901system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses 902system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses 903system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses 904system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses 905system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses 906system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses 907system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses 908system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses 909system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses 910system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses 911system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses 912system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles 913system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles 914system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles 915system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles 916system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles 917system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles 918system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles 919system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles | 883system.cpu0.dcache.writebacks::writebacks 306714 # number of writebacks 884system.cpu0.dcache.writebacks::total 306714 # number of writebacks 885system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses 886system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses 887system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses 888system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses 889system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses 890system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses 891system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses 892system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses 893system.cpu0.dcache.demand_mshr_misses::cpu0.data 369742 # number of demand (read+write) MSHR misses 894system.cpu0.dcache.demand_mshr_misses::total 369742 # number of demand (read+write) MSHR misses 895system.cpu0.dcache.overall_mshr_misses::cpu0.data 369742 # number of overall MSHR misses 896system.cpu0.dcache.overall_mshr_misses::total 369742 # number of overall MSHR misses 897system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2690632000 # number of ReadReq MSHR miss cycles 898system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2690632000 # number of ReadReq MSHR miss cycles 899system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3849543500 # number of WriteReq MSHR miss cycles 900system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3849543500 # number of WriteReq MSHR miss cycles 901system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69909500 # number of LoadLockedReq MSHR miss cycles 902system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69909500 # number of LoadLockedReq MSHR miss cycles 903system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29541500 # number of StoreCondReq MSHR miss cycles 904system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29541500 # number of StoreCondReq MSHR miss cycles |
| 920system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 921system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles | 905system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 906system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles |
| 922system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles 923system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles 924system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles 925system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles 926system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles 927system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles 928system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles 929system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles 930system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles 931system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles 932system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses 933system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses 934system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses 935system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses 936system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses 937system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses 938system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses 939system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses 940system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses 941system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses 942system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses 943system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses 944system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency 945system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency 946system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency 947system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency 948system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency 949system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency 950system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency 951system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency | 907system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles 908system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles 909system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles 910system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles 911system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles 912system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles 913system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles 914system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles 915system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles 916system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles 917system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses 918system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses 919system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses 920system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses 921system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses 922system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses 923system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses 924system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses 925system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses 926system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses 927system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses 928system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses 929system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency 930system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency 931system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency 932system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency 933system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency 934system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency 935system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency 936system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency |
| 952system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 953system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 937system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 938system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 954system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency 955system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency 956system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency 957system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency | 939system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency 940system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency 941system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency 942system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency |
| 958system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 959system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 960system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 961system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 962system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 963system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 964system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 965system.cpu1.dtb.inst_hits 0 # ITB inst hits 966system.cpu1.dtb.inst_misses 0 # ITB inst misses | 943system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 944system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 945system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 946system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 947system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 948system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 949system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 950system.cpu1.dtb.inst_hits 0 # ITB inst hits 951system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 967system.cpu1.dtb.read_hits 9504194 # DTB read hits 968system.cpu1.dtb.read_misses 5263 # DTB read misses 969system.cpu1.dtb.write_hits 6646220 # DTB write hits 970system.cpu1.dtb.write_misses 1833 # DTB write misses | 952system.cpu1.dtb.read_hits 8309714 # DTB read hits 953system.cpu1.dtb.read_misses 3643 # DTB read misses 954system.cpu1.dtb.write_hits 5826503 # DTB write hits 955system.cpu1.dtb.write_misses 1435 # DTB write misses |
| 971system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 972system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 973system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 974system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 956system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 957system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 958system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 959system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 975system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB | 960system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB |
| 976system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 961system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 977system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch | 962system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch |
| 978system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 963system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 979system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions 980system.cpu1.dtb.read_accesses 9509457 # DTB read accesses 981system.cpu1.dtb.write_accesses 6648053 # DTB write accesses | 964system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 965system.cpu1.dtb.read_accesses 8313357 # DTB read accesses 966system.cpu1.dtb.write_accesses 5827938 # DTB write accesses |
| 982system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 967system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 983system.cpu1.dtb.hits 16150414 # DTB hits 984system.cpu1.dtb.misses 7096 # DTB misses 985system.cpu1.dtb.accesses 16157510 # DTB accesses 986system.cpu1.itb.inst_hits 37994467 # ITB inst hits 987system.cpu1.itb.inst_misses 3017 # ITB inst misses | 968system.cpu1.dtb.hits 14136217 # DTB hits 969system.cpu1.dtb.misses 5078 # DTB misses 970system.cpu1.dtb.accesses 14141295 # DTB accesses 971system.cpu1.itb.inst_hits 33189716 # ITB inst hits 972system.cpu1.itb.inst_misses 2171 # ITB inst misses |
| 988system.cpu1.itb.read_hits 0 # DTB read hits 989system.cpu1.itb.read_misses 0 # DTB read misses 990system.cpu1.itb.write_hits 0 # DTB write hits 991system.cpu1.itb.write_misses 0 # DTB write misses 992system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 993system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 994system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 995system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 973system.cpu1.itb.read_hits 0 # DTB read hits 974system.cpu1.itb.read_misses 0 # DTB read misses 975system.cpu1.itb.write_hits 0 # DTB write hits 976system.cpu1.itb.write_misses 0 # DTB write misses 977system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 978system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 979system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 980system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 996system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB | 981system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB |
| 997system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 998system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 999system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1000system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1001system.cpu1.itb.read_accesses 0 # DTB read accesses 1002system.cpu1.itb.write_accesses 0 # DTB write accesses | 982system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 983system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 984system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 985system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 986system.cpu1.itb.read_accesses 0 # DTB read accesses 987system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1003system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses 1004system.cpu1.itb.hits 37994467 # DTB hits 1005system.cpu1.itb.misses 3017 # DTB misses 1006system.cpu1.itb.accesses 37997484 # DTB accesses 1007system.cpu1.numCycles 2366006228 # number of cpu cycles simulated | 988system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses 989system.cpu1.itb.hits 33189716 # DTB hits 990system.cpu1.itb.misses 2171 # DTB misses 991system.cpu1.itb.accesses 33191887 # DTB accesses 992system.cpu1.numCycles 2364475282 # number of cpu cycles simulated |
| 1008system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1009system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 993system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 994system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1010system.cpu1.committedInsts 37084001 # Number of instructions committed 1011system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed 1012system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses 1013system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses 1014system.cpu1.num_func_calls 1133542 # number of times a function call or return occured 1015system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls 1016system.cpu1.num_int_insts 42360540 # number of integer instructions 1017system.cpu1.num_fp_insts 5457 # number of float instructions 1018system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read 1019system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written 1020system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read 1021system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written 1022system.cpu1.num_mem_refs 16764021 # number of memory refs 1023system.cpu1.num_load_insts 9884261 # Number of load instructions 1024system.cpu1.num_store_insts 6879760 # Number of store instructions 1025system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles 1026system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles 1027system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles 1028system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles | 995system.cpu1.committedInsts 32579235 # Number of instructions committed 996system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed 997system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses 998system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 999system.cpu1.num_func_calls 962009 # number of times a function call or return occured 1000system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls 1001system.cpu1.num_int_insts 37310899 # number of integer instructions 1002system.cpu1.num_fp_insts 6793 # number of float instructions 1003system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read 1004system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written 1005system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1006system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1007system.cpu1.num_mem_refs 14673985 # number of memory refs 1008system.cpu1.num_load_insts 8631614 # Number of load instructions 1009system.cpu1.num_store_insts 6042371 # Number of store instructions 1010system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles 1011system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles 1012system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles 1013system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles |
| 1029system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1014system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1030system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed 1031system.cpu1.icache.replacements 540342 # number of replacements 1032system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use 1033system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks. 1034system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks. 1035system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks. | 1015system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed 1016system.cpu1.icache.replacements 469209 # number of replacements 1017system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use 1018system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks. 1019system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks. 1020system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks. |
| 1036system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. | 1021system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. |
| 1037system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor 1038system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy 1039system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy 1040system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits 1041system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits 1042system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits 1043system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits 1044system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits 1045system.cpu1.icache.overall_hits::total 37453609 # number of overall hits 1046system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses 1047system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses 1048system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses 1049system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses 1050system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses 1051system.cpu1.icache.overall_misses::total 540854 # number of overall misses 1052system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles 1053system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles 1054system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles 1055system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles 1056system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles 1057system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles 1058system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses) 1059system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses) 1060system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses 1061system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses 1062system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses 1063system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses 1064system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses 1065system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses 1066system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses 1067system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses 1068system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses 1069system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses 1070system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency 1071system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency 1072system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency 1073system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency 1074system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency 1075system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency | 1022system.cpu1.icache.occ_blocks::cpu1.inst 478.755545 # Average occupied blocks per requestor 1023system.cpu1.icache.occ_percent::cpu1.inst 0.935069 # Average percentage of cache occupancy 1024system.cpu1.icache.occ_percent::total 0.935069 # Average percentage of cache occupancy 1025system.cpu1.icache.ReadReq_hits::cpu1.inst 32719991 # number of ReadReq hits 1026system.cpu1.icache.ReadReq_hits::total 32719991 # number of ReadReq hits 1027system.cpu1.icache.demand_hits::cpu1.inst 32719991 # number of demand (read+write) hits 1028system.cpu1.icache.demand_hits::total 32719991 # number of demand (read+write) hits 1029system.cpu1.icache.overall_hits::cpu1.inst 32719991 # number of overall hits 1030system.cpu1.icache.overall_hits::total 32719991 # number of overall hits 1031system.cpu1.icache.ReadReq_misses::cpu1.inst 469721 # number of ReadReq misses 1032system.cpu1.icache.ReadReq_misses::total 469721 # number of ReadReq misses 1033system.cpu1.icache.demand_misses::cpu1.inst 469721 # number of demand (read+write) misses 1034system.cpu1.icache.demand_misses::total 469721 # number of demand (read+write) misses 1035system.cpu1.icache.overall_misses::cpu1.inst 469721 # number of overall misses 1036system.cpu1.icache.overall_misses::total 469721 # number of overall misses 1037system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6363755000 # number of ReadReq miss cycles 1038system.cpu1.icache.ReadReq_miss_latency::total 6363755000 # number of ReadReq miss cycles 1039system.cpu1.icache.demand_miss_latency::cpu1.inst 6363755000 # number of demand (read+write) miss cycles 1040system.cpu1.icache.demand_miss_latency::total 6363755000 # number of demand (read+write) miss cycles 1041system.cpu1.icache.overall_miss_latency::cpu1.inst 6363755000 # number of overall miss cycles 1042system.cpu1.icache.overall_miss_latency::total 6363755000 # number of overall miss cycles 1043system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189712 # number of ReadReq accesses(hits+misses) 1044system.cpu1.icache.ReadReq_accesses::total 33189712 # number of ReadReq accesses(hits+misses) 1045system.cpu1.icache.demand_accesses::cpu1.inst 33189712 # number of demand (read+write) accesses 1046system.cpu1.icache.demand_accesses::total 33189712 # number of demand (read+write) accesses 1047system.cpu1.icache.overall_accesses::cpu1.inst 33189712 # number of overall (read+write) accesses 1048system.cpu1.icache.overall_accesses::total 33189712 # number of overall (read+write) accesses 1049system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses 1050system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses 1051system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses 1052system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses 1053system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses 1054system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses 1055system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.946547 # average ReadReq miss latency 1056system.cpu1.icache.ReadReq_avg_miss_latency::total 13547.946547 # average ReadReq miss latency 1057system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency 1058system.cpu1.icache.demand_avg_miss_latency::total 13547.946547 # average overall miss latency 1059system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency 1060system.cpu1.icache.overall_avg_miss_latency::total 13547.946547 # average overall miss latency |
| 1076system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1077system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1078system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1079system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1080system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1081system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1082system.cpu1.icache.fast_writes 0 # number of fast writes performed 1083system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1061system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1067system.cpu1.icache.fast_writes 0 # number of fast writes performed 1068system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1084system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses 1085system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses 1086system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses 1087system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses 1088system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses 1089system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses 1090system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles 1091system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles 1092system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles 1093system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles 1094system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles 1095system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles | 1069system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469721 # number of ReadReq MSHR misses 1070system.cpu1.icache.ReadReq_mshr_misses::total 469721 # number of ReadReq MSHR misses 1071system.cpu1.icache.demand_mshr_misses::cpu1.inst 469721 # number of demand (read+write) MSHR misses 1072system.cpu1.icache.demand_mshr_misses::total 469721 # number of demand (read+write) MSHR misses 1073system.cpu1.icache.overall_mshr_misses::cpu1.inst 469721 # number of overall MSHR misses 1074system.cpu1.icache.overall_mshr_misses::total 469721 # number of overall MSHR misses 1075system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5424313000 # number of ReadReq MSHR miss cycles 1076system.cpu1.icache.ReadReq_mshr_miss_latency::total 5424313000 # number of ReadReq MSHR miss cycles 1077system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5424313000 # number of demand (read+write) MSHR miss cycles 1078system.cpu1.icache.demand_mshr_miss_latency::total 5424313000 # number of demand (read+write) MSHR miss cycles 1079system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5424313000 # number of overall MSHR miss cycles 1080system.cpu1.icache.overall_mshr_miss_latency::total 5424313000 # number of overall MSHR miss cycles |
| 1096system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles 1097system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles 1098system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles 1099system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles | 1081system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles 1082system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles 1083system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles 1084system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles |
| 1100system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for ReadReq accesses 1101system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014235 # mshr miss rate for ReadReq accesses 1102system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for demand accesses 1103system.cpu1.icache.demand_mshr_miss_rate::total 0.014235 # mshr miss rate for demand accesses 1104system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for overall accesses 1105system.cpu1.icache.overall_mshr_miss_rate::total 0.014235 # mshr miss rate for overall accesses 1106system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average ReadReq mshr miss latency 1107system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11500.045299 # average ReadReq mshr miss latency 1108system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency 1109system.cpu1.icache.demand_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency 1110system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency 1111system.cpu1.icache.overall_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency | 1085system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses 1086system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses 1087system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses 1088system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses 1089system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses 1090system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses 1091system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average ReadReq mshr miss latency 1092system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11547.946547 # average ReadReq mshr miss latency 1093system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency 1094system.cpu1.icache.demand_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency 1095system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency 1096system.cpu1.icache.overall_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency |
| 1112system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1113system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1114system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1115system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1116system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1097system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1098system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1099system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1100system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1101system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1117system.cpu1.dcache.replacements 343957 # number of replacements 1118system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use 1119system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks. 1120system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks. 1121system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks. | 1102system.cpu1.dcache.replacements 292184 # number of replacements 1103system.cpu1.dcache.tagsinuse 472.133429 # Cycle average of tags in use 1104system.cpu1.dcache.total_refs 11959580 # Total number of references to valid blocks. 1105system.cpu1.dcache.sampled_refs 292554 # Sample count of references to valid blocks. 1106system.cpu1.dcache.avg_refs 40.879906 # Average number of references to valid blocks. |
| 1122system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit. | 1107system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit. |
| 1123system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor 1124system.cpu1.dcache.occ_percent::cpu1.data 0.924000 # Average percentage of cache occupancy 1125system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy 1126system.cpu1.dcache.ReadReq_hits::cpu1.data 8074934 # number of ReadReq hits 1127system.cpu1.dcache.ReadReq_hits::total 8074934 # number of ReadReq hits 1128system.cpu1.dcache.WriteReq_hits::cpu1.data 5611325 # number of WriteReq hits 1129system.cpu1.dcache.WriteReq_hits::total 5611325 # number of WriteReq hits 1130system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100335 # number of LoadLockedReq hits 1131system.cpu1.dcache.LoadLockedReq_hits::total 100335 # number of LoadLockedReq hits 1132system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102214 # number of StoreCondReq hits 1133system.cpu1.dcache.StoreCondReq_hits::total 102214 # number of StoreCondReq hits 1134system.cpu1.dcache.demand_hits::cpu1.data 13686259 # number of demand (read+write) hits 1135system.cpu1.dcache.demand_hits::total 13686259 # number of demand (read+write) hits 1136system.cpu1.dcache.overall_hits::cpu1.data 13686259 # number of overall hits 1137system.cpu1.dcache.overall_hits::total 13686259 # number of overall hits 1138system.cpu1.dcache.ReadReq_misses::cpu1.data 207178 # number of ReadReq misses 1139system.cpu1.dcache.ReadReq_misses::total 207178 # number of ReadReq misses 1140system.cpu1.dcache.WriteReq_misses::cpu1.data 165249 # number of WriteReq misses 1141system.cpu1.dcache.WriteReq_misses::total 165249 # number of WriteReq misses 1142system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11790 # number of LoadLockedReq misses 1143system.cpu1.dcache.LoadLockedReq_misses::total 11790 # number of LoadLockedReq misses 1144system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9834 # number of StoreCondReq misses 1145system.cpu1.dcache.StoreCondReq_misses::total 9834 # number of StoreCondReq misses 1146system.cpu1.dcache.demand_misses::cpu1.data 372427 # number of demand (read+write) misses 1147system.cpu1.dcache.demand_misses::total 372427 # number of demand (read+write) misses 1148system.cpu1.dcache.overall_misses::cpu1.data 372427 # number of overall misses 1149system.cpu1.dcache.overall_misses::total 372427 # number of overall misses 1150system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2639135500 # number of ReadReq miss cycles 1151system.cpu1.dcache.ReadReq_miss_latency::total 2639135500 # number of ReadReq miss cycles 1152system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4834942000 # number of WriteReq miss cycles 1153system.cpu1.dcache.WriteReq_miss_latency::total 4834942000 # number of WriteReq miss cycles 1154system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103120000 # number of LoadLockedReq miss cycles 1155system.cpu1.dcache.LoadLockedReq_miss_latency::total 103120000 # number of LoadLockedReq miss cycles 1156system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50505000 # number of StoreCondReq miss cycles 1157system.cpu1.dcache.StoreCondReq_miss_latency::total 50505000 # number of StoreCondReq miss cycles 1158system.cpu1.dcache.demand_miss_latency::cpu1.data 7474077500 # number of demand (read+write) miss cycles 1159system.cpu1.dcache.demand_miss_latency::total 7474077500 # number of demand (read+write) miss cycles 1160system.cpu1.dcache.overall_miss_latency::cpu1.data 7474077500 # number of overall miss cycles 1161system.cpu1.dcache.overall_miss_latency::total 7474077500 # number of overall miss cycles 1162system.cpu1.dcache.ReadReq_accesses::cpu1.data 8282112 # number of ReadReq accesses(hits+misses) 1163system.cpu1.dcache.ReadReq_accesses::total 8282112 # number of ReadReq accesses(hits+misses) 1164system.cpu1.dcache.WriteReq_accesses::cpu1.data 5776574 # number of WriteReq accesses(hits+misses) 1165system.cpu1.dcache.WriteReq_accesses::total 5776574 # number of WriteReq accesses(hits+misses) 1166system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112125 # number of LoadLockedReq accesses(hits+misses) 1167system.cpu1.dcache.LoadLockedReq_accesses::total 112125 # number of LoadLockedReq accesses(hits+misses) 1168system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112048 # number of StoreCondReq accesses(hits+misses) 1169system.cpu1.dcache.StoreCondReq_accesses::total 112048 # number of StoreCondReq accesses(hits+misses) 1170system.cpu1.dcache.demand_accesses::cpu1.data 14058686 # number of demand (read+write) accesses 1171system.cpu1.dcache.demand_accesses::total 14058686 # number of demand (read+write) accesses 1172system.cpu1.dcache.overall_accesses::cpu1.data 14058686 # number of overall (read+write) accesses 1173system.cpu1.dcache.overall_accesses::total 14058686 # number of overall (read+write) accesses 1174system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.025015 # miss rate for ReadReq accesses 1175system.cpu1.dcache.ReadReq_miss_rate::total 0.025015 # miss rate for ReadReq accesses 1176system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses 1177system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses 1178system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses 1179system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses 1180system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses 1181system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses 1182system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses 1183system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses 1184system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses 1185system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses 1186system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency 1187system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency 1188system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # average WriteReq miss latency 1189system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency 1190system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency 1191system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency 1192system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency 1193system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency 1194system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency 1195system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency 1196system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency 1197system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency | 1108system.cpu1.dcache.occ_blocks::cpu1.data 472.133429 # Average occupied blocks per requestor 1109system.cpu1.dcache.occ_percent::cpu1.data 0.922136 # Average percentage of cache occupancy 1110system.cpu1.dcache.occ_percent::total 0.922136 # Average percentage of cache occupancy 1111system.cpu1.dcache.ReadReq_hits::cpu1.data 6945060 # number of ReadReq hits 1112system.cpu1.dcache.ReadReq_hits::total 6945060 # number of ReadReq hits 1113system.cpu1.dcache.WriteReq_hits::cpu1.data 4826351 # number of WriteReq hits 1114system.cpu1.dcache.WriteReq_hits::total 4826351 # number of WriteReq hits 1115system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81758 # number of LoadLockedReq hits 1116system.cpu1.dcache.LoadLockedReq_hits::total 81758 # number of LoadLockedReq hits 1117system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82709 # number of StoreCondReq hits 1118system.cpu1.dcache.StoreCondReq_hits::total 82709 # number of StoreCondReq hits 1119system.cpu1.dcache.demand_hits::cpu1.data 11771411 # number of demand (read+write) hits 1120system.cpu1.dcache.demand_hits::total 11771411 # number of demand (read+write) hits 1121system.cpu1.dcache.overall_hits::cpu1.data 11771411 # number of overall hits 1122system.cpu1.dcache.overall_hits::total 11771411 # number of overall hits 1123system.cpu1.dcache.ReadReq_misses::cpu1.data 170725 # number of ReadReq misses 1124system.cpu1.dcache.ReadReq_misses::total 170725 # number of ReadReq misses 1125system.cpu1.dcache.WriteReq_misses::cpu1.data 149867 # number of WriteReq misses 1126system.cpu1.dcache.WriteReq_misses::total 149867 # number of WriteReq misses 1127system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11052 # number of LoadLockedReq misses 1128system.cpu1.dcache.LoadLockedReq_misses::total 11052 # number of LoadLockedReq misses 1129system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10028 # number of StoreCondReq misses 1130system.cpu1.dcache.StoreCondReq_misses::total 10028 # number of StoreCondReq misses 1131system.cpu1.dcache.demand_misses::cpu1.data 320592 # number of demand (read+write) misses 1132system.cpu1.dcache.demand_misses::total 320592 # number of demand (read+write) misses 1133system.cpu1.dcache.overall_misses::cpu1.data 320592 # number of overall misses 1134system.cpu1.dcache.overall_misses::total 320592 # number of overall misses 1135system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2168241500 # number of ReadReq miss cycles 1136system.cpu1.dcache.ReadReq_miss_latency::total 2168241500 # number of ReadReq miss cycles 1137system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4524943000 # number of WriteReq miss cycles 1138system.cpu1.dcache.WriteReq_miss_latency::total 4524943000 # number of WriteReq miss cycles 1139system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92270500 # number of LoadLockedReq miss cycles 1140system.cpu1.dcache.LoadLockedReq_miss_latency::total 92270500 # number of LoadLockedReq miss cycles 1141system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51657000 # number of StoreCondReq miss cycles 1142system.cpu1.dcache.StoreCondReq_miss_latency::total 51657000 # number of StoreCondReq miss cycles 1143system.cpu1.dcache.demand_miss_latency::cpu1.data 6693184500 # number of demand (read+write) miss cycles 1144system.cpu1.dcache.demand_miss_latency::total 6693184500 # number of demand (read+write) miss cycles 1145system.cpu1.dcache.overall_miss_latency::cpu1.data 6693184500 # number of overall miss cycles 1146system.cpu1.dcache.overall_miss_latency::total 6693184500 # number of overall miss cycles 1147system.cpu1.dcache.ReadReq_accesses::cpu1.data 7115785 # number of ReadReq accesses(hits+misses) 1148system.cpu1.dcache.ReadReq_accesses::total 7115785 # number of ReadReq accesses(hits+misses) 1149system.cpu1.dcache.WriteReq_accesses::cpu1.data 4976218 # number of WriteReq accesses(hits+misses) 1150system.cpu1.dcache.WriteReq_accesses::total 4976218 # number of WriteReq accesses(hits+misses) 1151system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92810 # number of LoadLockedReq accesses(hits+misses) 1152system.cpu1.dcache.LoadLockedReq_accesses::total 92810 # number of LoadLockedReq accesses(hits+misses) 1153system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92737 # number of StoreCondReq accesses(hits+misses) 1154system.cpu1.dcache.StoreCondReq_accesses::total 92737 # number of StoreCondReq accesses(hits+misses) 1155system.cpu1.dcache.demand_accesses::cpu1.data 12092003 # number of demand (read+write) accesses 1156system.cpu1.dcache.demand_accesses::total 12092003 # number of demand (read+write) accesses 1157system.cpu1.dcache.overall_accesses::cpu1.data 12092003 # number of overall (read+write) accesses 1158system.cpu1.dcache.overall_accesses::total 12092003 # number of overall (read+write) accesses 1159system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023992 # miss rate for ReadReq accesses 1160system.cpu1.dcache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses 1161system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030117 # miss rate for WriteReq accesses 1162system.cpu1.dcache.WriteReq_miss_rate::total 0.030117 # miss rate for WriteReq accesses 1163system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119082 # miss rate for LoadLockedReq accesses 1164system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119082 # miss rate for LoadLockedReq accesses 1165system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108134 # miss rate for StoreCondReq accesses 1166system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108134 # miss rate for StoreCondReq accesses 1167system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses 1168system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses 1169system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses 1170system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses 1171system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12700.199151 # average ReadReq miss latency 1172system.cpu1.dcache.ReadReq_avg_miss_latency::total 12700.199151 # average ReadReq miss latency 1173system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30193.057845 # average WriteReq miss latency 1174system.cpu1.dcache.WriteReq_avg_miss_latency::total 30193.057845 # average WriteReq miss latency 1175system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8348.760405 # average LoadLockedReq miss latency 1176system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8348.760405 # average LoadLockedReq miss latency 1177system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5151.276426 # average StoreCondReq miss latency 1178system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5151.276426 # average StoreCondReq miss latency 1179system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency 1180system.cpu1.dcache.demand_avg_miss_latency::total 20877.578043 # average overall miss latency 1181system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency 1182system.cpu1.dcache.overall_avg_miss_latency::total 20877.578043 # average overall miss latency |
| 1198system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1199system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1200system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1201system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1202system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1203system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1204system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1205system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1183system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1190system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1206system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks 1207system.cpu1.dcache.writebacks::total 315665 # number of writebacks 1208system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses 1209system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses 1210system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses 1211system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses 1212system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses 1213system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses 1214system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses 1215system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses 1216system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses 1217system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses 1218system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses 1219system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses 1220system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles 1221system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles 1222system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles 1223system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles 1224system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles 1225system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles 1226system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles 1227system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles | 1191system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks 1192system.cpu1.dcache.writebacks::total 265550 # number of writebacks 1193system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses 1194system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses 1195system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses 1196system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses 1197system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses 1198system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses 1199system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses 1200system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses 1201system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses 1202system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses 1203system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses 1204system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses 1205system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles 1206system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles 1207system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles 1208system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles 1209system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles 1210system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles 1211system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles 1212system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles |
| 1228system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1229system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles | 1213system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1214system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles |
| 1230system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles 1231system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles 1232system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles 1233system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles 1234system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles 1235system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles 1236system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles 1237system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles 1238system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles 1239system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles 1240system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses 1241system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses 1242system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses 1243system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses 1244system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses 1245system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses 1246system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses 1247system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses 1248system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses 1249system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses 1250system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses 1251system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses 1252system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency 1253system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency 1254system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency 1255system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency 1256system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency 1257system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency 1258system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency 1259system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency | 1215system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles 1216system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles 1217system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles 1218system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles 1219system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles 1220system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles 1221system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles 1222system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles 1223system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles 1224system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles 1225system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses 1226system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses 1227system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses 1228system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses 1229system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses 1230system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses 1231system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses 1232system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses 1233system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses 1234system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses 1235system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses 1236system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses 1237system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency 1238system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency 1239system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency 1240system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency 1241system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency 1242system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency 1243system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency 1244system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency |
| 1260system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1261system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1245system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1246system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1262system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency 1263system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency 1264system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency 1265system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency | 1247system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency 1248system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency 1249system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency 1250system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency |
| 1266system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1267system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1268system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1269system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1270system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1271system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1272system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1273system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1279system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1280system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1281system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1282system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1283system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1284system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1285system.iocache.fast_writes 0 # number of fast writes performed 1286system.iocache.cache_copies 0 # number of cache copies performed | 1251system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1252system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1253system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1254system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1255system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1256system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1257system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1258system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1264system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1265system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1266system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1267system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1268system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1269system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1270system.iocache.fast_writes 0 # number of fast writes performed 1271system.iocache.cache_copies 0 # number of cache copies performed |
| 1287system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles 1288system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles 1289system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles 1290system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles | 1272system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles 1273system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles 1274system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles 1275system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles |
| 1291system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1292system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1293system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1294system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1295system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1296 1297---------- End Simulation Statistics ---------- | 1276system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1277system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1278system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1279system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1280system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1281 1282---------- End Simulation Statistics ---------- |