| stats.txt (9308:f634a34f2f0b) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.203606 # Number of seconds simulated 4sim_ticks 1203606499000 # Number of ticks simulated 5final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.182883 # Number of seconds simulated 4sim_ticks 1182883077500 # Number of ticks simulated 5final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 418240 # Simulator instruction rate (inst/s) 8host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8191230777 # Simulator tick rate (ticks/s) 10host_mem_usage 386340 # Number of bytes of host memory used 11host_seconds 146.94 # Real time elapsed on the host 12sim_insts 61455549 # Number of instructions simulated 13sim_ops 78317886 # Number of ops (including micro ops) simulated | 7host_inst_rate 330156 # Simulator instruction rate (inst/s) 8host_op_rate 420694 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6355289452 # Simulator tick rate (ticks/s) 10host_mem_usage 400808 # Number of bytes of host memory used 11host_seconds 186.13 # Real time elapsed on the host 12sim_insts 61450599 # Number of instructions simulated 13sim_ops 78301940 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory | 29system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory |
| 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory | 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory |
| 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
| 42system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6653925 # Total number of read requests seen 70system.physmem.writeReqs 820679 # Total number of write requests seen 71system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 425851200 # Total number of bytes read from memory 73system.physmem.bytesWritten 52523456 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 112system.physmem.totGap 1182878628500 # Total gap between requests 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 6825 # Categorize read packet sizes 116system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes 119system.physmem.readPktSize::6 159036 # Categorize read packet sizes 120system.physmem.readPktSize::7 0 # Categorize read packet sizes 121system.physmem.readPktSize::8 0 # Categorize read packet sizes 122system.physmem.writePktSize::0 0 # categorize write packet sizes 123system.physmem.writePktSize::1 0 # categorize write packet sizes 124system.physmem.writePktSize::2 756836 # categorize write packet sizes 125system.physmem.writePktSize::3 0 # categorize write packet sizes 126system.physmem.writePktSize::4 0 # categorize write packet sizes 127system.physmem.writePktSize::5 0 # categorize write packet sizes 128system.physmem.writePktSize::6 63843 # categorize write packet sizes 129system.physmem.writePktSize::7 0 # categorize write packet sizes 130system.physmem.writePktSize::8 0 # categorize write packet sizes 131system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 132system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 133system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 134system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 135system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 136system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 137system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes 138system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 139system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 140system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 1777 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 643 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 481 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 367 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 155 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 139 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 117 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 109 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 44 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 35682 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 206system.physmem.totQLat 3516126974 # Total cycles spent in queuing delays 207system.physmem.totMemAccLat 123045854974 # Sum of mem lat for all requests 208system.physmem.totBusLat 26615172000 # Total cycles spent in databus access 209system.physmem.totBankLat 92914556000 # Total cycles spent in bank access 210system.physmem.avgQLat 528.44 # Average queueing delay per request 211system.physmem.avgBankLat 13964.15 # Average bank access latency per request 212system.physmem.avgBusLat 4000.00 # Average bus latency per request 213system.physmem.avgMemAccLat 18492.59 # Average memory access latency 214system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s 215system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s 216system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s 217system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s 218system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 219system.physmem.busUtil 2.53 # Data bus utilization in percentage 220system.physmem.avgRdQLen 0.10 # Average read queue length over time 221system.physmem.avgWrQLen 15.12 # Average write queue length over time 222system.physmem.readRowHits 6625021 # Number of row buffer hits during reads 223system.physmem.writeRowHits 788582 # Number of row buffer hits during writes 224system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads 225system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes 226system.physmem.avgGap 158253.02 # Average gap between requests |
| 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) | 227system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 228system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 229system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 230system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 231system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 232system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 233system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 234system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 235system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 236system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) |
| 79system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) | 237system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 238system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) |
| 81system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) | 239system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) |
| 82system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) | 240system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 241system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) |
| 84system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) | 242system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) |
| 85system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 70188 # number of replacements 88system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use 89system.l2c.total_refs 1643838 # Total number of references to valid blocks. 90system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. 91system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. | 243system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 244system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) 245system.l2c.replacements 68923 # number of replacements 246system.l2c.tagsinuse 53039.119781 # Cycle average of tags in use 247system.l2c.total_refs 1673706 # Total number of references to valid blocks. 248system.l2c.sampled_refs 134114 # Sample count of references to valid blocks. 249system.l2c.avg_refs 12.479726 # Average number of references to valid blocks. |
| 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 93system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 3394.604865 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 2735.402876 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 2.669960 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 3118.943835 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 3522.873439 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.617273 # Average percentage of cache occupancy | 251system.l2c.occ_blocks::writebacks 40183.428696 # Average occupied blocks per requestor 252system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor 253system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor 254system.l2c.occ_blocks::cpu0.inst 3728.892697 # Average occupied blocks per requestor 255system.l2c.occ_blocks::cpu0.data 4238.506487 # Average occupied blocks per requestor 256system.l2c.occ_blocks::cpu1.dtb.walker 2.742166 # Average occupied blocks per requestor 257system.l2c.occ_blocks::cpu1.inst 2823.934351 # Average occupied blocks per requestor 258system.l2c.occ_blocks::cpu1.data 2061.613566 # Average occupied blocks per requestor 259system.l2c.occ_percent::writebacks 0.613150 # Average percentage of cache occupancy |
| 102system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 260system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 261system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 104system.l2c.occ_percent::cpu0.inst 0.051798 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.047591 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.053755 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.812196 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 278308 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 124645 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 5210 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 576222 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 223363 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1213263 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 571562 # number of Writeback hits 120system.l2c.Writeback_hits::total 571562 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 878 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1870 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 285 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 39231 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 70244 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 278308 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 163876 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 5210 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 576222 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 293607 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1322738 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 278308 # number of overall hits 142system.l2c.overall_hits::cpu0.data 163876 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 5210 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 576222 # number of overall hits 146system.l2c.overall_hits::cpu1.data 293607 # number of overall hits 147system.l2c.overall_hits::total 1322738 # number of overall hits | 262system.l2c.occ_percent::cpu0.inst 0.056898 # Average percentage of cache occupancy 263system.l2c.occ_percent::cpu0.data 0.064674 # Average percentage of cache occupancy 264system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 265system.l2c.occ_percent::cpu1.inst 0.043090 # Average percentage of cache occupancy 266system.l2c.occ_percent::cpu1.data 0.031458 # Average percentage of cache occupancy 267system.l2c.occ_percent::total 0.809313 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.dtb.walker 4148 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.itb.walker 1813 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu0.inst 419656 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu0.data 206316 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu1.itb.walker 1906 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu1.inst 464180 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu1.data 143508 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1247033 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 571732 # number of Writeback hits 278system.l2c.Writeback_hits::total 571732 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 1159 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::cpu1.data 640 # number of UpgradeReq hits 281system.l2c.UpgradeReq_hits::total 1799 # number of UpgradeReq hits 282system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits 283system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits 284system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits 285system.l2c.ReadExReq_hits::cpu0.data 56965 # number of ReadExReq hits 286system.l2c.ReadExReq_hits::cpu1.data 52844 # number of ReadExReq hits 287system.l2c.ReadExReq_hits::total 109809 # number of ReadExReq hits 288system.l2c.demand_hits::cpu0.dtb.walker 4148 # number of demand (read+write) hits 289system.l2c.demand_hits::cpu0.itb.walker 1813 # number of demand (read+write) hits 290system.l2c.demand_hits::cpu0.inst 419656 # number of demand (read+write) hits 291system.l2c.demand_hits::cpu0.data 263281 # number of demand (read+write) hits 292system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits 293system.l2c.demand_hits::cpu1.itb.walker 1906 # number of demand (read+write) hits 294system.l2c.demand_hits::cpu1.inst 464180 # number of demand (read+write) hits 295system.l2c.demand_hits::cpu1.data 196352 # number of demand (read+write) hits 296system.l2c.demand_hits::total 1356842 # number of demand (read+write) hits 297system.l2c.overall_hits::cpu0.dtb.walker 4148 # number of overall hits 298system.l2c.overall_hits::cpu0.itb.walker 1813 # number of overall hits 299system.l2c.overall_hits::cpu0.inst 419656 # number of overall hits 300system.l2c.overall_hits::cpu0.data 263281 # number of overall hits 301system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits 302system.l2c.overall_hits::cpu1.itb.walker 1906 # number of overall hits 303system.l2c.overall_hits::cpu1.inst 464180 # number of overall hits 304system.l2c.overall_hits::cpu1.data 196352 # number of overall hits 305system.l2c.overall_hits::total 1356842 # number of overall hits |
| 148system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses | 306system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses |
| 149system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 150system.l2c.ReadReq_misses::cpu0.inst 5119 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 6000 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu1.inst 5697 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 5608 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 4011 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 4908 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 8919 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 652 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1040 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 61450 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses | 307system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 308system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses 309system.l2c.ReadReq_misses::cpu0.data 7859 # number of ReadReq misses 310system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 311system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses 312system.l2c.ReadReq_misses::cpu1.data 3621 # number of ReadReq misses 313system.l2c.ReadReq_misses::total 22264 # number of ReadReq misses 314system.l2c.UpgradeReq_misses::cpu0.data 4676 # number of UpgradeReq misses 315system.l2c.UpgradeReq_misses::cpu1.data 3594 # number of UpgradeReq misses 316system.l2c.UpgradeReq_misses::total 8270 # number of UpgradeReq misses 317system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses 318system.l2c.SCUpgradeReq_misses::cpu1.data 474 # number of SCUpgradeReq misses 319system.l2c.SCUpgradeReq_misses::total 1038 # number of SCUpgradeReq misses 320system.l2c.ReadExReq_misses::cpu0.data 67114 # number of ReadExReq misses 321system.l2c.ReadExReq_misses::cpu1.data 72101 # number of ReadExReq misses 322system.l2c.ReadExReq_misses::total 139215 # number of ReadExReq misses |
| 165system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses | 323system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses |
| 166system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu0.inst 5119 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu1.inst 5697 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 84447 # number of demand (read+write) misses 172system.l2c.demand_misses::total 162720 # number of demand (read+write) misses | 324system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 325system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses 326system.l2c.demand_misses::cpu0.data 74973 # number of demand (read+write) misses 327system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 328system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses 329system.l2c.demand_misses::cpu1.data 75722 # number of demand (read+write) misses 330system.l2c.demand_misses::total 161479 # number of demand (read+write) misses |
| 173system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses | 331system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses |
| 174system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 175system.l2c.overall_misses::cpu0.inst 5119 # number of overall misses 176system.l2c.overall_misses::cpu0.data 67450 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 5697 # number of overall misses 179system.l2c.overall_misses::cpu1.data 84447 # number of overall misses 180system.l2c.overall_misses::total 162720 # number of overall misses 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 267825000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 313081000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 156000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 298083000 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 292866500 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1172220000 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 15780999 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 31202500 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 46983499 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1357500 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6172500 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 7530000 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3221673990 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 4120152496 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7341826486 # number of ReadExReq miss cycles 198system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu0.inst 267825000 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3534754990 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 156000 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 298083000 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 4413018996 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8514046486 # number of demand (read+write) miss cycles 206system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu0.inst 267825000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3534754990 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 156000 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 298083000 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 4413018996 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8514046486 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 283427 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 130645 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 5213 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 581919 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 228971 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1235694 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 571562 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 571562 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 5003 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 5786 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 10789 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 841 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 484 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1325 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 100681 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 149083 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 249764 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 283427 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 231326 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 5213 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 581919 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 378054 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1485458 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 283427 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 231326 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 5213 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 581919 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 378054 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1485458 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.018061 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.045926 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.009790 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.024492 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.018153 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801719 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848254 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.826675 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.775268 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.801653 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.784906 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.610344 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.528826 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.561686 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.018061 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.291580 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.009790 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.223373 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.109542 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.018061 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.291580 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.009790 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.223373 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.109542 # miss rate for overall accesses 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52319.789021 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52180.166667 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52322.801474 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52222.985021 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52258.927377 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3934.430067 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6357.477588 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 5267.798968 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2082.055215 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15908.505155 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 7240.384615 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52427.566965 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52260.334302 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 52333.586283 # average ReadExReq miss latency 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52323.294530 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 52323.294530 # average overall miss latency | 332system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 333system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses 334system.l2c.overall_misses::cpu0.data 74973 # number of overall misses 335system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 336system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses 337system.l2c.overall_misses::cpu1.data 75722 # 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number of UpgradeReq miss cycles 350system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1751500 # number of SCUpgradeReq miss cycles 351system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles 352system.l2c.SCUpgradeReq_miss_latency::total 4160000 # number of SCUpgradeReq miss cycles 353system.l2c.ReadExReq_miss_latency::cpu0.data 3003544975 # number of ReadExReq miss cycles 354system.l2c.ReadExReq_miss_latency::cpu1.data 3416776995 # number of ReadExReq miss cycles 355system.l2c.ReadExReq_miss_latency::total 6420321970 # number of ReadExReq miss cycles 356system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles 357system.l2c.demand_miss_latency::cpu0.itb.walker 67500 # number of demand (read+write) miss cycles 358system.l2c.demand_miss_latency::cpu0.inst 285133000 # number of demand (read+write) miss cycles 359system.l2c.demand_miss_latency::cpu0.data 3407574975 # number of demand (read+write) miss cycles 360system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles 361system.l2c.demand_miss_latency::cpu1.inst 261135000 # number of demand (read+write) miss cycles 362system.l2c.demand_miss_latency::cpu1.data 3628946495 # number of demand (read+write) miss cycles 363system.l2c.demand_miss_latency::total 7583173470 # number of demand (read+write) miss cycles 364system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles 365system.l2c.overall_miss_latency::cpu0.itb.walker 67500 # number of overall miss cycles 366system.l2c.overall_miss_latency::cpu0.inst 285133000 # number of overall miss cycles 367system.l2c.overall_miss_latency::cpu0.data 3407574975 # number of overall miss cycles 368system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles 369system.l2c.overall_miss_latency::cpu1.inst 261135000 # number of overall miss cycles 370system.l2c.overall_miss_latency::cpu1.data 3628946495 # number of overall miss cycles 371system.l2c.overall_miss_latency::total 7583173470 # number of overall miss cycles 372system.l2c.ReadReq_accesses::cpu0.dtb.walker 4149 # number of ReadReq accesses(hits+misses) 373system.l2c.ReadReq_accesses::cpu0.itb.walker 1815 # number of ReadReq accesses(hits+misses) 374system.l2c.ReadReq_accesses::cpu0.inst 425389 # number of ReadReq accesses(hits+misses) 375system.l2c.ReadReq_accesses::cpu0.data 214175 # number of ReadReq accesses(hits+misses) 376system.l2c.ReadReq_accesses::cpu1.dtb.walker 5510 # number of ReadReq accesses(hits+misses) 377system.l2c.ReadReq_accesses::cpu1.itb.walker 1906 # number of ReadReq accesses(hits+misses) 378system.l2c.ReadReq_accesses::cpu1.inst 469224 # number of ReadReq accesses(hits+misses) 379system.l2c.ReadReq_accesses::cpu1.data 147129 # number of ReadReq accesses(hits+misses) 380system.l2c.ReadReq_accesses::total 1269297 # number of ReadReq accesses(hits+misses) 381system.l2c.Writeback_accesses::writebacks 571732 # number of Writeback accesses(hits+misses) 382system.l2c.Writeback_accesses::total 571732 # number of Writeback accesses(hits+misses) 383system.l2c.UpgradeReq_accesses::cpu0.data 5835 # number of UpgradeReq accesses(hits+misses) 384system.l2c.UpgradeReq_accesses::cpu1.data 4234 # number of UpgradeReq accesses(hits+misses) 385system.l2c.UpgradeReq_accesses::total 10069 # number of UpgradeReq accesses(hits+misses) 386system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) 387system.l2c.SCUpgradeReq_accesses::cpu1.data 571 # number of SCUpgradeReq accesses(hits+misses) 388system.l2c.SCUpgradeReq_accesses::total 1350 # number of SCUpgradeReq accesses(hits+misses) 389system.l2c.ReadExReq_accesses::cpu0.data 124079 # number of ReadExReq accesses(hits+misses) 390system.l2c.ReadExReq_accesses::cpu1.data 124945 # number of ReadExReq accesses(hits+misses) 391system.l2c.ReadExReq_accesses::total 249024 # number of ReadExReq accesses(hits+misses) 392system.l2c.demand_accesses::cpu0.dtb.walker 4149 # number of demand (read+write) accesses 393system.l2c.demand_accesses::cpu0.itb.walker 1815 # number of demand (read+write) accesses 394system.l2c.demand_accesses::cpu0.inst 425389 # number of demand (read+write) accesses 395system.l2c.demand_accesses::cpu0.data 338254 # number of demand (read+write) accesses 396system.l2c.demand_accesses::cpu1.dtb.walker 5510 # number of demand (read+write) accesses 397system.l2c.demand_accesses::cpu1.itb.walker 1906 # number of demand (read+write) accesses 398system.l2c.demand_accesses::cpu1.inst 469224 # number of demand (read+write) accesses 399system.l2c.demand_accesses::cpu1.data 272074 # number of demand (read+write) accesses 400system.l2c.demand_accesses::total 1518321 # number of demand (read+write) accesses 401system.l2c.overall_accesses::cpu0.dtb.walker 4149 # number of overall (read+write) accesses 402system.l2c.overall_accesses::cpu0.itb.walker 1815 # number of overall (read+write) accesses 403system.l2c.overall_accesses::cpu0.inst 425389 # number of overall (read+write) accesses 404system.l2c.overall_accesses::cpu0.data 338254 # number of overall (read+write) accesses 405system.l2c.overall_accesses::cpu1.dtb.walker 5510 # number of overall (read+write) accesses 406system.l2c.overall_accesses::cpu1.itb.walker 1906 # number of overall (read+write) accesses 407system.l2c.overall_accesses::cpu1.inst 469224 # number of overall (read+write) accesses 408system.l2c.overall_accesses::cpu1.data 272074 # number of overall (read+write) accesses 409system.l2c.overall_accesses::total 1518321 # number of overall (read+write) accesses 410system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for ReadReq accesses 411system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001102 # miss rate for ReadReq accesses 412system.l2c.ReadReq_miss_rate::cpu0.inst 0.013477 # miss rate for ReadReq accesses 413system.l2c.ReadReq_miss_rate::cpu0.data 0.036694 # miss rate for ReadReq accesses 414system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses 415system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses 416system.l2c.ReadReq_miss_rate::cpu1.data 0.024611 # miss rate for ReadReq accesses 417system.l2c.ReadReq_miss_rate::total 0.017540 # miss rate for ReadReq accesses 418system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801371 # miss rate for UpgradeReq accesses 419system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848843 # miss rate for UpgradeReq accesses 420system.l2c.UpgradeReq_miss_rate::total 0.821333 # miss rate for UpgradeReq accesses 421system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724005 # miss rate for SCUpgradeReq accesses 422system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830123 # miss rate for SCUpgradeReq accesses 423system.l2c.SCUpgradeReq_miss_rate::total 0.768889 # miss rate for SCUpgradeReq accesses 424system.l2c.ReadExReq_miss_rate::cpu0.data 0.540897 # miss rate for ReadExReq accesses 425system.l2c.ReadExReq_miss_rate::cpu1.data 0.577062 # miss rate for ReadExReq accesses 426system.l2c.ReadExReq_miss_rate::total 0.559043 # miss rate for ReadExReq accesses 427system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for demand accesses 428system.l2c.demand_miss_rate::cpu0.itb.walker 0.001102 # miss rate for demand accesses 429system.l2c.demand_miss_rate::cpu0.inst 0.013477 # miss rate for demand accesses 430system.l2c.demand_miss_rate::cpu0.data 0.221647 # miss rate for demand accesses 431system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses 432system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses 433system.l2c.demand_miss_rate::cpu1.data 0.278314 # miss rate for demand accesses 434system.l2c.demand_miss_rate::total 0.106354 # miss rate for demand accesses 435system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for overall accesses 436system.l2c.overall_miss_rate::cpu0.itb.walker 0.001102 # miss rate for overall accesses 437system.l2c.overall_miss_rate::cpu0.inst 0.013477 # miss rate for overall accesses 438system.l2c.overall_miss_rate::cpu0.data 0.221647 # miss rate for overall accesses 439system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses 440system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses 441system.l2c.overall_miss_rate::cpu1.data 0.278314 # miss rate for overall accesses 442system.l2c.overall_miss_rate::total 0.106354 # miss rate for overall accesses 443system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency 444system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 33750 # average ReadReq miss latency 445system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49735.391593 # average ReadReq miss latency 446system.l2c.ReadReq_avg_miss_latency::cpu0.data 51409.848581 # average ReadReq miss latency 447system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency 448system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51771.411578 # average ReadReq miss latency 449system.l2c.ReadReq_avg_miss_latency::cpu1.data 58594.172880 # average ReadReq miss latency 450system.l2c.ReadReq_avg_miss_latency::total 52230.124865 # average ReadReq miss latency 451system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2702.950599 # average UpgradeReq miss latency 452system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3269.337507 # average UpgradeReq miss latency 453system.l2c.UpgradeReq_avg_miss_latency::total 2949.092624 # average UpgradeReq miss latency 454system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3105.496454 # average SCUpgradeReq miss latency 455system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5081.223629 # average SCUpgradeReq miss latency 456system.l2c.SCUpgradeReq_avg_miss_latency::total 4007.707129 # average SCUpgradeReq miss latency 457system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44752.882782 # average ReadExReq miss latency 458system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47388.760142 # average ReadExReq miss latency 459system.l2c.ReadExReq_avg_miss_latency::total 46118.033042 # average ReadExReq miss latency 460system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency 461system.l2c.demand_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency 462system.l2c.demand_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency 463system.l2c.demand_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency 464system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency 465system.l2c.demand_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency 466system.l2c.demand_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency 467system.l2c.demand_avg_miss_latency::total 46960.740839 # average overall miss latency 468system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency 469system.l2c.overall_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency 470system.l2c.overall_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency 471system.l2c.overall_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency 472system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency 473system.l2c.overall_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency 474system.l2c.overall_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency 475system.l2c.overall_avg_miss_latency::total 46960.740839 # average overall miss latency |
| 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed | 476system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 477system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 478system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 479system.l2c.blocked::no_targets 0 # number of cycles access was blocked 480system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 481system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 482system.l2c.fast_writes 0 # number of fast writes performed 483system.l2c.cache_copies 0 # number of cache copies performed |
| 326system.l2c.writebacks::writebacks 65061 # number of writebacks 327system.l2c.writebacks::total 65061 # number of writebacks | 484system.l2c.writebacks::writebacks 63843 # number of writebacks 485system.l2c.writebacks::total 63843 # number of writebacks |
| 328system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 330system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 331system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 332system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 333system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 334system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses | 486system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 487system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 488system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 489system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 490system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 491system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 492system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses |
| 335system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses 336system.l2c.ReadReq_mshr_misses::cpu0.inst 5118 # number of ReadReq MSHR misses 337system.l2c.ReadReq_mshr_misses::cpu0.data 6000 # number of ReadReq MSHR misses 338system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses 339system.l2c.ReadReq_mshr_misses::cpu1.inst 5697 # number of ReadReq MSHR misses 340system.l2c.ReadReq_mshr_misses::cpu1.data 5608 # number of ReadReq MSHR misses 341system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses 342system.l2c.UpgradeReq_mshr_misses::cpu0.data 4011 # number of UpgradeReq MSHR misses 343system.l2c.UpgradeReq_mshr_misses::cpu1.data 4908 # number of UpgradeReq MSHR misses 344system.l2c.UpgradeReq_mshr_misses::total 8919 # number of UpgradeReq MSHR misses 345system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 652 # number of SCUpgradeReq MSHR misses 346system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses 347system.l2c.SCUpgradeReq_mshr_misses::total 1040 # number of SCUpgradeReq MSHR misses 348system.l2c.ReadExReq_mshr_misses::cpu0.data 61450 # number of ReadExReq MSHR misses 349system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses 350system.l2c.ReadExReq_mshr_misses::total 140289 # number of ReadExReq MSHR misses | 493system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 494system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses 495system.l2c.ReadReq_mshr_misses::cpu0.data 7859 # number of ReadReq MSHR misses 496system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses 497system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses 498system.l2c.ReadReq_mshr_misses::cpu1.data 3621 # number of ReadReq MSHR misses 499system.l2c.ReadReq_mshr_misses::total 22263 # number of ReadReq MSHR misses 500system.l2c.UpgradeReq_mshr_misses::cpu0.data 4676 # number of UpgradeReq MSHR misses 501system.l2c.UpgradeReq_mshr_misses::cpu1.data 3594 # number of UpgradeReq MSHR misses 502system.l2c.UpgradeReq_mshr_misses::total 8270 # number of UpgradeReq MSHR misses 503system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses 504system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 474 # number of SCUpgradeReq MSHR misses 505system.l2c.SCUpgradeReq_mshr_misses::total 1038 # number of SCUpgradeReq MSHR misses 506system.l2c.ReadExReq_mshr_misses::cpu0.data 67114 # number of ReadExReq MSHR misses 507system.l2c.ReadExReq_mshr_misses::cpu1.data 72101 # number of ReadExReq MSHR misses 508system.l2c.ReadExReq_mshr_misses::total 139215 # number of ReadExReq MSHR misses |
| 351system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses | 509system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses |
| 352system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 353system.l2c.demand_mshr_misses::cpu0.inst 5118 # number of demand (read+write) MSHR misses 354system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses 355system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses 356system.l2c.demand_mshr_misses::cpu1.inst 5697 # number of demand (read+write) MSHR misses 357system.l2c.demand_mshr_misses::cpu1.data 84447 # number of demand (read+write) MSHR misses 358system.l2c.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses | 510system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 511system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses 512system.l2c.demand_mshr_misses::cpu0.data 74973 # number of demand (read+write) MSHR misses 513system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses 514system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses 515system.l2c.demand_mshr_misses::cpu1.data 75722 # number of demand (read+write) MSHR misses 516system.l2c.demand_mshr_misses::total 161478 # number of demand (read+write) MSHR misses |
| 359system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses | 517system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses |
| 360system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 361system.l2c.overall_mshr_misses::cpu0.inst 5118 # number of overall MSHR misses 362system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses 363system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses 364system.l2c.overall_mshr_misses::cpu1.inst 5697 # number of overall MSHR misses 365system.l2c.overall_mshr_misses::cpu1.data 84447 # number of overall MSHR misses 366system.l2c.overall_mshr_misses::total 162719 # number of overall MSHR misses 367system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles 368system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles 369system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204790500 # number of ReadReq MSHR miss cycles 370system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240017000 # number of ReadReq MSHR miss cycles 371system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 120000 # number of ReadReq MSHR miss cycles 372system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 227965500 # number of ReadReq MSHR miss cycles 373system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224340500 # number of ReadReq MSHR miss cycles 374system.l2c.ReadReq_mshr_miss_latency::total 897393500 # number of ReadReq MSHR miss cycles 375system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160489997 # number of UpgradeReq MSHR miss cycles 376system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196385999 # number of UpgradeReq MSHR miss cycles 377system.l2c.UpgradeReq_mshr_miss_latency::total 356875996 # number of UpgradeReq MSHR miss cycles 378system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26081499 # number of SCUpgradeReq MSHR miss cycles 379system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15523499 # number of SCUpgradeReq MSHR miss cycles 380system.l2c.SCUpgradeReq_mshr_miss_latency::total 41604998 # number of SCUpgradeReq MSHR miss cycles 381system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458644990 # number of ReadExReq MSHR miss cycles 382system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3153935496 # number of ReadExReq MSHR miss cycles 383system.l2c.ReadExReq_mshr_miss_latency::total 5612580486 # number of ReadExReq MSHR miss cycles 384system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles 385system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles 386system.l2c.demand_mshr_miss_latency::cpu0.inst 204790500 # number of demand (read+write) MSHR miss cycles 387system.l2c.demand_mshr_miss_latency::cpu0.data 2698661990 # number of demand (read+write) MSHR miss cycles 388system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 120000 # number of demand (read+write) MSHR miss cycles 389system.l2c.demand_mshr_miss_latency::cpu1.inst 227965500 # number of demand (read+write) MSHR miss cycles 390system.l2c.demand_mshr_miss_latency::cpu1.data 3378275996 # number of demand (read+write) MSHR miss cycles 391system.l2c.demand_mshr_miss_latency::total 6509973986 # number of demand (read+write) MSHR miss cycles 392system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles 393system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles 394system.l2c.overall_mshr_miss_latency::cpu0.inst 204790500 # number of overall MSHR miss cycles 395system.l2c.overall_mshr_miss_latency::cpu0.data 2698661990 # number of overall MSHR miss cycles 396system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 120000 # number of overall MSHR miss cycles 397system.l2c.overall_mshr_miss_latency::cpu1.inst 227965500 # number of overall MSHR miss cycles 398system.l2c.overall_mshr_miss_latency::cpu1.data 3378275996 # number of overall MSHR miss cycles 399system.l2c.overall_mshr_miss_latency::total 6509973986 # number of overall MSHR miss cycles 400system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles 401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136863000 # number of ReadReq MSHR uncacheable cycles 402system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles 403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155607031000 # number of ReadReq MSHR uncacheable cycles 404system.l2c.ReadReq_mshr_uncacheable_latency::total 167013375500 # number of ReadReq MSHR uncacheable cycles 405system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070738498 # number of WriteReq MSHR uncacheable cycles 406system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30849143000 # number of WriteReq MSHR uncacheable cycles 407system.l2c.WriteReq_mshr_uncacheable_latency::total 31919881498 # number of WriteReq MSHR uncacheable cycles 408system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles 409system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207601498 # number of overall MSHR uncacheable cycles 410system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles 411system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186456174000 # number of overall MSHR uncacheable cycles 412system.l2c.overall_mshr_uncacheable_latency::total 198933256998 # number of overall MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045926 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses 418system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for ReadReq accesses 419system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024492 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::total 0.018152 # mshr miss rate for ReadReq accesses 421system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801719 # mshr miss rate for UpgradeReq accesses 422system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848254 # mshr miss rate for UpgradeReq accesses 423system.l2c.UpgradeReq_mshr_miss_rate::total 0.826675 # mshr miss rate for UpgradeReq accesses 424system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.775268 # mshr miss rate for SCUpgradeReq accesses 425system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.801653 # mshr miss rate for SCUpgradeReq accesses 426system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784906 # mshr miss rate for SCUpgradeReq accesses 427system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610344 # mshr miss rate for ReadExReq accesses 428system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528826 # mshr miss rate for ReadExReq accesses 429system.l2c.ReadExReq_mshr_miss_rate::total 0.561686 # mshr miss rate for ReadExReq accesses 430system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses 431system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses 432system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for demand accesses 433system.l2c.demand_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for demand accesses 434system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for demand accesses 435system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for demand accesses 436system.l2c.demand_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for demand accesses 437system.l2c.demand_mshr_miss_rate::total 0.109541 # mshr miss rate for demand accesses 438system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses 439system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses 440system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for overall accesses 441system.l2c.overall_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for overall accesses 442system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for overall accesses 443system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for overall accesses 444system.l2c.overall_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for overall accesses 445system.l2c.overall_mshr_miss_rate::total 0.109541 # mshr miss rate for overall accesses 446system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 447system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency 448system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average ReadReq mshr miss latency 449system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40002.833333 # average ReadReq mshr miss latency 450system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency 451system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average ReadReq mshr miss latency 452system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40003.655492 # average ReadReq mshr miss latency 453system.l2c.ReadReq_avg_mshr_miss_latency::total 40008.626839 # average ReadReq mshr miss latency 454system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40012.464971 # average UpgradeReq mshr miss latency 455system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40013.447229 # average UpgradeReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40013.005494 # average UpgradeReq mshr miss latency 457system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.299080 # average SCUpgradeReq mshr miss latency 458system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40009.018041 # average SCUpgradeReq mshr miss latency 459system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40004.805769 # average SCUpgradeReq mshr miss latency 460system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.496176 # average ReadExReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40004.762820 # average ReadExReq mshr miss latency 462system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.274170 # average ReadExReq mshr miss latency 463system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 464system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency 465system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency 466system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency 471system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 472system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency 473system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency 474system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency 475system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency | 518system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 519system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses 520system.l2c.overall_mshr_misses::cpu0.data 74973 # number of overall MSHR misses 521system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses 522system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses 523system.l2c.overall_mshr_misses::cpu1.data 75722 # number of overall MSHR misses 524system.l2c.overall_mshr_misses::total 161478 # number of overall MSHR misses 525system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56002 # number of ReadReq MSHR miss cycles 526system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 42004 # number of ReadReq MSHR miss cycles 527system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212317379 # number of ReadReq MSHR miss cycles 528system.l2c.ReadReq_mshr_miss_latency::cpu0.data 303283129 # number of ReadReq MSHR miss cycles 529system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 196008 # number of ReadReq MSHR miss cycles 530system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 197074983 # number of ReadReq MSHR miss cycles 531system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165938649 # number of ReadReq MSHR miss cycles 532system.l2c.ReadReq_mshr_miss_latency::total 878908154 # number of ReadReq MSHR miss cycles 533system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46908094 # number of UpgradeReq MSHR miss cycles 534system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36050560 # number of UpgradeReq MSHR miss cycles 535system.l2c.UpgradeReq_mshr_miss_latency::total 82958654 # number of UpgradeReq MSHR miss cycles 536system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5654558 # number of SCUpgradeReq MSHR miss cycles 537system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4769959 # number of SCUpgradeReq MSHR miss cycles 538system.l2c.SCUpgradeReq_mshr_miss_latency::total 10424517 # number of SCUpgradeReq MSHR miss cycles 539system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2158776151 # number of ReadExReq MSHR miss cycles 540system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2496303754 # number of ReadExReq MSHR miss cycles 541system.l2c.ReadExReq_mshr_miss_latency::total 4655079905 # number of ReadExReq MSHR miss cycles 542system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles 543system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 42004 # number of demand (read+write) MSHR miss cycles 544system.l2c.demand_mshr_miss_latency::cpu0.inst 212317379 # number of demand (read+write) MSHR miss cycles 545system.l2c.demand_mshr_miss_latency::cpu0.data 2462059280 # number of demand (read+write) MSHR miss cycles 546system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 196008 # number of demand (read+write) MSHR miss cycles 547system.l2c.demand_mshr_miss_latency::cpu1.inst 197074983 # number of demand (read+write) MSHR miss cycles 548system.l2c.demand_mshr_miss_latency::cpu1.data 2662242403 # number of demand (read+write) MSHR miss cycles 549system.l2c.demand_mshr_miss_latency::total 5533988059 # number of demand (read+write) MSHR miss cycles 550system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56002 # number of overall MSHR miss cycles 551system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 42004 # number of overall MSHR miss cycles 552system.l2c.overall_mshr_miss_latency::cpu0.inst 212317379 # number of overall MSHR miss cycles 553system.l2c.overall_mshr_miss_latency::cpu0.data 2462059280 # number of overall MSHR miss cycles 554system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196008 # number of overall MSHR miss cycles 555system.l2c.overall_mshr_miss_latency::cpu1.inst 197074983 # number of overall MSHR miss cycles 556system.l2c.overall_mshr_miss_latency::cpu1.data 2662242403 # number of overall MSHR miss cycles 557system.l2c.overall_mshr_miss_latency::total 5533988059 # number of overall MSHR miss cycles 558system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197971583 # number of ReadReq MSHR uncacheable cycles 559system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448379609 # number of ReadReq MSHR uncacheable cycles 560system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3031674 # number of ReadReq MSHR uncacheable cycles 561system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154289730543 # number of ReadReq MSHR uncacheable cycles 562system.l2c.ReadReq_mshr_uncacheable_latency::total 166939113409 # number of ReadReq MSHR uncacheable cycles 563system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000300750 # number of WriteReq MSHR uncacheable cycles 564system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8208718440 # number of WriteReq MSHR uncacheable cycles 565system.l2c.WriteReq_mshr_uncacheable_latency::total 9209019190 # number of WriteReq MSHR uncacheable cycles 566system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197971583 # number of overall MSHR uncacheable cycles 567system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13448680359 # number of overall MSHR uncacheable cycles 568system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles 569system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162498448983 # number of overall MSHR uncacheable cycles 570system.l2c.overall_mshr_uncacheable_latency::total 176148132599 # number of overall MSHR uncacheable cycles 571system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for ReadReq accesses 572system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for ReadReq accesses 573system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses 574system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036694 # mshr miss rate for ReadReq accesses 575system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses 576system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses 577system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024611 # mshr miss rate for ReadReq accesses 578system.l2c.ReadReq_mshr_miss_rate::total 0.017540 # mshr miss rate for ReadReq accesses 579system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801371 # mshr miss rate for UpgradeReq accesses 580system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848843 # mshr miss rate for UpgradeReq accesses 581system.l2c.UpgradeReq_mshr_miss_rate::total 0.821333 # mshr miss rate for UpgradeReq accesses 582system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses 583system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830123 # mshr miss rate for SCUpgradeReq accesses 584system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.768889 # mshr miss rate for SCUpgradeReq accesses 585system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540897 # mshr miss rate for ReadExReq accesses 586system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577062 # mshr miss rate for ReadExReq accesses 587system.l2c.ReadExReq_mshr_miss_rate::total 0.559043 # mshr miss rate for ReadExReq accesses 588system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for demand accesses 589system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for demand accesses 590system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses 591system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses 592system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses 593system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses 594system.l2c.demand_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for demand accesses 595system.l2c.demand_mshr_miss_rate::total 0.106353 # mshr miss rate for demand accesses 596system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for overall accesses 597system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for overall accesses 598system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses 599system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses 600system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses 601system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses 602system.l2c.overall_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for overall accesses 603system.l2c.overall_mshr_miss_rate::total 0.106353 # mshr miss rate for overall accesses 604system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency 605system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency 606system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average ReadReq mshr miss latency 607system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38590.549561 # average ReadReq mshr miss latency 608system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency 609system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average ReadReq mshr miss latency 610system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45826.746479 # average ReadReq mshr miss latency 611system.l2c.ReadReq_avg_mshr_miss_latency::total 39478.424022 # average ReadReq mshr miss latency 612system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.671086 # average UpgradeReq mshr miss latency 613system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.762382 # average UpgradeReq mshr miss latency 614system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.276179 # average UpgradeReq mshr miss latency 615system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.812057 # average SCUpgradeReq mshr miss latency 616system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.204641 # average SCUpgradeReq mshr miss latency 617system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.887283 # average SCUpgradeReq mshr miss latency 618system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32165.809682 # average ReadExReq mshr miss latency 619system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34622.318054 # average ReadExReq mshr miss latency 620system.l2c.ReadExReq_avg_mshr_miss_latency::total 33438.062745 # average ReadExReq mshr miss latency 621system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency 622system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency 623system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency 624system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency 625system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency 626system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency 627system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency 628system.l2c.demand_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency 629system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency 630system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency 631system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency 632system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency 633system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency 634system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency 635system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency 636system.l2c.overall_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency |
| 479system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 483system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 486system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 493system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 494system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 495system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 496system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 497system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 498system.cf0.dma_write_txs 0 # Number of DMA write transactions. 499system.cpu0.dtb.inst_hits 0 # ITB inst hits 500system.cpu0.dtb.inst_misses 0 # ITB inst misses | 637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 638system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 639system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 640system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 641system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 642system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 643system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 644system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 651system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 652system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 653system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 654system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 655system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 656system.cf0.dma_write_txs 0 # Number of DMA write transactions. 657system.cpu0.dtb.inst_hits 0 # ITB inst hits 658system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 501system.cpu0.dtb.read_hits 4800569 # DTB read hits 502system.cpu0.dtb.read_misses 2116 # DTB read misses 503system.cpu0.dtb.write_hits 4101188 # DTB write hits 504system.cpu0.dtb.write_misses 405 # DTB write misses | 659system.cpu0.dtb.read_hits 7072899 # DTB read hits 660system.cpu0.dtb.read_misses 3762 # DTB read misses 661system.cpu0.dtb.write_hits 5658444 # DTB write hits 662system.cpu0.dtb.write_misses 809 # DTB write misses |
| 505system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 506system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 507system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 508system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 663system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 664system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 665system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 666system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 509system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB | 667system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB |
| 510system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 668system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 511system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch | 669system.cpu0.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch |
| 512system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 670system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 513system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions 514system.cpu0.dtb.read_accesses 4802685 # DTB read accesses 515system.cpu0.dtb.write_accesses 4101593 # DTB write accesses | 671system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 672system.cpu0.dtb.read_accesses 7076661 # DTB read accesses 673system.cpu0.dtb.write_accesses 5659253 # DTB write accesses |
| 516system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 674system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 517system.cpu0.dtb.hits 8901757 # DTB hits 518system.cpu0.dtb.misses 2521 # DTB misses 519system.cpu0.dtb.accesses 8904278 # DTB accesses 520system.cpu0.itb.inst_hits 19425317 # ITB inst hits 521system.cpu0.itb.inst_misses 1350 # ITB inst misses | 675system.cpu0.dtb.hits 12731343 # DTB hits 676system.cpu0.dtb.misses 4571 # DTB misses 677system.cpu0.dtb.accesses 12735914 # DTB accesses 678system.cpu0.itb.inst_hits 29570664 # ITB inst hits 679system.cpu0.itb.inst_misses 2205 # ITB inst misses |
| 522system.cpu0.itb.read_hits 0 # DTB read hits 523system.cpu0.itb.read_misses 0 # DTB read misses 524system.cpu0.itb.write_hits 0 # DTB write hits 525system.cpu0.itb.write_misses 0 # DTB write misses 526system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 527system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 528system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 529system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 680system.cpu0.itb.read_hits 0 # DTB read hits 681system.cpu0.itb.read_misses 0 # DTB read misses 682system.cpu0.itb.write_hits 0 # DTB write hits 683system.cpu0.itb.write_misses 0 # DTB write misses 684system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 685system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 686system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 687system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 530system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB | 688system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB |
| 531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.itb.read_accesses 0 # DTB read accesses 536system.cpu0.itb.write_accesses 0 # DTB write accesses | 689system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 690system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 691system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 692system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 693system.cpu0.itb.read_accesses 0 # DTB read accesses 694system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 537system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses 538system.cpu0.itb.hits 19425317 # DTB hits 539system.cpu0.itb.misses 1350 # DTB misses 540system.cpu0.itb.accesses 19426667 # DTB accesses 541system.cpu0.numCycles 2405785466 # number of cpu cycles simulated | 695system.cpu0.itb.inst_accesses 29572869 # ITB inst accesses 696system.cpu0.itb.hits 29570664 # DTB hits 697system.cpu0.itb.misses 2205 # DTB misses 698system.cpu0.itb.accesses 29572869 # DTB accesses 699system.cpu0.numCycles 2365766155 # number of cpu cycles simulated |
| 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 700system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 701system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 544system.cpu0.committedInsts 19048205 # Number of instructions committed 545system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses 547system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses 548system.cpu0.num_func_calls 868672 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 22684157 # number of integer instructions 551system.cpu0.num_fp_insts 4364 # number of float instructions 552system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written 554system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written 556system.cpu0.num_mem_refs 9388218 # number of memory refs 557system.cpu0.num_load_insts 5047895 # Number of load instructions 558system.cpu0.num_store_insts 4340323 # Number of store instructions 559system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles 560system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles 561system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles | 702system.cpu0.committedInsts 28872728 # Number of instructions committed 703system.cpu0.committedOps 37219681 # Number of ops (including micro ops) committed 704system.cpu0.num_int_alu_accesses 33106320 # Number of integer alu accesses 705system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 706system.cpu0.num_func_calls 1241688 # number of times a function call or return occured 707system.cpu0.num_conditional_control_insts 4373344 # number of instructions that are conditional controls 708system.cpu0.num_int_insts 33106320 # number of integer instructions 709system.cpu0.num_fp_insts 3860 # number of float instructions 710system.cpu0.num_int_register_reads 190095843 # number of times the integer registers were read 711system.cpu0.num_int_register_writes 36231130 # number of times the integer registers were written 712system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 713system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 714system.cpu0.num_mem_refs 13399483 # number of memory refs 715system.cpu0.num_load_insts 7410404 # Number of load instructions 716system.cpu0.num_store_insts 5989079 # Number of store instructions 717system.cpu0.num_idle_cycles 2224921697.356119 # Number of idle cycles 718system.cpu0.num_busy_cycles 140844457.643881 # Number of busy cycles 719system.cpu0.not_idle_fraction 0.059534 # Percentage of non-idle cycles 720system.cpu0.idle_fraction 0.940466 # Percentage of idle cycles |
| 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 721system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 564system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed 565system.cpu0.icache.replacements 283204 # number of replacements 566system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use 567system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. 568system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. 569system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. 570system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor 572system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy 573system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy 574system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits 579system.cpu0.icache.overall_hits::total 19141584 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses 585system.cpu0.icache.overall_misses::total 283716 # number of overall misses 586system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles 587system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles 588system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles 589system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles 590system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles 591system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles 592system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) 593system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) 594system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses 595system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses 596system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses 597system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses 598system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses 599system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses 600system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses 601system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses 602system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses 603system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses 604system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency 605system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency 606system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency 607system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency 608system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency 609system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # average overall miss latency | 722system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed 723system.cpu0.icache.replacements 425421 # number of replacements 724system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use 725system.cpu0.icache.total_refs 29144714 # Total number of references to valid blocks. 726system.cpu0.icache.sampled_refs 425933 # Sample count of references to valid blocks. 727system.cpu0.icache.avg_refs 68.425583 # Average number of references to valid blocks. 728system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. 729system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor 730system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy 731system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy 732system.cpu0.icache.ReadReq_hits::cpu0.inst 29144714 # number of ReadReq hits 733system.cpu0.icache.ReadReq_hits::total 29144714 # number of ReadReq hits 734system.cpu0.icache.demand_hits::cpu0.inst 29144714 # number of demand (read+write) hits 735system.cpu0.icache.demand_hits::total 29144714 # number of demand (read+write) hits 736system.cpu0.icache.overall_hits::cpu0.inst 29144714 # number of overall hits 737system.cpu0.icache.overall_hits::total 29144714 # number of overall hits 738system.cpu0.icache.ReadReq_misses::cpu0.inst 425933 # number of ReadReq misses 739system.cpu0.icache.ReadReq_misses::total 425933 # number of ReadReq misses 740system.cpu0.icache.demand_misses::cpu0.inst 425933 # number of demand (read+write) misses 741system.cpu0.icache.demand_misses::total 425933 # number of demand (read+write) misses 742system.cpu0.icache.overall_misses::cpu0.inst 425933 # number of overall misses 743system.cpu0.icache.overall_misses::total 425933 # number of overall misses 744system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794506500 # number of ReadReq miss cycles 745system.cpu0.icache.ReadReq_miss_latency::total 5794506500 # number of ReadReq miss cycles 746system.cpu0.icache.demand_miss_latency::cpu0.inst 5794506500 # number of demand (read+write) miss cycles 747system.cpu0.icache.demand_miss_latency::total 5794506500 # number of demand (read+write) miss cycles 748system.cpu0.icache.overall_miss_latency::cpu0.inst 5794506500 # number of overall miss cycles 749system.cpu0.icache.overall_miss_latency::total 5794506500 # number of overall miss cycles 750system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570647 # number of ReadReq accesses(hits+misses) 751system.cpu0.icache.ReadReq_accesses::total 29570647 # number of ReadReq accesses(hits+misses) 752system.cpu0.icache.demand_accesses::cpu0.inst 29570647 # number of demand (read+write) accesses 753system.cpu0.icache.demand_accesses::total 29570647 # number of demand (read+write) accesses 754system.cpu0.icache.overall_accesses::cpu0.inst 29570647 # number of overall (read+write) accesses 755system.cpu0.icache.overall_accesses::total 29570647 # number of overall (read+write) accesses 756system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses 757system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses 758system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses 759system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses 760system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses 761system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses 762system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.267573 # average ReadReq miss latency 763system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.267573 # average ReadReq miss latency 764system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency 765system.cpu0.icache.demand_avg_miss_latency::total 13604.267573 # average overall miss latency 766system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency 767system.cpu0.icache.overall_avg_miss_latency::total 13604.267573 # average overall miss latency |
| 610system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu0.icache.fast_writes 0 # number of fast writes performed 617system.cpu0.icache.cache_copies 0 # number of cache copies performed | 768system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 771system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 772system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 773system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu0.icache.fast_writes 0 # number of fast writes performed 775system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 618system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283716 # number of ReadReq MSHR misses 619system.cpu0.icache.ReadReq_mshr_misses::total 283716 # number of ReadReq MSHR misses 620system.cpu0.icache.demand_mshr_misses::cpu0.inst 283716 # number of demand (read+write) MSHR misses 621system.cpu0.icache.demand_mshr_misses::total 283716 # number of demand (read+write) MSHR misses 622system.cpu0.icache.overall_mshr_misses::cpu0.inst 283716 # number of overall MSHR misses 623system.cpu0.icache.overall_mshr_misses::total 283716 # number of overall MSHR misses 624system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362427500 # number of ReadReq MSHR miss cycles 625system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362427500 # number of ReadReq MSHR miss cycles 626system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362427500 # number of demand (read+write) MSHR miss cycles 627system.cpu0.icache.demand_mshr_miss_latency::total 3362427500 # number of demand (read+write) MSHR miss cycles 628system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362427500 # number of overall MSHR miss cycles 629system.cpu0.icache.overall_mshr_miss_latency::total 3362427500 # number of overall MSHR miss cycles 630system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles 631system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles 632system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles 633system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles 634system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for ReadReq accesses 635system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014605 # mshr miss rate for ReadReq accesses 636system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for demand accesses 637system.cpu0.icache.demand_mshr_miss_rate::total 0.014605 # mshr miss rate for demand accesses 638system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for overall accesses 639system.cpu0.icache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses 640system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average ReadReq mshr miss latency 641system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11851.384836 # average ReadReq mshr miss latency 642system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency 643system.cpu0.icache.demand_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency 644system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency 645system.cpu0.icache.overall_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency | 776system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425933 # number of ReadReq MSHR misses 777system.cpu0.icache.ReadReq_mshr_misses::total 425933 # number of ReadReq MSHR misses 778system.cpu0.icache.demand_mshr_misses::cpu0.inst 425933 # number of demand (read+write) MSHR misses 779system.cpu0.icache.demand_mshr_misses::total 425933 # number of demand (read+write) MSHR misses 780system.cpu0.icache.overall_mshr_misses::cpu0.inst 425933 # number of overall MSHR misses 781system.cpu0.icache.overall_mshr_misses::total 425933 # number of overall MSHR misses 782system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942640500 # number of ReadReq MSHR miss cycles 783system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942640500 # number of ReadReq MSHR miss cycles 784system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942640500 # number of demand (read+write) MSHR miss cycles 785system.cpu0.icache.demand_mshr_miss_latency::total 4942640500 # number of demand (read+write) MSHR miss cycles 786system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942640500 # number of overall MSHR miss cycles 787system.cpu0.icache.overall_mshr_miss_latency::total 4942640500 # number of overall MSHR miss cycles 788system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles 789system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles 790system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles 791system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles 792system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for ReadReq accesses 793system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014404 # mshr miss rate for ReadReq accesses 794system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for demand accesses 795system.cpu0.icache.demand_mshr_miss_rate::total 0.014404 # mshr miss rate for demand accesses 796system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for overall accesses 797system.cpu0.icache.overall_mshr_miss_rate::total 0.014404 # mshr miss rate for overall accesses 798system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average ReadReq mshr miss latency 799system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.267573 # average ReadReq mshr miss latency 800system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency 801system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency 802system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency 803system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency |
| 646system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 648system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 649system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 650system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 804system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 805system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 806system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 807system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 651system.cpu0.dcache.replacements 220249 # number of replacements 652system.cpu0.dcache.tagsinuse 456.517669 # Cycle average of tags in use 653system.cpu0.dcache.total_refs 8560161 # Total number of references to valid blocks. 654system.cpu0.dcache.sampled_refs 220619 # Sample count of references to valid blocks. 655system.cpu0.dcache.avg_refs 38.800652 # Average number of references to valid blocks. 656system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. 657system.cpu0.dcache.occ_blocks::cpu0.data 456.517669 # Average occupied blocks per requestor 658system.cpu0.dcache.occ_percent::cpu0.data 0.891636 # Average percentage of cache occupancy 659system.cpu0.dcache.occ_percent::total 0.891636 # Average percentage of cache occupancy 660system.cpu0.dcache.ReadReq_hits::cpu0.data 4452439 # number of ReadReq hits 661system.cpu0.dcache.ReadReq_hits::total 4452439 # number of ReadReq hits 662system.cpu0.dcache.WriteReq_hits::cpu0.data 3852551 # number of WriteReq hits 663system.cpu0.dcache.WriteReq_hits::total 3852551 # number of WriteReq hits 664system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117730 # number of LoadLockedReq hits 665system.cpu0.dcache.LoadLockedReq_hits::total 117730 # number of LoadLockedReq hits 666system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117854 # number of StoreCondReq hits 667system.cpu0.dcache.StoreCondReq_hits::total 117854 # number of StoreCondReq hits 668system.cpu0.dcache.demand_hits::cpu0.data 8304990 # number of demand (read+write) hits 669system.cpu0.dcache.demand_hits::total 8304990 # number of demand (read+write) hits 670system.cpu0.dcache.overall_hits::cpu0.data 8304990 # number of overall hits 671system.cpu0.dcache.overall_hits::total 8304990 # number of overall hits 672system.cpu0.dcache.ReadReq_misses::cpu0.data 146457 # number of ReadReq misses 673system.cpu0.dcache.ReadReq_misses::total 146457 # number of ReadReq misses 674system.cpu0.dcache.WriteReq_misses::cpu0.data 116961 # number of WriteReq misses 675system.cpu0.dcache.WriteReq_misses::total 116961 # number of WriteReq misses 676system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7881 # number of LoadLockedReq misses 677system.cpu0.dcache.LoadLockedReq_misses::total 7881 # number of LoadLockedReq misses 678system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7692 # number of StoreCondReq misses 679system.cpu0.dcache.StoreCondReq_misses::total 7692 # number of StoreCondReq misses 680system.cpu0.dcache.demand_misses::cpu0.data 263418 # number of demand (read+write) misses 681system.cpu0.dcache.demand_misses::total 263418 # number of demand (read+write) misses 682system.cpu0.dcache.overall_misses::cpu0.data 263418 # number of overall misses 683system.cpu0.dcache.overall_misses::total 263418 # number of overall misses 684system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991139500 # number of ReadReq miss cycles 685system.cpu0.dcache.ReadReq_miss_latency::total 1991139500 # number of ReadReq miss cycles 686system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199443500 # number of WriteReq miss cycles 687system.cpu0.dcache.WriteReq_miss_latency::total 4199443500 # number of WriteReq miss cycles 688system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70259000 # number of LoadLockedReq miss cycles 689system.cpu0.dcache.LoadLockedReq_miss_latency::total 70259000 # number of LoadLockedReq miss cycles 690system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66131000 # number of StoreCondReq miss cycles 691system.cpu0.dcache.StoreCondReq_miss_latency::total 66131000 # number of StoreCondReq miss cycles 692system.cpu0.dcache.demand_miss_latency::cpu0.data 6190583000 # number of demand (read+write) miss cycles 693system.cpu0.dcache.demand_miss_latency::total 6190583000 # number of demand (read+write) miss cycles 694system.cpu0.dcache.overall_miss_latency::cpu0.data 6190583000 # number of overall miss cycles 695system.cpu0.dcache.overall_miss_latency::total 6190583000 # number of overall miss cycles 696system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598896 # number of ReadReq accesses(hits+misses) 697system.cpu0.dcache.ReadReq_accesses::total 4598896 # number of ReadReq accesses(hits+misses) 698system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969512 # number of WriteReq accesses(hits+misses) 699system.cpu0.dcache.WriteReq_accesses::total 3969512 # number of WriteReq accesses(hits+misses) 700system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.demand_accesses::cpu0.data 8568408 # number of demand (read+write) accesses 705system.cpu0.dcache.demand_accesses::total 8568408 # number of demand (read+write) accesses 706system.cpu0.dcache.overall_accesses::cpu0.data 8568408 # number of overall (read+write) accesses 707system.cpu0.dcache.overall_accesses::total 8568408 # number of overall (read+write) accesses 708system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031846 # miss rate for ReadReq accesses 709system.cpu0.dcache.ReadReq_miss_rate::total 0.031846 # miss rate for ReadReq accesses 710system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029465 # miss rate for WriteReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::total 0.029465 # miss rate for WriteReq accesses 712system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062741 # miss rate for LoadLockedReq accesses 713system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062741 # miss rate for LoadLockedReq accesses 714system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061268 # miss rate for StoreCondReq accesses 715system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061268 # miss rate for StoreCondReq accesses 716system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses 717system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses 718system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses 719system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses 720system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13595.386359 # average ReadReq miss latency 721system.cpu0.dcache.ReadReq_avg_miss_latency::total 13595.386359 # average ReadReq miss latency 722system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35904.647703 # average WriteReq miss latency 723system.cpu0.dcache.WriteReq_avg_miss_latency::total 35904.647703 # average WriteReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8914.985408 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8914.985408 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8597.373895 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8597.373895 # average StoreCondReq miss latency 728system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency 729system.cpu0.dcache.demand_avg_miss_latency::total 23500.987024 # average overall miss latency 730system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency 731system.cpu0.dcache.overall_avg_miss_latency::total 23500.987024 # average overall miss latency | 809system.cpu0.dcache.replacements 330958 # number of replacements 810system.cpu0.dcache.tagsinuse 453.838533 # Cycle average of tags in use 811system.cpu0.dcache.total_refs 12275558 # Total number of references to valid blocks. 812system.cpu0.dcache.sampled_refs 331470 # Sample count of references to valid blocks. 813system.cpu0.dcache.avg_refs 37.033692 # Average number of references to valid blocks. 814system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. 815system.cpu0.dcache.occ_blocks::cpu0.data 453.838533 # Average occupied blocks per requestor 816system.cpu0.dcache.occ_percent::cpu0.data 0.886403 # Average percentage of cache occupancy 817system.cpu0.dcache.occ_percent::total 0.886403 # Average percentage of cache occupancy 818system.cpu0.dcache.ReadReq_hits::cpu0.data 6602415 # number of ReadReq hits 819system.cpu0.dcache.ReadReq_hits::total 6602415 # number of ReadReq hits 820system.cpu0.dcache.WriteReq_hits::cpu0.data 5353315 # number of WriteReq hits 821system.cpu0.dcache.WriteReq_hits::total 5353315 # number of WriteReq hits 822system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits 823system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits 824system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149687 # number of StoreCondReq hits 825system.cpu0.dcache.StoreCondReq_hits::total 149687 # number of StoreCondReq hits 826system.cpu0.dcache.demand_hits::cpu0.data 11955730 # number of demand (read+write) hits 827system.cpu0.dcache.demand_hits::total 11955730 # number of demand (read+write) hits 828system.cpu0.dcache.overall_hits::cpu0.data 11955730 # number of overall hits 829system.cpu0.dcache.overall_hits::total 11955730 # number of overall hits 830system.cpu0.dcache.ReadReq_misses::cpu0.data 228156 # number of ReadReq misses 831system.cpu0.dcache.ReadReq_misses::total 228156 # number of ReadReq misses 832system.cpu0.dcache.WriteReq_misses::cpu0.data 141693 # number of WriteReq misses 833system.cpu0.dcache.WriteReq_misses::total 141693 # number of WriteReq misses 834system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9329 # number of LoadLockedReq misses 835system.cpu0.dcache.LoadLockedReq_misses::total 9329 # number of LoadLockedReq misses 836system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7496 # number of StoreCondReq misses 837system.cpu0.dcache.StoreCondReq_misses::total 7496 # number of StoreCondReq misses 838system.cpu0.dcache.demand_misses::cpu0.data 369849 # number of demand (read+write) misses 839system.cpu0.dcache.demand_misses::total 369849 # number of demand (read+write) misses 840system.cpu0.dcache.overall_misses::cpu0.data 369849 # number of overall misses 841system.cpu0.dcache.overall_misses::total 369849 # number of overall misses 842system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3134416000 # number of ReadReq miss cycles 843system.cpu0.dcache.ReadReq_miss_latency::total 3134416000 # number of ReadReq miss cycles 844system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4131327000 # number of WriteReq miss cycles 845system.cpu0.dcache.WriteReq_miss_latency::total 4131327000 # number of WriteReq miss cycles 846system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88312000 # number of LoadLockedReq miss cycles 847system.cpu0.dcache.LoadLockedReq_miss_latency::total 88312000 # number of LoadLockedReq miss cycles 848system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44497000 # number of StoreCondReq miss cycles 849system.cpu0.dcache.StoreCondReq_miss_latency::total 44497000 # number of StoreCondReq miss cycles 850system.cpu0.dcache.demand_miss_latency::cpu0.data 7265743000 # number of demand (read+write) miss cycles 851system.cpu0.dcache.demand_miss_latency::total 7265743000 # number of demand (read+write) miss cycles 852system.cpu0.dcache.overall_miss_latency::cpu0.data 7265743000 # number of overall miss cycles 853system.cpu0.dcache.overall_miss_latency::total 7265743000 # number of overall miss cycles 854system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830571 # number of ReadReq accesses(hits+misses) 855system.cpu0.dcache.ReadReq_accesses::total 6830571 # number of ReadReq accesses(hits+misses) 856system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495008 # number of WriteReq accesses(hits+misses) 857system.cpu0.dcache.WriteReq_accesses::total 5495008 # number of WriteReq accesses(hits+misses) 858system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157268 # number of LoadLockedReq accesses(hits+misses) 859system.cpu0.dcache.LoadLockedReq_accesses::total 157268 # number of LoadLockedReq accesses(hits+misses) 860system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157183 # number of StoreCondReq accesses(hits+misses) 861system.cpu0.dcache.StoreCondReq_accesses::total 157183 # number of StoreCondReq accesses(hits+misses) 862system.cpu0.dcache.demand_accesses::cpu0.data 12325579 # number of demand (read+write) accesses 863system.cpu0.dcache.demand_accesses::total 12325579 # number of demand (read+write) accesses 864system.cpu0.dcache.overall_accesses::cpu0.data 12325579 # number of overall (read+write) accesses 865system.cpu0.dcache.overall_accesses::total 12325579 # number of overall (read+write) accesses 866system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033402 # miss rate for ReadReq accesses 867system.cpu0.dcache.ReadReq_miss_rate::total 0.033402 # miss rate for ReadReq accesses 868system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025786 # miss rate for WriteReq accesses 869system.cpu0.dcache.WriteReq_miss_rate::total 0.025786 # miss rate for WriteReq accesses 870system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059319 # miss rate for LoadLockedReq accesses 871system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059319 # miss rate for LoadLockedReq accesses 872system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047690 # miss rate for StoreCondReq accesses 873system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047690 # miss rate for StoreCondReq accesses 874system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030007 # miss rate for demand accesses 875system.cpu0.dcache.demand_miss_rate::total 0.030007 # miss rate for demand accesses 876system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030007 # miss rate for overall accesses 877system.cpu0.dcache.overall_miss_rate::total 0.030007 # miss rate for overall accesses 878system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13738.038886 # average ReadReq miss latency 879system.cpu0.dcache.ReadReq_avg_miss_latency::total 13738.038886 # average ReadReq miss latency 880system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29156.888484 # average WriteReq miss latency 881system.cpu0.dcache.WriteReq_avg_miss_latency::total 29156.888484 # average WriteReq miss latency 882system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9466.395112 # average LoadLockedReq miss latency 883system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9466.395112 # average LoadLockedReq miss latency 884system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5936.099253 # average StoreCondReq miss latency 885system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5936.099253 # average StoreCondReq miss latency 886system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency 887system.cpu0.dcache.demand_avg_miss_latency::total 19645.160593 # average overall miss latency 888system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency 889system.cpu0.dcache.overall_avg_miss_latency::total 19645.160593 # average overall miss latency |
| 732system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 733system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.cpu0.dcache.fast_writes 0 # number of fast writes performed 739system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 890system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 891system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 892system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 894system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 895system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 896system.cpu0.dcache.fast_writes 0 # number of fast writes performed 897system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 740system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks 741system.cpu0.dcache.writebacks::total 205058 # number of writebacks 742system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses 743system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses 744system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses 745system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses 746system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses 747system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses 748system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses 749system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses 750system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses 751system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses 752system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses 753system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses 754system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles 755system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles 756system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles 757system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles 758system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles 759system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles 760system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles 761system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles | 898system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks 899system.cpu0.dcache.writebacks::total 306622 # number of writebacks 900system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses 901system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses 902system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses 903system.cpu0.dcache.WriteReq_mshr_misses::total 141693 # number of WriteReq MSHR misses 904system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9329 # number of LoadLockedReq MSHR misses 905system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses 906system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7493 # number of StoreCondReq MSHR misses 907system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses 908system.cpu0.dcache.demand_mshr_misses::cpu0.data 369849 # number of demand (read+write) MSHR misses 909system.cpu0.dcache.demand_mshr_misses::total 369849 # number of demand (read+write) MSHR misses 910system.cpu0.dcache.overall_mshr_misses::cpu0.data 369849 # number of overall MSHR misses 911system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses 912system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678104000 # number of ReadReq MSHR miss cycles 913system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles 914system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3847941000 # number of WriteReq MSHR miss cycles 915system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles 916system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles 917system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles 918system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29513000 # number of StoreCondReq MSHR miss cycles 919system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles |
| 762system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 763system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles | 920system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 921system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles |
| 764system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles 768system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles 771system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles 774system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses 783system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses 784system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses 785system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency 790system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency 791system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency 792system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency 793system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency | 922system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6526045000 # number of demand (read+write) MSHR miss cycles 923system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles 924system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6526045000 # number of overall MSHR miss cycles 925system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles 926system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559793500 # number of ReadReq MSHR uncacheable cycles 927system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles 928system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128518500 # number of WriteReq MSHR uncacheable cycles 929system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128518500 # number of WriteReq MSHR uncacheable cycles 930system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688312000 # number of overall MSHR uncacheable cycles 931system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688312000 # number of overall MSHR uncacheable cycles 932system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses 933system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadReq accesses 934system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025786 # mshr miss rate for WriteReq accesses 935system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses 936system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses 937system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses 938system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047671 # mshr miss rate for StoreCondReq accesses 939system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047671 # mshr miss rate for StoreCondReq accesses 940system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for demand accesses 941system.cpu0.dcache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses 942system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses 943system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses 944system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency 945system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency 946system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency 947system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency 948system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7466.395112 # average LoadLockedReq mshr miss latency 949system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency 950system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3938.742827 # average StoreCondReq mshr miss latency 951system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency |
| 794system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 795system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 952system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 953system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 796system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency 797system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency 798system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency 799system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency | 954system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency 955system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency 956system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency 957system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency |
| 800system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 801system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 802system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 803system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 804system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 805system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 806system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 807system.cpu1.dtb.inst_hits 0 # ITB inst hits 808system.cpu1.dtb.inst_misses 0 # ITB inst misses | 958system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 959system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 960system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 961system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 962system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 963system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 964system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 965system.cpu1.dtb.inst_hits 0 # ITB inst hits 966system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 809system.cpu1.dtb.read_hits 10589201 # DTB read hits 810system.cpu1.dtb.read_misses 5231 # DTB read misses 811system.cpu1.dtb.write_hits 7383574 # DTB write hits 812system.cpu1.dtb.write_misses 1834 # DTB write misses | 967system.cpu1.dtb.read_hits 8308478 # DTB read hits 968system.cpu1.dtb.read_misses 3644 # DTB read misses 969system.cpu1.dtb.write_hits 5825596 # DTB write hits 970system.cpu1.dtb.write_misses 1434 # DTB write misses |
| 813system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 814system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 815system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 816system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 971system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 972system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 973system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 974system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 817system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB | 975system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB |
| 818system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 976system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 819system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch | 977system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch |
| 820system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 978system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 821system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions 822system.cpu1.dtb.read_accesses 10594432 # DTB read accesses 823system.cpu1.dtb.write_accesses 7385408 # DTB write accesses | 979system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 980system.cpu1.dtb.read_accesses 8312122 # DTB read accesses 981system.cpu1.dtb.write_accesses 5827030 # DTB write accesses |
| 824system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 982system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 825system.cpu1.dtb.hits 17972775 # DTB hits 826system.cpu1.dtb.misses 7065 # DTB misses 827system.cpu1.dtb.accesses 17979840 # DTB accesses 828system.cpu1.itb.inst_hits 43338256 # ITB inst hits 829system.cpu1.itb.inst_misses 3017 # ITB inst misses | 983system.cpu1.dtb.hits 14134074 # DTB hits 984system.cpu1.dtb.misses 5078 # DTB misses 985system.cpu1.dtb.accesses 14139152 # DTB accesses 986system.cpu1.itb.inst_hits 33188345 # ITB inst hits 987system.cpu1.itb.inst_misses 2171 # ITB inst misses |
| 830system.cpu1.itb.read_hits 0 # DTB read hits 831system.cpu1.itb.read_misses 0 # DTB read misses 832system.cpu1.itb.write_hits 0 # DTB write hits 833system.cpu1.itb.write_misses 0 # DTB write misses 834system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 835system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 836system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 837system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 988system.cpu1.itb.read_hits 0 # DTB read hits 989system.cpu1.itb.read_misses 0 # DTB read misses 990system.cpu1.itb.write_hits 0 # DTB write hits 991system.cpu1.itb.write_misses 0 # DTB write misses 992system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 993system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 994system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 995system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 838system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB | 996system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB |
| 839system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 840system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 841system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 842system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 843system.cpu1.itb.read_accesses 0 # DTB read accesses 844system.cpu1.itb.write_accesses 0 # DTB write accesses | 997system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 998system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 999system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1000system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1001system.cpu1.itb.read_accesses 0 # DTB read accesses 1002system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 845system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses 846system.cpu1.itb.hits 43338256 # DTB hits 847system.cpu1.itb.misses 3017 # DTB misses 848system.cpu1.itb.accesses 43341273 # DTB accesses 849system.cpu1.numCycles 2407212998 # number of cpu cycles simulated | 1003system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses 1004system.cpu1.itb.hits 33188345 # DTB hits 1005system.cpu1.itb.misses 2171 # DTB misses 1006system.cpu1.itb.accesses 33190516 # DTB accesses 1007system.cpu1.numCycles 2364324255 # number of cpu cycles simulated |
| 850system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 851system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1008system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1009system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 852system.cpu1.committedInsts 42407344 # Number of instructions committed 853system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed 854system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses 855system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses 856system.cpu1.num_func_calls 1334953 # number of times a function call or return occured 857system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls 858system.cpu1.num_int_insts 47734651 # number of integer instructions 859system.cpu1.num_fp_insts 5457 # number of float instructions 860system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read 861system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written 862system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read 863system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written 864system.cpu1.num_mem_refs 18681443 # number of memory refs 865system.cpu1.num_load_insts 10999206 # Number of load instructions 866system.cpu1.num_store_insts 7682237 # Number of store instructions 867system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles 868system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles 869system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles 870system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles | 1010system.cpu1.committedInsts 32577871 # Number of instructions committed 1011system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed 1012system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses 1013system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 1014system.cpu1.num_func_calls 961975 # number of times a function call or return occured 1015system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls 1016system.cpu1.num_int_insts 37307050 # number of integer instructions 1017system.cpu1.num_fp_insts 6793 # number of float instructions 1018system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read 1019system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written 1020system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1021system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1022system.cpu1.num_mem_refs 14671800 # number of memory refs 1023system.cpu1.num_load_insts 8630367 # Number of load instructions 1024system.cpu1.num_store_insts 6041433 # Number of store instructions 1025system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles 1026system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles 1027system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles 1028system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles |
| 871system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1029system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 872system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed 873system.cpu1.icache.replacements 582576 # number of replacements 874system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use 875system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. 876system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. 877system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. 878system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. 879system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor 880system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy 881system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy 882system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits 883system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits 884system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits 885system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits 886system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits 887system.cpu1.icache.overall_hits::total 42755164 # number of overall hits 888system.cpu1.icache.ReadReq_misses::cpu1.inst 583088 # number of ReadReq misses 889system.cpu1.icache.ReadReq_misses::total 583088 # number of ReadReq misses 890system.cpu1.icache.demand_misses::cpu1.inst 583088 # number of demand (read+write) misses 891system.cpu1.icache.demand_misses::total 583088 # number of demand (read+write) misses 892system.cpu1.icache.overall_misses::cpu1.inst 583088 # number of overall misses 893system.cpu1.icache.overall_misses::total 583088 # number of overall misses 894system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7852005500 # number of ReadReq miss cycles 895system.cpu1.icache.ReadReq_miss_latency::total 7852005500 # number of ReadReq miss cycles 896system.cpu1.icache.demand_miss_latency::cpu1.inst 7852005500 # number of demand (read+write) miss cycles 897system.cpu1.icache.demand_miss_latency::total 7852005500 # number of demand (read+write) miss cycles 898system.cpu1.icache.overall_miss_latency::cpu1.inst 7852005500 # number of overall miss cycles 899system.cpu1.icache.overall_miss_latency::total 7852005500 # number of overall miss cycles 900system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses) 901system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses) 902system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses 903system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses 904system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # number of overall (read+write) accesses 905system.cpu1.icache.overall_accesses::total 43338252 # number of overall (read+write) accesses 906system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013454 # miss rate for ReadReq accesses 907system.cpu1.icache.ReadReq_miss_rate::total 0.013454 # miss rate for ReadReq accesses 908system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013454 # miss rate for demand accesses 909system.cpu1.icache.demand_miss_rate::total 0.013454 # miss rate for demand accesses 910system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013454 # miss rate for overall accesses 911system.cpu1.icache.overall_miss_rate::total 0.013454 # miss rate for overall accesses 912system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13466.244375 # average ReadReq miss latency 913system.cpu1.icache.ReadReq_avg_miss_latency::total 13466.244375 # average ReadReq miss latency 914system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency 915system.cpu1.icache.demand_avg_miss_latency::total 13466.244375 # average overall miss latency 916system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency 917system.cpu1.icache.overall_avg_miss_latency::total 13466.244375 # average overall miss latency | 1030system.cpu1.kern.inst.quiesce 43884 # number of quiesce instructions executed 1031system.cpu1.icache.replacements 469230 # number of replacements 1032system.cpu1.icache.tagsinuse 478.783120 # Cycle average of tags in use 1033system.cpu1.icache.total_refs 32718599 # Total number of references to valid blocks. 1034system.cpu1.icache.sampled_refs 469742 # Sample count of references to valid blocks. 1035system.cpu1.icache.avg_refs 69.652275 # Average number of references to valid blocks. 1036system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit. 1037system.cpu1.icache.occ_blocks::cpu1.inst 478.783120 # Average occupied blocks per requestor 1038system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy 1039system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy 1040system.cpu1.icache.ReadReq_hits::cpu1.inst 32718599 # number of ReadReq hits 1041system.cpu1.icache.ReadReq_hits::total 32718599 # number of ReadReq hits 1042system.cpu1.icache.demand_hits::cpu1.inst 32718599 # number of demand (read+write) hits 1043system.cpu1.icache.demand_hits::total 32718599 # number of demand (read+write) hits 1044system.cpu1.icache.overall_hits::cpu1.inst 32718599 # number of overall hits 1045system.cpu1.icache.overall_hits::total 32718599 # number of overall hits 1046system.cpu1.icache.ReadReq_misses::cpu1.inst 469742 # number of ReadReq misses 1047system.cpu1.icache.ReadReq_misses::total 469742 # number of ReadReq misses 1048system.cpu1.icache.demand_misses::cpu1.inst 469742 # number of demand (read+write) misses 1049system.cpu1.icache.demand_misses::total 469742 # number of demand (read+write) misses 1050system.cpu1.icache.overall_misses::cpu1.inst 469742 # number of overall misses 1051system.cpu1.icache.overall_misses::total 469742 # number of overall misses 1052system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6348514000 # number of ReadReq miss cycles 1053system.cpu1.icache.ReadReq_miss_latency::total 6348514000 # number of ReadReq miss cycles 1054system.cpu1.icache.demand_miss_latency::cpu1.inst 6348514000 # number of demand (read+write) miss cycles 1055system.cpu1.icache.demand_miss_latency::total 6348514000 # number of demand (read+write) miss cycles 1056system.cpu1.icache.overall_miss_latency::cpu1.inst 6348514000 # number of overall miss cycles 1057system.cpu1.icache.overall_miss_latency::total 6348514000 # number of overall miss cycles 1058system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188341 # number of ReadReq accesses(hits+misses) 1059system.cpu1.icache.ReadReq_accesses::total 33188341 # number of ReadReq accesses(hits+misses) 1060system.cpu1.icache.demand_accesses::cpu1.inst 33188341 # number of demand (read+write) accesses 1061system.cpu1.icache.demand_accesses::total 33188341 # number of demand (read+write) accesses 1062system.cpu1.icache.overall_accesses::cpu1.inst 33188341 # number of overall (read+write) accesses 1063system.cpu1.icache.overall_accesses::total 33188341 # number of overall (read+write) accesses 1064system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014154 # miss rate for ReadReq accesses 1065system.cpu1.icache.ReadReq_miss_rate::total 0.014154 # miss rate for ReadReq accesses 1066system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014154 # miss rate for demand accesses 1067system.cpu1.icache.demand_miss_rate::total 0.014154 # miss rate for demand accesses 1068system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014154 # miss rate for overall accesses 1069system.cpu1.icache.overall_miss_rate::total 0.014154 # miss rate for overall accesses 1070system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.895411 # average ReadReq miss latency 1071system.cpu1.icache.ReadReq_avg_miss_latency::total 13514.895411 # average ReadReq miss latency 1072system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency 1073system.cpu1.icache.demand_avg_miss_latency::total 13514.895411 # average overall miss latency 1074system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency 1075system.cpu1.icache.overall_avg_miss_latency::total 13514.895411 # average overall miss latency |
| 918system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu1.icache.fast_writes 0 # number of fast writes performed 925system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1076system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1077system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1078system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1079system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1080system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1081system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1082system.cpu1.icache.fast_writes 0 # number of fast writes performed 1083system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 926system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583088 # number of ReadReq MSHR misses 927system.cpu1.icache.ReadReq_mshr_misses::total 583088 # number of ReadReq MSHR misses 928system.cpu1.icache.demand_mshr_misses::cpu1.inst 583088 # number of demand (read+write) MSHR misses 929system.cpu1.icache.demand_mshr_misses::total 583088 # number of demand (read+write) MSHR misses 930system.cpu1.icache.overall_mshr_misses::cpu1.inst 583088 # number of overall MSHR misses 931system.cpu1.icache.overall_mshr_misses::total 583088 # number of overall MSHR misses 932system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6685829500 # number of ReadReq MSHR miss cycles 933system.cpu1.icache.ReadReq_mshr_miss_latency::total 6685829500 # number of ReadReq MSHR miss cycles 934system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6685829500 # number of demand (read+write) MSHR miss cycles 935system.cpu1.icache.demand_mshr_miss_latency::total 6685829500 # number of demand (read+write) MSHR miss cycles 936system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6685829500 # number of overall MSHR miss cycles 937system.cpu1.icache.overall_mshr_miss_latency::total 6685829500 # number of overall MSHR miss cycles 938system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles 939system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles 940system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles 941system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles 942system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for ReadReq accesses 943system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013454 # mshr miss rate for ReadReq accesses 944system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for demand accesses 945system.cpu1.icache.demand_mshr_miss_rate::total 0.013454 # mshr miss rate for demand accesses 946system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for overall accesses 947system.cpu1.icache.overall_mshr_miss_rate::total 0.013454 # mshr miss rate for overall accesses 948system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average ReadReq mshr miss latency 949system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11466.244375 # average ReadReq mshr miss latency 950system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency 951system.cpu1.icache.demand_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency 952system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency 953system.cpu1.icache.overall_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency | 1084system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469742 # number of ReadReq MSHR misses 1085system.cpu1.icache.ReadReq_mshr_misses::total 469742 # number of ReadReq MSHR misses 1086system.cpu1.icache.demand_mshr_misses::cpu1.inst 469742 # number of demand (read+write) MSHR misses 1087system.cpu1.icache.demand_mshr_misses::total 469742 # number of demand (read+write) MSHR misses 1088system.cpu1.icache.overall_mshr_misses::cpu1.inst 469742 # number of overall MSHR misses 1089system.cpu1.icache.overall_mshr_misses::total 469742 # number of overall MSHR misses 1090system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5409030000 # number of ReadReq MSHR miss cycles 1091system.cpu1.icache.ReadReq_mshr_miss_latency::total 5409030000 # number of ReadReq MSHR miss cycles 1092system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5409030000 # number of demand (read+write) MSHR miss cycles 1093system.cpu1.icache.demand_mshr_miss_latency::total 5409030000 # number of demand (read+write) MSHR miss cycles 1094system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5409030000 # number of overall MSHR miss cycles 1095system.cpu1.icache.overall_mshr_miss_latency::total 5409030000 # number of overall MSHR miss cycles 1096system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles 1097system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles 1098system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles 1099system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles 1100system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for ReadReq accesses 1101system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014154 # mshr miss rate for ReadReq accesses 1102system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for demand accesses 1103system.cpu1.icache.demand_mshr_miss_rate::total 0.014154 # mshr miss rate for demand accesses 1104system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for overall accesses 1105system.cpu1.icache.overall_mshr_miss_rate::total 0.014154 # mshr miss rate for overall accesses 1106system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average ReadReq mshr miss latency 1107system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11514.895411 # average ReadReq mshr miss latency 1108system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency 1109system.cpu1.icache.demand_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency 1110system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency 1111system.cpu1.icache.overall_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency |
| 954system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 955system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 956system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 957system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 958system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1112system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1113system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1114system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1115system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1116system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 959system.cpu1.dcache.replacements 401285 # number of replacements 960system.cpu1.dcache.tagsinuse 473.299929 # Cycle average of tags in use 961system.cpu1.dcache.total_refs 15679399 # Total number of references to valid blocks. 962system.cpu1.dcache.sampled_refs 401797 # Sample count of references to valid blocks. 963system.cpu1.dcache.avg_refs 39.023186 # Average number of references to valid blocks. 964system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. 965system.cpu1.dcache.occ_blocks::cpu1.data 473.299929 # Average occupied blocks per requestor 966system.cpu1.dcache.occ_percent::cpu1.data 0.924414 # Average percentage of cache occupancy 967system.cpu1.dcache.occ_percent::total 0.924414 # Average percentage of cache occupancy 968system.cpu1.dcache.ReadReq_hits::cpu1.data 9100620 # number of ReadReq hits 969system.cpu1.dcache.ReadReq_hits::total 9100620 # number of ReadReq hits 970system.cpu1.dcache.WriteReq_hits::cpu1.data 6322619 # number of WriteReq hits 971system.cpu1.dcache.WriteReq_hits::total 6322619 # number of WriteReq hits 972system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111839 # number of LoadLockedReq hits 973system.cpu1.dcache.LoadLockedReq_hits::total 111839 # number of LoadLockedReq hits 974system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114463 # number of StoreCondReq hits 975system.cpu1.dcache.StoreCondReq_hits::total 114463 # number of StoreCondReq hits 976system.cpu1.dcache.demand_hits::cpu1.data 15423239 # number of demand (read+write) hits 977system.cpu1.dcache.demand_hits::total 15423239 # number of demand (read+write) hits 978system.cpu1.dcache.overall_hits::cpu1.data 15423239 # number of overall hits 979system.cpu1.dcache.overall_hits::total 15423239 # number of overall hits 980system.cpu1.dcache.ReadReq_misses::cpu1.data 253127 # number of ReadReq misses 981system.cpu1.dcache.ReadReq_misses::total 253127 # number of ReadReq misses 982system.cpu1.dcache.WriteReq_misses::cpu1.data 178055 # number of WriteReq misses 983system.cpu1.dcache.WriteReq_misses::total 178055 # number of WriteReq misses 984system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13099 # number of LoadLockedReq misses 985system.cpu1.dcache.LoadLockedReq_misses::total 13099 # number of LoadLockedReq misses 986system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10399 # number of StoreCondReq misses 987system.cpu1.dcache.StoreCondReq_misses::total 10399 # number of StoreCondReq misses 988system.cpu1.dcache.demand_misses::cpu1.data 431182 # number of demand (read+write) misses 989system.cpu1.dcache.demand_misses::total 431182 # number of demand (read+write) misses 990system.cpu1.dcache.overall_misses::cpu1.data 431182 # number of overall misses 991system.cpu1.dcache.overall_misses::total 431182 # number of overall misses 992system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277248500 # number of ReadReq miss cycles 993system.cpu1.dcache.ReadReq_miss_latency::total 3277248500 # number of ReadReq miss cycles 994system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5648876500 # number of WriteReq miss cycles 995system.cpu1.dcache.WriteReq_miss_latency::total 5648876500 # number of WriteReq miss cycles 996system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115793500 # number of LoadLockedReq miss cycles 997system.cpu1.dcache.LoadLockedReq_miss_latency::total 115793500 # number of LoadLockedReq miss cycles 998system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63008000 # number of StoreCondReq miss cycles 999system.cpu1.dcache.StoreCondReq_miss_latency::total 63008000 # number of StoreCondReq miss cycles 1000system.cpu1.dcache.demand_miss_latency::cpu1.data 8926125000 # number of demand (read+write) miss cycles 1001system.cpu1.dcache.demand_miss_latency::total 8926125000 # number of demand (read+write) miss cycles 1002system.cpu1.dcache.overall_miss_latency::cpu1.data 8926125000 # number of overall miss cycles 1003system.cpu1.dcache.overall_miss_latency::total 8926125000 # number of overall miss cycles 1004system.cpu1.dcache.ReadReq_accesses::cpu1.data 9353747 # number of ReadReq accesses(hits+misses) 1005system.cpu1.dcache.ReadReq_accesses::total 9353747 # number of ReadReq accesses(hits+misses) 1006system.cpu1.dcache.WriteReq_accesses::cpu1.data 6500674 # number of WriteReq accesses(hits+misses) 1007system.cpu1.dcache.WriteReq_accesses::total 6500674 # number of WriteReq accesses(hits+misses) 1008system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124938 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu1.dcache.LoadLockedReq_accesses::total 124938 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124862 # number of StoreCondReq accesses(hits+misses) 1011system.cpu1.dcache.StoreCondReq_accesses::total 124862 # number of StoreCondReq accesses(hits+misses) 1012system.cpu1.dcache.demand_accesses::cpu1.data 15854421 # number of demand (read+write) accesses 1013system.cpu1.dcache.demand_accesses::total 15854421 # number of demand (read+write) accesses 1014system.cpu1.dcache.overall_accesses::cpu1.data 15854421 # number of overall (read+write) accesses 1015system.cpu1.dcache.overall_accesses::total 15854421 # number of overall (read+write) accesses 1016system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027062 # miss rate for ReadReq accesses 1017system.cpu1.dcache.ReadReq_miss_rate::total 0.027062 # miss rate for ReadReq accesses 1018system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027390 # miss rate for WriteReq accesses 1019system.cpu1.dcache.WriteReq_miss_rate::total 0.027390 # miss rate for WriteReq accesses 1020system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104844 # miss rate for LoadLockedReq accesses 1021system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104844 # miss rate for LoadLockedReq accesses 1022system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083284 # miss rate for StoreCondReq accesses 1023system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083284 # miss rate for StoreCondReq accesses 1024system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027196 # miss rate for demand accesses 1025system.cpu1.dcache.demand_miss_rate::total 0.027196 # miss rate for demand accesses 1026system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027196 # miss rate for overall accesses 1027system.cpu1.dcache.overall_miss_rate::total 0.027196 # miss rate for overall accesses 1028system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.052270 # average ReadReq miss latency 1029system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.052270 # average ReadReq miss latency 1030system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31725.458426 # average WriteReq miss latency 1031system.cpu1.dcache.WriteReq_avg_miss_latency::total 31725.458426 # average WriteReq miss latency 1032system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8839.873273 # average LoadLockedReq miss latency 1033system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8839.873273 # average LoadLockedReq miss latency 1034system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6059.044139 # average StoreCondReq miss latency 1035system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6059.044139 # average StoreCondReq miss latency 1036system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency 1037system.cpu1.dcache.demand_avg_miss_latency::total 20701.525110 # average overall miss latency 1038system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency 1039system.cpu1.dcache.overall_avg_miss_latency::total 20701.525110 # average overall miss latency | 1117system.cpu1.dcache.replacements 291659 # number of replacements 1118system.cpu1.dcache.tagsinuse 472.058793 # Cycle average of tags in use 1119system.cpu1.dcache.total_refs 11957529 # Total number of references to valid blocks. 1120system.cpu1.dcache.sampled_refs 292006 # Sample count of references to valid blocks. 1121system.cpu1.dcache.avg_refs 40.949600 # Average number of references to valid blocks. 1122system.cpu1.dcache.warmup_cycle 83625331000 # Cycle when the warmup percentage was hit. 1123system.cpu1.dcache.occ_blocks::cpu1.data 472.058793 # Average occupied blocks per requestor 1124system.cpu1.dcache.occ_percent::cpu1.data 0.921990 # Average percentage of cache occupancy 1125system.cpu1.dcache.occ_percent::total 0.921990 # Average percentage of cache occupancy 1126system.cpu1.dcache.ReadReq_hits::cpu1.data 6944275 # number of ReadReq hits 1127system.cpu1.dcache.ReadReq_hits::total 6944275 # number of ReadReq hits 1128system.cpu1.dcache.WriteReq_hits::cpu1.data 4825543 # number of WriteReq hits 1129system.cpu1.dcache.WriteReq_hits::total 4825543 # number of WriteReq hits 1130system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81753 # number of LoadLockedReq hits 1131system.cpu1.dcache.LoadLockedReq_hits::total 81753 # number of LoadLockedReq hits 1132system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82700 # number of StoreCondReq hits 1133system.cpu1.dcache.StoreCondReq_hits::total 82700 # number of StoreCondReq hits 1134system.cpu1.dcache.demand_hits::cpu1.data 11769818 # number of demand (read+write) hits 1135system.cpu1.dcache.demand_hits::total 11769818 # number of demand (read+write) hits 1136system.cpu1.dcache.overall_hits::cpu1.data 11769818 # number of overall hits 1137system.cpu1.dcache.overall_hits::total 11769818 # number of overall hits 1138system.cpu1.dcache.ReadReq_misses::cpu1.data 170271 # number of ReadReq misses 1139system.cpu1.dcache.ReadReq_misses::total 170271 # number of ReadReq misses 1140system.cpu1.dcache.WriteReq_misses::cpu1.data 149767 # number of WriteReq misses 1141system.cpu1.dcache.WriteReq_misses::total 149767 # number of WriteReq misses 1142system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11060 # number of LoadLockedReq misses 1143system.cpu1.dcache.LoadLockedReq_misses::total 11060 # number of LoadLockedReq misses 1144system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10038 # number of StoreCondReq misses 1145system.cpu1.dcache.StoreCondReq_misses::total 10038 # number of StoreCondReq misses 1146system.cpu1.dcache.demand_misses::cpu1.data 320038 # number of demand (read+write) misses 1147system.cpu1.dcache.demand_misses::total 320038 # number of demand (read+write) misses 1148system.cpu1.dcache.overall_misses::cpu1.data 320038 # number of overall misses 1149system.cpu1.dcache.overall_misses::total 320038 # number of overall misses 1150system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2152137500 # number of ReadReq miss cycles 1151system.cpu1.dcache.ReadReq_miss_latency::total 2152137500 # number of ReadReq miss cycles 1152system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4507881000 # number of WriteReq miss cycles 1153system.cpu1.dcache.WriteReq_miss_latency::total 4507881000 # number of WriteReq miss cycles 1154system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91883000 # number of LoadLockedReq miss cycles 1155system.cpu1.dcache.LoadLockedReq_miss_latency::total 91883000 # number of LoadLockedReq miss cycles 1156system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51759500 # number of StoreCondReq miss cycles 1157system.cpu1.dcache.StoreCondReq_miss_latency::total 51759500 # number of StoreCondReq miss cycles 1158system.cpu1.dcache.demand_miss_latency::cpu1.data 6660018500 # number of demand (read+write) miss cycles 1159system.cpu1.dcache.demand_miss_latency::total 6660018500 # number of demand (read+write) miss cycles 1160system.cpu1.dcache.overall_miss_latency::cpu1.data 6660018500 # number of overall miss cycles 1161system.cpu1.dcache.overall_miss_latency::total 6660018500 # number of overall miss cycles 1162system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114546 # number of ReadReq accesses(hits+misses) 1163system.cpu1.dcache.ReadReq_accesses::total 7114546 # number of ReadReq accesses(hits+misses) 1164system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975310 # number of WriteReq accesses(hits+misses) 1165system.cpu1.dcache.WriteReq_accesses::total 4975310 # number of WriteReq accesses(hits+misses) 1166system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92813 # number of LoadLockedReq accesses(hits+misses) 1167system.cpu1.dcache.LoadLockedReq_accesses::total 92813 # number of LoadLockedReq accesses(hits+misses) 1168system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92738 # number of StoreCondReq accesses(hits+misses) 1169system.cpu1.dcache.StoreCondReq_accesses::total 92738 # number of StoreCondReq accesses(hits+misses) 1170system.cpu1.dcache.demand_accesses::cpu1.data 12089856 # number of demand (read+write) accesses 1171system.cpu1.dcache.demand_accesses::total 12089856 # number of demand (read+write) accesses 1172system.cpu1.dcache.overall_accesses::cpu1.data 12089856 # number of overall (read+write) accesses 1173system.cpu1.dcache.overall_accesses::total 12089856 # number of overall (read+write) accesses 1174system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023933 # miss rate for ReadReq accesses 1175system.cpu1.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses 1176system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030102 # miss rate for WriteReq accesses 1177system.cpu1.dcache.WriteReq_miss_rate::total 0.030102 # miss rate for WriteReq accesses 1178system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119164 # miss rate for LoadLockedReq accesses 1179system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119164 # miss rate for LoadLockedReq accesses 1180system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108240 # miss rate for StoreCondReq accesses 1181system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108240 # miss rate for StoreCondReq accesses 1182system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026472 # miss rate for demand accesses 1183system.cpu1.dcache.demand_miss_rate::total 0.026472 # miss rate for demand accesses 1184system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026472 # miss rate for overall accesses 1185system.cpu1.dcache.overall_miss_rate::total 0.026472 # miss rate for overall accesses 1186system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12639.483529 # average ReadReq miss latency 1187system.cpu1.dcache.ReadReq_avg_miss_latency::total 12639.483529 # average ReadReq miss latency 1188system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30099.294237 # average WriteReq miss latency 1189system.cpu1.dcache.WriteReq_avg_miss_latency::total 30099.294237 # average WriteReq miss latency 1190system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8307.685353 # average LoadLockedReq miss latency 1191system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8307.685353 # average LoadLockedReq miss latency 1192system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5156.355848 # average StoreCondReq miss latency 1193system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5156.355848 # average StoreCondReq miss latency 1194system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency 1195system.cpu1.dcache.demand_avg_miss_latency::total 20810.086615 # average overall miss latency 1196system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency 1197system.cpu1.dcache.overall_avg_miss_latency::total 20810.086615 # average overall miss latency |
| 1040system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1047system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1198system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1199system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1200system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1201system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1202system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1203system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1204system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1205system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1048system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks 1049system.cpu1.dcache.writebacks::total 366504 # number of writebacks 1050system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses 1051system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses 1052system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses 1053system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses 1054system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses 1055system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses 1056system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses 1057system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses 1058system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses 1059system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses 1060system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses 1061system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses 1062system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles 1063system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles 1064system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles 1065system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles 1066system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles 1067system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles 1068system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles 1069system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles 1070system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles 1071system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1072system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles 1073system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles 1074system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles 1075system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles 1076system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles 1077system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles 1078system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles 1079system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles 1080system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles 1081system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles 1082system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses 1083system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses 1084system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses 1085system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses 1086system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses 1087system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses 1088system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses 1089system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses 1090system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses 1091system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses 1092system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses 1093system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses 1094system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency 1095system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency 1096system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency 1097system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency 1098system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency 1099system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency 1100system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency 1101system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency | 1206system.cpu1.dcache.writebacks::writebacks 265110 # number of writebacks 1207system.cpu1.dcache.writebacks::total 265110 # number of writebacks 1208system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170271 # number of ReadReq MSHR misses 1209system.cpu1.dcache.ReadReq_mshr_misses::total 170271 # number of ReadReq MSHR misses 1210system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149767 # number of WriteReq MSHR misses 1211system.cpu1.dcache.WriteReq_mshr_misses::total 149767 # number of WriteReq MSHR misses 1212system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11060 # number of LoadLockedReq MSHR misses 1213system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11060 # number of LoadLockedReq MSHR misses 1214system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10034 # number of StoreCondReq MSHR misses 1215system.cpu1.dcache.StoreCondReq_mshr_misses::total 10034 # number of StoreCondReq MSHR misses 1216system.cpu1.dcache.demand_mshr_misses::cpu1.data 320038 # number of demand (read+write) MSHR misses 1217system.cpu1.dcache.demand_mshr_misses::total 320038 # number of demand (read+write) MSHR misses 1218system.cpu1.dcache.overall_mshr_misses::cpu1.data 320038 # number of overall MSHR misses 1219system.cpu1.dcache.overall_mshr_misses::total 320038 # number of overall MSHR misses 1220system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811595500 # number of ReadReq MSHR miss cycles 1221system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811595500 # number of ReadReq MSHR miss cycles 1222system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4208347000 # number of WriteReq MSHR miss cycles 1223system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4208347000 # number of WriteReq MSHR miss cycles 1224system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69763000 # number of LoadLockedReq MSHR miss cycles 1225system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69763000 # number of LoadLockedReq MSHR miss cycles 1226system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31693500 # number of StoreCondReq MSHR miss cycles 1227system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31693500 # number of StoreCondReq MSHR miss cycles 1228system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1229system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1230system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6019942500 # number of demand (read+write) MSHR miss cycles 1231system.cpu1.dcache.demand_mshr_miss_latency::total 6019942500 # number of demand (read+write) MSHR miss cycles 1232system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6019942500 # number of overall MSHR miss cycles 1233system.cpu1.dcache.overall_mshr_miss_latency::total 6019942500 # number of overall MSHR miss cycles 1234system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168625975500 # number of ReadReq MSHR uncacheable cycles 1235system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168625975500 # number of ReadReq MSHR uncacheable cycles 1236system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666930000 # number of WriteReq MSHR uncacheable cycles 1237system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666930000 # number of WriteReq MSHR uncacheable cycles 1238system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186292905500 # number of overall MSHR uncacheable cycles 1239system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186292905500 # number of overall MSHR uncacheable cycles 1240system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023933 # mshr miss rate for ReadReq accesses 1241system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023933 # mshr miss rate for ReadReq accesses 1242system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030102 # mshr miss rate for WriteReq accesses 1243system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030102 # mshr miss rate for WriteReq accesses 1244system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119164 # mshr miss rate for LoadLockedReq accesses 1245system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119164 # mshr miss rate for LoadLockedReq accesses 1246system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108197 # mshr miss rate for StoreCondReq accesses 1247system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108197 # mshr miss rate for StoreCondReq accesses 1248system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for demand accesses 1249system.cpu1.dcache.demand_mshr_miss_rate::total 0.026472 # mshr miss rate for demand accesses 1250system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for overall accesses 1251system.cpu1.dcache.overall_mshr_miss_rate::total 0.026472 # mshr miss rate for overall accesses 1252system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10639.483529 # average ReadReq mshr miss latency 1253system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10639.483529 # average ReadReq mshr miss latency 1254system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28099.294237 # average WriteReq mshr miss latency 1255system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28099.294237 # average WriteReq mshr miss latency 1256system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6307.685353 # average LoadLockedReq mshr miss latency 1257system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6307.685353 # average LoadLockedReq mshr miss latency 1258system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3158.610724 # average StoreCondReq mshr miss latency 1259system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3158.610724 # average StoreCondReq mshr miss latency |
| 1102system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1103system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1260system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1261system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1104system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency 1105system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency 1106system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency 1107system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency | 1262system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency 1263system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency 1264system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency 1265system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency |
| 1108system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1109system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1110system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1111system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1112system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1113system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1114system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1115system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1121system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1125system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.iocache.fast_writes 0 # number of fast writes performed 1128system.iocache.cache_copies 0 # number of cache copies performed | 1266system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1267system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1268system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1269system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1270system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1271system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1272system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1273system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1279system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1280system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1281system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1282system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1283system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1284system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1285system.iocache.fast_writes 0 # number of fast writes performed 1286system.iocache.cache_copies 0 # number of cache copies performed |
| 1129system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles 1130system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles 1131system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles 1132system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles | 1287system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446709885400 # number of ReadReq MSHR uncacheable cycles 1288system.iocache.ReadReq_mshr_uncacheable_latency::total 446709885400 # number of ReadReq MSHR uncacheable cycles 1289system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446709885400 # number of overall MSHR uncacheable cycles 1290system.iocache.overall_mshr_uncacheable_latency::total 446709885400 # number of overall MSHR uncacheable cycles |
| 1133system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1134system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1135system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1136system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1137system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1138 1139---------- End Simulation Statistics ---------- | 1291system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1292system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1293system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1294system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1295system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1296 1297---------- End Simulation Statistics ---------- |