| stats.txt (9265:8fe936e937bd) | stats.txt (9289:a31a1243a3ed) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.207291 # Number of seconds simulated 4sim_ticks 1207290627000 # Number of ticks simulated 5final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.203695 # Number of seconds simulated 4sim_ticks 1203694548000 # Number of ticks simulated 5final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 648322 # Simulator instruction rate (inst/s) 8host_op_rate 826248 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12731770448 # Simulator tick rate (ticks/s) 10host_mem_usage 380152 # Number of bytes of host memory used 11host_seconds 94.83 # Real time elapsed on the host 12sim_insts 61477134 # Number of instructions simulated 13sim_ops 78349023 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory 23system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 30system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 610810 # Simulator instruction rate (inst/s) 8host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11963163223 # Simulator tick rate (ticks/s) 10host_mem_usage 383784 # Number of bytes of host memory used 11host_seconds 100.62 # Real time elapsed on the host 12sim_insts 61457649 # Number of instructions simulated 13sim_ops 78322983 # Number of ops (including micro ops) simulated |
| 73system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 74system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 76system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 79system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 80system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 82system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 86system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 87system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) 88system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 89system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 90system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) | 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) |
| 91system.l2c.replacements 69267 # number of replacements 92system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use 93system.l2c.total_refs 1645693 # Total number of references to valid blocks. 94system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. 95system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. | 32system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory 40system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory 41system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory 42system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory 44system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory 45system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 47system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory 48system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 49system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory 58system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 59system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 60system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) 74system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) 75system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 70187 # number of replacements 88system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use 89system.l2c.total_refs 1643789 # Total number of references to valid blocks. 90system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. 91system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. |
| 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 97system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor 102system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor 104system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor 106system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy | 93system.l2c.occ_blocks::writebacks 40454.040636 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.003088 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 3394.914064 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 2735.381228 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 2.669984 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 3118.851455 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 3522.782116 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.617280 # Average percentage of cache occupancy |
| 107system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 102system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 109system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy 114system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy 115system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy 116system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits 121system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits 122system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits 123system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits 124system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits 125system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits 126system.l2c.Writeback_hits::total 572580 # number of Writeback hits 127system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits 128system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits 129system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits 130system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits 131system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits 132system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits 133system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits 134system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits 135system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits 136system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits 141system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits 142system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits 143system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits 144system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits 145system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits 146system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits 147system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits 148system.l2c.overall_hits::cpu0.data 262598 # number of overall hits 149system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits 150system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits 151system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits 152system.l2c.overall_hits::cpu1.data 197108 # number of overall hits 153system.l2c.overall_hits::total 1325620 # number of overall hits | 104system.l2c.occ_percent::cpu0.inst 0.051802 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.047590 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.053753 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.812205 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 278283 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 124654 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 5208 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 576279 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 223386 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1213325 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 571443 # number of Writeback hits 120system.l2c.Writeback_hits::total 571443 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 888 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1880 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 95 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 286 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 39230 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 70245 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 278283 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 163884 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 576279 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 293631 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1322800 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 278283 # number of overall hits 142system.l2c.overall_hits::cpu0.data 163884 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 576279 # number of overall hits 146system.l2c.overall_hits::cpu1.data 293631 # number of overall hits 147system.l2c.overall_hits::total 1322800 # number of overall hits |
| 154system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses | 148system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses |
| 155system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 156system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses 157system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses 158system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 159system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 160system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses 161system.l2c.ReadReq_misses::cpu1.data 3639 # number of ReadReq misses 162system.l2c.ReadReq_misses::total 22308 # number of ReadReq misses 163system.l2c.UpgradeReq_misses::cpu0.data 4704 # number of UpgradeReq misses 164system.l2c.UpgradeReq_misses::cpu1.data 3584 # number of UpgradeReq misses 165system.l2c.UpgradeReq_misses::total 8288 # number of UpgradeReq misses 166system.l2c.SCUpgradeReq_misses::cpu0.data 569 # number of SCUpgradeReq misses 167system.l2c.SCUpgradeReq_misses::cpu1.data 485 # number of SCUpgradeReq misses 168system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses 169system.l2c.ReadExReq_misses::cpu0.data 67193 # number of ReadExReq misses 170system.l2c.ReadExReq_misses::cpu1.data 72340 # number of ReadExReq misses 171system.l2c.ReadExReq_misses::total 139533 # number of ReadExReq misses | 149system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 150system.l2c.ReadReq_misses::cpu0.inst 5124 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 6001 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu1.inst 5692 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 5607 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 4012 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 4909 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 8921 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 61449 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 140288 # number of ReadExReq misses |
| 172system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses | 165system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses |
| 173system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 174system.l2c.demand_misses::cpu0.inst 5744 # number of demand (read+write) misses 175system.l2c.demand_misses::cpu0.data 75067 # number of demand (read+write) misses 176system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 177system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu1.inst 5043 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu1.data 75979 # number of demand (read+write) misses 180system.l2c.demand_misses::total 161841 # number of demand (read+write) misses | 166system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu0.inst 5124 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu1.inst 5692 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 84446 # number of demand (read+write) misses 172system.l2c.demand_misses::total 162719 # number of demand (read+write) misses |
| 181system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses | 173system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses |
| 182system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 183system.l2c.overall_misses::cpu0.inst 5744 # number of overall misses 184system.l2c.overall_misses::cpu0.data 75067 # number of overall misses 185system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses 188system.l2c.overall_misses::cpu1.data 75979 # number of overall misses 189system.l2c.overall_misses::total 161841 # number of overall misses | 174system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 175system.l2c.overall_misses::cpu0.inst 5124 # number of overall misses 176system.l2c.overall_misses::cpu0.data 67450 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 5692 # number of overall misses 179system.l2c.overall_misses::cpu1.data 84446 # number of overall misses 180system.l2c.overall_misses::total 162719 # number of overall misses |
| 190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles | 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles |
| 191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles 192system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles 194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles 195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles 196system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles 197system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles 198system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles 199system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles 200system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles 201system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles 202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles 203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles 204system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles 205system.l2c.ReadExReq_miss_latency::cpu0.data 3494513965 # number of ReadExReq miss cycles 206system.l2c.ReadExReq_miss_latency::cpu1.data 3764719994 # number of ReadExReq miss cycles 207system.l2c.ReadExReq_miss_latency::total 7259233959 # number of ReadExReq miss cycles | 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 268094000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 313174000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 298650000 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 293295000 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1173581500 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 15964999 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 31408500 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 47373499 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1462500 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6173000 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 7635500 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3221682991 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 4131389996 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7353072987 # number of ReadExReq miss cycles |
| 208system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles | 198system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles |
| 209system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles 210system.l2c.demand_miss_latency::cpu0.inst 298939500 # number of demand (read+write) miss cycles 211system.l2c.demand_miss_latency::cpu0.data 3904184465 # number of demand (read+write) miss cycles 212system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles 213system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles 214system.l2c.demand_miss_latency::cpu1.inst 263172000 # number of demand (read+write) miss cycles 215system.l2c.demand_miss_latency::cpu1.data 3954214494 # number of demand (read+write) miss cycles 216system.l2c.demand_miss_latency::total 8420927459 # number of demand (read+write) miss cycles | 199system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu0.inst 268094000 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3534856991 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 298650000 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 4424684996 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8526654487 # number of demand (read+write) miss cycles |
| 217system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles | 206system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles |
| 218system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles 219system.l2c.overall_miss_latency::cpu0.inst 298939500 # number of overall miss cycles 220system.l2c.overall_miss_latency::cpu0.data 3904184465 # number of overall miss cycles 221system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles 222system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles 223system.l2c.overall_miss_latency::cpu1.inst 263172000 # number of overall miss cycles 224system.l2c.overall_miss_latency::cpu1.data 3954214494 # number of overall miss cycles 225system.l2c.overall_miss_latency::total 8420927459 # number of overall miss cycles 226system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) 227system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) 228system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) 229system.l2c.ReadReq_accesses::cpu0.data 213749 # number of ReadReq accesses(hits+misses) 230system.l2c.ReadReq_accesses::cpu1.dtb.walker 5727 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu1.itb.walker 1960 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu1.inst 455013 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu1.data 147730 # number of ReadReq accesses(hits+misses) 234system.l2c.ReadReq_accesses::total 1238188 # number of ReadReq accesses(hits+misses) 235system.l2c.Writeback_accesses::writebacks 572580 # number of Writeback accesses(hits+misses) 236system.l2c.Writeback_accesses::total 572580 # number of Writeback accesses(hits+misses) 237system.l2c.UpgradeReq_accesses::cpu0.data 5834 # number of UpgradeReq accesses(hits+misses) 238system.l2c.UpgradeReq_accesses::cpu1.data 4156 # number of UpgradeReq accesses(hits+misses) 239system.l2c.UpgradeReq_accesses::total 9990 # number of UpgradeReq accesses(hits+misses) 240system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses) 241system.l2c.SCUpgradeReq_accesses::cpu1.data 589 # number of SCUpgradeReq accesses(hits+misses) 242system.l2c.SCUpgradeReq_accesses::total 1370 # number of SCUpgradeReq accesses(hits+misses) 243system.l2c.ReadExReq_accesses::cpu0.data 123916 # number of ReadExReq accesses(hits+misses) 244system.l2c.ReadExReq_accesses::cpu1.data 125357 # number of ReadExReq accesses(hits+misses) 245system.l2c.ReadExReq_accesses::total 249273 # number of ReadExReq accesses(hits+misses) 246system.l2c.demand_accesses::cpu0.dtb.walker 4115 # number of demand (read+write) accesses 247system.l2c.demand_accesses::cpu0.itb.walker 1843 # number of demand (read+write) accesses 248system.l2c.demand_accesses::cpu0.inst 408051 # number of demand (read+write) accesses 249system.l2c.demand_accesses::cpu0.data 337665 # number of demand (read+write) accesses 250system.l2c.demand_accesses::cpu1.dtb.walker 5727 # number of demand (read+write) accesses 251system.l2c.demand_accesses::cpu1.itb.walker 1960 # number of demand (read+write) accesses 252system.l2c.demand_accesses::cpu1.inst 455013 # number of demand (read+write) accesses 253system.l2c.demand_accesses::cpu1.data 273087 # number of demand (read+write) accesses 254system.l2c.demand_accesses::total 1487461 # number of demand (read+write) accesses 255system.l2c.overall_accesses::cpu0.dtb.walker 4115 # number of overall (read+write) accesses 256system.l2c.overall_accesses::cpu0.itb.walker 1843 # number of overall (read+write) accesses 257system.l2c.overall_accesses::cpu0.inst 408051 # number of overall (read+write) accesses 258system.l2c.overall_accesses::cpu0.data 337665 # number of overall (read+write) accesses 259system.l2c.overall_accesses::cpu1.dtb.walker 5727 # number of overall (read+write) accesses 260system.l2c.overall_accesses::cpu1.itb.walker 1960 # number of overall (read+write) accesses 261system.l2c.overall_accesses::cpu1.inst 455013 # number of overall (read+write) accesses 262system.l2c.overall_accesses::cpu1.data 273087 # number of overall (read+write) accesses 263system.l2c.overall_accesses::total 1487461 # number of overall (read+write) accesses 264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for ReadReq accesses 265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001085 # miss rate for ReadReq accesses 266system.l2c.ReadReq_miss_rate::cpu0.inst 0.014077 # miss rate for ReadReq accesses 267system.l2c.ReadReq_miss_rate::cpu0.data 0.036838 # miss rate for ReadReq accesses 268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000510 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu1.inst 0.011083 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu1.data 0.024633 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806308 # miss rate for UpgradeReq accesses 274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862368 # miss rate for UpgradeReq accesses 275system.l2c.UpgradeReq_miss_rate::total 0.829630 # miss rate for UpgradeReq accesses 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728553 # miss rate for SCUpgradeReq accesses 277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823430 # miss rate for SCUpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::total 0.769343 # miss rate for SCUpgradeReq accesses 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.542246 # miss rate for ReadExReq accesses 280system.l2c.ReadExReq_miss_rate::cpu1.data 0.577072 # miss rate for ReadExReq accesses 281system.l2c.ReadExReq_miss_rate::total 0.559760 # miss rate for ReadExReq accesses 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for demand accesses 283system.l2c.demand_miss_rate::cpu0.itb.walker 0.001085 # miss rate for demand accesses 284system.l2c.demand_miss_rate::cpu0.inst 0.014077 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.data 0.222312 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu1.itb.walker 0.000510 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.011083 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.278223 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.108804 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.001085 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.014077 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.222312 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000510 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.011083 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.278223 # miss rate for overall accesses 299system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses | 207system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu0.inst 268094000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3534856991 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 160000 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 298650000 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 4424684996 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8526654487 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 283407 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 130655 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 5211 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 581971 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 228993 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1235756 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 571443 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 571443 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 5004 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 5797 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 10801 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 846 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 483 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1329 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 100679 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 149084 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 249763 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 283407 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 231334 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 5211 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 581971 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 378077 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1485519 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 283407 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 231334 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 5211 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 581971 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 378077 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1485519 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.018080 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.045930 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.009781 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.024485 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.018152 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801759 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.846817 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.825942 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.774232 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.803313 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.784801 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.610346 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.528823 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.561684 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.018080 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.291570 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.009781 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.223357 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.109537 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.018080 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.291570 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.009781 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.223357 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.109537 # miss rate for overall accesses |
| 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency | 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency |
| 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557 # average ReadReq miss latency 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405 # average ReadReq miss latency 308system.l2c.ReadReq_avg_miss_latency::total 52075.197239 # average ReadReq miss latency 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6388.818027 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7629.185268 # average UpgradeReq miss latency 311system.l2c.UpgradeReq_avg_miss_latency::total 6925.193050 # average UpgradeReq miss latency 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12445.360825 # average SCUpgradeReq miss latency 314system.l2c.SCUpgradeReq_avg_miss_latency::total 9229.601518 # average SCUpgradeReq miss latency 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.113315 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52042.023694 # average ReadExReq miss latency 317system.l2c.ReadExReq_avg_miss_latency::total 52025.212380 # average ReadExReq miss latency | 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52321.233411 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52186.968839 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52468.376669 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52308.721241 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52319.624627 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3979.311815 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6398.146262 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 5310.335052 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2232.824427 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15909.793814 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 7320.709492 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52428.566632 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52402.871624 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 52414.126561 # average ReadExReq miss latency |
| 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency | 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency |
| 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency 320system.l2c.demand_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency 324system.l2c.demand_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 52032.102242 # average overall miss latency | 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52401.099361 # average overall miss latency |
| 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency | 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency |
| 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency 329system.l2c.overall_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency 333system.l2c.overall_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 52032.102242 # average overall miss latency | 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 52401.099361 # average overall miss latency |
| 336system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 337system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 338system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 339system.l2c.blocked::no_targets 0 # number of cycles access was blocked 340system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 341system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 342system.l2c.fast_writes 0 # number of fast writes performed 343system.l2c.cache_copies 0 # number of cache copies performed | 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed |
| 344system.l2c.writebacks::writebacks 64155 # number of writebacks 345system.l2c.writebacks::total 64155 # number of writebacks | 326system.l2c.writebacks::writebacks 65060 # number of writebacks 327system.l2c.writebacks::total 65060 # number of writebacks |
| 346system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 347system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 348system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 349system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 350system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 351system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 352system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses | 328system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 330system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 331system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 332system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 333system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 334system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses |
| 353system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 354system.l2c.ReadReq_mshr_misses::cpu0.inst 5743 # number of ReadReq MSHR misses 355system.l2c.ReadReq_mshr_misses::cpu0.data 7874 # number of ReadReq MSHR misses 356system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses 357system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 358system.l2c.ReadReq_mshr_misses::cpu1.inst 5043 # number of ReadReq MSHR misses 359system.l2c.ReadReq_mshr_misses::cpu1.data 3639 # number of ReadReq MSHR misses 360system.l2c.ReadReq_mshr_misses::total 22307 # number of ReadReq MSHR misses 361system.l2c.UpgradeReq_mshr_misses::cpu0.data 4704 # number of UpgradeReq MSHR misses 362system.l2c.UpgradeReq_mshr_misses::cpu1.data 3584 # number of UpgradeReq MSHR misses 363system.l2c.UpgradeReq_mshr_misses::total 8288 # number of UpgradeReq MSHR misses 364system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 569 # number of SCUpgradeReq MSHR misses 365system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 485 # number of SCUpgradeReq MSHR misses 366system.l2c.SCUpgradeReq_mshr_misses::total 1054 # number of SCUpgradeReq MSHR misses 367system.l2c.ReadExReq_mshr_misses::cpu0.data 67193 # number of ReadExReq MSHR misses 368system.l2c.ReadExReq_mshr_misses::cpu1.data 72340 # number of ReadExReq MSHR misses 369system.l2c.ReadExReq_mshr_misses::total 139533 # number of ReadExReq MSHR misses | 335system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses 336system.l2c.ReadReq_mshr_misses::cpu0.inst 5123 # number of ReadReq MSHR misses 337system.l2c.ReadReq_mshr_misses::cpu0.data 6001 # number of ReadReq MSHR misses 338system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses 339system.l2c.ReadReq_mshr_misses::cpu1.inst 5692 # number of ReadReq MSHR misses 340system.l2c.ReadReq_mshr_misses::cpu1.data 5607 # number of ReadReq MSHR misses 341system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses 342system.l2c.UpgradeReq_mshr_misses::cpu0.data 4012 # number of UpgradeReq MSHR misses 343system.l2c.UpgradeReq_mshr_misses::cpu1.data 4909 # number of UpgradeReq MSHR misses 344system.l2c.UpgradeReq_mshr_misses::total 8921 # number of UpgradeReq MSHR misses 345system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses 346system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses 347system.l2c.SCUpgradeReq_mshr_misses::total 1043 # number of SCUpgradeReq MSHR misses 348system.l2c.ReadExReq_mshr_misses::cpu0.data 61449 # number of ReadExReq MSHR misses 349system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses 350system.l2c.ReadExReq_mshr_misses::total 140288 # number of ReadExReq MSHR misses |
| 370system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses | 351system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses |
| 371system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 372system.l2c.demand_mshr_misses::cpu0.inst 5743 # number of demand (read+write) MSHR misses 373system.l2c.demand_mshr_misses::cpu0.data 75067 # number of demand (read+write) MSHR misses 374system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses 375system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 376system.l2c.demand_mshr_misses::cpu1.inst 5043 # number of demand (read+write) MSHR misses 377system.l2c.demand_mshr_misses::cpu1.data 75979 # number of demand (read+write) MSHR misses 378system.l2c.demand_mshr_misses::total 161840 # number of demand (read+write) MSHR misses | 352system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 353system.l2c.demand_mshr_misses::cpu0.inst 5123 # number of demand (read+write) MSHR misses 354system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses 355system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses 356system.l2c.demand_mshr_misses::cpu1.inst 5692 # number of demand (read+write) MSHR misses 357system.l2c.demand_mshr_misses::cpu1.data 84446 # number of demand (read+write) MSHR misses 358system.l2c.demand_mshr_misses::total 162718 # number of demand (read+write) MSHR misses |
| 379system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses | 359system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses |
| 380system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 381system.l2c.overall_mshr_misses::cpu0.inst 5743 # number of overall MSHR misses 382system.l2c.overall_mshr_misses::cpu0.data 75067 # number of overall MSHR misses 383system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses 384system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 385system.l2c.overall_mshr_misses::cpu1.inst 5043 # number of overall MSHR misses 386system.l2c.overall_mshr_misses::cpu1.data 75979 # number of overall MSHR misses 387system.l2c.overall_mshr_misses::total 161840 # number of overall MSHR misses | 360system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 361system.l2c.overall_mshr_misses::cpu0.inst 5123 # number of overall MSHR misses 362system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses 363system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses 364system.l2c.overall_mshr_misses::cpu1.inst 5692 # number of overall MSHR misses 365system.l2c.overall_mshr_misses::cpu1.data 84446 # number of overall MSHR misses 366system.l2c.overall_mshr_misses::total 162718 # number of overall MSHR misses |
| 388system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles | 367system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles |
| 389system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles 390system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229995000 # number of ReadReq MSHR miss cycles 391system.l2c.ReadReq_mshr_miss_latency::cpu0.data 315180000 # number of ReadReq MSHR miss cycles 392system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles 393system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles 394system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202652000 # number of ReadReq MSHR miss cycles 395system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145824000 # number of ReadReq MSHR miss cycles 396system.l2c.ReadReq_mshr_miss_latency::total 893971000 # number of ReadReq MSHR miss cycles 397system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188550000 # number of UpgradeReq MSHR miss cycles 398system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143713000 # number of UpgradeReq MSHR miss cycles 399system.l2c.UpgradeReq_mshr_miss_latency::total 332263000 # number of UpgradeReq MSHR miss cycles 400system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22778000 # number of SCUpgradeReq MSHR miss cycles 401system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19436000 # number of SCUpgradeReq MSHR miss cycles 402system.l2c.SCUpgradeReq_mshr_miss_latency::total 42214000 # number of SCUpgradeReq MSHR miss cycles 403system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2688153000 # number of ReadExReq MSHR miss cycles 404system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2896625000 # number of ReadExReq MSHR miss cycles 405system.l2c.ReadExReq_mshr_miss_latency::total 5584778000 # number of ReadExReq MSHR miss cycles | 368system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles 369system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204994000 # number of ReadReq MSHR miss cycles 370system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240097000 # number of ReadReq MSHR miss cycles 371system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 124000 # number of ReadReq MSHR miss cycles 372system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 228616000 # number of ReadReq MSHR miss cycles 373system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224783500 # number of ReadReq MSHR miss cycles 374system.l2c.ReadReq_mshr_miss_latency::total 898774500 # number of ReadReq MSHR miss cycles 375system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160670998 # number of UpgradeReq MSHR miss cycles 376system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196506499 # number of UpgradeReq MSHR miss cycles 377system.l2c.UpgradeReq_mshr_miss_latency::total 357177497 # number of UpgradeReq MSHR miss cycles 378system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26201999 # number of SCUpgradeReq MSHR miss cycles 379system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15527999 # number of SCUpgradeReq MSHR miss cycles 380system.l2c.SCUpgradeReq_mshr_miss_latency::total 41729998 # number of SCUpgradeReq MSHR miss cycles 381system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458624491 # number of ReadExReq MSHR miss cycles 382system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165174496 # number of ReadExReq MSHR miss cycles 383system.l2c.ReadExReq_mshr_miss_latency::total 5623798987 # number of ReadExReq MSHR miss cycles |
| 406system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles | 384system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles |
| 407system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 408system.l2c.demand_mshr_miss_latency::cpu0.inst 229995000 # number of demand (read+write) MSHR miss cycles 409system.l2c.demand_mshr_miss_latency::cpu0.data 3003333000 # number of demand (read+write) MSHR miss cycles 410system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles 411system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles 412system.l2c.demand_mshr_miss_latency::cpu1.inst 202652000 # number of demand (read+write) MSHR miss cycles 413system.l2c.demand_mshr_miss_latency::cpu1.data 3042449000 # number of demand (read+write) MSHR miss cycles 414system.l2c.demand_mshr_miss_latency::total 6478749000 # number of demand (read+write) MSHR miss cycles | 385system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles 386system.l2c.demand_mshr_miss_latency::cpu0.inst 204994000 # number of demand (read+write) MSHR miss cycles 387system.l2c.demand_mshr_miss_latency::cpu0.data 2698721491 # number of demand (read+write) MSHR miss cycles 388system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 124000 # number of demand (read+write) MSHR miss cycles 389system.l2c.demand_mshr_miss_latency::cpu1.inst 228616000 # number of demand (read+write) MSHR miss cycles 390system.l2c.demand_mshr_miss_latency::cpu1.data 3389957996 # number of demand (read+write) MSHR miss cycles 391system.l2c.demand_mshr_miss_latency::total 6522573487 # number of demand (read+write) MSHR miss cycles |
| 415system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles | 392system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles |
| 416system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles 417system.l2c.overall_mshr_miss_latency::cpu0.inst 229995000 # number of overall MSHR miss cycles 418system.l2c.overall_mshr_miss_latency::cpu0.data 3003333000 # number of overall MSHR miss cycles 419system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles 420system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles 421system.l2c.overall_mshr_miss_latency::cpu1.inst 202652000 # number of overall MSHR miss cycles 422system.l2c.overall_mshr_miss_latency::cpu1.data 3042449000 # number of overall MSHR miss cycles 423system.l2c.overall_mshr_miss_latency::total 6478749000 # number of overall MSHR miss cycles | 393system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles 394system.l2c.overall_mshr_miss_latency::cpu0.inst 204994000 # number of overall MSHR miss cycles 395system.l2c.overall_mshr_miss_latency::cpu0.data 2698721491 # number of overall MSHR miss cycles 396system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 124000 # number of overall MSHR miss cycles 397system.l2c.overall_mshr_miss_latency::cpu1.inst 228616000 # number of overall MSHR miss cycles 398system.l2c.overall_mshr_miss_latency::cpu1.data 3389957996 # number of overall MSHR miss cycles 399system.l2c.overall_mshr_miss_latency::total 6522573487 # number of overall MSHR miss cycles |
| 424system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles | 400system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles |
| 425system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448669498 # number of ReadReq MSHR uncacheable cycles 426system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles 427system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365762499 # number of ReadReq MSHR uncacheable cycles 428system.l2c.ReadReq_mshr_uncacheable_latency::total 167083912997 # number of ReadReq MSHR uncacheable cycles 429system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles 430system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843801500 # number of WriteReq MSHR uncacheable cycles 431system.l2c.WriteReq_mshr_uncacheable_latency::total 31972104500 # number of WriteReq MSHR uncacheable cycles | 401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136775500 # number of ReadReq MSHR uncacheable cycles 402system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles 403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155704815500 # number of ReadReq MSHR uncacheable cycles 404system.l2c.ReadReq_mshr_uncacheable_latency::total 167111072500 # number of ReadReq MSHR uncacheable cycles 405system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070730500 # number of WriteReq MSHR uncacheable cycles 406system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30910255000 # number of WriteReq MSHR uncacheable cycles 407system.l2c.WriteReq_mshr_uncacheable_latency::total 31980985500 # number of WriteReq MSHR uncacheable cycles |
| 432system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles | 408system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles |
| 433system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576972498 # number of overall MSHR uncacheable cycles 434system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles 435system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles 437system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses 438system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses 443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses 444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses 445system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses 446system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses 447system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses 448system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses 449system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses 450system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses 451system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses 452system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses 453system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses 454system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses 455system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses 456system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses 457system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses 458system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses 459system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses 460system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses 461system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses 463system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses 464system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses 465system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses 471system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses 472system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses | 409system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207506000 # number of overall MSHR uncacheable cycles 410system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles 411system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186615070500 # number of overall MSHR uncacheable cycles 412system.l2c.overall_mshr_uncacheable_latency::total 199092058000 # number of overall MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045930 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for ReadReq accesses 418system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for ReadReq accesses 419system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024485 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::total 0.018151 # mshr miss rate for ReadReq accesses 421system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801759 # mshr miss rate for UpgradeReq accesses 422system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846817 # mshr miss rate for UpgradeReq accesses 423system.l2c.UpgradeReq_mshr_miss_rate::total 0.825942 # mshr miss rate for UpgradeReq accesses 424system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.774232 # mshr miss rate for SCUpgradeReq accesses 425system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.803313 # mshr miss rate for SCUpgradeReq accesses 426system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784801 # mshr miss rate for SCUpgradeReq accesses 427system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610346 # mshr miss rate for ReadExReq accesses 428system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528823 # mshr miss rate for ReadExReq accesses 429system.l2c.ReadExReq_mshr_miss_rate::total 0.561684 # mshr miss rate for ReadExReq accesses 430system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses 431system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses 432system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for demand accesses 433system.l2c.demand_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for demand accesses 434system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for demand accesses 435system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for demand accesses 436system.l2c.demand_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for demand accesses 437system.l2c.demand_mshr_miss_rate::total 0.109536 # mshr miss rate for demand accesses 438system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses 439system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses 440system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for overall accesses 441system.l2c.overall_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for overall accesses 442system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for overall accesses 443system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for overall accesses 444system.l2c.overall_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for overall accesses 445system.l2c.overall_mshr_miss_rate::total 0.109536 # mshr miss rate for overall accesses |
| 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency | 446system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 447system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency |
| 475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency 476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency | 448system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency 449system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency 450system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency 451system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency 452system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency 453system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency 454system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency 455system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency 457system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency 458system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency 459system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency 460system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency 462system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency |
| 491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 463system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 464system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency 495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency 498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency 499system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency | 465system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency 466system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency |
| 500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 471system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 472system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency 503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency 504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency 507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency 508system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency | 473system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency 474system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency 475system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency |
| 509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 523system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 524system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 525system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 526system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 527system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 528system.cf0.dma_write_txs 0 # Number of DMA write transactions. 529system.cpu0.dtb.inst_hits 0 # ITB inst hits 530system.cpu0.dtb.inst_misses 0 # ITB inst misses | 479system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 483system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 486system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 493system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 494system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 495system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 496system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 497system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 498system.cf0.dma_write_txs 0 # Number of DMA write transactions. 499system.cpu0.dtb.inst_hits 0 # ITB inst hits 500system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 531system.cpu0.dtb.read_hits 7076084 # DTB read hits 532system.cpu0.dtb.read_misses 3743 # DTB read misses 533system.cpu0.dtb.write_hits 5660386 # DTB write hits 534system.cpu0.dtb.write_misses 804 # DTB write misses | 501system.cpu0.dtb.read_hits 4800541 # DTB read hits 502system.cpu0.dtb.read_misses 2116 # DTB read misses 503system.cpu0.dtb.write_hits 4101169 # DTB write hits 504system.cpu0.dtb.write_misses 405 # DTB write misses |
| 535system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 536system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 537system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 538system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 505system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 506system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 507system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 508system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 539system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB | 509system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB |
| 540system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 510system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 541system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch | 511system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch |
| 542system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 512system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 543system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 544system.cpu0.dtb.read_accesses 7079827 # DTB read accesses 545system.cpu0.dtb.write_accesses 5661190 # DTB write accesses | 513system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions 514system.cpu0.dtb.read_accesses 4802657 # DTB read accesses 515system.cpu0.dtb.write_accesses 4101574 # DTB write accesses |
| 546system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 516system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 547system.cpu0.dtb.hits 12736470 # DTB hits 548system.cpu0.dtb.misses 4547 # DTB misses 549system.cpu0.dtb.accesses 12741017 # DTB accesses 550system.cpu0.itb.inst_hits 29574655 # ITB inst hits 551system.cpu0.itb.inst_misses 2205 # ITB inst misses | 517system.cpu0.dtb.hits 8901710 # DTB hits 518system.cpu0.dtb.misses 2521 # DTB misses 519system.cpu0.dtb.accesses 8904231 # DTB accesses 520system.cpu0.itb.inst_hits 19425295 # ITB inst hits 521system.cpu0.itb.inst_misses 1350 # ITB inst misses |
| 552system.cpu0.itb.read_hits 0 # DTB read hits 553system.cpu0.itb.read_misses 0 # DTB read misses 554system.cpu0.itb.write_hits 0 # DTB write hits 555system.cpu0.itb.write_misses 0 # DTB write misses 556system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 558system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 559system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 522system.cpu0.itb.read_hits 0 # DTB read hits 523system.cpu0.itb.read_misses 0 # DTB read misses 524system.cpu0.itb.write_hits 0 # DTB write hits 525system.cpu0.itb.write_misses 0 # DTB write misses 526system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 527system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 528system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 529system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 560system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB | 530system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB |
| 561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 564system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 565system.cpu0.itb.read_accesses 0 # DTB read accesses 566system.cpu0.itb.write_accesses 0 # DTB write accesses | 531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.itb.read_accesses 0 # DTB read accesses 536system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 567system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses 568system.cpu0.itb.hits 29574655 # DTB hits 569system.cpu0.itb.misses 2205 # DTB misses 570system.cpu0.itb.accesses 29576860 # DTB accesses 571system.cpu0.numCycles 2414581254 # number of cpu cycles simulated | 537system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses 538system.cpu0.itb.hits 19425295 # DTB hits 539system.cpu0.itb.misses 1350 # DTB misses 540system.cpu0.itb.accesses 19426645 # DTB accesses 541system.cpu0.numCycles 2405961611 # number of cpu cycles simulated |
| 572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 574system.cpu0.committedInsts 28876799 # Number of instructions committed 575system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed 576system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses 577system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 578system.cpu0.num_func_calls 1241592 # number of times a function call or return occured 579system.cpu0.num_conditional_control_insts 4373527 # number of instructions that are conditional controls 580system.cpu0.num_int_insts 33114839 # number of integer instructions 581system.cpu0.num_fp_insts 3860 # number of float instructions 582system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read 583system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written 584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 586system.cpu0.num_mem_refs 13404188 # number of memory refs 587system.cpu0.num_load_insts 7413537 # Number of load instructions 588system.cpu0.num_store_insts 5990651 # Number of store instructions 589system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles 590system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles 591system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles 592system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles | 544system.cpu0.committedInsts 19048182 # Number of instructions committed 545system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 22684080 # Number of integer alu accesses 547system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses 548system.cpu0.num_func_calls 868675 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 2620305 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 22684080 # number of integer instructions 551system.cpu0.num_fp_insts 4364 # number of float instructions 552system.cpu0.num_int_register_reads 128950966 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 23731370 # number of times the integer registers were written 554system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written 556system.cpu0.num_mem_refs 9388163 # number of memory refs 557system.cpu0.num_load_insts 5047859 # Number of load instructions 558system.cpu0.num_store_insts 4340304 # Number of store instructions 559system.cpu0.num_idle_cycles 2301502404.823749 # Number of idle cycles 560system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles 561system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles |
| 593system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 594system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed 595system.cpu0.icache.replacements 408135 # number of replacements 596system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use 597system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. 598system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. 599system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. 600system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. 601system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor 602system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy 603system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy 604system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits 605system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits 606system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits 607system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits 608system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits 609system.cpu0.icache.overall_hits::total 29165991 # number of overall hits 610system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses 611system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses 612system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses 613system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses 614system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses 615system.cpu0.icache.overall_misses::total 408647 # number of overall misses 616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles 617system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles 618system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles 619system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles 620system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles 621system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles 622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) 623system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) 624system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses 625system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses 626system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses 627system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses 628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses 629system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses 630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses 631system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses 632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses 633system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses 634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency 635system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency 636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency 637system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency 638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency 639system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency | 564system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed 565system.cpu0.icache.replacements 283184 # number of replacements 566system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use 567system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. 568system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. 569system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. 570system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor 572system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy 573system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy 574system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits 579system.cpu0.icache.overall_hits::total 19141582 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses 585system.cpu0.icache.overall_misses::total 283696 # number of overall misses 586system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # number of ReadReq miss cycles 587system.cpu0.icache.ReadReq_miss_latency::total 3929923500 # number of ReadReq miss cycles 588system.cpu0.icache.demand_miss_latency::cpu0.inst 3929923500 # number of demand (read+write) miss cycles 589system.cpu0.icache.demand_miss_latency::total 3929923500 # number of demand (read+write) miss cycles 590system.cpu0.icache.overall_miss_latency::cpu0.inst 3929923500 # number of overall miss cycles 591system.cpu0.icache.overall_miss_latency::total 3929923500 # number of overall miss cycles 592system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425278 # number of ReadReq accesses(hits+misses) 593system.cpu0.icache.ReadReq_accesses::total 19425278 # number of ReadReq accesses(hits+misses) 594system.cpu0.icache.demand_accesses::cpu0.inst 19425278 # number of demand (read+write) accesses 595system.cpu0.icache.demand_accesses::total 19425278 # number of demand (read+write) accesses 596system.cpu0.icache.overall_accesses::cpu0.inst 19425278 # number of overall (read+write) accesses 597system.cpu0.icache.overall_accesses::total 19425278 # number of overall (read+write) accesses 598system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses 599system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses 600system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses 601system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses 602system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses 603system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses 604system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency 605system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency 606system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency 607system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency 608system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency 609system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency |
| 640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu0.icache.fast_writes 0 # number of fast writes performed 647system.cpu0.icache.cache_copies 0 # number of cache copies performed | 610system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu0.icache.fast_writes 0 # number of fast writes performed 617system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 648system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses 649system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses 650system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses 651system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses 652system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses 653system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses 654system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles 655system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles 656system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles 657system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles 658system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles 659system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles 660system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 661system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 662system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 663system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles 664system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses 665system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses 666system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses 667system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses 668system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses 669system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses 670system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency 671system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency 672system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency 673system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency 674system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency 675system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency | 618system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283696 # number of ReadReq MSHR misses 619system.cpu0.icache.ReadReq_mshr_misses::total 283696 # number of ReadReq MSHR misses 620system.cpu0.icache.demand_mshr_misses::cpu0.inst 283696 # number of demand (read+write) MSHR misses 621system.cpu0.icache.demand_mshr_misses::total 283696 # number of demand (read+write) MSHR misses 622system.cpu0.icache.overall_mshr_misses::cpu0.inst 283696 # number of overall MSHR misses 623system.cpu0.icache.overall_mshr_misses::total 283696 # number of overall MSHR misses 624system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362531500 # number of ReadReq MSHR miss cycles 625system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362531500 # number of ReadReq MSHR miss cycles 626system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362531500 # number of demand (read+write) MSHR miss cycles 627system.cpu0.icache.demand_mshr_miss_latency::total 3362531500 # number of demand (read+write) MSHR miss cycles 628system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362531500 # number of overall MSHR miss cycles 629system.cpu0.icache.overall_mshr_miss_latency::total 3362531500 # number of overall MSHR miss cycles 630system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles 631system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles 632system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles 633system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles 634system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for ReadReq accesses 635system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014604 # mshr miss rate for ReadReq accesses 636system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for demand accesses 637system.cpu0.icache.demand_mshr_miss_rate::total 0.014604 # mshr miss rate for demand accesses 638system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for overall accesses 639system.cpu0.icache.overall_mshr_miss_rate::total 0.014604 # mshr miss rate for overall accesses 640system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average ReadReq mshr miss latency 641system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11852.586924 # average ReadReq mshr miss latency 642system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency 643system.cpu0.icache.demand_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency 644system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency 645system.cpu0.icache.overall_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency |
| 676system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 677system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 678system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 679system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 680system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 646system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 648system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 649system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 650system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 681system.cpu0.dcache.replacements 330734 # number of replacements 682system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use 683system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. 684system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. 685system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. 686system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. 687system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor 688system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy 689system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy 690system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits 691system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits 692system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits 693system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits 694system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits 695system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits 696system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits 697system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits 698system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits 699system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits 700system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits 701system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits 702system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses 703system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses 704system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses 705system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses 706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses 707system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses 708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses 709system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses 710system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses 711system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses 712system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses 713system.cpu0.dcache.overall_misses::total 369775 # number of overall misses 714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles 715system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles 716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles 717system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles 718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles 719system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles 720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles 721system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles 722system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles 723system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles 724system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles 725system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles 726system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) 727system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) 728system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) 729system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) 730system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) 731system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) 732system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) 733system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) 734system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses 735system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses 736system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses 737system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses 738system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses 739system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses 740system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses 741system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses 742system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses 743system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses 744system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses 745system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses 746system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses 747system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses 748system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses 749system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses 750system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency 751system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency 752system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency 753system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency 754system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency 755system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency 756system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency 757system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency 758system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency 759system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency 760system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency 761system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency | 651system.cpu0.dcache.replacements 220187 # number of replacements 652system.cpu0.dcache.tagsinuse 456.524851 # Cycle average of tags in use 653system.cpu0.dcache.total_refs 8560144 # Total number of references to valid blocks. 654system.cpu0.dcache.sampled_refs 220557 # Sample count of references to valid blocks. 655system.cpu0.dcache.avg_refs 38.811482 # Average number of references to valid blocks. 656system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. 657system.cpu0.dcache.occ_blocks::cpu0.data 456.524851 # Average occupied blocks per requestor 658system.cpu0.dcache.occ_percent::cpu0.data 0.891650 # Average percentage of cache occupancy 659system.cpu0.dcache.occ_percent::total 0.891650 # Average percentage of cache occupancy 660system.cpu0.dcache.ReadReq_hits::cpu0.data 4452407 # number of ReadReq hits 661system.cpu0.dcache.ReadReq_hits::total 4452407 # number of ReadReq hits 662system.cpu0.dcache.WriteReq_hits::cpu0.data 3852535 # number of WriteReq hits 663system.cpu0.dcache.WriteReq_hits::total 3852535 # number of WriteReq hits 664system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117731 # number of LoadLockedReq hits 665system.cpu0.dcache.LoadLockedReq_hits::total 117731 # number of LoadLockedReq hits 666system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117849 # number of StoreCondReq hits 667system.cpu0.dcache.StoreCondReq_hits::total 117849 # number of StoreCondReq hits 668system.cpu0.dcache.demand_hits::cpu0.data 8304942 # number of demand (read+write) hits 669system.cpu0.dcache.demand_hits::total 8304942 # number of demand (read+write) hits 670system.cpu0.dcache.overall_hits::cpu0.data 8304942 # number of overall hits 671system.cpu0.dcache.overall_hits::total 8304942 # number of overall hits 672system.cpu0.dcache.ReadReq_misses::cpu0.data 146461 # number of ReadReq misses 673system.cpu0.dcache.ReadReq_misses::total 146461 # number of ReadReq misses 674system.cpu0.dcache.WriteReq_misses::cpu0.data 116958 # number of WriteReq misses 675system.cpu0.dcache.WriteReq_misses::total 116958 # number of WriteReq misses 676system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7880 # number of LoadLockedReq misses 677system.cpu0.dcache.LoadLockedReq_misses::total 7880 # number of LoadLockedReq misses 678system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7697 # number of StoreCondReq misses 679system.cpu0.dcache.StoreCondReq_misses::total 7697 # number of StoreCondReq misses 680system.cpu0.dcache.demand_misses::cpu0.data 263419 # number of demand (read+write) misses 681system.cpu0.dcache.demand_misses::total 263419 # number of demand (read+write) misses 682system.cpu0.dcache.overall_misses::cpu0.data 263419 # number of overall misses 683system.cpu0.dcache.overall_misses::total 263419 # number of overall misses 684system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991314500 # number of ReadReq miss cycles 685system.cpu0.dcache.ReadReq_miss_latency::total 1991314500 # number of ReadReq miss cycles 686system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199641500 # number of WriteReq miss cycles 687system.cpu0.dcache.WriteReq_miss_latency::total 4199641500 # number of WriteReq miss cycles 688system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70263500 # number of LoadLockedReq miss cycles 689system.cpu0.dcache.LoadLockedReq_miss_latency::total 70263500 # number of LoadLockedReq miss cycles 690system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66334500 # number of StoreCondReq miss cycles 691system.cpu0.dcache.StoreCondReq_miss_latency::total 66334500 # number of StoreCondReq miss cycles 692system.cpu0.dcache.demand_miss_latency::cpu0.data 6190956000 # number of demand (read+write) miss cycles 693system.cpu0.dcache.demand_miss_latency::total 6190956000 # number of demand (read+write) miss cycles 694system.cpu0.dcache.overall_miss_latency::cpu0.data 6190956000 # number of overall miss cycles 695system.cpu0.dcache.overall_miss_latency::total 6190956000 # number of overall miss cycles 696system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598868 # number of ReadReq accesses(hits+misses) 697system.cpu0.dcache.ReadReq_accesses::total 4598868 # number of ReadReq accesses(hits+misses) 698system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969493 # number of WriteReq accesses(hits+misses) 699system.cpu0.dcache.WriteReq_accesses::total 3969493 # number of WriteReq accesses(hits+misses) 700system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.demand_accesses::cpu0.data 8568361 # number of demand (read+write) accesses 705system.cpu0.dcache.demand_accesses::total 8568361 # number of demand (read+write) accesses 706system.cpu0.dcache.overall_accesses::cpu0.data 8568361 # number of overall (read+write) accesses 707system.cpu0.dcache.overall_accesses::total 8568361 # number of overall (read+write) accesses 708system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031847 # miss rate for ReadReq accesses 709system.cpu0.dcache.ReadReq_miss_rate::total 0.031847 # miss rate for ReadReq accesses 710system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029464 # miss rate for WriteReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::total 0.029464 # miss rate for WriteReq accesses 712system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062733 # miss rate for LoadLockedReq accesses 713system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses 714system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses 715system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses 716system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses 717system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses 718system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses 719system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses 720system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency 721system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency 722system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency 723system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency 728system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency 729system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency 730system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency 731system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency |
| 762system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu0.dcache.fast_writes 0 # number of fast writes performed 769system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 732system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 733system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.cpu0.dcache.fast_writes 0 # number of fast writes performed 739system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 770system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks 771system.cpu0.dcache.writebacks::total 306480 # number of writebacks 772system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses 773system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses 774system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses 775system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses 776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses 777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses 778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses 779system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses 780system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses 781system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses 782system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses 783system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses 784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles 785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles 786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles 787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles 791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles 792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles 793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency | 740system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks 741system.cpu0.dcache.writebacks::total 204960 # number of writebacks 742system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses 743system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses 744system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses 745system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses 746system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses 747system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses 748system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses 749system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses 750system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses 751system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses 752system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses 753system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses 754system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles 755system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles 756system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles 757system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles 758system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles 759system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles 760system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles 761system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles 762system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 763system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 764system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles 768system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles 771system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles 774system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses 783system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses 784system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses 785system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency 790system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency 791system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency 792system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency 793system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency |
| 824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 794system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 795system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 826system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency 828system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency | 796system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency 797system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency 798system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency 799system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency |
| 830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 834system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 836system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 837system.cpu1.dtb.inst_hits 0 # ITB inst hits 838system.cpu1.dtb.inst_misses 0 # ITB inst misses | 800system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 801system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 802system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 803system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 804system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 805system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 806system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 807system.cpu1.dtb.inst_hits 0 # ITB inst hits 808system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 839system.cpu1.dtb.read_hits 8318170 # DTB read hits 840system.cpu1.dtb.read_misses 3663 # DTB read misses 841system.cpu1.dtb.write_hits 5832653 # DTB write hits 842system.cpu1.dtb.write_misses 1435 # DTB write misses | 809system.cpu1.dtb.read_hits 10590618 # DTB read hits 810system.cpu1.dtb.read_misses 5230 # DTB read misses 811system.cpu1.dtb.write_hits 7384755 # DTB write hits 812system.cpu1.dtb.write_misses 1835 # DTB write misses |
| 843system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 844system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 845system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 846system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 813system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 814system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 815system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 816system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 847system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB | 817system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB |
| 848system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 818system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 849system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch | 819system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch |
| 850system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 820system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 851system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 852system.cpu1.dtb.read_accesses 8321833 # DTB read accesses 853system.cpu1.dtb.write_accesses 5834088 # DTB write accesses | 821system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions 822system.cpu1.dtb.read_accesses 10595848 # DTB read accesses 823system.cpu1.dtb.write_accesses 7386590 # DTB write accesses |
| 854system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 824system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 855system.cpu1.dtb.hits 14150823 # DTB hits 856system.cpu1.dtb.misses 5098 # DTB misses 857system.cpu1.dtb.accesses 14155921 # DTB accesses 858system.cpu1.itb.inst_hits 33211066 # ITB inst hits 859system.cpu1.itb.inst_misses 2171 # ITB inst misses | 825system.cpu1.dtb.hits 17975373 # DTB hits 826system.cpu1.dtb.misses 7065 # DTB misses 827system.cpu1.dtb.accesses 17982438 # DTB accesses 828system.cpu1.itb.inst_hits 43340388 # ITB inst hits 829system.cpu1.itb.inst_misses 3017 # ITB inst misses |
| 860system.cpu1.itb.read_hits 0 # DTB read hits 861system.cpu1.itb.read_misses 0 # DTB read misses 862system.cpu1.itb.write_hits 0 # DTB write hits 863system.cpu1.itb.write_misses 0 # DTB write misses 864system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 865system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 866system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 867system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 830system.cpu1.itb.read_hits 0 # DTB read hits 831system.cpu1.itb.read_misses 0 # DTB read misses 832system.cpu1.itb.write_hits 0 # DTB write hits 833system.cpu1.itb.write_misses 0 # DTB write misses 834system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 835system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 836system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 837system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 868system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB | 838system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB |
| 869system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 870system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 871system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 872system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 873system.cpu1.itb.read_accesses 0 # DTB read accesses 874system.cpu1.itb.write_accesses 0 # DTB write accesses | 839system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 840system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 841system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 842system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 843system.cpu1.itb.read_accesses 0 # DTB read accesses 844system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 875system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses 876system.cpu1.itb.hits 33211066 # DTB hits 877system.cpu1.itb.misses 2171 # DTB misses 878system.cpu1.itb.accesses 33213237 # DTB accesses 879system.cpu1.numCycles 2413083038 # number of cpu cycles simulated | 845system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses 846system.cpu1.itb.hits 43340388 # DTB hits 847system.cpu1.itb.misses 3017 # DTB misses 848system.cpu1.itb.accesses 43343405 # DTB accesses 849system.cpu1.numCycles 2407389096 # number of cpu cycles simulated |
| 880system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 881system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 850system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 851system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 882system.cpu1.committedInsts 32600335 # Number of instructions committed 883system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed 884system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses 885system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 886system.cpu1.num_func_calls 963082 # number of times a function call or return occured 887system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls 888system.cpu1.num_int_insts 37342001 # number of integer instructions 889system.cpu1.num_fp_insts 6793 # number of float instructions 890system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read 891system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written 892system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 893system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 894system.cpu1.num_mem_refs 14689113 # number of memory refs 895system.cpu1.num_load_insts 8640454 # Number of load instructions 896system.cpu1.num_store_insts 6048659 # Number of store instructions 897system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles 898system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles 899system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles 900system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles | 852system.cpu1.committedInsts 42409467 # Number of instructions committed 853system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed 854system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses 855system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses 856system.cpu1.num_func_calls 1335008 # number of times a function call or return occured 857system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls 858system.cpu1.num_int_insts 47739499 # number of integer instructions 859system.cpu1.num_fp_insts 5457 # number of float instructions 860system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read 861system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written 862system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read 863system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written 864system.cpu1.num_mem_refs 18684058 # number of memory refs 865system.cpu1.num_load_insts 11000639 # Number of load instructions 866system.cpu1.num_store_insts 7683419 # Number of store instructions 867system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles 868system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles 869system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles 870system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles |
| 901system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 871system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 902system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed 903system.cpu1.icache.replacements 455071 # number of replacements 904system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use 905system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. 906system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. 907system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. 908system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. 909system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor 910system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy 911system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy 912system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits 913system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits 914system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits 915system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits 916system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits 917system.cpu1.icache.overall_hits::total 32755479 # number of overall hits 918system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses 919system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses 920system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses 921system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses 922system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses 923system.cpu1.icache.overall_misses::total 455583 # number of overall misses 924system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles 925system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles 926system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles 927system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles 928system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles 929system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles 930system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) 931system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) 932system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses 933system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses 934system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses 935system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses 936system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses 937system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses 938system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses 939system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses 940system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses 941system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses 942system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency 943system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency 944system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency 945system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency 946system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency 947system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency | 872system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed 873system.cpu1.icache.replacements 582628 # number of replacements 874system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use 875system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. 876system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. 877system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. 878system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. 879system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor 880system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy 881system.cpu1.icache.occ_percent::total 0.935682 # Average percentage of cache occupancy 882system.cpu1.icache.ReadReq_hits::cpu1.inst 42757244 # number of ReadReq hits 883system.cpu1.icache.ReadReq_hits::total 42757244 # number of ReadReq hits 884system.cpu1.icache.demand_hits::cpu1.inst 42757244 # number of demand (read+write) hits 885system.cpu1.icache.demand_hits::total 42757244 # number of demand (read+write) hits 886system.cpu1.icache.overall_hits::cpu1.inst 42757244 # number of overall hits 887system.cpu1.icache.overall_hits::total 42757244 # number of overall hits 888system.cpu1.icache.ReadReq_misses::cpu1.inst 583140 # number of ReadReq misses 889system.cpu1.icache.ReadReq_misses::total 583140 # number of ReadReq misses 890system.cpu1.icache.demand_misses::cpu1.inst 583140 # number of demand (read+write) misses 891system.cpu1.icache.demand_misses::total 583140 # number of demand (read+write) misses 892system.cpu1.icache.overall_misses::cpu1.inst 583140 # number of overall misses 893system.cpu1.icache.overall_misses::total 583140 # number of overall misses 894system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7853505000 # number of ReadReq miss cycles 895system.cpu1.icache.ReadReq_miss_latency::total 7853505000 # number of ReadReq miss cycles 896system.cpu1.icache.demand_miss_latency::cpu1.inst 7853505000 # number of demand (read+write) miss cycles 897system.cpu1.icache.demand_miss_latency::total 7853505000 # number of demand (read+write) miss cycles 898system.cpu1.icache.overall_miss_latency::cpu1.inst 7853505000 # number of overall miss cycles 899system.cpu1.icache.overall_miss_latency::total 7853505000 # number of overall miss cycles 900system.cpu1.icache.ReadReq_accesses::cpu1.inst 43340384 # number of ReadReq accesses(hits+misses) 901system.cpu1.icache.ReadReq_accesses::total 43340384 # number of ReadReq accesses(hits+misses) 902system.cpu1.icache.demand_accesses::cpu1.inst 43340384 # number of demand (read+write) accesses 903system.cpu1.icache.demand_accesses::total 43340384 # number of demand (read+write) accesses 904system.cpu1.icache.overall_accesses::cpu1.inst 43340384 # number of overall (read+write) accesses 905system.cpu1.icache.overall_accesses::total 43340384 # number of overall (read+write) accesses 906system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013455 # miss rate for ReadReq accesses 907system.cpu1.icache.ReadReq_miss_rate::total 0.013455 # miss rate for ReadReq accesses 908system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013455 # miss rate for demand accesses 909system.cpu1.icache.demand_miss_rate::total 0.013455 # miss rate for demand accesses 910system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013455 # miss rate for overall accesses 911system.cpu1.icache.overall_miss_rate::total 0.013455 # miss rate for overall accesses 912system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.614981 # average ReadReq miss latency 913system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.614981 # average ReadReq miss latency 914system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency 915system.cpu1.icache.demand_avg_miss_latency::total 13467.614981 # average overall miss latency 916system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency 917system.cpu1.icache.overall_avg_miss_latency::total 13467.614981 # average overall miss latency |
| 948system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 949system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 950system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 951system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 952system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 953system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 954system.cpu1.icache.fast_writes 0 # number of fast writes performed 955system.cpu1.icache.cache_copies 0 # number of cache copies performed | 918system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu1.icache.fast_writes 0 # number of fast writes performed 925system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses 957system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses 958system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses 959system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses 960system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses 961system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses 962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles 963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles 964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles 965system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles 966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles 967system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles 968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles 972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses 973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses 974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses 975system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses 976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses 977system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses 978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency 979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency 980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency 981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency 982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency 983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency | 926system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583140 # number of ReadReq MSHR misses 927system.cpu1.icache.ReadReq_mshr_misses::total 583140 # number of ReadReq MSHR misses 928system.cpu1.icache.demand_mshr_misses::cpu1.inst 583140 # number of demand (read+write) MSHR misses 929system.cpu1.icache.demand_mshr_misses::total 583140 # number of demand (read+write) MSHR misses 930system.cpu1.icache.overall_mshr_misses::cpu1.inst 583140 # number of overall MSHR misses 931system.cpu1.icache.overall_mshr_misses::total 583140 # number of overall MSHR misses 932system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6687225000 # number of ReadReq MSHR miss cycles 933system.cpu1.icache.ReadReq_mshr_miss_latency::total 6687225000 # number of ReadReq MSHR miss cycles 934system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6687225000 # number of demand (read+write) MSHR miss cycles 935system.cpu1.icache.demand_mshr_miss_latency::total 6687225000 # number of demand (read+write) MSHR miss cycles 936system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6687225000 # number of overall MSHR miss cycles 937system.cpu1.icache.overall_mshr_miss_latency::total 6687225000 # number of overall MSHR miss cycles 938system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles 939system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles 940system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles 941system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles 942system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for ReadReq accesses 943system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013455 # mshr miss rate for ReadReq accesses 944system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for demand accesses 945system.cpu1.icache.demand_mshr_miss_rate::total 0.013455 # mshr miss rate for demand accesses 946system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for overall accesses 947system.cpu1.icache.overall_mshr_miss_rate::total 0.013455 # mshr miss rate for overall accesses 948system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average ReadReq mshr miss latency 949system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11467.614981 # average ReadReq mshr miss latency 950system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency 951system.cpu1.icache.demand_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency 952system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency 953system.cpu1.icache.overall_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency |
| 984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 954system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 955system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 956system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 957system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 958system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 989system.cpu1.dcache.replacements 292605 # number of replacements 990system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use 991system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. 992system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. 993system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. 994system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. 995system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor 996system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy 997system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy 998system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits 999system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits 1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits 1001system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits 1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits 1003system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits 1004system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82891 # number of StoreCondReq hits 1005system.cpu1.dcache.StoreCondReq_hits::total 82891 # number of StoreCondReq hits 1006system.cpu1.dcache.demand_hits::cpu1.data 11784950 # number of demand (read+write) hits 1007system.cpu1.dcache.demand_hits::total 11784950 # number of demand (read+write) hits 1008system.cpu1.dcache.overall_hits::cpu1.data 11784950 # number of overall hits 1009system.cpu1.dcache.overall_hits::total 11784950 # number of overall hits 1010system.cpu1.dcache.ReadReq_misses::cpu1.data 170988 # number of ReadReq misses 1011system.cpu1.dcache.ReadReq_misses::total 170988 # number of ReadReq misses 1012system.cpu1.dcache.WriteReq_misses::cpu1.data 150171 # number of WriteReq misses 1013system.cpu1.dcache.WriteReq_misses::total 150171 # number of WriteReq misses 1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses 1015system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses 1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses 1017system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses 1018system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses 1019system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses 1020system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses 1021system.cpu1.dcache.overall_misses::total 321159 # number of overall misses 1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles 1023system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles 1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles 1025system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles 1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles 1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles 1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles 1029system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles 1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles 1031system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles 1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles 1033system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles 1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) 1035system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) 1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) 1037system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses) 1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses) 1039system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses) 1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses) 1041system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses) 1042system.cpu1.dcache.demand_accesses::cpu1.data 12106109 # number of demand (read+write) accesses 1043system.cpu1.dcache.demand_accesses::total 12106109 # number of demand (read+write) accesses 1044system.cpu1.dcache.overall_accesses::cpu1.data 12106109 # number of overall (read+write) accesses 1045system.cpu1.dcache.overall_accesses::total 12106109 # number of overall (read+write) accesses 1046system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024002 # miss rate for ReadReq accesses 1047system.cpu1.dcache.ReadReq_miss_rate::total 0.024002 # miss rate for ReadReq accesses 1048system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030142 # miss rate for WriteReq accesses 1049system.cpu1.dcache.WriteReq_miss_rate::total 0.030142 # miss rate for WriteReq accesses 1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses 1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses 1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses 1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses 1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses 1055system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses 1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses 1057system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses 1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency 1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency 1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency 1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency 1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency 1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency 1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency 1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency 1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency 1067system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency 1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency 1069system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency | 959system.cpu1.dcache.replacements 401361 # number of replacements 960system.cpu1.dcache.tagsinuse 473.304740 # Cycle average of tags in use 961system.cpu1.dcache.total_refs 15681919 # Total number of references to valid blocks. 962system.cpu1.dcache.sampled_refs 401873 # Sample count of references to valid blocks. 963system.cpu1.dcache.avg_refs 39.022077 # Average number of references to valid blocks. 964system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. 965system.cpu1.dcache.occ_blocks::cpu1.data 473.304740 # Average occupied blocks per requestor 966system.cpu1.dcache.occ_percent::cpu1.data 0.924423 # Average percentage of cache occupancy 967system.cpu1.dcache.occ_percent::total 0.924423 # Average percentage of cache occupancy 968system.cpu1.dcache.ReadReq_hits::cpu1.data 9101949 # number of ReadReq hits 969system.cpu1.dcache.ReadReq_hits::total 9101949 # number of ReadReq hits 970system.cpu1.dcache.WriteReq_hits::cpu1.data 6323711 # number of WriteReq hits 971system.cpu1.dcache.WriteReq_hits::total 6323711 # number of WriteReq hits 972system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111853 # number of LoadLockedReq hits 973system.cpu1.dcache.LoadLockedReq_hits::total 111853 # number of LoadLockedReq hits 974system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114473 # number of StoreCondReq hits 975system.cpu1.dcache.StoreCondReq_hits::total 114473 # number of StoreCondReq hits 976system.cpu1.dcache.demand_hits::cpu1.data 15425660 # number of demand (read+write) hits 977system.cpu1.dcache.demand_hits::total 15425660 # number of demand (read+write) hits 978system.cpu1.dcache.overall_hits::cpu1.data 15425660 # number of overall hits 979system.cpu1.dcache.overall_hits::total 15425660 # number of overall hits 980system.cpu1.dcache.ReadReq_misses::cpu1.data 253200 # number of ReadReq misses 981system.cpu1.dcache.ReadReq_misses::total 253200 # number of ReadReq misses 982system.cpu1.dcache.WriteReq_misses::cpu1.data 178129 # number of WriteReq misses 983system.cpu1.dcache.WriteReq_misses::total 178129 # number of WriteReq misses 984system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13100 # number of LoadLockedReq misses 985system.cpu1.dcache.LoadLockedReq_misses::total 13100 # number of LoadLockedReq misses 986system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10404 # number of StoreCondReq misses 987system.cpu1.dcache.StoreCondReq_misses::total 10404 # number of StoreCondReq misses 988system.cpu1.dcache.demand_misses::cpu1.data 431329 # number of demand (read+write) misses 989system.cpu1.dcache.demand_misses::total 431329 # number of demand (read+write) misses 990system.cpu1.dcache.overall_misses::cpu1.data 431329 # number of overall misses 991system.cpu1.dcache.overall_misses::total 431329 # number of overall misses 992system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3278248500 # number of ReadReq miss cycles 993system.cpu1.dcache.ReadReq_miss_latency::total 3278248500 # number of ReadReq miss cycles 994system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5660664500 # number of WriteReq miss cycles 995system.cpu1.dcache.WriteReq_miss_latency::total 5660664500 # number of WriteReq miss cycles 996system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115759000 # number of LoadLockedReq miss cycles 997system.cpu1.dcache.LoadLockedReq_miss_latency::total 115759000 # number of LoadLockedReq miss cycles 998system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63020500 # number of StoreCondReq miss cycles 999system.cpu1.dcache.StoreCondReq_miss_latency::total 63020500 # number of StoreCondReq miss cycles 1000system.cpu1.dcache.demand_miss_latency::cpu1.data 8938913000 # number of demand (read+write) miss cycles 1001system.cpu1.dcache.demand_miss_latency::total 8938913000 # number of demand (read+write) miss cycles 1002system.cpu1.dcache.overall_miss_latency::cpu1.data 8938913000 # number of overall miss cycles 1003system.cpu1.dcache.overall_miss_latency::total 8938913000 # number of overall miss cycles 1004system.cpu1.dcache.ReadReq_accesses::cpu1.data 9355149 # number of ReadReq accesses(hits+misses) 1005system.cpu1.dcache.ReadReq_accesses::total 9355149 # number of ReadReq accesses(hits+misses) 1006system.cpu1.dcache.WriteReq_accesses::cpu1.data 6501840 # number of WriteReq accesses(hits+misses) 1007system.cpu1.dcache.WriteReq_accesses::total 6501840 # number of WriteReq accesses(hits+misses) 1008system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124953 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu1.dcache.LoadLockedReq_accesses::total 124953 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124877 # number of StoreCondReq accesses(hits+misses) 1011system.cpu1.dcache.StoreCondReq_accesses::total 124877 # number of StoreCondReq accesses(hits+misses) 1012system.cpu1.dcache.demand_accesses::cpu1.data 15856989 # number of demand (read+write) accesses 1013system.cpu1.dcache.demand_accesses::total 15856989 # number of demand (read+write) accesses 1014system.cpu1.dcache.overall_accesses::cpu1.data 15856989 # number of overall (read+write) accesses 1015system.cpu1.dcache.overall_accesses::total 15856989 # number of overall (read+write) accesses 1016system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027065 # miss rate for ReadReq accesses 1017system.cpu1.dcache.ReadReq_miss_rate::total 0.027065 # miss rate for ReadReq accesses 1018system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027397 # miss rate for WriteReq accesses 1019system.cpu1.dcache.WriteReq_miss_rate::total 0.027397 # miss rate for WriteReq accesses 1020system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104839 # miss rate for LoadLockedReq accesses 1021system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104839 # miss rate for LoadLockedReq accesses 1022system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083314 # miss rate for StoreCondReq accesses 1023system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083314 # miss rate for StoreCondReq accesses 1024system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027201 # miss rate for demand accesses 1025system.cpu1.dcache.demand_miss_rate::total 0.027201 # miss rate for demand accesses 1026system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027201 # miss rate for overall accesses 1027system.cpu1.dcache.overall_miss_rate::total 0.027201 # miss rate for overall accesses 1028system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957 # average ReadReq miss latency 1029system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957 # average ReadReq miss latency 1030system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501 # average WriteReq miss latency 1031system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501 # average WriteReq miss latency 1032system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8836.564885 # average LoadLockedReq miss latency 1033system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8836.564885 # average LoadLockedReq miss latency 1034system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6057.333718 # average StoreCondReq miss latency 1035system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6057.333718 # average StoreCondReq miss latency 1036system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency 1037system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency 1038system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency 1039system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency |
| 1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1040system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1047system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1078system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks 1079system.cpu1.dcache.writebacks::total 266100 # number of writebacks 1080system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses 1081system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses 1082system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses 1083system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses 1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses 1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses 1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses 1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses 1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses 1089system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses 1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses 1091system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses 1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles 1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles 1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles 1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles 1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles 1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles 1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles 1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles 1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles 1101system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles 1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles 1103system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles 1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles 1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles 1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles 1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles 1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles 1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles 1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses 1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses 1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses 1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses 1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses 1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses 1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses 1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses 1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses 1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses 1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses 1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses 1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency 1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency 1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency 1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency 1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency 1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency 1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency 1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency 1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency 1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency 1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency 1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency | 1048system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks 1049system.cpu1.dcache.writebacks::total 366483 # number of writebacks 1050system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses 1051system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses 1052system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses 1053system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses 1054system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses 1055system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses 1056system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses 1057system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses 1058system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses 1059system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses 1060system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses 1061system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses 1062system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles 1063system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles 1064system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles 1065system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles 1066system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles 1067system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles 1068system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles 1069system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles 1070system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles 1071system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1072system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles 1073system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles 1074system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles 1075system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles 1076system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles 1077system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles 1078system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles 1079system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles 1080system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles 1081system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles 1082system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses 1083system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses 1084system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses 1085system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses 1086system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses 1087system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses 1088system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses 1089system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses 1090system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses 1091system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses 1092system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses 1093system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses 1094system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency 1095system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency 1096system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency 1097system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency 1098system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency 1099system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency 1100system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency 1101system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency 1102system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1103system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1104system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency 1105system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency 1106system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency 1107system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency |
| 1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1153system.iocache.fast_writes 0 # number of fast writes performed 1154system.iocache.cache_copies 0 # number of cache copies performed | 1108system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1109system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1110system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1111system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1112system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1113system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1114system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1115system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1121system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1125system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.iocache.fast_writes 0 # number of fast writes performed 1128system.iocache.cache_copies 0 # number of cache copies performed |
| 1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles 1156system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles 1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles 1158system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles | 1129system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles 1130system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles 1131system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles 1132system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles |
| 1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1164 1165---------- End Simulation Statistics ---------- | 1133system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1134system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1135system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1136system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1137system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1138 1139---------- End Simulation Statistics ---------- |