| stats.txt (9199:2a5516167688) | stats.txt (9229:65f927bda74d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.207291 # Number of seconds simulated 4sim_ticks 1207290627000 # Number of ticks simulated 5final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.207291 # Number of seconds simulated 4sim_ticks 1207290627000 # Number of ticks simulated 5final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1000042 # Simulator instruction rate (inst/s) 8host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19638848032 # Simulator tick rate (ticks/s) 10host_mem_usage 383956 # Number of bytes of host memory used 11host_seconds 61.47 # Real time elapsed on the host | 7host_inst_rate 965295 # Simulator instruction rate (inst/s) 8host_op_rate 1230212 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18956490102 # Simulator tick rate (ticks/s) 10host_mem_usage 382720 # Number of bytes of host memory used 11host_seconds 63.69 # Real time elapsed on the host |
| 12sim_insts 61477134 # Number of instructions simulated 13sim_ops 78349023 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory --- 64 unchanged lines hidden (view full) --- 84system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) 91system.l2c.replacements 69267 # number of replacements | 12sim_insts 61477134 # Number of instructions simulated 13sim_ops 78349023 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory --- 64 unchanged lines hidden (view full) --- 84system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) 91system.l2c.replacements 69267 # number of replacements |
| 92system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use | 92system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use |
| 93system.l2c.total_refs 1645693 # Total number of references to valid blocks. 94system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. 95system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 93system.l2c.total_refs 1645693 # Total number of references to valid blocks. 94system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. 95system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 97system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor | 97system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor |
| 98system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor | 98system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor |
| 100system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor | 100system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor |
| 102system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor | 102system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor |
| 104system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor | 104system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor |
| 106system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 109system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy --- 70 unchanged lines hidden (view full) --- 184system.l2c.overall_misses::cpu0.data 75067 # number of overall misses 185system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses 188system.l2c.overall_misses::cpu1.data 75979 # number of overall misses 189system.l2c.overall_misses::total 161841 # number of overall misses 190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles | 106system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 109system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy --- 70 unchanged lines hidden (view full) --- 184system.l2c.overall_misses::cpu0.data 75067 # number of overall misses 185system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses 188system.l2c.overall_misses::cpu1.data 75979 # number of overall misses 189system.l2c.overall_misses::total 161841 # number of overall misses 190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles |
| 192system.l2c.ReadReq_miss_latency::cpu0.inst 298918500 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu0.data 409688500 # number of ReadReq miss cycles | 192system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles |
| 194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles 195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles | 194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles 195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles |
| 196system.l2c.ReadReq_miss_latency::cpu1.inst 263122000 # number of ReadReq miss cycles 197system.l2c.ReadReq_miss_latency::cpu1.data 189491500 # number of ReadReq miss cycles 198system.l2c.ReadReq_miss_latency::total 1161637500 # number of ReadReq miss cycles 199system.l2c.UpgradeReq_miss_latency::cpu0.data 30055000 # number of UpgradeReq miss cycles 200system.l2c.UpgradeReq_miss_latency::cpu1.data 27347000 # number of UpgradeReq miss cycles 201system.l2c.UpgradeReq_miss_latency::total 57402000 # number of UpgradeReq miss cycles | 196system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles 197system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles 198system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles 199system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles 200system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles 201system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles |
| 202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles | 202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles |
| 203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6038000 # number of SCUpgradeReq miss cycles 204system.l2c.SCUpgradeReq_miss_latency::total 9730000 # number of SCUpgradeReq miss cycles 205system.l2c.ReadExReq_miss_latency::cpu0.data 3494564965 # number of ReadExReq miss cycles 206system.l2c.ReadExReq_miss_latency::cpu1.data 3764669994 # number of ReadExReq miss cycles 207system.l2c.ReadExReq_miss_latency::total 7259234959 # number of ReadExReq miss cycles | 203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles 204system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles 205system.l2c.ReadExReq_miss_latency::cpu0.data 3494513965 # number of ReadExReq miss cycles 206system.l2c.ReadExReq_miss_latency::cpu1.data 3764719994 # number of ReadExReq miss cycles 207system.l2c.ReadExReq_miss_latency::total 7259233959 # number of ReadExReq miss cycles |
| 208system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 209system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles | 208system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 209system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles |
| 210system.l2c.demand_miss_latency::cpu0.inst 298918500 # number of demand (read+write) miss cycles 211system.l2c.demand_miss_latency::cpu0.data 3904253465 # number of demand (read+write) miss cycles | 210system.l2c.demand_miss_latency::cpu0.inst 298939500 # number of demand (read+write) miss cycles 211system.l2c.demand_miss_latency::cpu0.data 3904184465 # number of demand (read+write) miss cycles |
| 212system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles 213system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles | 212system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles 213system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles |
| 214system.l2c.demand_miss_latency::cpu1.inst 263122000 # number of demand (read+write) miss cycles 215system.l2c.demand_miss_latency::cpu1.data 3954161494 # number of demand (read+write) miss cycles 216system.l2c.demand_miss_latency::total 8420872459 # number of demand (read+write) miss cycles | 214system.l2c.demand_miss_latency::cpu1.inst 263172000 # number of demand (read+write) miss cycles 215system.l2c.demand_miss_latency::cpu1.data 3954214494 # number of demand (read+write) miss cycles 216system.l2c.demand_miss_latency::total 8420927459 # number of demand (read+write) miss cycles |
| 217system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 218system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles | 217system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 218system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles |
| 219system.l2c.overall_miss_latency::cpu0.inst 298918500 # number of overall miss cycles 220system.l2c.overall_miss_latency::cpu0.data 3904253465 # number of overall miss cycles | 219system.l2c.overall_miss_latency::cpu0.inst 298939500 # number of overall miss cycles 220system.l2c.overall_miss_latency::cpu0.data 3904184465 # number of overall miss cycles |
| 221system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles 222system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles | 221system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles 222system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles |
| 223system.l2c.overall_miss_latency::cpu1.inst 263122000 # number of overall miss cycles 224system.l2c.overall_miss_latency::cpu1.data 3954161494 # number of overall miss cycles 225system.l2c.overall_miss_latency::total 8420872459 # number of overall miss cycles | 223system.l2c.overall_miss_latency::cpu1.inst 263172000 # number of overall miss cycles 224system.l2c.overall_miss_latency::cpu1.data 3954214494 # number of overall miss cycles 225system.l2c.overall_miss_latency::total 8420927459 # number of overall miss cycles |
| 226system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) 227system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) 228system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) 229system.l2c.ReadReq_accesses::cpu0.data 213749 # number of ReadReq accesses(hits+misses) 230system.l2c.ReadReq_accesses::cpu1.dtb.walker 5727 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu1.itb.walker 1960 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu1.inst 455013 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu1.data 147730 # number of ReadReq accesses(hits+misses) --- 60 unchanged lines hidden (view full) --- 294system.l2c.overall_miss_rate::cpu0.data 0.222312 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000510 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.011083 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.278223 # miss rate for overall accesses 299system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency | 226system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) 227system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) 228system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) 229system.l2c.ReadReq_accesses::cpu0.data 213749 # number of ReadReq accesses(hits+misses) 230system.l2c.ReadReq_accesses::cpu1.dtb.walker 5727 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu1.itb.walker 1960 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu1.inst 455013 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu1.data 147730 # number of ReadReq accesses(hits+misses) --- 60 unchanged lines hidden (view full) --- 294system.l2c.overall_miss_rate::cpu0.data 0.222312 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000510 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.011083 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.278223 # miss rate for overall accesses 299system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency |
| 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52040.128830 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52030.543561 # average ReadReq miss latency | 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557 # average ReadReq miss latency |
| 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency | 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency |
| 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52175.689074 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52072.410003 # average ReadReq miss latency 308system.l2c.ReadReq_avg_miss_latency::total 52072.686928 # average ReadReq miss latency 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.243197 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7630.301339 # average UpgradeReq miss latency 311system.l2c.UpgradeReq_avg_miss_latency::total 6925.916988 # average UpgradeReq miss latency | 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405 # average ReadReq miss latency 308system.l2c.ReadReq_avg_miss_latency::total 52075.197239 # average ReadReq miss latency 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6388.818027 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7629.185268 # average UpgradeReq miss latency 311system.l2c.UpgradeReq_avg_miss_latency::total 6925.193050 # average UpgradeReq miss latency |
| 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency | 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency |
| 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12449.484536 # average SCUpgradeReq miss latency 314system.l2c.SCUpgradeReq_avg_miss_latency::total 9231.499051 # average SCUpgradeReq miss latency 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.872323 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52041.332513 # average ReadExReq miss latency 317system.l2c.ReadExReq_avg_miss_latency::total 52025.219547 # average ReadExReq miss latency | 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12445.360825 # average SCUpgradeReq miss latency 314system.l2c.SCUpgradeReq_avg_miss_latency::total 9229.601518 # average SCUpgradeReq miss latency 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.113315 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52042.023694 # average ReadExReq miss latency 317system.l2c.ReadExReq_avg_miss_latency::total 52025.212380 # average ReadExReq miss latency |
| 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency | 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency |
| 320system.l2c.demand_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency | 320system.l2c.demand_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency |
| 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency | 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency |
| 324system.l2c.demand_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 52031.762403 # average overall miss latency | 324system.l2c.demand_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 52032.102242 # average overall miss latency |
| 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency | 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency |
| 329system.l2c.overall_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency | 329system.l2c.overall_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency |
| 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency | 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency |
| 333system.l2c.overall_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 52031.762403 # average overall miss latency | 333system.l2c.overall_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 52032.102242 # average overall miss latency |
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| 435system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209527997 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::total 199055980495 # number of overall MSHR uncacheable cycles | 435system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles |
| 437system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses 438system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses 443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses 444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses --- 22 unchanged lines hidden (view full) --- 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses 471system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses 472system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency | 437system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses 438system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses 443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses 444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses --- 22 unchanged lines hidden (view full) --- 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses 471system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses 472system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency |
| 475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average ReadReq mshr miss latency 476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060 # average ReadReq mshr miss latency | 475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency 476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency |
| 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency | 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency |
| 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40071.723001 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.295378 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40083.971088 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40087.890625 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40085.666023 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40014.059754 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40086.597938 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.438330 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40007.203131 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.125242 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.789835 # average ReadExReq mshr miss latency | 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency |
| 491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency | 493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency |
| 495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency | 495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency |
| 497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency 498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency 499system.l2c.demand_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency | 497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency 498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency 499system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency |
| 500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency 503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency | 502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency 503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency |
| 504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency | 504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency |
| 506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency 507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency 508system.l2c.overall_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency | 506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency 507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency 508system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency |
| 509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 64 unchanged lines hidden (view full) --- 581system.cpu0.num_fp_insts 3860 # number of float instructions 582system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read 583system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written 584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 586system.cpu0.num_mem_refs 13404188 # number of memory refs 587system.cpu0.num_load_insts 7413537 # Number of load instructions 588system.cpu0.num_store_insts 5990651 # Number of store instructions | 509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 64 unchanged lines hidden (view full) --- 581system.cpu0.num_fp_insts 3860 # number of float instructions 582system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read 583system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written 584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 586system.cpu0.num_mem_refs 13404188 # number of memory refs 587system.cpu0.num_load_insts 7413537 # Number of load instructions 588system.cpu0.num_store_insts 5990651 # Number of store instructions |
| 589system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles 590system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles | 589system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles 590system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles |
| 591system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles 592system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles 593system.cpu0.kern.inst.arm 0 # number of arm instructions executed 594system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed 595system.cpu0.icache.replacements 408135 # number of replacements 596system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use 597system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. 598system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. --- 9 unchanged lines hidden (view full) --- 608system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits 609system.cpu0.icache.overall_hits::total 29165991 # number of overall hits 610system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses 611system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses 612system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses 613system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses 614system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses 615system.cpu0.icache.overall_misses::total 408647 # number of overall misses | 591system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles 592system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles 593system.cpu0.kern.inst.arm 0 # number of arm instructions executed 594system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed 595system.cpu0.icache.replacements 408135 # number of replacements 596system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use 597system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. 598system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. --- 9 unchanged lines hidden (view full) --- 608system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits 609system.cpu0.icache.overall_hits::total 29165991 # number of overall hits 610system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses 611system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses 612system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses 613system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses 614system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses 615system.cpu0.icache.overall_misses::total 408647 # number of overall misses |
| 616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096214000 # number of ReadReq miss cycles 617system.cpu0.icache.ReadReq_miss_latency::total 6096214000 # number of ReadReq miss cycles 618system.cpu0.icache.demand_miss_latency::cpu0.inst 6096214000 # number of demand (read+write) miss cycles 619system.cpu0.icache.demand_miss_latency::total 6096214000 # number of demand (read+write) miss cycles 620system.cpu0.icache.overall_miss_latency::cpu0.inst 6096214000 # number of overall miss cycles 621system.cpu0.icache.overall_miss_latency::total 6096214000 # number of overall miss cycles | 616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles 617system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles 618system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles 619system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles 620system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles 621system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles |
| 622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) 623system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) 624system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses 625system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses 626system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses 627system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses 628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses 629system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses 630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses 631system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses 632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses 633system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses | 622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) 623system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) 624system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses 625system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses 626system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses 627system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses 628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses 629system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses 630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses 631system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses 632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses 633system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses |
| 634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency 635system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency 636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency 637system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency 638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency 639system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency | 634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency 635system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency 636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency 637system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency 638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency 639system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency |
| 640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu0.icache.fast_writes 0 # number of fast writes performed 647system.cpu0.icache.cache_copies 0 # number of cache copies performed 648system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses 649system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses 650system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses 651system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses 652system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses 653system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses | 640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu0.icache.fast_writes 0 # number of fast writes performed 647system.cpu0.icache.cache_copies 0 # number of cache copies performed 648system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses 649system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses 650system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses 651system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses 652system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses 653system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses |
| 654system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869428500 # number of ReadReq MSHR miss cycles 655system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869428500 # number of ReadReq MSHR miss cycles 656system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869428500 # number of demand (read+write) MSHR miss cycles 657system.cpu0.icache.demand_mshr_miss_latency::total 4869428500 # number of demand (read+write) MSHR miss cycles 658system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869428500 # number of overall MSHR miss cycles 659system.cpu0.icache.overall_mshr_miss_latency::total 4869428500 # number of overall MSHR miss cycles | 654system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles 655system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles 656system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles 657system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles 658system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles 659system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles |
| 660system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 661system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 662system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 663system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles 664system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses 665system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses 666system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses 667system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses 668system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses 669system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses | 660system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 661system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 662system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 663system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles 664system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses 665system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses 666system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses 667system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses 668system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses 669system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses |
| 670system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average ReadReq mshr miss latency 671system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604 # average ReadReq mshr miss latency 672system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency 673system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency 674system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency 675system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency | 670system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency 671system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency 672system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency 673system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency 674system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency 675system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency |
| 676system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 677system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 678system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 679system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 680system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 681system.cpu0.dcache.replacements 330734 # number of replacements | 676system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 677system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 678system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 679system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 680system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 681system.cpu0.dcache.replacements 330734 # number of replacements |
| 682system.cpu0.dcache.tagsinuse 459.649704 # Cycle average of tags in use | 682system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use |
| 683system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. 684system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. 685system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. 686system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. | 683system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. 684system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. 685system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. 686system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. |
| 687system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor | 687system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor |
| 688system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy 689system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy 690system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits 691system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits 692system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits 693system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits 694system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits 695system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits --- 10 unchanged lines hidden (view full) --- 706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses 707system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses 708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses 709system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses 710system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses 711system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses 712system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses 713system.cpu0.dcache.overall_misses::total 369775 # number of overall misses | 688system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy 689system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy 690system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits 691system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits 692system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits 693system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits 694system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits 695system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits --- 10 unchanged lines hidden (view full) --- 706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses 707system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses 708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses 709system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses 710system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses 711system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses 712system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses 713system.cpu0.dcache.overall_misses::total 369775 # number of overall misses |
| 714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles 715system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles 716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles 717system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles 718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles 719system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles 720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles 721system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles 722system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles 723system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles 724system.cpu0.dcache.overall_miss_latency::cpu0.data 8361798500 # number of overall miss cycles 725system.cpu0.dcache.overall_miss_latency::total 8361798500 # number of overall miss cycles | 714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles 715system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles 716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles 717system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles 718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles 719system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles 720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles 721system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles 722system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles 723system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles 724system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles 725system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles |
| 726system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) 727system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) 728system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) 729system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) 730system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) 731system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) 732system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) 733system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 742system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses 743system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses 744system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses 745system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses 746system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses 747system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses 748system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses 749system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses | 726system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) 727system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) 728system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) 729system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) 730system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) 731system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) 732system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) 733system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 742system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses 743system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses 744system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses 745system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses 746system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses 747system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses 748system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses 749system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses |
| 750system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency 751system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency 752system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency 753system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency 754system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency 755system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency 756system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency 757system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency 758system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency 759system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency 760system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency 761system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency | 750system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency 751system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency 752system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency 753system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency 754system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency 755system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency 756system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency 757system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency 758system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency 759system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency 760system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency 761system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency |
| 762system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu0.dcache.fast_writes 0 # number of fast writes performed 769system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses 777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses 778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses 779system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses 780system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses 781system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses 782system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses 783system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses | 762system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu0.dcache.fast_writes 0 # number of fast writes performed 769system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses 777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses 778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses 779system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses 780system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses 781system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses 782system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses 783system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses |
| 784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles 785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles 786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles 787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles 791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles | 784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles 785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles 786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles 787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles 791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles |
| 792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles 793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles | 792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles 793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles |
| 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles | 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles |
| 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses | 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses |
| 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency | 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency |
| 824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 826system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency 828system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency | 826system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency 828system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency |
| 830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 834system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 836system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 837system.cpu1.dtb.inst_hits 0 # ITB inst hits --- 51 unchanged lines hidden (view full) --- 889system.cpu1.num_fp_insts 6793 # number of float instructions 890system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read 891system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written 892system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 893system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 894system.cpu1.num_mem_refs 14689113 # number of memory refs 895system.cpu1.num_load_insts 8640454 # Number of load instructions 896system.cpu1.num_store_insts 6048659 # Number of store instructions | 830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 834system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 836system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 837system.cpu1.dtb.inst_hits 0 # ITB inst hits --- 51 unchanged lines hidden (view full) --- 889system.cpu1.num_fp_insts 6793 # number of float instructions 890system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read 891system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written 892system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 893system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 894system.cpu1.num_mem_refs 14689113 # number of memory refs 895system.cpu1.num_load_insts 8640454 # Number of load instructions 896system.cpu1.num_store_insts 6048659 # Number of store instructions |
| 897system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles 898system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles | 897system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles 898system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles |
| 899system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles 900system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles 901system.cpu1.kern.inst.arm 0 # number of arm instructions executed 902system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed 903system.cpu1.icache.replacements 455071 # number of replacements 904system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use 905system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. 906system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. --- 9 unchanged lines hidden (view full) --- 916system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits 917system.cpu1.icache.overall_hits::total 32755479 # number of overall hits 918system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses 919system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses 920system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses 921system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses 922system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses 923system.cpu1.icache.overall_misses::total 455583 # number of overall misses | 899system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles 900system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles 901system.cpu1.kern.inst.arm 0 # number of arm instructions executed 902system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed 903system.cpu1.icache.replacements 455071 # number of replacements 904system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use 905system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. 906system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. --- 9 unchanged lines hidden (view full) --- 916system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits 917system.cpu1.icache.overall_hits::total 32755479 # number of overall hits 918system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses 919system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses 920system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses 921system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses 922system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses 923system.cpu1.icache.overall_misses::total 455583 # number of overall misses |
| 924system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles 925system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles 926system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles 927system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles 928system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles 929system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles | 924system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles 925system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles 926system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles 927system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles 928system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles 929system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles |
| 930system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) 931system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) 932system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses 933system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses 934system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses 935system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses 936system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses 937system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses 938system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses 939system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses 940system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses 941system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses | 930system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) 931system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) 932system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses 933system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses 934system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses 935system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses 936system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses 937system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses 938system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses 939system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses 940system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses 941system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses |
| 942system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency 943system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency 944system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency 945system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency 946system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency 947system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency | 942system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency 943system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency 944system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency 945system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency 946system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency 947system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency |
| 948system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 949system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 950system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 951system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 952system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 953system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 954system.cpu1.icache.fast_writes 0 # number of fast writes performed 955system.cpu1.icache.cache_copies 0 # number of cache copies performed 956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses 957system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses 958system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses 959system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses 960system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses 961system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses | 948system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 949system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 950system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 951system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 952system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 953system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 954system.cpu1.icache.fast_writes 0 # number of fast writes performed 955system.cpu1.icache.cache_copies 0 # number of cache copies performed 956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses 957system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses 958system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses 959system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses 960system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses 961system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses |
| 962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles 963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles 964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles 965system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles 966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles 967system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles | 962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles 963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles 964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles 965system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles 966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles 967system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles |
| 968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles 972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses 973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses 974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses 975system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses 976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses 977system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses | 968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles 972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses 973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses 974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses 975system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses 976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses 977system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses |
| 978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency 979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency 980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency 981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency 982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency 983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency | 978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency 979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency 980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency 981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency 982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency 983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency |
| 984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 989system.cpu1.dcache.replacements 292605 # number of replacements | 984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 989system.cpu1.dcache.replacements 292605 # number of replacements |
| 990system.cpu1.dcache.tagsinuse 473.034253 # Cycle average of tags in use | 990system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use |
| 991system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. 992system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. 993system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. 994system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. | 991system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. 992system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. 993system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. 994system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. |
| 995system.cpu1.dcache.occ_blocks::cpu1.data 473.034253 # Average occupied blocks per requestor | 995system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor |
| 996system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy 997system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy 998system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits 999system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits 1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits 1001system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits 1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits 1003system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits --- 10 unchanged lines hidden (view full) --- 1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses 1015system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses 1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses 1017system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses 1018system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses 1019system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses 1020system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses 1021system.cpu1.dcache.overall_misses::total 321159 # number of overall misses | 996system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy 997system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy 998system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits 999system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits 1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits 1001system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits 1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits 1003system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits --- 10 unchanged lines hidden (view full) --- 1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses 1015system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses 1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses 1017system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses 1018system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses 1019system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses 1020system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses 1021system.cpu1.dcache.overall_misses::total 321159 # number of overall misses |
| 1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374183000 # number of ReadReq miss cycles 1023system.cpu1.dcache.ReadReq_miss_latency::total 2374183000 # number of ReadReq miss cycles 1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137653000 # number of WriteReq miss cycles 1025system.cpu1.dcache.WriteReq_miss_latency::total 5137653000 # number of WriteReq miss cycles 1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106350500 # number of LoadLockedReq miss cycles 1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 106350500 # number of LoadLockedReq miss cycles 1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87844000 # number of StoreCondReq miss cycles 1029system.cpu1.dcache.StoreCondReq_miss_latency::total 87844000 # number of StoreCondReq miss cycles 1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7511836000 # number of demand (read+write) miss cycles 1031system.cpu1.dcache.demand_miss_latency::total 7511836000 # number of demand (read+write) miss cycles 1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7511836000 # number of overall miss cycles 1033system.cpu1.dcache.overall_miss_latency::total 7511836000 # number of overall miss cycles | 1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles 1023system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles 1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles 1025system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles 1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles 1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles 1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles 1029system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles 1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles 1031system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles 1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles 1033system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles |
| 1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) 1035system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) 1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) 1037system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses) 1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses) 1039system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses) 1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses) 1041system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses 1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses 1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses 1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses 1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses 1055system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses 1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses 1057system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses | 1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) 1035system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) 1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) 1037system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses) 1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses) 1039system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses) 1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses) 1041system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses 1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses 1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses 1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses 1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses 1055system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses 1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses 1057system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses |
| 1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503 # average ReadReq miss latency 1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503 # average ReadReq miss latency 1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299 # average WriteReq miss latency 1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299 # average WriteReq miss latency 1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9563.033900 # average LoadLockedReq miss latency 1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9563.033900 # average LoadLockedReq miss latency 1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.411987 # average StoreCondReq miss latency 1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.411987 # average StoreCondReq miss latency 1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency 1067system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667 # average overall miss latency 1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency 1069system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667 # average overall miss latency | 1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency 1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency 1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency 1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency 1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency 1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency 1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency 1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency 1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency 1067system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency 1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency 1069system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency |
| 1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses 1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses 1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses 1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses 1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses 1089system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses 1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses 1091system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses | 1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses 1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses 1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses 1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses 1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses 1089system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses 1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses 1091system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses |
| 1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles 1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles 1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles 1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles 1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles 1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles 1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles 1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles 1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles 1101system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles 1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles 1103system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles 1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles 1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles 1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles 1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles 1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles 1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles | 1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles 1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles 1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles 1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles 1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles 1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles 1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles 1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles 1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles 1101system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles 1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles 1103system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles 1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles 1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles 1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles 1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles 1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles 1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles |
| 1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses 1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses 1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses 1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses 1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses 1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses 1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses 1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses 1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses 1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses 1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses 1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses | 1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses 1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses 1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses 1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses 1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses 1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses 1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses 1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses 1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses 1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses 1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses 1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses |
| 1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency 1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency 1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency 1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency 1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency 1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency 1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency 1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency 1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency 1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency 1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency 1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency | 1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency 1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency 1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency 1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency 1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency 1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency 1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency 1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency 1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency 1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency 1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency 1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency |
| 1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1153system.iocache.fast_writes 0 # number of fast writes performed 1154system.iocache.cache_copies 0 # number of cache copies performed | 1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1153system.iocache.fast_writes 0 # number of fast writes performed 1154system.iocache.cache_copies 0 # number of cache copies performed |
| 1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles 1156system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles 1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles 1158system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles | 1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles 1156system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles 1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles 1158system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles |
| 1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1164 1165---------- End Simulation Statistics ---------- | 1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1164 1165---------- End Simulation Statistics ---------- |